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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
4 */
5
6#ifndef __DSI_PHY_H__
7#define __DSI_PHY_H__
8
9#include <linux/regulator/consumer.h>
10
11#include "dsi.h"
12
13#define dsi_phy_read(offset) msm_readl((offset))
14#define dsi_phy_write(offset, data) msm_writel((data), (offset))
15
16/* v3.0.0 10nm implementation that requires the old timings settings */
17#define V3_0_0_10NM_OLD_TIMINGS_QUIRK BIT(0)
18
19struct msm_dsi_phy_ops {
20 int (*init) (struct msm_dsi_phy *phy);
21 int (*enable)(struct msm_dsi_phy *phy, int src_pll_id,
22 struct msm_dsi_phy_clk_request *clk_req);
23 void (*disable)(struct msm_dsi_phy *phy);
24};
25
26struct msm_dsi_phy_cfg {
27 enum msm_dsi_phy_type type;
28 struct dsi_reg_config reg_cfg;
29 struct msm_dsi_phy_ops ops;
30
31 /*
32 * Each cell {phy_id, pll_id} of the truth table indicates
33 * if the source PLL selection bit should be set for each PHY.
34 * Fill default H/W values in illegal cells, eg. cell {0, 1}.
35 */
36 bool src_pll_truthtable[DSI_MAX][DSI_MAX];
37 const resource_size_t io_start[DSI_MAX];
38 const int num_dsi_phy;
39 const int quirks;
40};
41
42extern const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs;
43extern const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_famb_cfgs;
44extern const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs;
45extern const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs;
46extern const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs;
47extern const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs;
48extern const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs;
49extern const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs;
50extern const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs;
51
52struct msm_dsi_dphy_timing {
53 u32 clk_pre;
54 u32 clk_post;
55 u32 clk_zero;
56 u32 clk_trail;
57 u32 clk_prepare;
58 u32 hs_exit;
59 u32 hs_zero;
60 u32 hs_prepare;
61 u32 hs_trail;
62 u32 hs_rqst;
63 u32 ta_go;
64 u32 ta_sure;
65 u32 ta_get;
66
67 struct msm_dsi_phy_shared_timings shared_timings;
68
69 /* For PHY v2 only */
70 u32 hs_rqst_ckln;
71 u32 hs_prep_dly;
72 u32 hs_prep_dly_ckln;
73 u8 hs_halfbyte_en;
74 u8 hs_halfbyte_en_ckln;
75};
76
77struct msm_dsi_phy {
78 struct platform_device *pdev;
79 void __iomem *base;
80 void __iomem *reg_base;
81 void __iomem *lane_base;
82 int id;
83
84 struct clk *ahb_clk;
85 struct regulator_bulk_data supplies[DSI_DEV_REGULATOR_MAX];
86
87 struct msm_dsi_dphy_timing timing;
88 const struct msm_dsi_phy_cfg *cfg;
89
90 enum msm_dsi_phy_usecase usecase;
91 bool regulator_ldo_mode;
92
93 struct msm_dsi_pll *pll;
94};
95
96/*
97 * PHY internal functions
98 */
99int msm_dsi_dphy_timing_calc(struct msm_dsi_dphy_timing *timing,
100 struct msm_dsi_phy_clk_request *clk_req);
101int msm_dsi_dphy_timing_calc_v2(struct msm_dsi_dphy_timing *timing,
102 struct msm_dsi_phy_clk_request *clk_req);
103int msm_dsi_dphy_timing_calc_v3(struct msm_dsi_dphy_timing *timing,
104 struct msm_dsi_phy_clk_request *clk_req);
105void msm_dsi_phy_set_src_pll(struct msm_dsi_phy *phy, int pll_id, u32 reg,
106 u32 bit_mask);
107int msm_dsi_phy_init_common(struct msm_dsi_phy *phy);
108
109#endif /* __DSI_PHY_H__ */
110
1/*
2 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#ifndef __DSI_PHY_H__
15#define __DSI_PHY_H__
16
17#include <linux/regulator/consumer.h>
18
19#include "dsi.h"
20
21#define dsi_phy_read(offset) msm_readl((offset))
22#define dsi_phy_write(offset, data) msm_writel((data), (offset))
23
24struct msm_dsi_phy_ops {
25 int (*enable)(struct msm_dsi_phy *phy, int src_pll_id,
26 const unsigned long bit_rate, const unsigned long esc_rate);
27 void (*disable)(struct msm_dsi_phy *phy);
28};
29
30struct msm_dsi_phy_cfg {
31 enum msm_dsi_phy_type type;
32 struct dsi_reg_config reg_cfg;
33 struct msm_dsi_phy_ops ops;
34
35 /*
36 * Each cell {phy_id, pll_id} of the truth table indicates
37 * if the source PLL selection bit should be set for each PHY.
38 * Fill default H/W values in illegal cells, eg. cell {0, 1}.
39 */
40 bool src_pll_truthtable[DSI_MAX][DSI_MAX];
41};
42
43extern const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs;
44extern const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs;
45extern const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs;
46extern const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs;
47
48struct msm_dsi_dphy_timing {
49 u32 clk_pre;
50 u32 clk_post;
51 u32 clk_zero;
52 u32 clk_trail;
53 u32 clk_prepare;
54 u32 hs_exit;
55 u32 hs_zero;
56 u32 hs_prepare;
57 u32 hs_trail;
58 u32 hs_rqst;
59 u32 ta_go;
60 u32 ta_sure;
61 u32 ta_get;
62};
63
64struct msm_dsi_phy {
65 struct platform_device *pdev;
66 void __iomem *base;
67 void __iomem *reg_base;
68 int id;
69
70 struct clk *ahb_clk;
71 struct regulator_bulk_data supplies[DSI_DEV_REGULATOR_MAX];
72
73 struct msm_dsi_dphy_timing timing;
74 const struct msm_dsi_phy_cfg *cfg;
75
76 bool regulator_ldo_mode;
77
78 struct msm_dsi_pll *pll;
79};
80
81/*
82 * PHY internal functions
83 */
84int msm_dsi_dphy_timing_calc(struct msm_dsi_dphy_timing *timing,
85 const unsigned long bit_rate, const unsigned long esc_rate);
86void msm_dsi_phy_set_src_pll(struct msm_dsi_phy *phy, int pll_id, u32 reg,
87 u32 bit_mask);
88
89#endif /* __DSI_PHY_H__ */
90