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1/* Copyright 2012-15 Advanced Micro Devices, Inc.
2 *
3 * Permission is hereby granted, free of charge, to any person obtaining a
4 * copy of this software and associated documentation files (the "Software"),
5 * to deal in the Software without restriction, including without limitation
6 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
7 * and/or sell copies of the Software, and to permit persons to whom the
8 * Software is furnished to do so, subject to the following conditions:
9 *
10 * The above copyright notice and this permission notice shall be included in
11 * all copies or substantial portions of the Software.
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
17 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
19 * OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * Authors: AMD
22 *
23 */
24
25#ifndef __DC_MEM_INPUT_DCN10_H__
26#define __DC_MEM_INPUT_DCN10_H__
27
28#include "hubp.h"
29
30#define TO_DCN10_HUBP(hubp)\
31 container_of(hubp, struct dcn10_hubp, base)
32
33/* Register address initialization macro for all ASICs (including those with reduced functionality) */
34#define HUBP_REG_LIST_DCN(id)\
35 SRI(DCHUBP_CNTL, HUBP, id),\
36 SRI(HUBPREQ_DEBUG_DB, HUBP, id),\
37 SRI(HUBPREQ_DEBUG, HUBP, id),\
38 SRI(DCSURF_ADDR_CONFIG, HUBP, id),\
39 SRI(DCSURF_TILING_CONFIG, HUBP, id),\
40 SRI(DCSURF_SURFACE_PITCH, HUBPREQ, id),\
41 SRI(DCSURF_SURFACE_PITCH_C, HUBPREQ, id),\
42 SRI(DCSURF_SURFACE_CONFIG, HUBP, id),\
43 SRI(DCSURF_FLIP_CONTROL, HUBPREQ, id),\
44 SRI(DCSURF_PRI_VIEWPORT_DIMENSION, HUBP, id), \
45 SRI(DCSURF_PRI_VIEWPORT_START, HUBP, id), \
46 SRI(DCSURF_SEC_VIEWPORT_DIMENSION, HUBP, id), \
47 SRI(DCSURF_SEC_VIEWPORT_START, HUBP, id), \
48 SRI(DCSURF_PRI_VIEWPORT_DIMENSION_C, HUBP, id), \
49 SRI(DCSURF_PRI_VIEWPORT_START_C, HUBP, id), \
50 SRI(DCSURF_SEC_VIEWPORT_DIMENSION_C, HUBP, id), \
51 SRI(DCSURF_SEC_VIEWPORT_START_C, HUBP, id), \
52 SRI(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, HUBPREQ, id),\
53 SRI(DCSURF_PRIMARY_SURFACE_ADDRESS, HUBPREQ, id),\
54 SRI(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, HUBPREQ, id),\
55 SRI(DCSURF_SECONDARY_SURFACE_ADDRESS, HUBPREQ, id),\
56 SRI(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, HUBPREQ, id),\
57 SRI(DCSURF_PRIMARY_META_SURFACE_ADDRESS, HUBPREQ, id),\
58 SRI(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, HUBPREQ, id),\
59 SRI(DCSURF_SECONDARY_META_SURFACE_ADDRESS, HUBPREQ, id),\
60 SRI(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id),\
61 SRI(DCSURF_PRIMARY_SURFACE_ADDRESS_C, HUBPREQ, id),\
62 SRI(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id),\
63 SRI(DCSURF_SECONDARY_SURFACE_ADDRESS_C, HUBPREQ, id),\
64 SRI(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id),\
65 SRI(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, HUBPREQ, id),\
66 SRI(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id),\
67 SRI(DCSURF_SECONDARY_META_SURFACE_ADDRESS_C, HUBPREQ, id),\
68 SRI(DCSURF_SURFACE_INUSE, HUBPREQ, id),\
69 SRI(DCSURF_SURFACE_INUSE_HIGH, HUBPREQ, id),\
70 SRI(DCSURF_SURFACE_INUSE_C, HUBPREQ, id),\
71 SRI(DCSURF_SURFACE_INUSE_HIGH_C, HUBPREQ, id),\
72 SRI(DCSURF_SURFACE_EARLIEST_INUSE, HUBPREQ, id),\
73 SRI(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, HUBPREQ, id),\
74 SRI(DCSURF_SURFACE_EARLIEST_INUSE_C, HUBPREQ, id),\
75 SRI(DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C, HUBPREQ, id),\
76 SRI(DCSURF_SURFACE_CONTROL, HUBPREQ, id),\
77 SRI(HUBPRET_CONTROL, HUBPRET, id),\
78 SRI(DCN_EXPANSION_MODE, HUBPREQ, id),\
79 SRI(DCHUBP_REQ_SIZE_CONFIG, HUBP, id),\
80 SRI(DCHUBP_REQ_SIZE_CONFIG_C, HUBP, id),\
81 SRI(BLANK_OFFSET_0, HUBPREQ, id),\
82 SRI(BLANK_OFFSET_1, HUBPREQ, id),\
83 SRI(DST_DIMENSIONS, HUBPREQ, id),\
84 SRI(DST_AFTER_SCALER, HUBPREQ, id),\
85 SRI(VBLANK_PARAMETERS_0, HUBPREQ, id),\
86 SRI(REF_FREQ_TO_PIX_FREQ, HUBPREQ, id),\
87 SRI(VBLANK_PARAMETERS_1, HUBPREQ, id),\
88 SRI(VBLANK_PARAMETERS_3, HUBPREQ, id),\
89 SRI(NOM_PARAMETERS_4, HUBPREQ, id),\
90 SRI(NOM_PARAMETERS_5, HUBPREQ, id),\
91 SRI(PER_LINE_DELIVERY_PRE, HUBPREQ, id),\
92 SRI(PER_LINE_DELIVERY, HUBPREQ, id),\
93 SRI(VBLANK_PARAMETERS_2, HUBPREQ, id),\
94 SRI(VBLANK_PARAMETERS_4, HUBPREQ, id),\
95 SRI(NOM_PARAMETERS_6, HUBPREQ, id),\
96 SRI(NOM_PARAMETERS_7, HUBPREQ, id),\
97 SRI(DCN_TTU_QOS_WM, HUBPREQ, id),\
98 SRI(DCN_GLOBAL_TTU_CNTL, HUBPREQ, id),\
99 SRI(DCN_SURF0_TTU_CNTL0, HUBPREQ, id),\
100 SRI(DCN_SURF0_TTU_CNTL1, HUBPREQ, id),\
101 SRI(DCN_SURF1_TTU_CNTL0, HUBPREQ, id),\
102 SRI(DCN_SURF1_TTU_CNTL1, HUBPREQ, id),\
103 SRI(DCN_CUR0_TTU_CNTL0, HUBPREQ, id),\
104 SRI(DCN_CUR0_TTU_CNTL1, HUBPREQ, id),\
105 SRI(HUBP_CLK_CNTL, HUBP, id)
106
107/* Register address initialization macro for ASICs with VM */
108#define HUBP_REG_LIST_DCN_VM(id)\
109 SRI(NOM_PARAMETERS_0, HUBPREQ, id),\
110 SRI(NOM_PARAMETERS_1, HUBPREQ, id),\
111 SRI(NOM_PARAMETERS_2, HUBPREQ, id),\
112 SRI(NOM_PARAMETERS_3, HUBPREQ, id),\
113 SRI(DCN_VM_MX_L1_TLB_CNTL, HUBPREQ, id)
114
115#define HUBP_REG_LIST_DCN10(id)\
116 HUBP_REG_LIST_DCN(id),\
117 HUBP_REG_LIST_DCN_VM(id),\
118 SRI(PREFETCH_SETTINS, HUBPREQ, id),\
119 SRI(PREFETCH_SETTINS_C, HUBPREQ, id),\
120 SRI(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, HUBPREQ, id),\
121 SRI(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, HUBPREQ, id),\
122 SRI(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, HUBPREQ, id),\
123 SRI(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, HUBPREQ, id),\
124 SRI(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, HUBPREQ, id),\
125 SRI(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, HUBPREQ, id),\
126 SRI(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, HUBPREQ, id),\
127 SRI(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, HUBPREQ, id),\
128 SRI(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, HUBPREQ, id),\
129 SRI(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, HUBPREQ, id),\
130 SRI(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, HUBPREQ, id),\
131 SRI(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, HUBPREQ, id),\
132 SRI(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, HUBPREQ, id),\
133 SRI(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, HUBPREQ, id),\
134 SRI(CURSOR_SETTINS, HUBPREQ, id), \
135 SRI(CURSOR_SURFACE_ADDRESS_HIGH, CURSOR, id), \
136 SRI(CURSOR_SURFACE_ADDRESS, CURSOR, id), \
137 SRI(CURSOR_SIZE, CURSOR, id), \
138 SRI(CURSOR_CONTROL, CURSOR, id), \
139 SRI(CURSOR_POSITION, CURSOR, id), \
140 SRI(CURSOR_HOT_SPOT, CURSOR, id), \
141 SRI(CURSOR_DST_OFFSET, CURSOR, id)
142
143#define HUBP_COMMON_REG_VARIABLE_LIST \
144 uint32_t DCHUBP_CNTL; \
145 uint32_t HUBPREQ_DEBUG_DB; \
146 uint32_t HUBPREQ_DEBUG; \
147 uint32_t DCSURF_ADDR_CONFIG; \
148 uint32_t DCSURF_TILING_CONFIG; \
149 uint32_t DCSURF_SURFACE_PITCH; \
150 uint32_t DCSURF_SURFACE_PITCH_C; \
151 uint32_t DCSURF_SURFACE_CONFIG; \
152 uint32_t DCSURF_FLIP_CONTROL; \
153 uint32_t DCSURF_PRI_VIEWPORT_DIMENSION; \
154 uint32_t DCSURF_PRI_VIEWPORT_START; \
155 uint32_t DCSURF_SEC_VIEWPORT_DIMENSION; \
156 uint32_t DCSURF_SEC_VIEWPORT_START; \
157 uint32_t DCSURF_PRI_VIEWPORT_DIMENSION_C; \
158 uint32_t DCSURF_PRI_VIEWPORT_START_C; \
159 uint32_t DCSURF_SEC_VIEWPORT_DIMENSION_C; \
160 uint32_t DCSURF_SEC_VIEWPORT_START_C; \
161 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; \
162 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; \
163 uint32_t DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH; \
164 uint32_t DCSURF_SECONDARY_SURFACE_ADDRESS; \
165 uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH; \
166 uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS; \
167 uint32_t DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH; \
168 uint32_t DCSURF_SECONDARY_META_SURFACE_ADDRESS; \
169 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; \
170 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; \
171 uint32_t DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C; \
172 uint32_t DCSURF_SECONDARY_SURFACE_ADDRESS_C; \
173 uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C; \
174 uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_C; \
175 uint32_t DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C; \
176 uint32_t DCSURF_SECONDARY_META_SURFACE_ADDRESS_C; \
177 uint32_t DCSURF_SURFACE_INUSE; \
178 uint32_t DCSURF_SURFACE_INUSE_HIGH; \
179 uint32_t DCSURF_SURFACE_INUSE_C; \
180 uint32_t DCSURF_SURFACE_INUSE_HIGH_C; \
181 uint32_t DCSURF_SURFACE_EARLIEST_INUSE; \
182 uint32_t DCSURF_SURFACE_EARLIEST_INUSE_HIGH; \
183 uint32_t DCSURF_SURFACE_EARLIEST_INUSE_C; \
184 uint32_t DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C; \
185 uint32_t DCSURF_SURFACE_CONTROL; \
186 uint32_t HUBPRET_CONTROL; \
187 uint32_t DCN_EXPANSION_MODE; \
188 uint32_t DCHUBP_REQ_SIZE_CONFIG; \
189 uint32_t DCHUBP_REQ_SIZE_CONFIG_C; \
190 uint32_t BLANK_OFFSET_0; \
191 uint32_t BLANK_OFFSET_1; \
192 uint32_t DST_DIMENSIONS; \
193 uint32_t DST_AFTER_SCALER; \
194 uint32_t PREFETCH_SETTINS; \
195 uint32_t PREFETCH_SETTINGS; \
196 uint32_t VBLANK_PARAMETERS_0; \
197 uint32_t REF_FREQ_TO_PIX_FREQ; \
198 uint32_t VBLANK_PARAMETERS_1; \
199 uint32_t VBLANK_PARAMETERS_3; \
200 uint32_t NOM_PARAMETERS_0; \
201 uint32_t NOM_PARAMETERS_1; \
202 uint32_t NOM_PARAMETERS_4; \
203 uint32_t NOM_PARAMETERS_5; \
204 uint32_t PER_LINE_DELIVERY_PRE; \
205 uint32_t PER_LINE_DELIVERY; \
206 uint32_t PREFETCH_SETTINS_C; \
207 uint32_t PREFETCH_SETTINGS_C; \
208 uint32_t VBLANK_PARAMETERS_2; \
209 uint32_t VBLANK_PARAMETERS_4; \
210 uint32_t NOM_PARAMETERS_2; \
211 uint32_t NOM_PARAMETERS_3; \
212 uint32_t NOM_PARAMETERS_6; \
213 uint32_t NOM_PARAMETERS_7; \
214 uint32_t DCN_TTU_QOS_WM; \
215 uint32_t DCN_GLOBAL_TTU_CNTL; \
216 uint32_t DCN_SURF0_TTU_CNTL0; \
217 uint32_t DCN_SURF0_TTU_CNTL1; \
218 uint32_t DCN_SURF1_TTU_CNTL0; \
219 uint32_t DCN_SURF1_TTU_CNTL1; \
220 uint32_t DCN_CUR0_TTU_CNTL0; \
221 uint32_t DCN_CUR0_TTU_CNTL1; \
222 uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB; \
223 uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB; \
224 uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB; \
225 uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB; \
226 uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB; \
227 uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB; \
228 uint32_t DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB; \
229 uint32_t DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB; \
230 uint32_t DCN_VM_MX_L1_TLB_CNTL; \
231 uint32_t DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB; \
232 uint32_t DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB; \
233 uint32_t DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB; \
234 uint32_t DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB; \
235 uint32_t DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB; \
236 uint32_t DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB; \
237 uint32_t DCN_VM_SYSTEM_APERTURE_LOW_ADDR; \
238 uint32_t DCN_VM_SYSTEM_APERTURE_HIGH_ADDR; \
239 uint32_t CURSOR_SETTINS; \
240 uint32_t CURSOR_SETTINGS; \
241 uint32_t CURSOR_SURFACE_ADDRESS_HIGH; \
242 uint32_t CURSOR_SURFACE_ADDRESS; \
243 uint32_t CURSOR_SIZE; \
244 uint32_t CURSOR_CONTROL; \
245 uint32_t CURSOR_POSITION; \
246 uint32_t CURSOR_HOT_SPOT; \
247 uint32_t CURSOR_DST_OFFSET; \
248 uint32_t HUBP_CLK_CNTL
249
250#define HUBP_SF(reg_name, field_name, post_fix)\
251 .field_name = reg_name ## __ ## field_name ## post_fix
252
253/* Mask/shift struct generation macro for all ASICs (including those with reduced functionality) */
254/*1.x, 2.x, and 3.x*/
255#define HUBP_MASK_SH_LIST_DCN_SHARE_COMMON(mask_sh)\
256 HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_BLANK_EN, mask_sh),\
257 HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_TTU_DISABLE, mask_sh),\
258 HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_UNDERFLOW_STATUS, mask_sh),\
259 HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_UNDERFLOW_CLEAR, mask_sh),\
260 HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_NO_OUTSTANDING_REQ, mask_sh),\
261 HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_VTG_SEL, mask_sh),\
262 HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_DISABLE, mask_sh),\
263 HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_PIPES, mask_sh),\
264 HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_BANKS, mask_sh),\
265 HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, PIPE_INTERLEAVE, mask_sh),\
266 HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_SE, mask_sh),\
267 HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_RB_PER_SE, mask_sh),\
268 HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, MAX_COMPRESSED_FRAGS, mask_sh),\
269 HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, SW_MODE, mask_sh),\
270 HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, META_LINEAR, mask_sh),\
271 HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, PIPE_ALIGNED, mask_sh),\
272 HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH, mask_sh),\
273 HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH, META_PITCH, mask_sh),\
274 HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH_C, PITCH_C, mask_sh),\
275 HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH_C, META_PITCH_C, mask_sh),\
276 HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, SURFACE_PIXEL_FORMAT, mask_sh),\
277 HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_TYPE, mask_sh),\
278 HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, mask_sh),\
279 HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, mask_sh),\
280 HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_PENDING, mask_sh),\
281 HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, mask_sh),\
282 HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH, mask_sh),\
283 HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT, mask_sh),\
284 HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START, PRI_VIEWPORT_X_START, mask_sh),\
285 HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START, PRI_VIEWPORT_Y_START, mask_sh),\
286 HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION, SEC_VIEWPORT_WIDTH, mask_sh),\
287 HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION, SEC_VIEWPORT_HEIGHT, mask_sh),\
288 HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_START, SEC_VIEWPORT_X_START, mask_sh),\
289 HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_START, SEC_VIEWPORT_Y_START, mask_sh),\
290 HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C, PRI_VIEWPORT_WIDTH_C, mask_sh),\
291 HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C, PRI_VIEWPORT_HEIGHT_C, mask_sh),\
292 HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START_C, PRI_VIEWPORT_X_START_C, mask_sh),\
293 HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START_C, PRI_VIEWPORT_Y_START_C, mask_sh),\
294 HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C, SEC_VIEWPORT_WIDTH_C, mask_sh),\
295 HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C, SEC_VIEWPORT_HEIGHT_C, mask_sh),\
296 HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_START_C, SEC_VIEWPORT_X_START_C, mask_sh),\
297 HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_START_C, SEC_VIEWPORT_Y_START_C, mask_sh),\
298 HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, PRIMARY_SURFACE_ADDRESS_HIGH, mask_sh),\
299 HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS, PRIMARY_SURFACE_ADDRESS, mask_sh),\
300 HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, SECONDARY_SURFACE_ADDRESS_HIGH, mask_sh),\
301 HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS, SECONDARY_SURFACE_ADDRESS, mask_sh),\
302 HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, PRIMARY_META_SURFACE_ADDRESS_HIGH, mask_sh),\
303 HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS, PRIMARY_META_SURFACE_ADDRESS, mask_sh),\
304 HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, SECONDARY_META_SURFACE_ADDRESS_HIGH, mask_sh),\
305 HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS, SECONDARY_META_SURFACE_ADDRESS, mask_sh),\
306 HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, PRIMARY_SURFACE_ADDRESS_HIGH_C, mask_sh),\
307 HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C, PRIMARY_SURFACE_ADDRESS_C, mask_sh),\
308 HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C, SECONDARY_SURFACE_ADDRESS_HIGH_C, mask_sh),\
309 HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C, SECONDARY_SURFACE_ADDRESS_C, mask_sh),\
310 HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, PRIMARY_META_SURFACE_ADDRESS_HIGH_C, mask_sh),\
311 HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, PRIMARY_META_SURFACE_ADDRESS_C, mask_sh),\
312 HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C, SECONDARY_META_SURFACE_ADDRESS_HIGH_C, mask_sh),\
313 HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C, SECONDARY_META_SURFACE_ADDRESS_C, mask_sh),\
314 HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE, SURFACE_INUSE_ADDRESS, mask_sh),\
315 HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH, SURFACE_INUSE_ADDRESS_HIGH, mask_sh),\
316 HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_C, SURFACE_INUSE_ADDRESS_C, mask_sh),\
317 HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C, SURFACE_INUSE_ADDRESS_HIGH_C, mask_sh),\
318 HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE, SURFACE_EARLIEST_INUSE_ADDRESS, mask_sh),\
319 HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH, SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, mask_sh),\
320 HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C, SURFACE_EARLIEST_INUSE_ADDRESS_C, mask_sh),\
321 HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C, SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C, mask_sh),\
322 HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_TMZ, mask_sh),\
323 HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_TMZ_C, mask_sh),\
324 HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_META_SURFACE_TMZ, mask_sh),\
325 HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_META_SURFACE_TMZ_C, mask_sh),\
326 HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_DCC_EN, mask_sh),\
327 HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_DCC_IND_64B_BLK, mask_sh),\
328 HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_TMZ, mask_sh),\
329 HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_TMZ_C, mask_sh),\
330 HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_META_SURFACE_TMZ, mask_sh),\
331 HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_META_SURFACE_TMZ_C, mask_sh),\
332 HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_DCC_EN, mask_sh),\
333 HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_DCC_IND_64B_BLK, mask_sh),\
334 HUBP_SF(HUBPRET0_HUBPRET_CONTROL, DET_BUF_PLANE1_BASE_ADDRESS, mask_sh),\
335 HUBP_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_CB_B, mask_sh),\
336 HUBP_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_CR_R, mask_sh),\
337 HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, DRQ_EXPANSION_MODE, mask_sh),\
338 HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, PRQ_EXPANSION_MODE, mask_sh),\
339 HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, MRQ_EXPANSION_MODE, mask_sh),\
340 HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, CRQ_EXPANSION_MODE, mask_sh),\
341 HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, CHUNK_SIZE, mask_sh),\
342 HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MIN_CHUNK_SIZE, mask_sh),\
343 HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, META_CHUNK_SIZE, mask_sh),\
344 HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MIN_META_CHUNK_SIZE, mask_sh),\
345 HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, DPTE_GROUP_SIZE, mask_sh),\
346 HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, SWATH_HEIGHT, mask_sh),\
347 HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, PTE_ROW_HEIGHT_LINEAR, mask_sh),\
348 HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, CHUNK_SIZE_C, mask_sh),\
349 HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MIN_CHUNK_SIZE_C, mask_sh),\
350 HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, META_CHUNK_SIZE_C, mask_sh),\
351 HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MIN_META_CHUNK_SIZE_C, mask_sh),\
352 HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, DPTE_GROUP_SIZE_C, mask_sh),\
353 HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, SWATH_HEIGHT_C, mask_sh),\
354 HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, PTE_ROW_HEIGHT_LINEAR_C, mask_sh),\
355 HUBP_SF(HUBPREQ0_BLANK_OFFSET_0, REFCYC_H_BLANK_END, mask_sh),\
356 HUBP_SF(HUBPREQ0_BLANK_OFFSET_0, DLG_V_BLANK_END, mask_sh),\
357 HUBP_SF(HUBPREQ0_BLANK_OFFSET_1, MIN_DST_Y_NEXT_START, mask_sh),\
358 HUBP_SF(HUBPREQ0_DST_DIMENSIONS, REFCYC_PER_HTOTAL, mask_sh),\
359 HUBP_SF(HUBPREQ0_DST_AFTER_SCALER, REFCYC_X_AFTER_SCALER, mask_sh),\
360 HUBP_SF(HUBPREQ0_DST_AFTER_SCALER, DST_Y_AFTER_SCALER, mask_sh),\
361 HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_0, DST_Y_PER_VM_VBLANK, mask_sh),\
362 HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_0, DST_Y_PER_ROW_VBLANK, mask_sh),\
363 HUBP_SF(HUBPREQ0_REF_FREQ_TO_PIX_FREQ, REF_FREQ_TO_PIX_FREQ, mask_sh),\
364 HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_1, REFCYC_PER_PTE_GROUP_VBLANK_L, mask_sh),\
365 HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_3, REFCYC_PER_META_CHUNK_VBLANK_L, mask_sh),\
366 HUBP_SF(HUBPREQ0_NOM_PARAMETERS_4, DST_Y_PER_META_ROW_NOM_L, mask_sh),\
367 HUBP_SF(HUBPREQ0_NOM_PARAMETERS_5, REFCYC_PER_META_CHUNK_NOM_L, mask_sh),\
368 HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY_PRE, REFCYC_PER_LINE_DELIVERY_PRE_L, mask_sh),\
369 HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY_PRE, REFCYC_PER_LINE_DELIVERY_PRE_C, mask_sh),\
370 HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY, REFCYC_PER_LINE_DELIVERY_L, mask_sh),\
371 HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY, REFCYC_PER_LINE_DELIVERY_C, mask_sh),\
372 HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_2, REFCYC_PER_PTE_GROUP_VBLANK_C, mask_sh),\
373 HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_4, REFCYC_PER_META_CHUNK_VBLANK_C, mask_sh),\
374 HUBP_SF(HUBPREQ0_NOM_PARAMETERS_6, DST_Y_PER_META_ROW_NOM_C, mask_sh),\
375 HUBP_SF(HUBPREQ0_NOM_PARAMETERS_7, REFCYC_PER_META_CHUNK_NOM_C, mask_sh),\
376 HUBP_SF(HUBPREQ0_DCN_TTU_QOS_WM, QoS_LEVEL_LOW_WM, mask_sh),\
377 HUBP_SF(HUBPREQ0_DCN_TTU_QOS_WM, QoS_LEVEL_HIGH_WM, mask_sh),\
378 HUBP_SF(HUBPREQ0_DCN_GLOBAL_TTU_CNTL, MIN_TTU_VBLANK, mask_sh),\
379 HUBP_SF(HUBPREQ0_DCN_GLOBAL_TTU_CNTL, QoS_LEVEL_FLIP, mask_sh),\
380 HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, REFCYC_PER_REQ_DELIVERY, mask_sh),\
381 HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, QoS_LEVEL_FIXED, mask_sh),\
382 HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, QoS_RAMP_DISABLE, mask_sh),\
383 HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL1, REFCYC_PER_REQ_DELIVERY_PRE, mask_sh),\
384 HUBP_SF(HUBP0_HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, mask_sh)
385/*2.x and 1.x only*/
386#define HUBP_MASK_SH_LIST_DCN_COMMON(mask_sh)\
387 HUBP_MASK_SH_LIST_DCN_SHARE_COMMON(mask_sh),\
388 HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, RB_ALIGNED, mask_sh),\
389 HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MPTE_GROUP_SIZE, mask_sh),\
390 HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MPTE_GROUP_SIZE_C, mask_sh)
391
392/*2.x and 1.x only*/
393#define HUBP_MASK_SH_LIST_DCN(mask_sh)\
394 HUBP_MASK_SH_LIST_DCN_COMMON(mask_sh)
395
396/* Mask/shift struct generation macro for ASICs with VM */
397#define HUBP_MASK_SH_LIST_DCN_VM(mask_sh)\
398 HUBP_SF(HUBPREQ0_NOM_PARAMETERS_0, DST_Y_PER_PTE_ROW_NOM_L, mask_sh),\
399 HUBP_SF(HUBPREQ0_NOM_PARAMETERS_1, REFCYC_PER_PTE_GROUP_NOM_L, mask_sh),\
400 HUBP_SF(HUBPREQ0_NOM_PARAMETERS_2, DST_Y_PER_PTE_ROW_NOM_C, mask_sh),\
401 HUBP_SF(HUBPREQ0_NOM_PARAMETERS_3, REFCYC_PER_PTE_GROUP_NOM_C, mask_sh),\
402 HUBP_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, mask_sh),\
403 HUBP_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, mask_sh),\
404 HUBP_SF(HUBPREQ0_DCN_CUR0_TTU_CNTL0, REFCYC_PER_REQ_DELIVERY, mask_sh),\
405 HUBP_SF(HUBPREQ0_DCN_CUR0_TTU_CNTL0, QoS_LEVEL_FIXED, mask_sh),\
406 HUBP_SF(HUBPREQ0_DCN_CUR0_TTU_CNTL0, QoS_RAMP_DISABLE, mask_sh),\
407 HUBP_SF(HUBPREQ0_DCN_CUR0_TTU_CNTL1, REFCYC_PER_REQ_DELIVERY_PRE, mask_sh)
408
409#define HUBP_MASK_SH_LIST_DCN10(mask_sh)\
410 HUBP_MASK_SH_LIST_DCN(mask_sh),\
411 HUBP_MASK_SH_LIST_DCN_VM(mask_sh),\
412 HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, ROTATION_ANGLE, mask_sh),\
413 HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, H_MIRROR_EN, mask_sh),\
414 HUBP_SF(HUBPREQ0_PREFETCH_SETTINS, DST_Y_PREFETCH, mask_sh),\
415 HUBP_SF(HUBPREQ0_PREFETCH_SETTINS, VRATIO_PREFETCH, mask_sh),\
416 HUBP_SF(HUBPREQ0_PREFETCH_SETTINS_C, VRATIO_PREFETCH_C, mask_sh),\
417 HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, mask_sh),\
418 HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, mask_sh),\
419 HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, mask_sh),\
420 HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, mask_sh),\
421 HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, mask_sh),\
422 HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, mask_sh),\
423 HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, mask_sh),\
424 HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM, mask_sh),\
425 HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, mask_sh),\
426 HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, mask_sh),\
427 HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, mask_sh),\
428 HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, mask_sh),\
429 HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, mask_sh),\
430 HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, mask_sh),\
431 HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mask_sh),\
432 HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mask_sh),\
433 HUBP_SF(HUBPREQ0_CURSOR_SETTINS, CURSOR0_DST_Y_OFFSET, mask_sh), \
434 HUBP_SF(HUBPREQ0_CURSOR_SETTINS, CURSOR0_CHUNK_HDL_ADJUST, mask_sh), \
435 HUBP_SF(CURSOR0_CURSOR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \
436 HUBP_SF(CURSOR0_CURSOR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \
437 HUBP_SF(CURSOR0_CURSOR_SIZE, CURSOR_WIDTH, mask_sh), \
438 HUBP_SF(CURSOR0_CURSOR_SIZE, CURSOR_HEIGHT, mask_sh), \
439 HUBP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \
440 HUBP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \
441 HUBP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \
442 HUBP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \
443 HUBP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \
444 HUBP_SF(CURSOR0_CURSOR_POSITION, CURSOR_X_POSITION, mask_sh), \
445 HUBP_SF(CURSOR0_CURSOR_POSITION, CURSOR_Y_POSITION, mask_sh), \
446 HUBP_SF(CURSOR0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \
447 HUBP_SF(CURSOR0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \
448 HUBP_SF(CURSOR0_CURSOR_DST_OFFSET, CURSOR_DST_X_OFFSET, mask_sh)
449
450#define DCN_HUBP_REG_FIELD_BASE_LIST(type) \
451 type HUBP_BLANK_EN;\
452 type HUBP_DISABLE;\
453 type HUBP_TTU_DISABLE;\
454 type HUBP_NO_OUTSTANDING_REQ;\
455 type HUBP_VTG_SEL;\
456 type HUBP_UNDERFLOW_STATUS;\
457 type HUBP_UNDERFLOW_CLEAR;\
458 type NUM_PIPES;\
459 type NUM_BANKS;\
460 type PIPE_INTERLEAVE;\
461 type NUM_SE;\
462 type NUM_RB_PER_SE;\
463 type MAX_COMPRESSED_FRAGS;\
464 type SW_MODE;\
465 type META_LINEAR;\
466 type RB_ALIGNED;\
467 type PIPE_ALIGNED;\
468 type PITCH;\
469 type META_PITCH;\
470 type PITCH_C;\
471 type META_PITCH_C;\
472 type ROTATION_ANGLE;\
473 type H_MIRROR_EN;\
474 type SURFACE_PIXEL_FORMAT;\
475 type SURFACE_FLIP_TYPE;\
476 type SURFACE_FLIP_MODE_FOR_STEREOSYNC;\
477 type SURFACE_FLIP_IN_STEREOSYNC;\
478 type SURFACE_UPDATE_LOCK;\
479 type SURFACE_FLIP_PENDING;\
480 type PRI_VIEWPORT_WIDTH; \
481 type PRI_VIEWPORT_HEIGHT; \
482 type PRI_VIEWPORT_X_START; \
483 type PRI_VIEWPORT_Y_START; \
484 type SEC_VIEWPORT_WIDTH; \
485 type SEC_VIEWPORT_HEIGHT; \
486 type SEC_VIEWPORT_X_START; \
487 type SEC_VIEWPORT_Y_START; \
488 type PRI_VIEWPORT_WIDTH_C; \
489 type PRI_VIEWPORT_HEIGHT_C; \
490 type PRI_VIEWPORT_X_START_C; \
491 type PRI_VIEWPORT_Y_START_C; \
492 type SEC_VIEWPORT_WIDTH_C; \
493 type SEC_VIEWPORT_HEIGHT_C; \
494 type SEC_VIEWPORT_X_START_C; \
495 type SEC_VIEWPORT_Y_START_C; \
496 type PRIMARY_SURFACE_ADDRESS_HIGH;\
497 type PRIMARY_SURFACE_ADDRESS;\
498 type SECONDARY_SURFACE_ADDRESS_HIGH;\
499 type SECONDARY_SURFACE_ADDRESS;\
500 type PRIMARY_META_SURFACE_ADDRESS_HIGH;\
501 type PRIMARY_META_SURFACE_ADDRESS;\
502 type SECONDARY_META_SURFACE_ADDRESS_HIGH;\
503 type SECONDARY_META_SURFACE_ADDRESS;\
504 type PRIMARY_SURFACE_ADDRESS_HIGH_C;\
505 type PRIMARY_SURFACE_ADDRESS_C;\
506 type SECONDARY_SURFACE_ADDRESS_HIGH_C;\
507 type SECONDARY_SURFACE_ADDRESS_C;\
508 type PRIMARY_META_SURFACE_ADDRESS_HIGH_C;\
509 type PRIMARY_META_SURFACE_ADDRESS_C;\
510 type SECONDARY_META_SURFACE_ADDRESS_HIGH_C;\
511 type SECONDARY_META_SURFACE_ADDRESS_C;\
512 type SURFACE_INUSE_ADDRESS;\
513 type SURFACE_INUSE_ADDRESS_HIGH;\
514 type SURFACE_INUSE_ADDRESS_C;\
515 type SURFACE_INUSE_ADDRESS_HIGH_C;\
516 type SURFACE_EARLIEST_INUSE_ADDRESS;\
517 type SURFACE_EARLIEST_INUSE_ADDRESS_HIGH;\
518 type SURFACE_EARLIEST_INUSE_ADDRESS_C;\
519 type SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C;\
520 type PRIMARY_SURFACE_TMZ;\
521 type PRIMARY_SURFACE_TMZ_C;\
522 type SECONDARY_SURFACE_TMZ;\
523 type SECONDARY_SURFACE_TMZ_C;\
524 type PRIMARY_META_SURFACE_TMZ;\
525 type PRIMARY_META_SURFACE_TMZ_C;\
526 type SECONDARY_META_SURFACE_TMZ;\
527 type SECONDARY_META_SURFACE_TMZ_C;\
528 type PRIMARY_SURFACE_DCC_EN;\
529 type PRIMARY_SURFACE_DCC_IND_64B_BLK;\
530 type SECONDARY_SURFACE_DCC_EN;\
531 type SECONDARY_SURFACE_DCC_IND_64B_BLK;\
532 type DET_BUF_PLANE1_BASE_ADDRESS;\
533 type CROSSBAR_SRC_CB_B;\
534 type CROSSBAR_SRC_CR_R;\
535 type DRQ_EXPANSION_MODE;\
536 type PRQ_EXPANSION_MODE;\
537 type MRQ_EXPANSION_MODE;\
538 type CRQ_EXPANSION_MODE;\
539 type CHUNK_SIZE;\
540 type MIN_CHUNK_SIZE;\
541 type META_CHUNK_SIZE;\
542 type MIN_META_CHUNK_SIZE;\
543 type DPTE_GROUP_SIZE;\
544 type MPTE_GROUP_SIZE;\
545 type SWATH_HEIGHT;\
546 type PTE_ROW_HEIGHT_LINEAR;\
547 type CHUNK_SIZE_C;\
548 type MIN_CHUNK_SIZE_C;\
549 type META_CHUNK_SIZE_C;\
550 type MIN_META_CHUNK_SIZE_C;\
551 type DPTE_GROUP_SIZE_C;\
552 type MPTE_GROUP_SIZE_C;\
553 type SWATH_HEIGHT_C;\
554 type PTE_ROW_HEIGHT_LINEAR_C;\
555 type REFCYC_H_BLANK_END;\
556 type DLG_V_BLANK_END;\
557 type MIN_DST_Y_NEXT_START;\
558 type REFCYC_PER_HTOTAL;\
559 type REFCYC_X_AFTER_SCALER;\
560 type DST_Y_AFTER_SCALER;\
561 type DST_Y_PREFETCH;\
562 type VRATIO_PREFETCH;\
563 type DST_Y_PER_VM_VBLANK;\
564 type DST_Y_PER_ROW_VBLANK;\
565 type REF_FREQ_TO_PIX_FREQ;\
566 type REFCYC_PER_PTE_GROUP_VBLANK_L;\
567 type REFCYC_PER_META_CHUNK_VBLANK_L;\
568 type DST_Y_PER_PTE_ROW_NOM_L;\
569 type REFCYC_PER_PTE_GROUP_NOM_L;\
570 type DST_Y_PER_META_ROW_NOM_L;\
571 type REFCYC_PER_META_CHUNK_NOM_L;\
572 type REFCYC_PER_LINE_DELIVERY_PRE_L;\
573 type REFCYC_PER_LINE_DELIVERY_PRE_C;\
574 type REFCYC_PER_LINE_DELIVERY_L;\
575 type REFCYC_PER_LINE_DELIVERY_C;\
576 type VRATIO_PREFETCH_C;\
577 type REFCYC_PER_PTE_GROUP_VBLANK_C;\
578 type REFCYC_PER_META_CHUNK_VBLANK_C;\
579 type DST_Y_PER_PTE_ROW_NOM_C;\
580 type REFCYC_PER_PTE_GROUP_NOM_C;\
581 type DST_Y_PER_META_ROW_NOM_C;\
582 type REFCYC_PER_META_CHUNK_NOM_C;\
583 type QoS_LEVEL_LOW_WM;\
584 type QoS_LEVEL_HIGH_WM;\
585 type MIN_TTU_VBLANK;\
586 type QoS_LEVEL_FLIP;\
587 type REFCYC_PER_REQ_DELIVERY;\
588 type QoS_LEVEL_FIXED;\
589 type QoS_RAMP_DISABLE;\
590 type REFCYC_PER_REQ_DELIVERY_PRE;\
591 type VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB;\
592 type VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB;\
593 type VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB;\
594 type VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB;\
595 type VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB;\
596 type VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB;\
597 type VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB;\
598 type VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM;\
599 type VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB;\
600 type ENABLE_L1_TLB;\
601 type SYSTEM_ACCESS_MODE;\
602 type HUBP_CLOCK_ENABLE;\
603 type MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM;\
604 type MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB;\
605 type MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB;\
606 type MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB;\
607 type MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB;\
608 type MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB;\
609 type MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB;\
610 type MC_VM_SYSTEM_APERTURE_LOW_ADDR;\
611 type MC_VM_SYSTEM_APERTURE_HIGH_ADDR;\
612 type DCN_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM;\
613 type DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB;\
614 type DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB;\
615 /* todo: get these from GVM instead of reading registers ourselves */\
616 type PAGE_DIRECTORY_ENTRY_HI32;\
617 type PAGE_DIRECTORY_ENTRY_LO32;\
618 type LOGICAL_PAGE_NUMBER_HI4;\
619 type LOGICAL_PAGE_NUMBER_LO32;\
620 type PHYSICAL_PAGE_ADDR_HI4;\
621 type PHYSICAL_PAGE_ADDR_LO32;\
622 type PHYSICAL_PAGE_NUMBER_MSB;\
623 type PHYSICAL_PAGE_NUMBER_LSB;\
624 type LOGICAL_ADDR;\
625 type CURSOR0_DST_Y_OFFSET; \
626 type CURSOR0_CHUNK_HDL_ADJUST; \
627 type CURSOR_SURFACE_ADDRESS_HIGH; \
628 type CURSOR_SURFACE_ADDRESS; \
629 type CURSOR_WIDTH; \
630 type CURSOR_HEIGHT; \
631 type CURSOR_MODE; \
632 type CURSOR_2X_MAGNIFY; \
633 type CURSOR_PITCH; \
634 type CURSOR_LINES_PER_CHUNK; \
635 type CURSOR_ENABLE; \
636 type CURSOR_X_POSITION; \
637 type CURSOR_Y_POSITION; \
638 type CURSOR_HOT_SPOT_X; \
639 type CURSOR_HOT_SPOT_Y; \
640 type CURSOR_DST_X_OFFSET; \
641 type OUTPUT_FP
642
643#define DCN_HUBP_REG_FIELD_LIST(type) \
644 DCN_HUBP_REG_FIELD_BASE_LIST(type);\
645 type ALPHA_PLANE_EN
646
647struct dcn_mi_registers {
648 HUBP_COMMON_REG_VARIABLE_LIST;
649};
650
651struct dcn_mi_shift {
652 DCN_HUBP_REG_FIELD_LIST(uint8_t);
653};
654
655struct dcn_mi_mask {
656 DCN_HUBP_REG_FIELD_LIST(uint32_t);
657};
658
659struct dcn_hubp_state {
660 struct _vcs_dpi_display_dlg_regs_st dlg_attr;
661 struct _vcs_dpi_display_ttu_regs_st ttu_attr;
662 struct _vcs_dpi_display_rq_regs_st rq_regs;
663 uint32_t pixel_format;
664 uint32_t inuse_addr_hi;
665 uint32_t inuse_addr_lo;
666 uint32_t viewport_width;
667 uint32_t viewport_height;
668 uint32_t rotation_angle;
669 uint32_t h_mirror_en;
670 uint32_t sw_mode;
671 uint32_t dcc_en;
672 uint32_t blank_en;
673 uint32_t clock_en;
674 uint32_t underflow_status;
675 uint32_t ttu_disable;
676 uint32_t min_ttu_vblank;
677 uint32_t qos_level_low_wm;
678 uint32_t qos_level_high_wm;
679};
680
681struct dcn10_hubp {
682 struct hubp base;
683 struct dcn_hubp_state state;
684 const struct dcn_mi_registers *hubp_regs;
685 const struct dcn_mi_shift *hubp_shift;
686 const struct dcn_mi_mask *hubp_mask;
687};
688
689void hubp1_program_surface_config(
690 struct hubp *hubp,
691 enum surface_pixel_format format,
692 union dc_tiling_info *tiling_info,
693 struct plane_size *plane_size,
694 enum dc_rotation_angle rotation,
695 struct dc_plane_dcc_param *dcc,
696 bool horizontal_mirror,
697 unsigned int compat_level);
698
699void hubp1_program_deadline(
700 struct hubp *hubp,
701 struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
702 struct _vcs_dpi_display_ttu_regs_st *ttu_attr);
703
704void hubp1_program_requestor(
705 struct hubp *hubp,
706 struct _vcs_dpi_display_rq_regs_st *rq_regs);
707
708void hubp1_program_pixel_format(
709 struct hubp *hubp,
710 enum surface_pixel_format format);
711
712void hubp1_program_size(
713 struct hubp *hubp,
714 enum surface_pixel_format format,
715 const struct plane_size *plane_size,
716 struct dc_plane_dcc_param *dcc);
717
718void hubp1_program_rotation(
719 struct hubp *hubp,
720 enum dc_rotation_angle rotation,
721 bool horizontal_mirror);
722
723void hubp1_program_tiling(
724 struct hubp *hubp,
725 const union dc_tiling_info *info,
726 const enum surface_pixel_format pixel_format);
727
728void hubp1_dcc_control(struct hubp *hubp,
729 bool enable,
730 enum hubp_ind_block_size independent_64b_blks);
731
732bool hubp1_program_surface_flip_and_addr(
733 struct hubp *hubp,
734 const struct dc_plane_address *address,
735 bool flip_immediate);
736
737bool hubp1_is_flip_pending(struct hubp *hubp);
738
739void hubp1_cursor_set_attributes(
740 struct hubp *hubp,
741 const struct dc_cursor_attributes *attr);
742
743void hubp1_cursor_set_position(
744 struct hubp *hubp,
745 const struct dc_cursor_position *pos,
746 const struct dc_cursor_mi_param *param);
747
748void hubp1_set_blank(struct hubp *hubp, bool blank);
749
750void min_set_viewport(struct hubp *hubp,
751 const struct rect *viewport,
752 const struct rect *viewport_c);
753
754void hubp1_clk_cntl(struct hubp *hubp, bool enable);
755void hubp1_vtg_sel(struct hubp *hubp, uint32_t otg_inst);
756
757void dcn10_hubp_construct(
758 struct dcn10_hubp *hubp1,
759 struct dc_context *ctx,
760 uint32_t inst,
761 const struct dcn_mi_registers *hubp_regs,
762 const struct dcn_mi_shift *hubp_shift,
763 const struct dcn_mi_mask *hubp_mask);
764
765void hubp1_read_state(struct hubp *hubp);
766void hubp1_clear_underflow(struct hubp *hubp);
767
768enum cursor_pitch hubp1_get_cursor_pitch(unsigned int pitch);
769
770void hubp1_vready_workaround(struct hubp *hubp,
771 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest);
772
773void hubp1_init(struct hubp *hubp);
774void hubp1_read_state_common(struct hubp *hubp);
775
776#endif