1/*
  2 * Copyright 2015 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 * Authors: AMD
 23 *
 24 */
 25
 26#include <drm/drm_crtc.h>
 27#include <drm/drm_vblank.h>
 28
 29#include "amdgpu.h"
 30#include "amdgpu_dm.h"
 31#include "dc.h"
 32
 33static const char *const pipe_crc_sources[] = {
 34	"none",
 35	"crtc",
 36	"crtc dither",
 37	"dprx",
 38	"dprx dither",
 39	"auto",
 40};
 41
 42static enum amdgpu_dm_pipe_crc_source dm_parse_crc_source(const char *source)
 43{
 44	if (!source || !strcmp(source, "none"))
 45		return AMDGPU_DM_PIPE_CRC_SOURCE_NONE;
 46	if (!strcmp(source, "auto") || !strcmp(source, "crtc"))
 47		return AMDGPU_DM_PIPE_CRC_SOURCE_CRTC;
 48	if (!strcmp(source, "dprx"))
 49		return AMDGPU_DM_PIPE_CRC_SOURCE_DPRX;
 50	if (!strcmp(source, "crtc dither"))
 51		return AMDGPU_DM_PIPE_CRC_SOURCE_CRTC_DITHER;
 52	if (!strcmp(source, "dprx dither"))
 53		return AMDGPU_DM_PIPE_CRC_SOURCE_DPRX_DITHER;
 54
 55	return AMDGPU_DM_PIPE_CRC_SOURCE_INVALID;
 56}
 57
 58static bool dm_is_crc_source_crtc(enum amdgpu_dm_pipe_crc_source src)
 59{
 60	return (src == AMDGPU_DM_PIPE_CRC_SOURCE_CRTC) ||
 61	       (src == AMDGPU_DM_PIPE_CRC_SOURCE_CRTC_DITHER);
 62}
 63
 64static bool dm_is_crc_source_dprx(enum amdgpu_dm_pipe_crc_source src)
 65{
 66	return (src == AMDGPU_DM_PIPE_CRC_SOURCE_DPRX) ||
 67	       (src == AMDGPU_DM_PIPE_CRC_SOURCE_DPRX_DITHER);
 68}
 69
 70static bool dm_need_crc_dither(enum amdgpu_dm_pipe_crc_source src)
 71{
 72	return (src == AMDGPU_DM_PIPE_CRC_SOURCE_CRTC_DITHER) ||
 73	       (src == AMDGPU_DM_PIPE_CRC_SOURCE_DPRX_DITHER) ||
 74	       (src == AMDGPU_DM_PIPE_CRC_SOURCE_NONE);
 75}
 76
 77const char *const *amdgpu_dm_crtc_get_crc_sources(struct drm_crtc *crtc,
 78						  size_t *count)
 79{
 80	*count = ARRAY_SIZE(pipe_crc_sources);
 81	return pipe_crc_sources;
 82}
 83
 84int
 85amdgpu_dm_crtc_verify_crc_source(struct drm_crtc *crtc, const char *src_name,
 86				 size_t *values_cnt)
 87{
 88	enum amdgpu_dm_pipe_crc_source source = dm_parse_crc_source(src_name);
 89
 90	if (source < 0) {
 91		DRM_DEBUG_DRIVER("Unknown CRC source %s for CRTC%d\n",
 92				 src_name, crtc->index);
 93		return -EINVAL;
 94	}
 95
 96	*values_cnt = 3;
 97	return 0;
 98}
 99
100int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc,
101					struct dm_crtc_state *dm_crtc_state,
102					enum amdgpu_dm_pipe_crc_source source)
103{
104	struct amdgpu_device *adev = crtc->dev->dev_private;
105	struct dc_stream_state *stream_state = dm_crtc_state->stream;
106	bool enable = amdgpu_dm_is_valid_crc_source(source);
107	int ret = 0;
108
109	/* Configuration will be deferred to stream enable. */
110	if (!stream_state)
111		return 0;
112
113	mutex_lock(&adev->dm.dc_lock);
114
115	/* Enable CRTC CRC generation if necessary. */
116	if (dm_is_crc_source_crtc(source)) {
117		if (!dc_stream_configure_crc(stream_state->ctx->dc,
118					     stream_state, enable, enable)) {
119			ret = -EINVAL;
120			goto unlock;
121		}
122	}
123
124	/* Configure dithering */
125	if (!dm_need_crc_dither(source)) {
126		dc_stream_set_dither_option(stream_state, DITHER_OPTION_TRUN8);
127		dc_stream_set_dyn_expansion(stream_state->ctx->dc, stream_state,
128					    DYN_EXPANSION_DISABLE);
129	} else {
130		dc_stream_set_dither_option(stream_state,
131					    DITHER_OPTION_DEFAULT);
132		dc_stream_set_dyn_expansion(stream_state->ctx->dc, stream_state,
133					    DYN_EXPANSION_AUTO);
134	}
135
136unlock:
137	mutex_unlock(&adev->dm.dc_lock);
138
139	return ret;
140}
141
142int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name)
143{
144	enum amdgpu_dm_pipe_crc_source source = dm_parse_crc_source(src_name);
145	struct drm_crtc_commit *commit;
146	struct dm_crtc_state *crtc_state;
147	struct drm_dp_aux *aux = NULL;
148	bool enable = false;
149	bool enabled = false;
150	int ret = 0;
151
152	if (source < 0) {
153		DRM_DEBUG_DRIVER("Unknown CRC source %s for CRTC%d\n",
154				 src_name, crtc->index);
155		return -EINVAL;
156	}
157
158	ret = drm_modeset_lock(&crtc->mutex, NULL);
159	if (ret)
160		return ret;
161
162	spin_lock(&crtc->commit_lock);
163	commit = list_first_entry_or_null(&crtc->commit_list,
164					  struct drm_crtc_commit, commit_entry);
165	if (commit)
166		drm_crtc_commit_get(commit);
167	spin_unlock(&crtc->commit_lock);
168
169	if (commit) {
170		/*
171		 * Need to wait for all outstanding programming to complete
172		 * in commit tail since it can modify CRC related fields and
173		 * hardware state. Since we're holding the CRTC lock we're
174		 * guaranteed that no other commit work can be queued off
175		 * before we modify the state below.
176		 */
177		ret = wait_for_completion_interruptible_timeout(
178			&commit->hw_done, 10 * HZ);
179		if (ret)
180			goto cleanup;
181	}
182
183	enable = amdgpu_dm_is_valid_crc_source(source);
184	crtc_state = to_dm_crtc_state(crtc->state);
185
186	/*
187	 * USER REQ SRC | CURRENT SRC | BEHAVIOR
188	 * -----------------------------
189	 * None         | None        | Do nothing
190	 * None         | CRTC        | Disable CRTC CRC, set default to dither
191	 * None         | DPRX        | Disable DPRX CRC, need 'aux', set default to dither
192	 * None         | CRTC DITHER | Disable CRTC CRC
193	 * None         | DPRX DITHER | Disable DPRX CRC, need 'aux'
194	 * CRTC         | XXXX        | Enable CRTC CRC, no dither
195	 * DPRX         | XXXX        | Enable DPRX CRC, need 'aux', no dither
196	 * CRTC DITHER  | XXXX        | Enable CRTC CRC, set dither
197	 * DPRX DITHER  | XXXX        | Enable DPRX CRC, need 'aux', set dither
198	 */
199	if (dm_is_crc_source_dprx(source) ||
200	    (source == AMDGPU_DM_PIPE_CRC_SOURCE_NONE &&
201	     dm_is_crc_source_dprx(crtc_state->crc_src))) {
202		struct amdgpu_dm_connector *aconn = NULL;
203		struct drm_connector *connector;
204		struct drm_connector_list_iter conn_iter;
205
206		drm_connector_list_iter_begin(crtc->dev, &conn_iter);
207		drm_for_each_connector_iter(connector, &conn_iter) {
208			if (!connector->state || connector->state->crtc != crtc)
209				continue;
210
211			aconn = to_amdgpu_dm_connector(connector);
212			break;
213		}
214		drm_connector_list_iter_end(&conn_iter);
215
216		if (!aconn) {
217			DRM_DEBUG_DRIVER("No amd connector matching CRTC-%d\n", crtc->index);
218			ret = -EINVAL;
219			goto cleanup;
220		}
221
222		aux = &aconn->dm_dp_aux.aux;
223
224		if (!aux) {
225			DRM_DEBUG_DRIVER("No dp aux for amd connector\n");
226			ret = -EINVAL;
227			goto cleanup;
228		}
229	}
230
231	if (amdgpu_dm_crtc_configure_crc_source(crtc, crtc_state, source)) {
232		ret = -EINVAL;
233		goto cleanup;
234	}
235
236	/*
237	 * Reading the CRC requires the vblank interrupt handler to be
238	 * enabled. Keep a reference until CRC capture stops.
239	 */
240	enabled = amdgpu_dm_is_valid_crc_source(crtc_state->crc_src);
241	if (!enabled && enable) {
242		ret = drm_crtc_vblank_get(crtc);
243		if (ret)
244			goto cleanup;
245
246		if (dm_is_crc_source_dprx(source)) {
247			if (drm_dp_start_crc(aux, crtc)) {
248				DRM_DEBUG_DRIVER("dp start crc failed\n");
249				ret = -EINVAL;
250				goto cleanup;
251			}
252		}
253	} else if (enabled && !enable) {
254		drm_crtc_vblank_put(crtc);
255		if (dm_is_crc_source_dprx(source)) {
256			if (drm_dp_stop_crc(aux)) {
257				DRM_DEBUG_DRIVER("dp stop crc failed\n");
258				ret = -EINVAL;
259				goto cleanup;
260			}
261		}
262	}
263
264	crtc_state->crc_src = source;
265
266	/* Reset crc_skipped on dm state */
267	crtc_state->crc_skip_count = 0;
268
269cleanup:
270	if (commit)
271		drm_crtc_commit_put(commit);
272
273	drm_modeset_unlock(&crtc->mutex);
274
275	return ret;
276}
277
278/**
279 * amdgpu_dm_crtc_handle_crc_irq: Report to DRM the CRC on given CRTC.
280 * @crtc: DRM CRTC object.
281 *
282 * This function should be called at the end of a vblank, when the fb has been
283 * fully processed through the pipe.
284 */
285void amdgpu_dm_crtc_handle_crc_irq(struct drm_crtc *crtc)
286{
287	struct dm_crtc_state *crtc_state;
288	struct dc_stream_state *stream_state;
289	uint32_t crcs[3];
290
291	if (crtc == NULL)
292		return;
293
294	crtc_state = to_dm_crtc_state(crtc->state);
295	stream_state = crtc_state->stream;
296
297	/* Early return if CRC capture is not enabled. */
298	if (!amdgpu_dm_is_valid_crc_source(crtc_state->crc_src))
299		return;
300
301	/*
302	 * Since flipping and crc enablement happen asynchronously, we - more
303	 * often than not - will be returning an 'uncooked' crc on first frame.
304	 * Probably because hw isn't ready yet. For added security, skip the
305	 * first two CRC values.
306	 */
307	if (crtc_state->crc_skip_count < 2) {
308		crtc_state->crc_skip_count += 1;
309		return;
310	}
311
312	if (dm_is_crc_source_crtc(crtc_state->crc_src)) {
313		if (!dc_stream_get_crc(stream_state->ctx->dc, stream_state,
314				       &crcs[0], &crcs[1], &crcs[2]))
315			return;
316
317		drm_crtc_add_crc_entry(crtc, true,
318				       drm_crtc_accurate_vblank_count(crtc), crcs);
319	}
320}