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1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <linux/firmware.h>
25#include <linux/module.h>
26#include <linux/pci.h>
27
28#include <drm/drm_cache.h>
29#include "amdgpu.h"
30#include "cikd.h"
31#include "cik.h"
32#include "gmc_v7_0.h"
33#include "amdgpu_ucode.h"
34#include "amdgpu_amdkfd.h"
35#include "amdgpu_gem.h"
36
37#include "bif/bif_4_1_d.h"
38#include "bif/bif_4_1_sh_mask.h"
39
40#include "gmc/gmc_7_1_d.h"
41#include "gmc/gmc_7_1_sh_mask.h"
42
43#include "oss/oss_2_0_d.h"
44#include "oss/oss_2_0_sh_mask.h"
45
46#include "dce/dce_8_0_d.h"
47#include "dce/dce_8_0_sh_mask.h"
48
49#include "amdgpu_atombios.h"
50
51#include "ivsrcid/ivsrcid_vislands30.h"
52
53static void gmc_v7_0_set_gmc_funcs(struct amdgpu_device *adev);
54static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev);
55static int gmc_v7_0_wait_for_idle(void *handle);
56
57MODULE_FIRMWARE("amdgpu/bonaire_mc.bin");
58MODULE_FIRMWARE("amdgpu/hawaii_mc.bin");
59MODULE_FIRMWARE("amdgpu/topaz_mc.bin");
60
61static const u32 golden_settings_iceland_a11[] =
62{
63 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
64 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
65 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
66 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
67};
68
69static const u32 iceland_mgcg_cgcg_init[] =
70{
71 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
72};
73
74static void gmc_v7_0_init_golden_registers(struct amdgpu_device *adev)
75{
76 switch (adev->asic_type) {
77 case CHIP_TOPAZ:
78 amdgpu_device_program_register_sequence(adev,
79 iceland_mgcg_cgcg_init,
80 ARRAY_SIZE(iceland_mgcg_cgcg_init));
81 amdgpu_device_program_register_sequence(adev,
82 golden_settings_iceland_a11,
83 ARRAY_SIZE(golden_settings_iceland_a11));
84 break;
85 default:
86 break;
87 }
88}
89
90static void gmc_v7_0_mc_stop(struct amdgpu_device *adev)
91{
92 u32 blackout;
93
94 gmc_v7_0_wait_for_idle((void *)adev);
95
96 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
97 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
98 /* Block CPU access */
99 WREG32(mmBIF_FB_EN, 0);
100 /* blackout the MC */
101 blackout = REG_SET_FIELD(blackout,
102 MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
103 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1);
104 }
105 /* wait for the MC to settle */
106 udelay(100);
107}
108
109static void gmc_v7_0_mc_resume(struct amdgpu_device *adev)
110{
111 u32 tmp;
112
113 /* unblackout the MC */
114 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
115 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
116 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
117 /* allow CPU access */
118 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
119 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
120 WREG32(mmBIF_FB_EN, tmp);
121}
122
123/**
124 * gmc_v7_0_init_microcode - load ucode images from disk
125 *
126 * @adev: amdgpu_device pointer
127 *
128 * Use the firmware interface to load the ucode images into
129 * the driver (not loaded into hw).
130 * Returns 0 on success, error on failure.
131 */
132static int gmc_v7_0_init_microcode(struct amdgpu_device *adev)
133{
134 const char *chip_name;
135 char fw_name[30];
136 int err;
137
138 DRM_DEBUG("\n");
139
140 switch (adev->asic_type) {
141 case CHIP_BONAIRE:
142 chip_name = "bonaire";
143 break;
144 case CHIP_HAWAII:
145 chip_name = "hawaii";
146 break;
147 case CHIP_TOPAZ:
148 chip_name = "topaz";
149 break;
150 case CHIP_KAVERI:
151 case CHIP_KABINI:
152 case CHIP_MULLINS:
153 return 0;
154 default: BUG();
155 }
156
157 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name);
158
159 err = request_firmware(&adev->gmc.fw, fw_name, adev->dev);
160 if (err)
161 goto out;
162 err = amdgpu_ucode_validate(adev->gmc.fw);
163
164out:
165 if (err) {
166 pr_err("cik_mc: Failed to load firmware \"%s\"\n", fw_name);
167 release_firmware(adev->gmc.fw);
168 adev->gmc.fw = NULL;
169 }
170 return err;
171}
172
173/**
174 * gmc_v7_0_mc_load_microcode - load MC ucode into the hw
175 *
176 * @adev: amdgpu_device pointer
177 *
178 * Load the GDDR MC ucode into the hw (CIK).
179 * Returns 0 on success, error on failure.
180 */
181static int gmc_v7_0_mc_load_microcode(struct amdgpu_device *adev)
182{
183 const struct mc_firmware_header_v1_0 *hdr;
184 const __le32 *fw_data = NULL;
185 const __le32 *io_mc_regs = NULL;
186 u32 running;
187 int i, ucode_size, regs_size;
188
189 if (!adev->gmc.fw)
190 return -EINVAL;
191
192 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data;
193 amdgpu_ucode_print_mc_hdr(&hdr->header);
194
195 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version);
196 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
197 io_mc_regs = (const __le32 *)
198 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
199 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
200 fw_data = (const __le32 *)
201 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
202
203 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN);
204
205 if (running == 0) {
206 /* reset the engine and set to writable */
207 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
208 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
209
210 /* load mc io regs */
211 for (i = 0; i < regs_size; i++) {
212 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
213 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
214 }
215 /* load the MC ucode */
216 for (i = 0; i < ucode_size; i++)
217 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
218
219 /* put the engine back into the active state */
220 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
221 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
222 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
223
224 /* wait for training to complete */
225 for (i = 0; i < adev->usec_timeout; i++) {
226 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
227 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0))
228 break;
229 udelay(1);
230 }
231 for (i = 0; i < adev->usec_timeout; i++) {
232 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
233 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1))
234 break;
235 udelay(1);
236 }
237 }
238
239 return 0;
240}
241
242static void gmc_v7_0_vram_gtt_location(struct amdgpu_device *adev,
243 struct amdgpu_gmc *mc)
244{
245 u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;
246 base <<= 24;
247
248 amdgpu_gmc_vram_location(adev, mc, base);
249 amdgpu_gmc_gart_location(adev, mc);
250}
251
252/**
253 * gmc_v7_0_mc_program - program the GPU memory controller
254 *
255 * @adev: amdgpu_device pointer
256 *
257 * Set the location of vram, gart, and AGP in the GPU's
258 * physical address space (CIK).
259 */
260static void gmc_v7_0_mc_program(struct amdgpu_device *adev)
261{
262 u32 tmp;
263 int i, j;
264
265 /* Initialize HDP */
266 for (i = 0, j = 0; i < 32; i++, j += 0x6) {
267 WREG32((0xb05 + j), 0x00000000);
268 WREG32((0xb06 + j), 0x00000000);
269 WREG32((0xb07 + j), 0x00000000);
270 WREG32((0xb08 + j), 0x00000000);
271 WREG32((0xb09 + j), 0x00000000);
272 }
273 WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
274
275 if (gmc_v7_0_wait_for_idle((void *)adev)) {
276 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
277 }
278 if (adev->mode_info.num_crtc) {
279 /* Lockout access through VGA aperture*/
280 tmp = RREG32(mmVGA_HDP_CONTROL);
281 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
282 WREG32(mmVGA_HDP_CONTROL, tmp);
283
284 /* disable VGA render */
285 tmp = RREG32(mmVGA_RENDER_CONTROL);
286 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
287 WREG32(mmVGA_RENDER_CONTROL, tmp);
288 }
289 /* Update configuration */
290 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
291 adev->gmc.vram_start >> 12);
292 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
293 adev->gmc.vram_end >> 12);
294 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
295 adev->vram_scratch.gpu_addr >> 12);
296 WREG32(mmMC_VM_AGP_BASE, 0);
297 WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
298 WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
299 if (gmc_v7_0_wait_for_idle((void *)adev)) {
300 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
301 }
302
303 WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
304
305 tmp = RREG32(mmHDP_MISC_CNTL);
306 tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0);
307 WREG32(mmHDP_MISC_CNTL, tmp);
308
309 tmp = RREG32(mmHDP_HOST_PATH_CNTL);
310 WREG32(mmHDP_HOST_PATH_CNTL, tmp);
311}
312
313/**
314 * gmc_v7_0_mc_init - initialize the memory controller driver params
315 *
316 * @adev: amdgpu_device pointer
317 *
318 * Look up the amount of vram, vram width, and decide how to place
319 * vram and gart within the GPU's physical address space (CIK).
320 * Returns 0 for success.
321 */
322static int gmc_v7_0_mc_init(struct amdgpu_device *adev)
323{
324 int r;
325
326 adev->gmc.vram_width = amdgpu_atombios_get_vram_width(adev);
327 if (!adev->gmc.vram_width) {
328 u32 tmp;
329 int chansize, numchan;
330
331 /* Get VRAM informations */
332 tmp = RREG32(mmMC_ARB_RAMCFG);
333 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) {
334 chansize = 64;
335 } else {
336 chansize = 32;
337 }
338 tmp = RREG32(mmMC_SHARED_CHMAP);
339 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
340 case 0:
341 default:
342 numchan = 1;
343 break;
344 case 1:
345 numchan = 2;
346 break;
347 case 2:
348 numchan = 4;
349 break;
350 case 3:
351 numchan = 8;
352 break;
353 case 4:
354 numchan = 3;
355 break;
356 case 5:
357 numchan = 6;
358 break;
359 case 6:
360 numchan = 10;
361 break;
362 case 7:
363 numchan = 12;
364 break;
365 case 8:
366 numchan = 16;
367 break;
368 }
369 adev->gmc.vram_width = numchan * chansize;
370 }
371 /* size in MB on si */
372 adev->gmc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
373 adev->gmc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
374
375 if (!(adev->flags & AMD_IS_APU)) {
376 r = amdgpu_device_resize_fb_bar(adev);
377 if (r)
378 return r;
379 }
380 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
381 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
382
383#ifdef CONFIG_X86_64
384 if (adev->flags & AMD_IS_APU &&
385 adev->gmc.real_vram_size > adev->gmc.aper_size) {
386 adev->gmc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22;
387 adev->gmc.aper_size = adev->gmc.real_vram_size;
388 }
389#endif
390
391 /* In case the PCI BAR is larger than the actual amount of vram */
392 adev->gmc.visible_vram_size = adev->gmc.aper_size;
393 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)
394 adev->gmc.visible_vram_size = adev->gmc.real_vram_size;
395
396 /* set the gart size */
397 if (amdgpu_gart_size == -1) {
398 switch (adev->asic_type) {
399 case CHIP_TOPAZ: /* no MM engines */
400 default:
401 adev->gmc.gart_size = 256ULL << 20;
402 break;
403#ifdef CONFIG_DRM_AMDGPU_CIK
404 case CHIP_BONAIRE: /* UVD, VCE do not support GPUVM */
405 case CHIP_HAWAII: /* UVD, VCE do not support GPUVM */
406 case CHIP_KAVERI: /* UVD, VCE do not support GPUVM */
407 case CHIP_KABINI: /* UVD, VCE do not support GPUVM */
408 case CHIP_MULLINS: /* UVD, VCE do not support GPUVM */
409 adev->gmc.gart_size = 1024ULL << 20;
410 break;
411#endif
412 }
413 } else {
414 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
415 }
416
417 gmc_v7_0_vram_gtt_location(adev, &adev->gmc);
418
419 return 0;
420}
421
422/**
423 * gmc_v7_0_flush_gpu_tlb_pasid - tlb flush via pasid
424 *
425 * @adev: amdgpu_device pointer
426 * @pasid: pasid to be flush
427 *
428 * Flush the TLB for the requested pasid.
429 */
430static int gmc_v7_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
431 uint16_t pasid, uint32_t flush_type,
432 bool all_hub)
433{
434 int vmid;
435 unsigned int tmp;
436
437 if (adev->in_gpu_reset)
438 return -EIO;
439
440 for (vmid = 1; vmid < 16; vmid++) {
441
442 tmp = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
443 if ((tmp & ATC_VMID0_PASID_MAPPING__VALID_MASK) &&
444 (tmp & ATC_VMID0_PASID_MAPPING__PASID_MASK) == pasid) {
445 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
446 RREG32(mmVM_INVALIDATE_RESPONSE);
447 break;
448 }
449 }
450
451 return 0;
452}
453
454/*
455 * GART
456 * VMID 0 is the physical GPU addresses as used by the kernel.
457 * VMIDs 1-15 are used for userspace clients and are handled
458 * by the amdgpu vm/hsa code.
459 */
460
461/**
462 * gmc_v7_0_flush_gpu_tlb - gart tlb flush callback
463 *
464 * @adev: amdgpu_device pointer
465 * @vmid: vm instance to flush
466 *
467 * Flush the TLB for the requested page table (CIK).
468 */
469static void gmc_v7_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
470 uint32_t vmhub, uint32_t flush_type)
471{
472 /* bits 0-15 are the VM contexts0-15 */
473 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
474}
475
476static uint64_t gmc_v7_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
477 unsigned vmid, uint64_t pd_addr)
478{
479 uint32_t reg;
480
481 if (vmid < 8)
482 reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid;
483 else
484 reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8;
485 amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12);
486
487 /* bits 0-15 are the VM contexts0-15 */
488 amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid);
489
490 return pd_addr;
491}
492
493static void gmc_v7_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid,
494 unsigned pasid)
495{
496 amdgpu_ring_emit_wreg(ring, mmIH_VMID_0_LUT + vmid, pasid);
497}
498
499static void gmc_v7_0_get_vm_pde(struct amdgpu_device *adev, int level,
500 uint64_t *addr, uint64_t *flags)
501{
502 BUG_ON(*addr & 0xFFFFFF0000000FFFULL);
503}
504
505static void gmc_v7_0_get_vm_pte(struct amdgpu_device *adev,
506 struct amdgpu_bo_va_mapping *mapping,
507 uint64_t *flags)
508{
509 *flags &= ~AMDGPU_PTE_EXECUTABLE;
510 *flags &= ~AMDGPU_PTE_PRT;
511}
512
513/**
514 * gmc_v8_0_set_fault_enable_default - update VM fault handling
515 *
516 * @adev: amdgpu_device pointer
517 * @value: true redirects VM faults to the default page
518 */
519static void gmc_v7_0_set_fault_enable_default(struct amdgpu_device *adev,
520 bool value)
521{
522 u32 tmp;
523
524 tmp = RREG32(mmVM_CONTEXT1_CNTL);
525 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
526 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
527 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
528 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
529 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
530 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
531 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
532 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
533 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
534 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
535 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
536 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
537 WREG32(mmVM_CONTEXT1_CNTL, tmp);
538}
539
540/**
541 * gmc_v7_0_set_prt - set PRT VM fault
542 *
543 * @adev: amdgpu_device pointer
544 * @enable: enable/disable VM fault handling for PRT
545 */
546static void gmc_v7_0_set_prt(struct amdgpu_device *adev, bool enable)
547{
548 uint32_t tmp;
549
550 if (enable && !adev->gmc.prt_warning) {
551 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n");
552 adev->gmc.prt_warning = true;
553 }
554
555 tmp = RREG32(mmVM_PRT_CNTL);
556 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
557 CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
558 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
559 CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
560 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
561 TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
562 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
563 TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
564 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
565 L2_CACHE_STORE_INVALID_ENTRIES, enable);
566 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
567 L1_TLB_STORE_INVALID_ENTRIES, enable);
568 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
569 MASK_PDE0_FAULT, enable);
570 WREG32(mmVM_PRT_CNTL, tmp);
571
572 if (enable) {
573 uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT;
574 uint32_t high = adev->vm_manager.max_pfn -
575 (AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT);
576
577 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);
578 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);
579 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);
580 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);
581 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);
582 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);
583 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);
584 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);
585 } else {
586 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff);
587 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff);
588 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff);
589 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff);
590 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);
591 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);
592 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);
593 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);
594 }
595}
596
597/**
598 * gmc_v7_0_gart_enable - gart enable
599 *
600 * @adev: amdgpu_device pointer
601 *
602 * This sets up the TLBs, programs the page tables for VMID0,
603 * sets up the hw for VMIDs 1-15 which are allocated on
604 * demand, and sets up the global locations for the LDS, GDS,
605 * and GPUVM for FSA64 clients (CIK).
606 * Returns 0 for success, errors for failure.
607 */
608static int gmc_v7_0_gart_enable(struct amdgpu_device *adev)
609{
610 uint64_t table_addr;
611 int r, i;
612 u32 tmp, field;
613
614 if (adev->gart.bo == NULL) {
615 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
616 return -EINVAL;
617 }
618 r = amdgpu_gart_table_vram_pin(adev);
619 if (r)
620 return r;
621
622 table_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
623
624 /* Setup TLB control */
625 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
626 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
627 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1);
628 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
629 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1);
630 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
631 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
632 /* Setup L2 cache */
633 tmp = RREG32(mmVM_L2_CNTL);
634 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
635 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
636 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1);
637 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1);
638 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7);
639 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
640 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
641 WREG32(mmVM_L2_CNTL, tmp);
642 tmp = REG_SET_FIELD(0, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
643 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
644 WREG32(mmVM_L2_CNTL2, tmp);
645
646 field = adev->vm_manager.fragment_size;
647 tmp = RREG32(mmVM_L2_CNTL3);
648 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1);
649 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field);
650 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field);
651 WREG32(mmVM_L2_CNTL3, tmp);
652 /* setup context0 */
653 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12);
654 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12);
655 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, table_addr >> 12);
656 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
657 (u32)(adev->dummy_page_addr >> 12));
658 WREG32(mmVM_CONTEXT0_CNTL2, 0);
659 tmp = RREG32(mmVM_CONTEXT0_CNTL);
660 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
661 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
662 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
663 WREG32(mmVM_CONTEXT0_CNTL, tmp);
664
665 WREG32(0x575, 0);
666 WREG32(0x576, 0);
667 WREG32(0x577, 0);
668
669 /* empty context1-15 */
670 /* FIXME start with 4G, once using 2 level pt switch to full
671 * vm size space
672 */
673 /* set vm size, must be a multiple of 4 */
674 WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
675 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
676 for (i = 1; i < 16; i++) {
677 if (i < 8)
678 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
679 table_addr >> 12);
680 else
681 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
682 table_addr >> 12);
683 }
684
685 /* enable context1-15 */
686 WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
687 (u32)(adev->dummy_page_addr >> 12));
688 WREG32(mmVM_CONTEXT1_CNTL2, 4);
689 tmp = RREG32(mmVM_CONTEXT1_CNTL);
690 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
691 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);
692 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE,
693 adev->vm_manager.block_size - 9);
694 WREG32(mmVM_CONTEXT1_CNTL, tmp);
695 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
696 gmc_v7_0_set_fault_enable_default(adev, false);
697 else
698 gmc_v7_0_set_fault_enable_default(adev, true);
699
700 if (adev->asic_type == CHIP_KAVERI) {
701 tmp = RREG32(mmCHUB_CONTROL);
702 tmp &= ~BYPASS_VM;
703 WREG32(mmCHUB_CONTROL, tmp);
704 }
705
706 gmc_v7_0_flush_gpu_tlb(adev, 0, 0, 0);
707 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
708 (unsigned)(adev->gmc.gart_size >> 20),
709 (unsigned long long)table_addr);
710 adev->gart.ready = true;
711 return 0;
712}
713
714static int gmc_v7_0_gart_init(struct amdgpu_device *adev)
715{
716 int r;
717
718 if (adev->gart.bo) {
719 WARN(1, "R600 PCIE GART already initialized\n");
720 return 0;
721 }
722 /* Initialize common gart structure */
723 r = amdgpu_gart_init(adev);
724 if (r)
725 return r;
726 adev->gart.table_size = adev->gart.num_gpu_pages * 8;
727 adev->gart.gart_pte_flags = 0;
728 return amdgpu_gart_table_vram_alloc(adev);
729}
730
731/**
732 * gmc_v7_0_gart_disable - gart disable
733 *
734 * @adev: amdgpu_device pointer
735 *
736 * This disables all VM page table (CIK).
737 */
738static void gmc_v7_0_gart_disable(struct amdgpu_device *adev)
739{
740 u32 tmp;
741
742 /* Disable all tables */
743 WREG32(mmVM_CONTEXT0_CNTL, 0);
744 WREG32(mmVM_CONTEXT1_CNTL, 0);
745 /* Setup TLB control */
746 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
747 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
748 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0);
749 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0);
750 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
751 /* Setup L2 cache */
752 tmp = RREG32(mmVM_L2_CNTL);
753 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
754 WREG32(mmVM_L2_CNTL, tmp);
755 WREG32(mmVM_L2_CNTL2, 0);
756 amdgpu_gart_table_vram_unpin(adev);
757}
758
759/**
760 * gmc_v7_0_vm_decode_fault - print human readable fault info
761 *
762 * @adev: amdgpu_device pointer
763 * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
764 * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
765 * @mc_client: VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT register value
766 *
767 * Print human readable fault information (CIK).
768 */
769static void gmc_v7_0_vm_decode_fault(struct amdgpu_device *adev, u32 status,
770 u32 addr, u32 mc_client, unsigned pasid)
771{
772 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
773 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
774 PROTECTIONS);
775 char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
776 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
777 u32 mc_id;
778
779 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
780 MEMORY_CLIENT_ID);
781
782 dev_err(adev->dev, "VM fault (0x%02x, vmid %d, pasid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
783 protections, vmid, pasid, addr,
784 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
785 MEMORY_CLIENT_RW) ?
786 "write" : "read", block, mc_client, mc_id);
787}
788
789
790static const u32 mc_cg_registers[] = {
791 mmMC_HUB_MISC_HUB_CG,
792 mmMC_HUB_MISC_SIP_CG,
793 mmMC_HUB_MISC_VM_CG,
794 mmMC_XPB_CLK_GAT,
795 mmATC_MISC_CG,
796 mmMC_CITF_MISC_WR_CG,
797 mmMC_CITF_MISC_RD_CG,
798 mmMC_CITF_MISC_VM_CG,
799 mmVM_L2_CG,
800};
801
802static const u32 mc_cg_ls_en[] = {
803 MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK,
804 MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK,
805 MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK,
806 MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK,
807 ATC_MISC_CG__MEM_LS_ENABLE_MASK,
808 MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK,
809 MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK,
810 MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK,
811 VM_L2_CG__MEM_LS_ENABLE_MASK,
812};
813
814static const u32 mc_cg_en[] = {
815 MC_HUB_MISC_HUB_CG__ENABLE_MASK,
816 MC_HUB_MISC_SIP_CG__ENABLE_MASK,
817 MC_HUB_MISC_VM_CG__ENABLE_MASK,
818 MC_XPB_CLK_GAT__ENABLE_MASK,
819 ATC_MISC_CG__ENABLE_MASK,
820 MC_CITF_MISC_WR_CG__ENABLE_MASK,
821 MC_CITF_MISC_RD_CG__ENABLE_MASK,
822 MC_CITF_MISC_VM_CG__ENABLE_MASK,
823 VM_L2_CG__ENABLE_MASK,
824};
825
826static void gmc_v7_0_enable_mc_ls(struct amdgpu_device *adev,
827 bool enable)
828{
829 int i;
830 u32 orig, data;
831
832 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
833 orig = data = RREG32(mc_cg_registers[i]);
834 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS))
835 data |= mc_cg_ls_en[i];
836 else
837 data &= ~mc_cg_ls_en[i];
838 if (data != orig)
839 WREG32(mc_cg_registers[i], data);
840 }
841}
842
843static void gmc_v7_0_enable_mc_mgcg(struct amdgpu_device *adev,
844 bool enable)
845{
846 int i;
847 u32 orig, data;
848
849 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
850 orig = data = RREG32(mc_cg_registers[i]);
851 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG))
852 data |= mc_cg_en[i];
853 else
854 data &= ~mc_cg_en[i];
855 if (data != orig)
856 WREG32(mc_cg_registers[i], data);
857 }
858}
859
860static void gmc_v7_0_enable_bif_mgls(struct amdgpu_device *adev,
861 bool enable)
862{
863 u32 orig, data;
864
865 orig = data = RREG32_PCIE(ixPCIE_CNTL2);
866
867 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) {
868 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 1);
869 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 1);
870 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 1);
871 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 1);
872 } else {
873 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 0);
874 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 0);
875 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 0);
876 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 0);
877 }
878
879 if (orig != data)
880 WREG32_PCIE(ixPCIE_CNTL2, data);
881}
882
883static void gmc_v7_0_enable_hdp_mgcg(struct amdgpu_device *adev,
884 bool enable)
885{
886 u32 orig, data;
887
888 orig = data = RREG32(mmHDP_HOST_PATH_CNTL);
889
890 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG))
891 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0);
892 else
893 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1);
894
895 if (orig != data)
896 WREG32(mmHDP_HOST_PATH_CNTL, data);
897}
898
899static void gmc_v7_0_enable_hdp_ls(struct amdgpu_device *adev,
900 bool enable)
901{
902 u32 orig, data;
903
904 orig = data = RREG32(mmHDP_MEM_POWER_LS);
905
906 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
907 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1);
908 else
909 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0);
910
911 if (orig != data)
912 WREG32(mmHDP_MEM_POWER_LS, data);
913}
914
915static int gmc_v7_0_convert_vram_type(int mc_seq_vram_type)
916{
917 switch (mc_seq_vram_type) {
918 case MC_SEQ_MISC0__MT__GDDR1:
919 return AMDGPU_VRAM_TYPE_GDDR1;
920 case MC_SEQ_MISC0__MT__DDR2:
921 return AMDGPU_VRAM_TYPE_DDR2;
922 case MC_SEQ_MISC0__MT__GDDR3:
923 return AMDGPU_VRAM_TYPE_GDDR3;
924 case MC_SEQ_MISC0__MT__GDDR4:
925 return AMDGPU_VRAM_TYPE_GDDR4;
926 case MC_SEQ_MISC0__MT__GDDR5:
927 return AMDGPU_VRAM_TYPE_GDDR5;
928 case MC_SEQ_MISC0__MT__HBM:
929 return AMDGPU_VRAM_TYPE_HBM;
930 case MC_SEQ_MISC0__MT__DDR3:
931 return AMDGPU_VRAM_TYPE_DDR3;
932 default:
933 return AMDGPU_VRAM_TYPE_UNKNOWN;
934 }
935}
936
937static int gmc_v7_0_early_init(void *handle)
938{
939 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
940
941 gmc_v7_0_set_gmc_funcs(adev);
942 gmc_v7_0_set_irq_funcs(adev);
943
944 adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
945 adev->gmc.shared_aperture_end =
946 adev->gmc.shared_aperture_start + (4ULL << 30) - 1;
947 adev->gmc.private_aperture_start =
948 adev->gmc.shared_aperture_end + 1;
949 adev->gmc.private_aperture_end =
950 adev->gmc.private_aperture_start + (4ULL << 30) - 1;
951
952 return 0;
953}
954
955static int gmc_v7_0_late_init(void *handle)
956{
957 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
958
959 amdgpu_bo_late_init(adev);
960
961 if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)
962 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
963 else
964 return 0;
965}
966
967static unsigned gmc_v7_0_get_vbios_fb_size(struct amdgpu_device *adev)
968{
969 u32 d1vga_control = RREG32(mmD1VGA_CONTROL);
970 unsigned size;
971
972 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
973 size = 9 * 1024 * 1024; /* reserve 8MB for vga emulator and 1 MB for FB */
974 } else {
975 u32 viewport = RREG32(mmVIEWPORT_SIZE);
976 size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) *
977 REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) *
978 4);
979 }
980 /* return 0 if the pre-OS buffer uses up most of vram */
981 if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024))
982 return 0;
983 return size;
984}
985
986static int gmc_v7_0_sw_init(void *handle)
987{
988 int r;
989 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
990
991 adev->num_vmhubs = 1;
992
993 if (adev->flags & AMD_IS_APU) {
994 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
995 } else {
996 u32 tmp = RREG32(mmMC_SEQ_MISC0);
997 tmp &= MC_SEQ_MISC0__MT__MASK;
998 adev->gmc.vram_type = gmc_v7_0_convert_vram_type(tmp);
999 }
1000
1001 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_PAGE_INV_FAULT, &adev->gmc.vm_fault);
1002 if (r)
1003 return r;
1004
1005 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_MEM_PROT_FAULT, &adev->gmc.vm_fault);
1006 if (r)
1007 return r;
1008
1009 /* Adjust VM size here.
1010 * Currently set to 4GB ((1 << 20) 4k pages).
1011 * Max GPUVM size for cayman and SI is 40 bits.
1012 */
1013 amdgpu_vm_adjust_size(adev, 64, 9, 1, 40);
1014
1015 /* Set the internal MC address mask
1016 * This is the max address of the GPU's
1017 * internal address space.
1018 */
1019 adev->gmc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
1020
1021 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(40));
1022 if (r) {
1023 pr_warn("No suitable DMA available\n");
1024 return r;
1025 }
1026 adev->need_swiotlb = drm_need_swiotlb(40);
1027
1028 r = gmc_v7_0_init_microcode(adev);
1029 if (r) {
1030 DRM_ERROR("Failed to load mc firmware!\n");
1031 return r;
1032 }
1033
1034 r = gmc_v7_0_mc_init(adev);
1035 if (r)
1036 return r;
1037
1038 adev->gmc.stolen_size = gmc_v7_0_get_vbios_fb_size(adev);
1039
1040 /* Memory manager */
1041 r = amdgpu_bo_init(adev);
1042 if (r)
1043 return r;
1044
1045 r = gmc_v7_0_gart_init(adev);
1046 if (r)
1047 return r;
1048
1049 /*
1050 * number of VMs
1051 * VMID 0 is reserved for System
1052 * amdgpu graphics/compute will use VMIDs 1-7
1053 * amdkfd will use VMIDs 8-15
1054 */
1055 adev->vm_manager.first_kfd_vmid = 8;
1056 amdgpu_vm_manager_init(adev);
1057
1058 /* base offset of vram pages */
1059 if (adev->flags & AMD_IS_APU) {
1060 u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
1061
1062 tmp <<= 22;
1063 adev->vm_manager.vram_base_offset = tmp;
1064 } else {
1065 adev->vm_manager.vram_base_offset = 0;
1066 }
1067
1068 adev->gmc.vm_fault_info = kmalloc(sizeof(struct kfd_vm_fault_info),
1069 GFP_KERNEL);
1070 if (!adev->gmc.vm_fault_info)
1071 return -ENOMEM;
1072 atomic_set(&adev->gmc.vm_fault_info_updated, 0);
1073
1074 return 0;
1075}
1076
1077static int gmc_v7_0_sw_fini(void *handle)
1078{
1079 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1080
1081 amdgpu_gem_force_release(adev);
1082 amdgpu_vm_manager_fini(adev);
1083 kfree(adev->gmc.vm_fault_info);
1084 amdgpu_gart_table_vram_free(adev);
1085 amdgpu_bo_fini(adev);
1086 amdgpu_gart_fini(adev);
1087 release_firmware(adev->gmc.fw);
1088 adev->gmc.fw = NULL;
1089
1090 return 0;
1091}
1092
1093static int gmc_v7_0_hw_init(void *handle)
1094{
1095 int r;
1096 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1097
1098 gmc_v7_0_init_golden_registers(adev);
1099
1100 gmc_v7_0_mc_program(adev);
1101
1102 if (!(adev->flags & AMD_IS_APU)) {
1103 r = gmc_v7_0_mc_load_microcode(adev);
1104 if (r) {
1105 DRM_ERROR("Failed to load MC firmware!\n");
1106 return r;
1107 }
1108 }
1109
1110 r = gmc_v7_0_gart_enable(adev);
1111 if (r)
1112 return r;
1113
1114 return r;
1115}
1116
1117static int gmc_v7_0_hw_fini(void *handle)
1118{
1119 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1120
1121 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
1122 gmc_v7_0_gart_disable(adev);
1123
1124 return 0;
1125}
1126
1127static int gmc_v7_0_suspend(void *handle)
1128{
1129 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1130
1131 gmc_v7_0_hw_fini(adev);
1132
1133 return 0;
1134}
1135
1136static int gmc_v7_0_resume(void *handle)
1137{
1138 int r;
1139 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1140
1141 r = gmc_v7_0_hw_init(adev);
1142 if (r)
1143 return r;
1144
1145 amdgpu_vmid_reset_all(adev);
1146
1147 return 0;
1148}
1149
1150static bool gmc_v7_0_is_idle(void *handle)
1151{
1152 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1153 u32 tmp = RREG32(mmSRBM_STATUS);
1154
1155 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1156 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))
1157 return false;
1158
1159 return true;
1160}
1161
1162static int gmc_v7_0_wait_for_idle(void *handle)
1163{
1164 unsigned i;
1165 u32 tmp;
1166 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1167
1168 for (i = 0; i < adev->usec_timeout; i++) {
1169 /* read MC_STATUS */
1170 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |
1171 SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1172 SRBM_STATUS__MCC_BUSY_MASK |
1173 SRBM_STATUS__MCD_BUSY_MASK |
1174 SRBM_STATUS__VMC_BUSY_MASK);
1175 if (!tmp)
1176 return 0;
1177 udelay(1);
1178 }
1179 return -ETIMEDOUT;
1180
1181}
1182
1183static int gmc_v7_0_soft_reset(void *handle)
1184{
1185 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1186 u32 srbm_soft_reset = 0;
1187 u32 tmp = RREG32(mmSRBM_STATUS);
1188
1189 if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
1190 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1191 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
1192
1193 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1194 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
1195 if (!(adev->flags & AMD_IS_APU))
1196 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1197 SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
1198 }
1199
1200 if (srbm_soft_reset) {
1201 gmc_v7_0_mc_stop(adev);
1202 if (gmc_v7_0_wait_for_idle((void *)adev)) {
1203 dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
1204 }
1205
1206
1207 tmp = RREG32(mmSRBM_SOFT_RESET);
1208 tmp |= srbm_soft_reset;
1209 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1210 WREG32(mmSRBM_SOFT_RESET, tmp);
1211 tmp = RREG32(mmSRBM_SOFT_RESET);
1212
1213 udelay(50);
1214
1215 tmp &= ~srbm_soft_reset;
1216 WREG32(mmSRBM_SOFT_RESET, tmp);
1217 tmp = RREG32(mmSRBM_SOFT_RESET);
1218
1219 /* Wait a little for things to settle down */
1220 udelay(50);
1221
1222 gmc_v7_0_mc_resume(adev);
1223 udelay(50);
1224 }
1225
1226 return 0;
1227}
1228
1229static int gmc_v7_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
1230 struct amdgpu_irq_src *src,
1231 unsigned type,
1232 enum amdgpu_interrupt_state state)
1233{
1234 u32 tmp;
1235 u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1236 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1237 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1238 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1239 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1240 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
1241
1242 switch (state) {
1243 case AMDGPU_IRQ_STATE_DISABLE:
1244 /* system context */
1245 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1246 tmp &= ~bits;
1247 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1248 /* VMs */
1249 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1250 tmp &= ~bits;
1251 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1252 break;
1253 case AMDGPU_IRQ_STATE_ENABLE:
1254 /* system context */
1255 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1256 tmp |= bits;
1257 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1258 /* VMs */
1259 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1260 tmp |= bits;
1261 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1262 break;
1263 default:
1264 break;
1265 }
1266
1267 return 0;
1268}
1269
1270static int gmc_v7_0_process_interrupt(struct amdgpu_device *adev,
1271 struct amdgpu_irq_src *source,
1272 struct amdgpu_iv_entry *entry)
1273{
1274 u32 addr, status, mc_client, vmid;
1275
1276 addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
1277 status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
1278 mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);
1279 /* reset addr and status */
1280 WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
1281
1282 if (!addr && !status)
1283 return 0;
1284
1285 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
1286 gmc_v7_0_set_fault_enable_default(adev, false);
1287
1288 if (printk_ratelimit()) {
1289 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1290 entry->src_id, entry->src_data[0]);
1291 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
1292 addr);
1293 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1294 status);
1295 gmc_v7_0_vm_decode_fault(adev, status, addr, mc_client,
1296 entry->pasid);
1297 }
1298
1299 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1300 VMID);
1301 if (amdgpu_amdkfd_is_kfd_vmid(adev, vmid)
1302 && !atomic_read(&adev->gmc.vm_fault_info_updated)) {
1303 struct kfd_vm_fault_info *info = adev->gmc.vm_fault_info;
1304 u32 protections = REG_GET_FIELD(status,
1305 VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1306 PROTECTIONS);
1307
1308 info->vmid = vmid;
1309 info->mc_id = REG_GET_FIELD(status,
1310 VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1311 MEMORY_CLIENT_ID);
1312 info->status = status;
1313 info->page_addr = addr;
1314 info->prot_valid = protections & 0x7 ? true : false;
1315 info->prot_read = protections & 0x8 ? true : false;
1316 info->prot_write = protections & 0x10 ? true : false;
1317 info->prot_exec = protections & 0x20 ? true : false;
1318 mb();
1319 atomic_set(&adev->gmc.vm_fault_info_updated, 1);
1320 }
1321
1322 return 0;
1323}
1324
1325static int gmc_v7_0_set_clockgating_state(void *handle,
1326 enum amd_clockgating_state state)
1327{
1328 bool gate = false;
1329 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1330
1331 if (state == AMD_CG_STATE_GATE)
1332 gate = true;
1333
1334 if (!(adev->flags & AMD_IS_APU)) {
1335 gmc_v7_0_enable_mc_mgcg(adev, gate);
1336 gmc_v7_0_enable_mc_ls(adev, gate);
1337 }
1338 gmc_v7_0_enable_bif_mgls(adev, gate);
1339 gmc_v7_0_enable_hdp_mgcg(adev, gate);
1340 gmc_v7_0_enable_hdp_ls(adev, gate);
1341
1342 return 0;
1343}
1344
1345static int gmc_v7_0_set_powergating_state(void *handle,
1346 enum amd_powergating_state state)
1347{
1348 return 0;
1349}
1350
1351static const struct amd_ip_funcs gmc_v7_0_ip_funcs = {
1352 .name = "gmc_v7_0",
1353 .early_init = gmc_v7_0_early_init,
1354 .late_init = gmc_v7_0_late_init,
1355 .sw_init = gmc_v7_0_sw_init,
1356 .sw_fini = gmc_v7_0_sw_fini,
1357 .hw_init = gmc_v7_0_hw_init,
1358 .hw_fini = gmc_v7_0_hw_fini,
1359 .suspend = gmc_v7_0_suspend,
1360 .resume = gmc_v7_0_resume,
1361 .is_idle = gmc_v7_0_is_idle,
1362 .wait_for_idle = gmc_v7_0_wait_for_idle,
1363 .soft_reset = gmc_v7_0_soft_reset,
1364 .set_clockgating_state = gmc_v7_0_set_clockgating_state,
1365 .set_powergating_state = gmc_v7_0_set_powergating_state,
1366};
1367
1368static const struct amdgpu_gmc_funcs gmc_v7_0_gmc_funcs = {
1369 .flush_gpu_tlb = gmc_v7_0_flush_gpu_tlb,
1370 .flush_gpu_tlb_pasid = gmc_v7_0_flush_gpu_tlb_pasid,
1371 .emit_flush_gpu_tlb = gmc_v7_0_emit_flush_gpu_tlb,
1372 .emit_pasid_mapping = gmc_v7_0_emit_pasid_mapping,
1373 .set_prt = gmc_v7_0_set_prt,
1374 .get_vm_pde = gmc_v7_0_get_vm_pde,
1375 .get_vm_pte = gmc_v7_0_get_vm_pte
1376};
1377
1378static const struct amdgpu_irq_src_funcs gmc_v7_0_irq_funcs = {
1379 .set = gmc_v7_0_vm_fault_interrupt_state,
1380 .process = gmc_v7_0_process_interrupt,
1381};
1382
1383static void gmc_v7_0_set_gmc_funcs(struct amdgpu_device *adev)
1384{
1385 adev->gmc.gmc_funcs = &gmc_v7_0_gmc_funcs;
1386}
1387
1388static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev)
1389{
1390 adev->gmc.vm_fault.num_types = 1;
1391 adev->gmc.vm_fault.funcs = &gmc_v7_0_irq_funcs;
1392}
1393
1394const struct amdgpu_ip_block_version gmc_v7_0_ip_block =
1395{
1396 .type = AMD_IP_BLOCK_TYPE_GMC,
1397 .major = 7,
1398 .minor = 0,
1399 .rev = 0,
1400 .funcs = &gmc_v7_0_ip_funcs,
1401};
1402
1403const struct amdgpu_ip_block_version gmc_v7_4_ip_block =
1404{
1405 .type = AMD_IP_BLOCK_TYPE_GMC,
1406 .major = 7,
1407 .minor = 4,
1408 .rev = 0,
1409 .funcs = &gmc_v7_0_ip_funcs,
1410};
1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
24#include "drmP.h"
25#include "amdgpu.h"
26#include "cikd.h"
27#include "cik.h"
28#include "gmc_v7_0.h"
29#include "amdgpu_ucode.h"
30
31#include "bif/bif_4_1_d.h"
32#include "bif/bif_4_1_sh_mask.h"
33
34#include "gmc/gmc_7_1_d.h"
35#include "gmc/gmc_7_1_sh_mask.h"
36
37#include "oss/oss_2_0_d.h"
38#include "oss/oss_2_0_sh_mask.h"
39
40static void gmc_v7_0_set_gart_funcs(struct amdgpu_device *adev);
41static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev);
42
43MODULE_FIRMWARE("radeon/bonaire_mc.bin");
44MODULE_FIRMWARE("radeon/hawaii_mc.bin");
45MODULE_FIRMWARE("amdgpu/topaz_mc.bin");
46
47static const u32 golden_settings_iceland_a11[] =
48{
49 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
50 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
51 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
52 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
53};
54
55static const u32 iceland_mgcg_cgcg_init[] =
56{
57 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
58};
59
60static void gmc_v7_0_init_golden_registers(struct amdgpu_device *adev)
61{
62 switch (adev->asic_type) {
63 case CHIP_TOPAZ:
64 amdgpu_program_register_sequence(adev,
65 iceland_mgcg_cgcg_init,
66 (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
67 amdgpu_program_register_sequence(adev,
68 golden_settings_iceland_a11,
69 (const u32)ARRAY_SIZE(golden_settings_iceland_a11));
70 break;
71 default:
72 break;
73 }
74}
75
76/**
77 * gmc7_mc_wait_for_idle - wait for MC idle callback.
78 *
79 * @adev: amdgpu_device pointer
80 *
81 * Wait for the MC (memory controller) to be idle.
82 * (evergreen+).
83 * Returns 0 if the MC is idle, -1 if not.
84 */
85int gmc_v7_0_mc_wait_for_idle(struct amdgpu_device *adev)
86{
87 unsigned i;
88 u32 tmp;
89
90 for (i = 0; i < adev->usec_timeout; i++) {
91 /* read MC_STATUS */
92 tmp = RREG32(mmSRBM_STATUS) & 0x1F00;
93 if (!tmp)
94 return 0;
95 udelay(1);
96 }
97 return -1;
98}
99
100void gmc_v7_0_mc_stop(struct amdgpu_device *adev,
101 struct amdgpu_mode_mc_save *save)
102{
103 u32 blackout;
104
105 if (adev->mode_info.num_crtc)
106 amdgpu_display_stop_mc_access(adev, save);
107
108 amdgpu_asic_wait_for_mc_idle(adev);
109
110 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
111 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
112 /* Block CPU access */
113 WREG32(mmBIF_FB_EN, 0);
114 /* blackout the MC */
115 blackout = REG_SET_FIELD(blackout,
116 MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
117 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1);
118 }
119 /* wait for the MC to settle */
120 udelay(100);
121}
122
123void gmc_v7_0_mc_resume(struct amdgpu_device *adev,
124 struct amdgpu_mode_mc_save *save)
125{
126 u32 tmp;
127
128 /* unblackout the MC */
129 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
130 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
131 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
132 /* allow CPU access */
133 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
134 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
135 WREG32(mmBIF_FB_EN, tmp);
136
137 if (adev->mode_info.num_crtc)
138 amdgpu_display_resume_mc_access(adev, save);
139}
140
141/**
142 * gmc_v7_0_init_microcode - load ucode images from disk
143 *
144 * @adev: amdgpu_device pointer
145 *
146 * Use the firmware interface to load the ucode images into
147 * the driver (not loaded into hw).
148 * Returns 0 on success, error on failure.
149 */
150static int gmc_v7_0_init_microcode(struct amdgpu_device *adev)
151{
152 const char *chip_name;
153 char fw_name[30];
154 int err;
155
156 DRM_DEBUG("\n");
157
158 switch (adev->asic_type) {
159 case CHIP_BONAIRE:
160 chip_name = "bonaire";
161 break;
162 case CHIP_HAWAII:
163 chip_name = "hawaii";
164 break;
165 case CHIP_TOPAZ:
166 chip_name = "topaz";
167 break;
168 case CHIP_KAVERI:
169 case CHIP_KABINI:
170 return 0;
171 default: BUG();
172 }
173
174 if (adev->asic_type == CHIP_TOPAZ)
175 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name);
176 else
177 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
178
179 err = request_firmware(&adev->mc.fw, fw_name, adev->dev);
180 if (err)
181 goto out;
182 err = amdgpu_ucode_validate(adev->mc.fw);
183
184out:
185 if (err) {
186 printk(KERN_ERR
187 "cik_mc: Failed to load firmware \"%s\"\n",
188 fw_name);
189 release_firmware(adev->mc.fw);
190 adev->mc.fw = NULL;
191 }
192 return err;
193}
194
195/**
196 * gmc_v7_0_mc_load_microcode - load MC ucode into the hw
197 *
198 * @adev: amdgpu_device pointer
199 *
200 * Load the GDDR MC ucode into the hw (CIK).
201 * Returns 0 on success, error on failure.
202 */
203static int gmc_v7_0_mc_load_microcode(struct amdgpu_device *adev)
204{
205 const struct mc_firmware_header_v1_0 *hdr;
206 const __le32 *fw_data = NULL;
207 const __le32 *io_mc_regs = NULL;
208 u32 running, blackout = 0;
209 int i, ucode_size, regs_size;
210
211 if (!adev->mc.fw)
212 return -EINVAL;
213
214 hdr = (const struct mc_firmware_header_v1_0 *)adev->mc.fw->data;
215 amdgpu_ucode_print_mc_hdr(&hdr->header);
216
217 adev->mc.fw_version = le32_to_cpu(hdr->header.ucode_version);
218 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
219 io_mc_regs = (const __le32 *)
220 (adev->mc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
221 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
222 fw_data = (const __le32 *)
223 (adev->mc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
224
225 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN);
226
227 if (running == 0) {
228 if (running) {
229 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
230 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1);
231 }
232
233 /* reset the engine and set to writable */
234 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
235 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
236
237 /* load mc io regs */
238 for (i = 0; i < regs_size; i++) {
239 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
240 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
241 }
242 /* load the MC ucode */
243 for (i = 0; i < ucode_size; i++)
244 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
245
246 /* put the engine back into the active state */
247 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
248 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
249 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
250
251 /* wait for training to complete */
252 for (i = 0; i < adev->usec_timeout; i++) {
253 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
254 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0))
255 break;
256 udelay(1);
257 }
258 for (i = 0; i < adev->usec_timeout; i++) {
259 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
260 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1))
261 break;
262 udelay(1);
263 }
264
265 if (running)
266 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout);
267 }
268
269 return 0;
270}
271
272static void gmc_v7_0_vram_gtt_location(struct amdgpu_device *adev,
273 struct amdgpu_mc *mc)
274{
275 if (mc->mc_vram_size > 0xFFC0000000ULL) {
276 /* leave room for at least 1024M GTT */
277 dev_warn(adev->dev, "limiting VRAM\n");
278 mc->real_vram_size = 0xFFC0000000ULL;
279 mc->mc_vram_size = 0xFFC0000000ULL;
280 }
281 amdgpu_vram_location(adev, &adev->mc, 0);
282 adev->mc.gtt_base_align = 0;
283 amdgpu_gtt_location(adev, mc);
284}
285
286/**
287 * gmc_v7_0_mc_program - program the GPU memory controller
288 *
289 * @adev: amdgpu_device pointer
290 *
291 * Set the location of vram, gart, and AGP in the GPU's
292 * physical address space (CIK).
293 */
294static void gmc_v7_0_mc_program(struct amdgpu_device *adev)
295{
296 struct amdgpu_mode_mc_save save;
297 u32 tmp;
298 int i, j;
299
300 /* Initialize HDP */
301 for (i = 0, j = 0; i < 32; i++, j += 0x6) {
302 WREG32((0xb05 + j), 0x00000000);
303 WREG32((0xb06 + j), 0x00000000);
304 WREG32((0xb07 + j), 0x00000000);
305 WREG32((0xb08 + j), 0x00000000);
306 WREG32((0xb09 + j), 0x00000000);
307 }
308 WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
309
310 if (adev->mode_info.num_crtc)
311 amdgpu_display_set_vga_render_state(adev, false);
312
313 gmc_v7_0_mc_stop(adev, &save);
314 if (amdgpu_asic_wait_for_mc_idle(adev)) {
315 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
316 }
317 /* Update configuration */
318 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
319 adev->mc.vram_start >> 12);
320 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
321 adev->mc.vram_end >> 12);
322 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
323 adev->vram_scratch.gpu_addr >> 12);
324 tmp = ((adev->mc.vram_end >> 24) & 0xFFFF) << 16;
325 tmp |= ((adev->mc.vram_start >> 24) & 0xFFFF);
326 WREG32(mmMC_VM_FB_LOCATION, tmp);
327 /* XXX double check these! */
328 WREG32(mmHDP_NONSURFACE_BASE, (adev->mc.vram_start >> 8));
329 WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
330 WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF);
331 WREG32(mmMC_VM_AGP_BASE, 0);
332 WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
333 WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
334 if (amdgpu_asic_wait_for_mc_idle(adev)) {
335 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
336 }
337 gmc_v7_0_mc_resume(adev, &save);
338
339 WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
340
341 tmp = RREG32(mmHDP_MISC_CNTL);
342 tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0);
343 WREG32(mmHDP_MISC_CNTL, tmp);
344
345 tmp = RREG32(mmHDP_HOST_PATH_CNTL);
346 WREG32(mmHDP_HOST_PATH_CNTL, tmp);
347}
348
349/**
350 * gmc_v7_0_mc_init - initialize the memory controller driver params
351 *
352 * @adev: amdgpu_device pointer
353 *
354 * Look up the amount of vram, vram width, and decide how to place
355 * vram and gart within the GPU's physical address space (CIK).
356 * Returns 0 for success.
357 */
358static int gmc_v7_0_mc_init(struct amdgpu_device *adev)
359{
360 u32 tmp;
361 int chansize, numchan;
362
363 /* Get VRAM informations */
364 tmp = RREG32(mmMC_ARB_RAMCFG);
365 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) {
366 chansize = 64;
367 } else {
368 chansize = 32;
369 }
370 tmp = RREG32(mmMC_SHARED_CHMAP);
371 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
372 case 0:
373 default:
374 numchan = 1;
375 break;
376 case 1:
377 numchan = 2;
378 break;
379 case 2:
380 numchan = 4;
381 break;
382 case 3:
383 numchan = 8;
384 break;
385 case 4:
386 numchan = 3;
387 break;
388 case 5:
389 numchan = 6;
390 break;
391 case 6:
392 numchan = 10;
393 break;
394 case 7:
395 numchan = 12;
396 break;
397 case 8:
398 numchan = 16;
399 break;
400 }
401 adev->mc.vram_width = numchan * chansize;
402 /* Could aper size report 0 ? */
403 adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
404 adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
405 /* size in MB on si */
406 adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
407 adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
408 adev->mc.visible_vram_size = adev->mc.aper_size;
409
410 /* In case the PCI BAR is larger than the actual amount of vram */
411 if (adev->mc.visible_vram_size > adev->mc.real_vram_size)
412 adev->mc.visible_vram_size = adev->mc.real_vram_size;
413
414 /* unless the user had overridden it, set the gart
415 * size equal to the 1024 or vram, whichever is larger.
416 */
417 if (amdgpu_gart_size == -1)
418 adev->mc.gtt_size = max((1024ULL << 20), adev->mc.mc_vram_size);
419 else
420 adev->mc.gtt_size = (uint64_t)amdgpu_gart_size << 20;
421
422 gmc_v7_0_vram_gtt_location(adev, &adev->mc);
423
424 return 0;
425}
426
427/*
428 * GART
429 * VMID 0 is the physical GPU addresses as used by the kernel.
430 * VMIDs 1-15 are used for userspace clients and are handled
431 * by the amdgpu vm/hsa code.
432 */
433
434/**
435 * gmc_v7_0_gart_flush_gpu_tlb - gart tlb flush callback
436 *
437 * @adev: amdgpu_device pointer
438 * @vmid: vm instance to flush
439 *
440 * Flush the TLB for the requested page table (CIK).
441 */
442static void gmc_v7_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
443 uint32_t vmid)
444{
445 /* flush hdp cache */
446 WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
447
448 /* bits 0-15 are the VM contexts0-15 */
449 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
450}
451
452/**
453 * gmc_v7_0_gart_set_pte_pde - update the page tables using MMIO
454 *
455 * @adev: amdgpu_device pointer
456 * @cpu_pt_addr: cpu address of the page table
457 * @gpu_page_idx: entry in the page table to update
458 * @addr: dst addr to write into pte/pde
459 * @flags: access flags
460 *
461 * Update the page tables using the CPU.
462 */
463static int gmc_v7_0_gart_set_pte_pde(struct amdgpu_device *adev,
464 void *cpu_pt_addr,
465 uint32_t gpu_page_idx,
466 uint64_t addr,
467 uint32_t flags)
468{
469 void __iomem *ptr = (void *)cpu_pt_addr;
470 uint64_t value;
471
472 value = addr & 0xFFFFFFFFFFFFF000ULL;
473 value |= flags;
474 writeq(value, ptr + (gpu_page_idx * 8));
475
476 return 0;
477}
478
479/**
480 * gmc_v8_0_set_fault_enable_default - update VM fault handling
481 *
482 * @adev: amdgpu_device pointer
483 * @value: true redirects VM faults to the default page
484 */
485static void gmc_v7_0_set_fault_enable_default(struct amdgpu_device *adev,
486 bool value)
487{
488 u32 tmp;
489
490 tmp = RREG32(mmVM_CONTEXT1_CNTL);
491 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
492 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
493 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
494 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
495 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
496 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
497 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
498 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
499 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
500 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
501 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
502 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
503 WREG32(mmVM_CONTEXT1_CNTL, tmp);
504}
505
506/**
507 * gmc_v7_0_gart_enable - gart enable
508 *
509 * @adev: amdgpu_device pointer
510 *
511 * This sets up the TLBs, programs the page tables for VMID0,
512 * sets up the hw for VMIDs 1-15 which are allocated on
513 * demand, and sets up the global locations for the LDS, GDS,
514 * and GPUVM for FSA64 clients (CIK).
515 * Returns 0 for success, errors for failure.
516 */
517static int gmc_v7_0_gart_enable(struct amdgpu_device *adev)
518{
519 int r, i;
520 u32 tmp;
521
522 if (adev->gart.robj == NULL) {
523 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
524 return -EINVAL;
525 }
526 r = amdgpu_gart_table_vram_pin(adev);
527 if (r)
528 return r;
529 /* Setup TLB control */
530 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
531 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
532 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1);
533 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
534 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1);
535 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
536 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
537 /* Setup L2 cache */
538 tmp = RREG32(mmVM_L2_CNTL);
539 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
540 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
541 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1);
542 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1);
543 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7);
544 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
545 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
546 WREG32(mmVM_L2_CNTL, tmp);
547 tmp = REG_SET_FIELD(0, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
548 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
549 WREG32(mmVM_L2_CNTL2, tmp);
550 tmp = RREG32(mmVM_L2_CNTL3);
551 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1);
552 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 4);
553 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 4);
554 WREG32(mmVM_L2_CNTL3, tmp);
555 /* setup context0 */
556 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gtt_start >> 12);
557 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gtt_end >> 12);
558 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12);
559 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
560 (u32)(adev->dummy_page.addr >> 12));
561 WREG32(mmVM_CONTEXT0_CNTL2, 0);
562 tmp = RREG32(mmVM_CONTEXT0_CNTL);
563 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
564 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
565 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
566 WREG32(mmVM_CONTEXT0_CNTL, tmp);
567
568 WREG32(0x575, 0);
569 WREG32(0x576, 0);
570 WREG32(0x577, 0);
571
572 /* empty context1-15 */
573 /* FIXME start with 4G, once using 2 level pt switch to full
574 * vm size space
575 */
576 /* set vm size, must be a multiple of 4 */
577 WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
578 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
579 for (i = 1; i < 16; i++) {
580 if (i < 8)
581 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
582 adev->gart.table_addr >> 12);
583 else
584 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
585 adev->gart.table_addr >> 12);
586 }
587
588 /* enable context1-15 */
589 WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
590 (u32)(adev->dummy_page.addr >> 12));
591 WREG32(mmVM_CONTEXT1_CNTL2, 4);
592 tmp = RREG32(mmVM_CONTEXT1_CNTL);
593 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
594 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);
595 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE,
596 amdgpu_vm_block_size - 9);
597 WREG32(mmVM_CONTEXT1_CNTL, tmp);
598 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
599 gmc_v7_0_set_fault_enable_default(adev, false);
600 else
601 gmc_v7_0_set_fault_enable_default(adev, true);
602
603 if (adev->asic_type == CHIP_KAVERI) {
604 tmp = RREG32(mmCHUB_CONTROL);
605 tmp &= ~BYPASS_VM;
606 WREG32(mmCHUB_CONTROL, tmp);
607 }
608
609 gmc_v7_0_gart_flush_gpu_tlb(adev, 0);
610 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
611 (unsigned)(adev->mc.gtt_size >> 20),
612 (unsigned long long)adev->gart.table_addr);
613 adev->gart.ready = true;
614 return 0;
615}
616
617static int gmc_v7_0_gart_init(struct amdgpu_device *adev)
618{
619 int r;
620
621 if (adev->gart.robj) {
622 WARN(1, "R600 PCIE GART already initialized\n");
623 return 0;
624 }
625 /* Initialize common gart structure */
626 r = amdgpu_gart_init(adev);
627 if (r)
628 return r;
629 adev->gart.table_size = adev->gart.num_gpu_pages * 8;
630 return amdgpu_gart_table_vram_alloc(adev);
631}
632
633/**
634 * gmc_v7_0_gart_disable - gart disable
635 *
636 * @adev: amdgpu_device pointer
637 *
638 * This disables all VM page table (CIK).
639 */
640static void gmc_v7_0_gart_disable(struct amdgpu_device *adev)
641{
642 u32 tmp;
643
644 /* Disable all tables */
645 WREG32(mmVM_CONTEXT0_CNTL, 0);
646 WREG32(mmVM_CONTEXT1_CNTL, 0);
647 /* Setup TLB control */
648 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
649 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
650 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0);
651 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0);
652 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
653 /* Setup L2 cache */
654 tmp = RREG32(mmVM_L2_CNTL);
655 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
656 WREG32(mmVM_L2_CNTL, tmp);
657 WREG32(mmVM_L2_CNTL2, 0);
658 amdgpu_gart_table_vram_unpin(adev);
659}
660
661/**
662 * gmc_v7_0_gart_fini - vm fini callback
663 *
664 * @adev: amdgpu_device pointer
665 *
666 * Tears down the driver GART/VM setup (CIK).
667 */
668static void gmc_v7_0_gart_fini(struct amdgpu_device *adev)
669{
670 amdgpu_gart_table_vram_free(adev);
671 amdgpu_gart_fini(adev);
672}
673
674/*
675 * vm
676 * VMID 0 is the physical GPU addresses as used by the kernel.
677 * VMIDs 1-15 are used for userspace clients and are handled
678 * by the amdgpu vm/hsa code.
679 */
680/**
681 * gmc_v7_0_vm_init - cik vm init callback
682 *
683 * @adev: amdgpu_device pointer
684 *
685 * Inits cik specific vm parameters (number of VMs, base of vram for
686 * VMIDs 1-15) (CIK).
687 * Returns 0 for success.
688 */
689static int gmc_v7_0_vm_init(struct amdgpu_device *adev)
690{
691 /*
692 * number of VMs
693 * VMID 0 is reserved for System
694 * amdgpu graphics/compute will use VMIDs 1-7
695 * amdkfd will use VMIDs 8-15
696 */
697 adev->vm_manager.num_ids = AMDGPU_NUM_OF_VMIDS;
698 amdgpu_vm_manager_init(adev);
699
700 /* base offset of vram pages */
701 if (adev->flags & AMD_IS_APU) {
702 u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
703 tmp <<= 22;
704 adev->vm_manager.vram_base_offset = tmp;
705 } else
706 adev->vm_manager.vram_base_offset = 0;
707
708 return 0;
709}
710
711/**
712 * gmc_v7_0_vm_fini - cik vm fini callback
713 *
714 * @adev: amdgpu_device pointer
715 *
716 * Tear down any asic specific VM setup (CIK).
717 */
718static void gmc_v7_0_vm_fini(struct amdgpu_device *adev)
719{
720}
721
722/**
723 * gmc_v7_0_vm_decode_fault - print human readable fault info
724 *
725 * @adev: amdgpu_device pointer
726 * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
727 * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
728 *
729 * Print human readable fault information (CIK).
730 */
731static void gmc_v7_0_vm_decode_fault(struct amdgpu_device *adev,
732 u32 status, u32 addr, u32 mc_client)
733{
734 u32 mc_id;
735 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
736 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
737 PROTECTIONS);
738 char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
739 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
740
741 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
742 MEMORY_CLIENT_ID);
743
744 printk("VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
745 protections, vmid, addr,
746 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
747 MEMORY_CLIENT_RW) ?
748 "write" : "read", block, mc_client, mc_id);
749}
750
751
752static const u32 mc_cg_registers[] = {
753 mmMC_HUB_MISC_HUB_CG,
754 mmMC_HUB_MISC_SIP_CG,
755 mmMC_HUB_MISC_VM_CG,
756 mmMC_XPB_CLK_GAT,
757 mmATC_MISC_CG,
758 mmMC_CITF_MISC_WR_CG,
759 mmMC_CITF_MISC_RD_CG,
760 mmMC_CITF_MISC_VM_CG,
761 mmVM_L2_CG,
762};
763
764static const u32 mc_cg_ls_en[] = {
765 MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK,
766 MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK,
767 MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK,
768 MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK,
769 ATC_MISC_CG__MEM_LS_ENABLE_MASK,
770 MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK,
771 MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK,
772 MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK,
773 VM_L2_CG__MEM_LS_ENABLE_MASK,
774};
775
776static const u32 mc_cg_en[] = {
777 MC_HUB_MISC_HUB_CG__ENABLE_MASK,
778 MC_HUB_MISC_SIP_CG__ENABLE_MASK,
779 MC_HUB_MISC_VM_CG__ENABLE_MASK,
780 MC_XPB_CLK_GAT__ENABLE_MASK,
781 ATC_MISC_CG__ENABLE_MASK,
782 MC_CITF_MISC_WR_CG__ENABLE_MASK,
783 MC_CITF_MISC_RD_CG__ENABLE_MASK,
784 MC_CITF_MISC_VM_CG__ENABLE_MASK,
785 VM_L2_CG__ENABLE_MASK,
786};
787
788static void gmc_v7_0_enable_mc_ls(struct amdgpu_device *adev,
789 bool enable)
790{
791 int i;
792 u32 orig, data;
793
794 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
795 orig = data = RREG32(mc_cg_registers[i]);
796 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS))
797 data |= mc_cg_ls_en[i];
798 else
799 data &= ~mc_cg_ls_en[i];
800 if (data != orig)
801 WREG32(mc_cg_registers[i], data);
802 }
803}
804
805static void gmc_v7_0_enable_mc_mgcg(struct amdgpu_device *adev,
806 bool enable)
807{
808 int i;
809 u32 orig, data;
810
811 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
812 orig = data = RREG32(mc_cg_registers[i]);
813 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG))
814 data |= mc_cg_en[i];
815 else
816 data &= ~mc_cg_en[i];
817 if (data != orig)
818 WREG32(mc_cg_registers[i], data);
819 }
820}
821
822static void gmc_v7_0_enable_bif_mgls(struct amdgpu_device *adev,
823 bool enable)
824{
825 u32 orig, data;
826
827 orig = data = RREG32_PCIE(ixPCIE_CNTL2);
828
829 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) {
830 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 1);
831 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 1);
832 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 1);
833 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 1);
834 } else {
835 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 0);
836 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 0);
837 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 0);
838 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 0);
839 }
840
841 if (orig != data)
842 WREG32_PCIE(ixPCIE_CNTL2, data);
843}
844
845static void gmc_v7_0_enable_hdp_mgcg(struct amdgpu_device *adev,
846 bool enable)
847{
848 u32 orig, data;
849
850 orig = data = RREG32(mmHDP_HOST_PATH_CNTL);
851
852 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG))
853 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0);
854 else
855 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1);
856
857 if (orig != data)
858 WREG32(mmHDP_HOST_PATH_CNTL, data);
859}
860
861static void gmc_v7_0_enable_hdp_ls(struct amdgpu_device *adev,
862 bool enable)
863{
864 u32 orig, data;
865
866 orig = data = RREG32(mmHDP_MEM_POWER_LS);
867
868 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
869 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1);
870 else
871 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0);
872
873 if (orig != data)
874 WREG32(mmHDP_MEM_POWER_LS, data);
875}
876
877static int gmc_v7_0_convert_vram_type(int mc_seq_vram_type)
878{
879 switch (mc_seq_vram_type) {
880 case MC_SEQ_MISC0__MT__GDDR1:
881 return AMDGPU_VRAM_TYPE_GDDR1;
882 case MC_SEQ_MISC0__MT__DDR2:
883 return AMDGPU_VRAM_TYPE_DDR2;
884 case MC_SEQ_MISC0__MT__GDDR3:
885 return AMDGPU_VRAM_TYPE_GDDR3;
886 case MC_SEQ_MISC0__MT__GDDR4:
887 return AMDGPU_VRAM_TYPE_GDDR4;
888 case MC_SEQ_MISC0__MT__GDDR5:
889 return AMDGPU_VRAM_TYPE_GDDR5;
890 case MC_SEQ_MISC0__MT__HBM:
891 return AMDGPU_VRAM_TYPE_HBM;
892 case MC_SEQ_MISC0__MT__DDR3:
893 return AMDGPU_VRAM_TYPE_DDR3;
894 default:
895 return AMDGPU_VRAM_TYPE_UNKNOWN;
896 }
897}
898
899static int gmc_v7_0_early_init(void *handle)
900{
901 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
902
903 gmc_v7_0_set_gart_funcs(adev);
904 gmc_v7_0_set_irq_funcs(adev);
905
906 return 0;
907}
908
909static int gmc_v7_0_late_init(void *handle)
910{
911 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
912
913 if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)
914 return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
915 else
916 return 0;
917}
918
919static int gmc_v7_0_sw_init(void *handle)
920{
921 int r;
922 int dma_bits;
923 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
924
925 if (adev->flags & AMD_IS_APU) {
926 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
927 } else {
928 u32 tmp = RREG32(mmMC_SEQ_MISC0);
929 tmp &= MC_SEQ_MISC0__MT__MASK;
930 adev->mc.vram_type = gmc_v7_0_convert_vram_type(tmp);
931 }
932
933 r = amdgpu_irq_add_id(adev, 146, &adev->mc.vm_fault);
934 if (r)
935 return r;
936
937 r = amdgpu_irq_add_id(adev, 147, &adev->mc.vm_fault);
938 if (r)
939 return r;
940
941 /* Adjust VM size here.
942 * Currently set to 4GB ((1 << 20) 4k pages).
943 * Max GPUVM size for cayman and SI is 40 bits.
944 */
945 adev->vm_manager.max_pfn = amdgpu_vm_size << 18;
946
947 /* Set the internal MC address mask
948 * This is the max address of the GPU's
949 * internal address space.
950 */
951 adev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
952
953 /* set DMA mask + need_dma32 flags.
954 * PCIE - can handle 40-bits.
955 * IGP - can handle 40-bits
956 * PCI - dma32 for legacy pci gart, 40 bits on newer asics
957 */
958 adev->need_dma32 = false;
959 dma_bits = adev->need_dma32 ? 32 : 40;
960 r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
961 if (r) {
962 adev->need_dma32 = true;
963 dma_bits = 32;
964 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n");
965 }
966 r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
967 if (r) {
968 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
969 printk(KERN_WARNING "amdgpu: No coherent DMA available.\n");
970 }
971
972 r = gmc_v7_0_init_microcode(adev);
973 if (r) {
974 DRM_ERROR("Failed to load mc firmware!\n");
975 return r;
976 }
977
978 r = gmc_v7_0_mc_init(adev);
979 if (r)
980 return r;
981
982 /* Memory manager */
983 r = amdgpu_bo_init(adev);
984 if (r)
985 return r;
986
987 r = gmc_v7_0_gart_init(adev);
988 if (r)
989 return r;
990
991 if (!adev->vm_manager.enabled) {
992 r = gmc_v7_0_vm_init(adev);
993 if (r) {
994 dev_err(adev->dev, "vm manager initialization failed (%d).\n", r);
995 return r;
996 }
997 adev->vm_manager.enabled = true;
998 }
999
1000 return r;
1001}
1002
1003static int gmc_v7_0_sw_fini(void *handle)
1004{
1005 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1006
1007 if (adev->vm_manager.enabled) {
1008 amdgpu_vm_manager_fini(adev);
1009 gmc_v7_0_vm_fini(adev);
1010 adev->vm_manager.enabled = false;
1011 }
1012 gmc_v7_0_gart_fini(adev);
1013 amdgpu_gem_force_release(adev);
1014 amdgpu_bo_fini(adev);
1015
1016 return 0;
1017}
1018
1019static int gmc_v7_0_hw_init(void *handle)
1020{
1021 int r;
1022 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1023
1024 gmc_v7_0_init_golden_registers(adev);
1025
1026 gmc_v7_0_mc_program(adev);
1027
1028 if (!(adev->flags & AMD_IS_APU)) {
1029 r = gmc_v7_0_mc_load_microcode(adev);
1030 if (r) {
1031 DRM_ERROR("Failed to load MC firmware!\n");
1032 return r;
1033 }
1034 }
1035
1036 r = gmc_v7_0_gart_enable(adev);
1037 if (r)
1038 return r;
1039
1040 return r;
1041}
1042
1043static int gmc_v7_0_hw_fini(void *handle)
1044{
1045 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1046
1047 amdgpu_irq_put(adev, &adev->mc.vm_fault, 0);
1048 gmc_v7_0_gart_disable(adev);
1049
1050 return 0;
1051}
1052
1053static int gmc_v7_0_suspend(void *handle)
1054{
1055 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1056
1057 if (adev->vm_manager.enabled) {
1058 gmc_v7_0_vm_fini(adev);
1059 adev->vm_manager.enabled = false;
1060 }
1061 gmc_v7_0_hw_fini(adev);
1062
1063 return 0;
1064}
1065
1066static int gmc_v7_0_resume(void *handle)
1067{
1068 int r;
1069 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1070
1071 r = gmc_v7_0_hw_init(adev);
1072 if (r)
1073 return r;
1074
1075 if (!adev->vm_manager.enabled) {
1076 r = gmc_v7_0_vm_init(adev);
1077 if (r) {
1078 dev_err(adev->dev, "vm manager initialization failed (%d).\n", r);
1079 return r;
1080 }
1081 adev->vm_manager.enabled = true;
1082 }
1083
1084 return r;
1085}
1086
1087static bool gmc_v7_0_is_idle(void *handle)
1088{
1089 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1090 u32 tmp = RREG32(mmSRBM_STATUS);
1091
1092 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1093 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))
1094 return false;
1095
1096 return true;
1097}
1098
1099static int gmc_v7_0_wait_for_idle(void *handle)
1100{
1101 unsigned i;
1102 u32 tmp;
1103 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1104
1105 for (i = 0; i < adev->usec_timeout; i++) {
1106 /* read MC_STATUS */
1107 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |
1108 SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1109 SRBM_STATUS__MCC_BUSY_MASK |
1110 SRBM_STATUS__MCD_BUSY_MASK |
1111 SRBM_STATUS__VMC_BUSY_MASK);
1112 if (!tmp)
1113 return 0;
1114 udelay(1);
1115 }
1116 return -ETIMEDOUT;
1117
1118}
1119
1120static void gmc_v7_0_print_status(void *handle)
1121{
1122 int i, j;
1123 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1124
1125 dev_info(adev->dev, "GMC 8.x registers\n");
1126 dev_info(adev->dev, " SRBM_STATUS=0x%08X\n",
1127 RREG32(mmSRBM_STATUS));
1128 dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n",
1129 RREG32(mmSRBM_STATUS2));
1130
1131 dev_info(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
1132 RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR));
1133 dev_info(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1134 RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS));
1135 dev_info(adev->dev, " MC_VM_MX_L1_TLB_CNTL=0x%08X\n",
1136 RREG32(mmMC_VM_MX_L1_TLB_CNTL));
1137 dev_info(adev->dev, " VM_L2_CNTL=0x%08X\n",
1138 RREG32(mmVM_L2_CNTL));
1139 dev_info(adev->dev, " VM_L2_CNTL2=0x%08X\n",
1140 RREG32(mmVM_L2_CNTL2));
1141 dev_info(adev->dev, " VM_L2_CNTL3=0x%08X\n",
1142 RREG32(mmVM_L2_CNTL3));
1143 dev_info(adev->dev, " VM_CONTEXT0_PAGE_TABLE_START_ADDR=0x%08X\n",
1144 RREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR));
1145 dev_info(adev->dev, " VM_CONTEXT0_PAGE_TABLE_END_ADDR=0x%08X\n",
1146 RREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR));
1147 dev_info(adev->dev, " VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR=0x%08X\n",
1148 RREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR));
1149 dev_info(adev->dev, " VM_CONTEXT0_CNTL2=0x%08X\n",
1150 RREG32(mmVM_CONTEXT0_CNTL2));
1151 dev_info(adev->dev, " VM_CONTEXT0_CNTL=0x%08X\n",
1152 RREG32(mmVM_CONTEXT0_CNTL));
1153 dev_info(adev->dev, " 0x15D4=0x%08X\n",
1154 RREG32(0x575));
1155 dev_info(adev->dev, " 0x15D8=0x%08X\n",
1156 RREG32(0x576));
1157 dev_info(adev->dev, " 0x15DC=0x%08X\n",
1158 RREG32(0x577));
1159 dev_info(adev->dev, " VM_CONTEXT1_PAGE_TABLE_START_ADDR=0x%08X\n",
1160 RREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR));
1161 dev_info(adev->dev, " VM_CONTEXT1_PAGE_TABLE_END_ADDR=0x%08X\n",
1162 RREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR));
1163 dev_info(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR=0x%08X\n",
1164 RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR));
1165 dev_info(adev->dev, " VM_CONTEXT1_CNTL2=0x%08X\n",
1166 RREG32(mmVM_CONTEXT1_CNTL2));
1167 dev_info(adev->dev, " VM_CONTEXT1_CNTL=0x%08X\n",
1168 RREG32(mmVM_CONTEXT1_CNTL));
1169 for (i = 0; i < 16; i++) {
1170 if (i < 8)
1171 dev_info(adev->dev, " VM_CONTEXT%d_PAGE_TABLE_BASE_ADDR=0x%08X\n",
1172 i, RREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i));
1173 else
1174 dev_info(adev->dev, " VM_CONTEXT%d_PAGE_TABLE_BASE_ADDR=0x%08X\n",
1175 i, RREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8));
1176 }
1177 dev_info(adev->dev, " MC_VM_SYSTEM_APERTURE_LOW_ADDR=0x%08X\n",
1178 RREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR));
1179 dev_info(adev->dev, " MC_VM_SYSTEM_APERTURE_HIGH_ADDR=0x%08X\n",
1180 RREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR));
1181 dev_info(adev->dev, " MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR=0x%08X\n",
1182 RREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR));
1183 dev_info(adev->dev, " MC_VM_FB_LOCATION=0x%08X\n",
1184 RREG32(mmMC_VM_FB_LOCATION));
1185 dev_info(adev->dev, " MC_VM_AGP_BASE=0x%08X\n",
1186 RREG32(mmMC_VM_AGP_BASE));
1187 dev_info(adev->dev, " MC_VM_AGP_TOP=0x%08X\n",
1188 RREG32(mmMC_VM_AGP_TOP));
1189 dev_info(adev->dev, " MC_VM_AGP_BOT=0x%08X\n",
1190 RREG32(mmMC_VM_AGP_BOT));
1191
1192 if (adev->asic_type == CHIP_KAVERI) {
1193 dev_info(adev->dev, " CHUB_CONTROL=0x%08X\n",
1194 RREG32(mmCHUB_CONTROL));
1195 }
1196
1197 dev_info(adev->dev, " HDP_REG_COHERENCY_FLUSH_CNTL=0x%08X\n",
1198 RREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL));
1199 dev_info(adev->dev, " HDP_NONSURFACE_BASE=0x%08X\n",
1200 RREG32(mmHDP_NONSURFACE_BASE));
1201 dev_info(adev->dev, " HDP_NONSURFACE_INFO=0x%08X\n",
1202 RREG32(mmHDP_NONSURFACE_INFO));
1203 dev_info(adev->dev, " HDP_NONSURFACE_SIZE=0x%08X\n",
1204 RREG32(mmHDP_NONSURFACE_SIZE));
1205 dev_info(adev->dev, " HDP_MISC_CNTL=0x%08X\n",
1206 RREG32(mmHDP_MISC_CNTL));
1207 dev_info(adev->dev, " HDP_HOST_PATH_CNTL=0x%08X\n",
1208 RREG32(mmHDP_HOST_PATH_CNTL));
1209
1210 for (i = 0, j = 0; i < 32; i++, j += 0x6) {
1211 dev_info(adev->dev, " %d:\n", i);
1212 dev_info(adev->dev, " 0x%04X=0x%08X\n",
1213 0xb05 + j, RREG32(0xb05 + j));
1214 dev_info(adev->dev, " 0x%04X=0x%08X\n",
1215 0xb06 + j, RREG32(0xb06 + j));
1216 dev_info(adev->dev, " 0x%04X=0x%08X\n",
1217 0xb07 + j, RREG32(0xb07 + j));
1218 dev_info(adev->dev, " 0x%04X=0x%08X\n",
1219 0xb08 + j, RREG32(0xb08 + j));
1220 dev_info(adev->dev, " 0x%04X=0x%08X\n",
1221 0xb09 + j, RREG32(0xb09 + j));
1222 }
1223
1224 dev_info(adev->dev, " BIF_FB_EN=0x%08X\n",
1225 RREG32(mmBIF_FB_EN));
1226}
1227
1228static int gmc_v7_0_soft_reset(void *handle)
1229{
1230 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1231 struct amdgpu_mode_mc_save save;
1232 u32 srbm_soft_reset = 0;
1233 u32 tmp = RREG32(mmSRBM_STATUS);
1234
1235 if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
1236 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1237 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
1238
1239 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1240 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
1241 if (!(adev->flags & AMD_IS_APU))
1242 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1243 SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
1244 }
1245
1246 if (srbm_soft_reset) {
1247 gmc_v7_0_print_status((void *)adev);
1248
1249 gmc_v7_0_mc_stop(adev, &save);
1250 if (gmc_v7_0_wait_for_idle(adev)) {
1251 dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
1252 }
1253
1254
1255 tmp = RREG32(mmSRBM_SOFT_RESET);
1256 tmp |= srbm_soft_reset;
1257 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1258 WREG32(mmSRBM_SOFT_RESET, tmp);
1259 tmp = RREG32(mmSRBM_SOFT_RESET);
1260
1261 udelay(50);
1262
1263 tmp &= ~srbm_soft_reset;
1264 WREG32(mmSRBM_SOFT_RESET, tmp);
1265 tmp = RREG32(mmSRBM_SOFT_RESET);
1266
1267 /* Wait a little for things to settle down */
1268 udelay(50);
1269
1270 gmc_v7_0_mc_resume(adev, &save);
1271 udelay(50);
1272
1273 gmc_v7_0_print_status((void *)adev);
1274 }
1275
1276 return 0;
1277}
1278
1279static int gmc_v7_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
1280 struct amdgpu_irq_src *src,
1281 unsigned type,
1282 enum amdgpu_interrupt_state state)
1283{
1284 u32 tmp;
1285 u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1286 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1287 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1288 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1289 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1290 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
1291
1292 switch (state) {
1293 case AMDGPU_IRQ_STATE_DISABLE:
1294 /* system context */
1295 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1296 tmp &= ~bits;
1297 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1298 /* VMs */
1299 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1300 tmp &= ~bits;
1301 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1302 break;
1303 case AMDGPU_IRQ_STATE_ENABLE:
1304 /* system context */
1305 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1306 tmp |= bits;
1307 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1308 /* VMs */
1309 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1310 tmp |= bits;
1311 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1312 break;
1313 default:
1314 break;
1315 }
1316
1317 return 0;
1318}
1319
1320static int gmc_v7_0_process_interrupt(struct amdgpu_device *adev,
1321 struct amdgpu_irq_src *source,
1322 struct amdgpu_iv_entry *entry)
1323{
1324 u32 addr, status, mc_client;
1325
1326 addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
1327 status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
1328 mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);
1329 /* reset addr and status */
1330 WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
1331
1332 if (!addr && !status)
1333 return 0;
1334
1335 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
1336 gmc_v7_0_set_fault_enable_default(adev, false);
1337
1338 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1339 entry->src_id, entry->src_data);
1340 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
1341 addr);
1342 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1343 status);
1344 gmc_v7_0_vm_decode_fault(adev, status, addr, mc_client);
1345
1346 return 0;
1347}
1348
1349static int gmc_v7_0_set_clockgating_state(void *handle,
1350 enum amd_clockgating_state state)
1351{
1352 bool gate = false;
1353 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1354
1355 if (state == AMD_CG_STATE_GATE)
1356 gate = true;
1357
1358 if (!(adev->flags & AMD_IS_APU)) {
1359 gmc_v7_0_enable_mc_mgcg(adev, gate);
1360 gmc_v7_0_enable_mc_ls(adev, gate);
1361 }
1362 gmc_v7_0_enable_bif_mgls(adev, gate);
1363 gmc_v7_0_enable_hdp_mgcg(adev, gate);
1364 gmc_v7_0_enable_hdp_ls(adev, gate);
1365
1366 return 0;
1367}
1368
1369static int gmc_v7_0_set_powergating_state(void *handle,
1370 enum amd_powergating_state state)
1371{
1372 return 0;
1373}
1374
1375const struct amd_ip_funcs gmc_v7_0_ip_funcs = {
1376 .early_init = gmc_v7_0_early_init,
1377 .late_init = gmc_v7_0_late_init,
1378 .sw_init = gmc_v7_0_sw_init,
1379 .sw_fini = gmc_v7_0_sw_fini,
1380 .hw_init = gmc_v7_0_hw_init,
1381 .hw_fini = gmc_v7_0_hw_fini,
1382 .suspend = gmc_v7_0_suspend,
1383 .resume = gmc_v7_0_resume,
1384 .is_idle = gmc_v7_0_is_idle,
1385 .wait_for_idle = gmc_v7_0_wait_for_idle,
1386 .soft_reset = gmc_v7_0_soft_reset,
1387 .print_status = gmc_v7_0_print_status,
1388 .set_clockgating_state = gmc_v7_0_set_clockgating_state,
1389 .set_powergating_state = gmc_v7_0_set_powergating_state,
1390};
1391
1392static const struct amdgpu_gart_funcs gmc_v7_0_gart_funcs = {
1393 .flush_gpu_tlb = gmc_v7_0_gart_flush_gpu_tlb,
1394 .set_pte_pde = gmc_v7_0_gart_set_pte_pde,
1395};
1396
1397static const struct amdgpu_irq_src_funcs gmc_v7_0_irq_funcs = {
1398 .set = gmc_v7_0_vm_fault_interrupt_state,
1399 .process = gmc_v7_0_process_interrupt,
1400};
1401
1402static void gmc_v7_0_set_gart_funcs(struct amdgpu_device *adev)
1403{
1404 if (adev->gart.gart_funcs == NULL)
1405 adev->gart.gart_funcs = &gmc_v7_0_gart_funcs;
1406}
1407
1408static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev)
1409{
1410 adev->mc.vm_fault.num_types = 1;
1411 adev->mc.vm_fault.funcs = &gmc_v7_0_irq_funcs;
1412}