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1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28
29/**
30 * DOC: Interrupt Handling
31 *
32 * Interrupts generated within GPU hardware raise interrupt requests that are
33 * passed to amdgpu IRQ handler which is responsible for detecting source and
34 * type of the interrupt and dispatching matching handlers. If handling an
35 * interrupt requires calling kernel functions that may sleep processing is
36 * dispatched to work handlers.
37 *
38 * If MSI functionality is not disabled by module parameter then MSI
39 * support will be enabled.
40 *
41 * For GPU interrupt sources that may be driven by another driver, IRQ domain
42 * support is used (with mapping between virtual and hardware IRQs).
43 */
44
45#include <linux/irq.h>
46#include <linux/pci.h>
47
48#include <drm/drm_crtc_helper.h>
49#include <drm/drm_irq.h>
50#include <drm/drm_vblank.h>
51#include <drm/amdgpu_drm.h>
52#include "amdgpu.h"
53#include "amdgpu_ih.h"
54#include "atom.h"
55#include "amdgpu_connectors.h"
56#include "amdgpu_trace.h"
57#include "amdgpu_amdkfd.h"
58#include "amdgpu_ras.h"
59
60#include <linux/pm_runtime.h>
61
62#ifdef CONFIG_DRM_AMD_DC
63#include "amdgpu_dm_irq.h"
64#endif
65
66#define AMDGPU_WAIT_IDLE_TIMEOUT 200
67
68/**
69 * amdgpu_hotplug_work_func - work handler for display hotplug event
70 *
71 * @work: work struct pointer
72 *
73 * This is the hotplug event work handler (all ASICs).
74 * The work gets scheduled from the IRQ handler if there
75 * was a hotplug interrupt. It walks through the connector table
76 * and calls hotplug handler for each connector. After this, it sends
77 * a DRM hotplug event to alert userspace.
78 *
79 * This design approach is required in order to defer hotplug event handling
80 * from the IRQ handler to a work handler because hotplug handler has to use
81 * mutexes which cannot be locked in an IRQ handler (since &mutex_lock may
82 * sleep).
83 */
84static void amdgpu_hotplug_work_func(struct work_struct *work)
85{
86 struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
87 hotplug_work);
88 struct drm_device *dev = adev->ddev;
89 struct drm_mode_config *mode_config = &dev->mode_config;
90 struct drm_connector *connector;
91 struct drm_connector_list_iter iter;
92
93 mutex_lock(&mode_config->mutex);
94 drm_connector_list_iter_begin(dev, &iter);
95 drm_for_each_connector_iter(connector, &iter)
96 amdgpu_connector_hotplug(connector);
97 drm_connector_list_iter_end(&iter);
98 mutex_unlock(&mode_config->mutex);
99 /* Just fire off a uevent and let userspace tell us what to do */
100 drm_helper_hpd_irq_event(dev);
101}
102
103/**
104 * amdgpu_irq_disable_all - disable *all* interrupts
105 *
106 * @adev: amdgpu device pointer
107 *
108 * Disable all types of interrupts from all sources.
109 */
110void amdgpu_irq_disable_all(struct amdgpu_device *adev)
111{
112 unsigned long irqflags;
113 unsigned i, j, k;
114 int r;
115
116 spin_lock_irqsave(&adev->irq.lock, irqflags);
117 for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) {
118 if (!adev->irq.client[i].sources)
119 continue;
120
121 for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) {
122 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j];
123
124 if (!src || !src->funcs->set || !src->num_types)
125 continue;
126
127 for (k = 0; k < src->num_types; ++k) {
128 atomic_set(&src->enabled_types[k], 0);
129 r = src->funcs->set(adev, src, k,
130 AMDGPU_IRQ_STATE_DISABLE);
131 if (r)
132 DRM_ERROR("error disabling interrupt (%d)\n",
133 r);
134 }
135 }
136 }
137 spin_unlock_irqrestore(&adev->irq.lock, irqflags);
138}
139
140/**
141 * amdgpu_irq_handler - IRQ handler
142 *
143 * @irq: IRQ number (unused)
144 * @arg: pointer to DRM device
145 *
146 * IRQ handler for amdgpu driver (all ASICs).
147 *
148 * Returns:
149 * result of handling the IRQ, as defined by &irqreturn_t
150 */
151irqreturn_t amdgpu_irq_handler(int irq, void *arg)
152{
153 struct drm_device *dev = (struct drm_device *) arg;
154 struct amdgpu_device *adev = dev->dev_private;
155 irqreturn_t ret;
156
157 ret = amdgpu_ih_process(adev, &adev->irq.ih);
158 if (ret == IRQ_HANDLED)
159 pm_runtime_mark_last_busy(dev->dev);
160
161 /* For the hardware that cannot enable bif ring for both ras_controller_irq
162 * and ras_err_evnet_athub_irq ih cookies, the driver has to poll status
163 * register to check whether the interrupt is triggered or not, and properly
164 * ack the interrupt if it is there
165 */
166 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__PCIE_BIF)) {
167 if (adev->nbio.funcs &&
168 adev->nbio.funcs->handle_ras_controller_intr_no_bifring)
169 adev->nbio.funcs->handle_ras_controller_intr_no_bifring(adev);
170
171 if (adev->nbio.funcs &&
172 adev->nbio.funcs->handle_ras_err_event_athub_intr_no_bifring)
173 adev->nbio.funcs->handle_ras_err_event_athub_intr_no_bifring(adev);
174 }
175
176 return ret;
177}
178
179/**
180 * amdgpu_irq_handle_ih1 - kick of processing for IH1
181 *
182 * @work: work structure in struct amdgpu_irq
183 *
184 * Kick of processing IH ring 1.
185 */
186static void amdgpu_irq_handle_ih1(struct work_struct *work)
187{
188 struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
189 irq.ih1_work);
190
191 amdgpu_ih_process(adev, &adev->irq.ih1);
192}
193
194/**
195 * amdgpu_irq_handle_ih2 - kick of processing for IH2
196 *
197 * @work: work structure in struct amdgpu_irq
198 *
199 * Kick of processing IH ring 2.
200 */
201static void amdgpu_irq_handle_ih2(struct work_struct *work)
202{
203 struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
204 irq.ih2_work);
205
206 amdgpu_ih_process(adev, &adev->irq.ih2);
207}
208
209/**
210 * amdgpu_msi_ok - check whether MSI functionality is enabled
211 *
212 * @adev: amdgpu device pointer (unused)
213 *
214 * Checks whether MSI functionality has been disabled via module parameter
215 * (all ASICs).
216 *
217 * Returns:
218 * *true* if MSIs are allowed to be enabled or *false* otherwise
219 */
220static bool amdgpu_msi_ok(struct amdgpu_device *adev)
221{
222 if (amdgpu_msi == 1)
223 return true;
224 else if (amdgpu_msi == 0)
225 return false;
226
227 return true;
228}
229
230/**
231 * amdgpu_irq_init - initialize interrupt handling
232 *
233 * @adev: amdgpu device pointer
234 *
235 * Sets up work functions for hotplug and reset interrupts, enables MSI
236 * functionality, initializes vblank, hotplug and reset interrupt handling.
237 *
238 * Returns:
239 * 0 on success or error code on failure
240 */
241int amdgpu_irq_init(struct amdgpu_device *adev)
242{
243 int r = 0;
244
245 spin_lock_init(&adev->irq.lock);
246
247 /* Enable MSI if not disabled by module parameter */
248 adev->irq.msi_enabled = false;
249
250 if (amdgpu_msi_ok(adev)) {
251 int nvec = pci_msix_vec_count(adev->pdev);
252 unsigned int flags;
253
254 if (nvec <= 0) {
255 flags = PCI_IRQ_MSI;
256 } else {
257 flags = PCI_IRQ_MSI | PCI_IRQ_MSIX;
258 }
259 /* we only need one vector */
260 nvec = pci_alloc_irq_vectors(adev->pdev, 1, 1, flags);
261 if (nvec > 0) {
262 adev->irq.msi_enabled = true;
263 dev_dbg(adev->dev, "using MSI/MSI-X.\n");
264 }
265 }
266
267 if (!amdgpu_device_has_dc_support(adev)) {
268 if (!adev->enable_virtual_display)
269 /* Disable vblank IRQs aggressively for power-saving */
270 /* XXX: can this be enabled for DC? */
271 adev->ddev->vblank_disable_immediate = true;
272
273 r = drm_vblank_init(adev->ddev, adev->mode_info.num_crtc);
274 if (r)
275 return r;
276
277 /* Pre-DCE11 */
278 INIT_WORK(&adev->hotplug_work,
279 amdgpu_hotplug_work_func);
280 }
281
282 INIT_WORK(&adev->irq.ih1_work, amdgpu_irq_handle_ih1);
283 INIT_WORK(&adev->irq.ih2_work, amdgpu_irq_handle_ih2);
284
285 adev->irq.installed = true;
286 /* Use vector 0 for MSI-X */
287 r = drm_irq_install(adev->ddev, pci_irq_vector(adev->pdev, 0));
288 if (r) {
289 adev->irq.installed = false;
290 if (!amdgpu_device_has_dc_support(adev))
291 flush_work(&adev->hotplug_work);
292 return r;
293 }
294 adev->ddev->max_vblank_count = 0x00ffffff;
295
296 DRM_DEBUG("amdgpu: irq initialized.\n");
297 return 0;
298}
299
300/**
301 * amdgpu_irq_fini - shut down interrupt handling
302 *
303 * @adev: amdgpu device pointer
304 *
305 * Tears down work functions for hotplug and reset interrupts, disables MSI
306 * functionality, shuts down vblank, hotplug and reset interrupt handling,
307 * turns off interrupts from all sources (all ASICs).
308 */
309void amdgpu_irq_fini(struct amdgpu_device *adev)
310{
311 unsigned i, j;
312
313 if (adev->irq.installed) {
314 drm_irq_uninstall(adev->ddev);
315 adev->irq.installed = false;
316 if (adev->irq.msi_enabled)
317 pci_free_irq_vectors(adev->pdev);
318 if (!amdgpu_device_has_dc_support(adev))
319 flush_work(&adev->hotplug_work);
320 }
321
322 for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) {
323 if (!adev->irq.client[i].sources)
324 continue;
325
326 for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) {
327 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j];
328
329 if (!src)
330 continue;
331
332 kfree(src->enabled_types);
333 src->enabled_types = NULL;
334 if (src->data) {
335 kfree(src->data);
336 kfree(src);
337 adev->irq.client[i].sources[j] = NULL;
338 }
339 }
340 kfree(adev->irq.client[i].sources);
341 adev->irq.client[i].sources = NULL;
342 }
343}
344
345/**
346 * amdgpu_irq_add_id - register IRQ source
347 *
348 * @adev: amdgpu device pointer
349 * @client_id: client id
350 * @src_id: source id
351 * @source: IRQ source pointer
352 *
353 * Registers IRQ source on a client.
354 *
355 * Returns:
356 * 0 on success or error code otherwise
357 */
358int amdgpu_irq_add_id(struct amdgpu_device *adev,
359 unsigned client_id, unsigned src_id,
360 struct amdgpu_irq_src *source)
361{
362 if (client_id >= AMDGPU_IRQ_CLIENTID_MAX)
363 return -EINVAL;
364
365 if (src_id >= AMDGPU_MAX_IRQ_SRC_ID)
366 return -EINVAL;
367
368 if (!source->funcs)
369 return -EINVAL;
370
371 if (!adev->irq.client[client_id].sources) {
372 adev->irq.client[client_id].sources =
373 kcalloc(AMDGPU_MAX_IRQ_SRC_ID,
374 sizeof(struct amdgpu_irq_src *),
375 GFP_KERNEL);
376 if (!adev->irq.client[client_id].sources)
377 return -ENOMEM;
378 }
379
380 if (adev->irq.client[client_id].sources[src_id] != NULL)
381 return -EINVAL;
382
383 if (source->num_types && !source->enabled_types) {
384 atomic_t *types;
385
386 types = kcalloc(source->num_types, sizeof(atomic_t),
387 GFP_KERNEL);
388 if (!types)
389 return -ENOMEM;
390
391 source->enabled_types = types;
392 }
393
394 adev->irq.client[client_id].sources[src_id] = source;
395 return 0;
396}
397
398/**
399 * amdgpu_irq_dispatch - dispatch IRQ to IP blocks
400 *
401 * @adev: amdgpu device pointer
402 * @ih: interrupt ring instance
403 *
404 * Dispatches IRQ to IP blocks.
405 */
406void amdgpu_irq_dispatch(struct amdgpu_device *adev,
407 struct amdgpu_ih_ring *ih)
408{
409 u32 ring_index = ih->rptr >> 2;
410 struct amdgpu_iv_entry entry;
411 unsigned client_id, src_id;
412 struct amdgpu_irq_src *src;
413 bool handled = false;
414 int r;
415
416 entry.iv_entry = (const uint32_t *)&ih->ring[ring_index];
417 amdgpu_ih_decode_iv(adev, &entry);
418
419 trace_amdgpu_iv(ih - &adev->irq.ih, &entry);
420
421 client_id = entry.client_id;
422 src_id = entry.src_id;
423
424 if (client_id >= AMDGPU_IRQ_CLIENTID_MAX) {
425 DRM_DEBUG("Invalid client_id in IV: %d\n", client_id);
426
427 } else if (src_id >= AMDGPU_MAX_IRQ_SRC_ID) {
428 DRM_DEBUG("Invalid src_id in IV: %d\n", src_id);
429
430 } else if (adev->irq.virq[src_id]) {
431 generic_handle_irq(irq_find_mapping(adev->irq.domain, src_id));
432
433 } else if (!adev->irq.client[client_id].sources) {
434 DRM_DEBUG("Unregistered interrupt client_id: %d src_id: %d\n",
435 client_id, src_id);
436
437 } else if ((src = adev->irq.client[client_id].sources[src_id])) {
438 r = src->funcs->process(adev, src, &entry);
439 if (r < 0)
440 DRM_ERROR("error processing interrupt (%d)\n", r);
441 else if (r)
442 handled = true;
443
444 } else {
445 DRM_DEBUG("Unhandled interrupt src_id: %d\n", src_id);
446 }
447
448 /* Send it to amdkfd as well if it isn't already handled */
449 if (!handled)
450 amdgpu_amdkfd_interrupt(adev, entry.iv_entry);
451}
452
453/**
454 * amdgpu_irq_update - update hardware interrupt state
455 *
456 * @adev: amdgpu device pointer
457 * @src: interrupt source pointer
458 * @type: type of interrupt
459 *
460 * Updates interrupt state for the specific source (all ASICs).
461 */
462int amdgpu_irq_update(struct amdgpu_device *adev,
463 struct amdgpu_irq_src *src, unsigned type)
464{
465 unsigned long irqflags;
466 enum amdgpu_interrupt_state state;
467 int r;
468
469 spin_lock_irqsave(&adev->irq.lock, irqflags);
470
471 /* We need to determine after taking the lock, otherwise
472 we might disable just enabled interrupts again */
473 if (amdgpu_irq_enabled(adev, src, type))
474 state = AMDGPU_IRQ_STATE_ENABLE;
475 else
476 state = AMDGPU_IRQ_STATE_DISABLE;
477
478 r = src->funcs->set(adev, src, type, state);
479 spin_unlock_irqrestore(&adev->irq.lock, irqflags);
480 return r;
481}
482
483/**
484 * amdgpu_irq_gpu_reset_resume_helper - update interrupt states on all sources
485 *
486 * @adev: amdgpu device pointer
487 *
488 * Updates state of all types of interrupts on all sources on resume after
489 * reset.
490 */
491void amdgpu_irq_gpu_reset_resume_helper(struct amdgpu_device *adev)
492{
493 int i, j, k;
494
495 for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) {
496 if (!adev->irq.client[i].sources)
497 continue;
498
499 for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) {
500 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j];
501
502 if (!src)
503 continue;
504 for (k = 0; k < src->num_types; k++)
505 amdgpu_irq_update(adev, src, k);
506 }
507 }
508}
509
510/**
511 * amdgpu_irq_get - enable interrupt
512 *
513 * @adev: amdgpu device pointer
514 * @src: interrupt source pointer
515 * @type: type of interrupt
516 *
517 * Enables specified type of interrupt on the specified source (all ASICs).
518 *
519 * Returns:
520 * 0 on success or error code otherwise
521 */
522int amdgpu_irq_get(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
523 unsigned type)
524{
525 if (!adev->ddev->irq_enabled)
526 return -ENOENT;
527
528 if (type >= src->num_types)
529 return -EINVAL;
530
531 if (!src->enabled_types || !src->funcs->set)
532 return -EINVAL;
533
534 if (atomic_inc_return(&src->enabled_types[type]) == 1)
535 return amdgpu_irq_update(adev, src, type);
536
537 return 0;
538}
539
540/**
541 * amdgpu_irq_put - disable interrupt
542 *
543 * @adev: amdgpu device pointer
544 * @src: interrupt source pointer
545 * @type: type of interrupt
546 *
547 * Enables specified type of interrupt on the specified source (all ASICs).
548 *
549 * Returns:
550 * 0 on success or error code otherwise
551 */
552int amdgpu_irq_put(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
553 unsigned type)
554{
555 if (!adev->ddev->irq_enabled)
556 return -ENOENT;
557
558 if (type >= src->num_types)
559 return -EINVAL;
560
561 if (!src->enabled_types || !src->funcs->set)
562 return -EINVAL;
563
564 if (atomic_dec_and_test(&src->enabled_types[type]))
565 return amdgpu_irq_update(adev, src, type);
566
567 return 0;
568}
569
570/**
571 * amdgpu_irq_enabled - check whether interrupt is enabled or not
572 *
573 * @adev: amdgpu device pointer
574 * @src: interrupt source pointer
575 * @type: type of interrupt
576 *
577 * Checks whether the given type of interrupt is enabled on the given source.
578 *
579 * Returns:
580 * *true* if interrupt is enabled, *false* if interrupt is disabled or on
581 * invalid parameters
582 */
583bool amdgpu_irq_enabled(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
584 unsigned type)
585{
586 if (!adev->ddev->irq_enabled)
587 return false;
588
589 if (type >= src->num_types)
590 return false;
591
592 if (!src->enabled_types || !src->funcs->set)
593 return false;
594
595 return !!atomic_read(&src->enabled_types[type]);
596}
597
598/* XXX: Generic IRQ handling */
599static void amdgpu_irq_mask(struct irq_data *irqd)
600{
601 /* XXX */
602}
603
604static void amdgpu_irq_unmask(struct irq_data *irqd)
605{
606 /* XXX */
607}
608
609/* amdgpu hardware interrupt chip descriptor */
610static struct irq_chip amdgpu_irq_chip = {
611 .name = "amdgpu-ih",
612 .irq_mask = amdgpu_irq_mask,
613 .irq_unmask = amdgpu_irq_unmask,
614};
615
616/**
617 * amdgpu_irqdomain_map - create mapping between virtual and hardware IRQ numbers
618 *
619 * @d: amdgpu IRQ domain pointer (unused)
620 * @irq: virtual IRQ number
621 * @hwirq: hardware irq number
622 *
623 * Current implementation assigns simple interrupt handler to the given virtual
624 * IRQ.
625 *
626 * Returns:
627 * 0 on success or error code otherwise
628 */
629static int amdgpu_irqdomain_map(struct irq_domain *d,
630 unsigned int irq, irq_hw_number_t hwirq)
631{
632 if (hwirq >= AMDGPU_MAX_IRQ_SRC_ID)
633 return -EPERM;
634
635 irq_set_chip_and_handler(irq,
636 &amdgpu_irq_chip, handle_simple_irq);
637 return 0;
638}
639
640/* Implementation of methods for amdgpu IRQ domain */
641static const struct irq_domain_ops amdgpu_hw_irqdomain_ops = {
642 .map = amdgpu_irqdomain_map,
643};
644
645/**
646 * amdgpu_irq_add_domain - create a linear IRQ domain
647 *
648 * @adev: amdgpu device pointer
649 *
650 * Creates an IRQ domain for GPU interrupt sources
651 * that may be driven by another driver (e.g., ACP).
652 *
653 * Returns:
654 * 0 on success or error code otherwise
655 */
656int amdgpu_irq_add_domain(struct amdgpu_device *adev)
657{
658 adev->irq.domain = irq_domain_add_linear(NULL, AMDGPU_MAX_IRQ_SRC_ID,
659 &amdgpu_hw_irqdomain_ops, adev);
660 if (!adev->irq.domain) {
661 DRM_ERROR("GPU irq add domain failed\n");
662 return -ENODEV;
663 }
664
665 return 0;
666}
667
668/**
669 * amdgpu_irq_remove_domain - remove the IRQ domain
670 *
671 * @adev: amdgpu device pointer
672 *
673 * Removes the IRQ domain for GPU interrupt sources
674 * that may be driven by another driver (e.g., ACP).
675 */
676void amdgpu_irq_remove_domain(struct amdgpu_device *adev)
677{
678 if (adev->irq.domain) {
679 irq_domain_remove(adev->irq.domain);
680 adev->irq.domain = NULL;
681 }
682}
683
684/**
685 * amdgpu_irq_create_mapping - create mapping between domain Linux IRQs
686 *
687 * @adev: amdgpu device pointer
688 * @src_id: IH source id
689 *
690 * Creates mapping between a domain IRQ (GPU IH src id) and a Linux IRQ
691 * Use this for components that generate a GPU interrupt, but are driven
692 * by a different driver (e.g., ACP).
693 *
694 * Returns:
695 * Linux IRQ
696 */
697unsigned amdgpu_irq_create_mapping(struct amdgpu_device *adev, unsigned src_id)
698{
699 adev->irq.virq[src_id] = irq_create_mapping(adev->irq.domain, src_id);
700
701 return adev->irq.virq[src_id];
702}
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include <linux/irq.h>
29#include <drm/drmP.h>
30#include <drm/drm_crtc_helper.h>
31#include <drm/amdgpu_drm.h>
32#include "amdgpu.h"
33#include "amdgpu_ih.h"
34#include "atom.h"
35#include "amdgpu_connectors.h"
36
37#include <linux/pm_runtime.h>
38
39#define AMDGPU_WAIT_IDLE_TIMEOUT 200
40
41/*
42 * Handle hotplug events outside the interrupt handler proper.
43 */
44/**
45 * amdgpu_hotplug_work_func - display hotplug work handler
46 *
47 * @work: work struct
48 *
49 * This is the hot plug event work handler (all asics).
50 * The work gets scheduled from the irq handler if there
51 * was a hot plug interrupt. It walks the connector table
52 * and calls the hotplug handler for each one, then sends
53 * a drm hotplug event to alert userspace.
54 */
55static void amdgpu_hotplug_work_func(struct work_struct *work)
56{
57 struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
58 hotplug_work);
59 struct drm_device *dev = adev->ddev;
60 struct drm_mode_config *mode_config = &dev->mode_config;
61 struct drm_connector *connector;
62
63 mutex_lock(&mode_config->mutex);
64 if (mode_config->num_connector) {
65 list_for_each_entry(connector, &mode_config->connector_list, head)
66 amdgpu_connector_hotplug(connector);
67 }
68 mutex_unlock(&mode_config->mutex);
69 /* Just fire off a uevent and let userspace tell us what to do */
70 drm_helper_hpd_irq_event(dev);
71}
72
73/**
74 * amdgpu_irq_reset_work_func - execute gpu reset
75 *
76 * @work: work struct
77 *
78 * Execute scheduled gpu reset (cayman+).
79 * This function is called when the irq handler
80 * thinks we need a gpu reset.
81 */
82static void amdgpu_irq_reset_work_func(struct work_struct *work)
83{
84 struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
85 reset_work);
86
87 amdgpu_gpu_reset(adev);
88}
89
90/* Disable *all* interrupts */
91static void amdgpu_irq_disable_all(struct amdgpu_device *adev)
92{
93 unsigned long irqflags;
94 unsigned i, j;
95 int r;
96
97 spin_lock_irqsave(&adev->irq.lock, irqflags);
98 for (i = 0; i < AMDGPU_MAX_IRQ_SRC_ID; ++i) {
99 struct amdgpu_irq_src *src = adev->irq.sources[i];
100
101 if (!src || !src->funcs->set || !src->num_types)
102 continue;
103
104 for (j = 0; j < src->num_types; ++j) {
105 atomic_set(&src->enabled_types[j], 0);
106 r = src->funcs->set(adev, src, j,
107 AMDGPU_IRQ_STATE_DISABLE);
108 if (r)
109 DRM_ERROR("error disabling interrupt (%d)\n",
110 r);
111 }
112 }
113 spin_unlock_irqrestore(&adev->irq.lock, irqflags);
114}
115
116/**
117 * amdgpu_irq_preinstall - drm irq preinstall callback
118 *
119 * @dev: drm dev pointer
120 *
121 * Gets the hw ready to enable irqs (all asics).
122 * This function disables all interrupt sources on the GPU.
123 */
124void amdgpu_irq_preinstall(struct drm_device *dev)
125{
126 struct amdgpu_device *adev = dev->dev_private;
127
128 /* Disable *all* interrupts */
129 amdgpu_irq_disable_all(adev);
130 /* Clear bits */
131 amdgpu_ih_process(adev);
132}
133
134/**
135 * amdgpu_irq_postinstall - drm irq preinstall callback
136 *
137 * @dev: drm dev pointer
138 *
139 * Handles stuff to be done after enabling irqs (all asics).
140 * Returns 0 on success.
141 */
142int amdgpu_irq_postinstall(struct drm_device *dev)
143{
144 dev->max_vblank_count = 0x00ffffff;
145 return 0;
146}
147
148/**
149 * amdgpu_irq_uninstall - drm irq uninstall callback
150 *
151 * @dev: drm dev pointer
152 *
153 * This function disables all interrupt sources on the GPU (all asics).
154 */
155void amdgpu_irq_uninstall(struct drm_device *dev)
156{
157 struct amdgpu_device *adev = dev->dev_private;
158
159 if (adev == NULL) {
160 return;
161 }
162 amdgpu_irq_disable_all(adev);
163}
164
165/**
166 * amdgpu_irq_handler - irq handler
167 *
168 * @int irq, void *arg: args
169 *
170 * This is the irq handler for the amdgpu driver (all asics).
171 */
172irqreturn_t amdgpu_irq_handler(int irq, void *arg)
173{
174 struct drm_device *dev = (struct drm_device *) arg;
175 struct amdgpu_device *adev = dev->dev_private;
176 irqreturn_t ret;
177
178 ret = amdgpu_ih_process(adev);
179 if (ret == IRQ_HANDLED)
180 pm_runtime_mark_last_busy(dev->dev);
181 return ret;
182}
183
184/**
185 * amdgpu_msi_ok - asic specific msi checks
186 *
187 * @adev: amdgpu device pointer
188 *
189 * Handles asic specific MSI checks to determine if
190 * MSIs should be enabled on a particular chip (all asics).
191 * Returns true if MSIs should be enabled, false if MSIs
192 * should not be enabled.
193 */
194static bool amdgpu_msi_ok(struct amdgpu_device *adev)
195{
196 /* force MSI on */
197 if (amdgpu_msi == 1)
198 return true;
199 else if (amdgpu_msi == 0)
200 return false;
201
202 return true;
203}
204
205/**
206 * amdgpu_irq_init - init driver interrupt info
207 *
208 * @adev: amdgpu device pointer
209 *
210 * Sets up the work irq handlers, vblank init, MSIs, etc. (all asics).
211 * Returns 0 for success, error for failure.
212 */
213int amdgpu_irq_init(struct amdgpu_device *adev)
214{
215 int r = 0;
216
217 spin_lock_init(&adev->irq.lock);
218 r = drm_vblank_init(adev->ddev, adev->mode_info.num_crtc);
219 if (r) {
220 return r;
221 }
222 adev->ddev->vblank_disable_allowed = true;
223
224 /* enable msi */
225 adev->irq.msi_enabled = false;
226
227 if (amdgpu_msi_ok(adev)) {
228 int ret = pci_enable_msi(adev->pdev);
229 if (!ret) {
230 adev->irq.msi_enabled = true;
231 dev_info(adev->dev, "amdgpu: using MSI.\n");
232 }
233 }
234
235 INIT_WORK(&adev->hotplug_work, amdgpu_hotplug_work_func);
236 INIT_WORK(&adev->reset_work, amdgpu_irq_reset_work_func);
237
238 adev->irq.installed = true;
239 r = drm_irq_install(adev->ddev, adev->ddev->pdev->irq);
240 if (r) {
241 adev->irq.installed = false;
242 flush_work(&adev->hotplug_work);
243 return r;
244 }
245
246 DRM_INFO("amdgpu: irq initialized.\n");
247 return 0;
248}
249
250/**
251 * amdgpu_irq_fini - tear down driver interrupt info
252 *
253 * @adev: amdgpu device pointer
254 *
255 * Tears down the work irq handlers, vblank handlers, MSIs, etc. (all asics).
256 */
257void amdgpu_irq_fini(struct amdgpu_device *adev)
258{
259 unsigned i;
260
261 drm_vblank_cleanup(adev->ddev);
262 if (adev->irq.installed) {
263 drm_irq_uninstall(adev->ddev);
264 adev->irq.installed = false;
265 if (adev->irq.msi_enabled)
266 pci_disable_msi(adev->pdev);
267 flush_work(&adev->hotplug_work);
268 }
269
270 for (i = 0; i < AMDGPU_MAX_IRQ_SRC_ID; ++i) {
271 struct amdgpu_irq_src *src = adev->irq.sources[i];
272
273 if (!src)
274 continue;
275
276 kfree(src->enabled_types);
277 src->enabled_types = NULL;
278 if (src->data) {
279 kfree(src->data);
280 kfree(src);
281 adev->irq.sources[i] = NULL;
282 }
283 }
284}
285
286/**
287 * amdgpu_irq_add_id - register irq source
288 *
289 * @adev: amdgpu device pointer
290 * @src_id: source id for this source
291 * @source: irq source
292 *
293 */
294int amdgpu_irq_add_id(struct amdgpu_device *adev, unsigned src_id,
295 struct amdgpu_irq_src *source)
296{
297 if (src_id >= AMDGPU_MAX_IRQ_SRC_ID)
298 return -EINVAL;
299
300 if (adev->irq.sources[src_id] != NULL)
301 return -EINVAL;
302
303 if (!source->funcs)
304 return -EINVAL;
305
306 if (source->num_types && !source->enabled_types) {
307 atomic_t *types;
308
309 types = kcalloc(source->num_types, sizeof(atomic_t),
310 GFP_KERNEL);
311 if (!types)
312 return -ENOMEM;
313
314 source->enabled_types = types;
315 }
316
317 adev->irq.sources[src_id] = source;
318
319 return 0;
320}
321
322/**
323 * amdgpu_irq_dispatch - dispatch irq to IP blocks
324 *
325 * @adev: amdgpu device pointer
326 * @entry: interrupt vector
327 *
328 * Dispatches the irq to the different IP blocks
329 */
330void amdgpu_irq_dispatch(struct amdgpu_device *adev,
331 struct amdgpu_iv_entry *entry)
332{
333 unsigned src_id = entry->src_id;
334 struct amdgpu_irq_src *src;
335 int r;
336
337 if (src_id >= AMDGPU_MAX_IRQ_SRC_ID) {
338 DRM_DEBUG("Invalid src_id in IV: %d\n", src_id);
339 return;
340 }
341
342 if (adev->irq.virq[src_id]) {
343 generic_handle_irq(irq_find_mapping(adev->irq.domain, src_id));
344 } else {
345 src = adev->irq.sources[src_id];
346 if (!src) {
347 DRM_DEBUG("Unhandled interrupt src_id: %d\n", src_id);
348 return;
349 }
350
351 r = src->funcs->process(adev, src, entry);
352 if (r)
353 DRM_ERROR("error processing interrupt (%d)\n", r);
354 }
355}
356
357/**
358 * amdgpu_irq_update - update hw interrupt state
359 *
360 * @adev: amdgpu device pointer
361 * @src: interrupt src you want to enable
362 * @type: type of interrupt you want to update
363 *
364 * Updates the interrupt state for a specific src (all asics).
365 */
366int amdgpu_irq_update(struct amdgpu_device *adev,
367 struct amdgpu_irq_src *src, unsigned type)
368{
369 unsigned long irqflags;
370 enum amdgpu_interrupt_state state;
371 int r;
372
373 spin_lock_irqsave(&adev->irq.lock, irqflags);
374
375 /* we need to determine after taking the lock, otherwise
376 we might disable just enabled interrupts again */
377 if (amdgpu_irq_enabled(adev, src, type))
378 state = AMDGPU_IRQ_STATE_ENABLE;
379 else
380 state = AMDGPU_IRQ_STATE_DISABLE;
381
382 r = src->funcs->set(adev, src, type, state);
383 spin_unlock_irqrestore(&adev->irq.lock, irqflags);
384 return r;
385}
386
387/**
388 * amdgpu_irq_get - enable interrupt
389 *
390 * @adev: amdgpu device pointer
391 * @src: interrupt src you want to enable
392 * @type: type of interrupt you want to enable
393 *
394 * Enables the interrupt type for a specific src (all asics).
395 */
396int amdgpu_irq_get(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
397 unsigned type)
398{
399 if (!adev->ddev->irq_enabled)
400 return -ENOENT;
401
402 if (type >= src->num_types)
403 return -EINVAL;
404
405 if (!src->enabled_types || !src->funcs->set)
406 return -EINVAL;
407
408 if (atomic_inc_return(&src->enabled_types[type]) == 1)
409 return amdgpu_irq_update(adev, src, type);
410
411 return 0;
412}
413
414bool amdgpu_irq_get_delayed(struct amdgpu_device *adev,
415 struct amdgpu_irq_src *src,
416 unsigned type)
417{
418 if ((type >= src->num_types) || !src->enabled_types)
419 return false;
420 return atomic_inc_return(&src->enabled_types[type]) == 1;
421}
422
423/**
424 * amdgpu_irq_put - disable interrupt
425 *
426 * @adev: amdgpu device pointer
427 * @src: interrupt src you want to disable
428 * @type: type of interrupt you want to disable
429 *
430 * Disables the interrupt type for a specific src (all asics).
431 */
432int amdgpu_irq_put(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
433 unsigned type)
434{
435 if (!adev->ddev->irq_enabled)
436 return -ENOENT;
437
438 if (type >= src->num_types)
439 return -EINVAL;
440
441 if (!src->enabled_types || !src->funcs->set)
442 return -EINVAL;
443
444 if (atomic_dec_and_test(&src->enabled_types[type]))
445 return amdgpu_irq_update(adev, src, type);
446
447 return 0;
448}
449
450/**
451 * amdgpu_irq_enabled - test if irq is enabled or not
452 *
453 * @adev: amdgpu device pointer
454 * @idx: interrupt src you want to test
455 *
456 * Tests if the given interrupt source is enabled or not
457 */
458bool amdgpu_irq_enabled(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
459 unsigned type)
460{
461 if (!adev->ddev->irq_enabled)
462 return false;
463
464 if (type >= src->num_types)
465 return false;
466
467 if (!src->enabled_types || !src->funcs->set)
468 return false;
469
470 return !!atomic_read(&src->enabled_types[type]);
471}
472
473/* gen irq */
474static void amdgpu_irq_mask(struct irq_data *irqd)
475{
476 /* XXX */
477}
478
479static void amdgpu_irq_unmask(struct irq_data *irqd)
480{
481 /* XXX */
482}
483
484static struct irq_chip amdgpu_irq_chip = {
485 .name = "amdgpu-ih",
486 .irq_mask = amdgpu_irq_mask,
487 .irq_unmask = amdgpu_irq_unmask,
488};
489
490static int amdgpu_irqdomain_map(struct irq_domain *d,
491 unsigned int irq, irq_hw_number_t hwirq)
492{
493 if (hwirq >= AMDGPU_MAX_IRQ_SRC_ID)
494 return -EPERM;
495
496 irq_set_chip_and_handler(irq,
497 &amdgpu_irq_chip, handle_simple_irq);
498 return 0;
499}
500
501static struct irq_domain_ops amdgpu_hw_irqdomain_ops = {
502 .map = amdgpu_irqdomain_map,
503};
504
505/**
506 * amdgpu_irq_add_domain - create a linear irq domain
507 *
508 * @adev: amdgpu device pointer
509 *
510 * Create an irq domain for GPU interrupt sources
511 * that may be driven by another driver (e.g., ACP).
512 */
513int amdgpu_irq_add_domain(struct amdgpu_device *adev)
514{
515 adev->irq.domain = irq_domain_add_linear(NULL, AMDGPU_MAX_IRQ_SRC_ID,
516 &amdgpu_hw_irqdomain_ops, adev);
517 if (!adev->irq.domain) {
518 DRM_ERROR("GPU irq add domain failed\n");
519 return -ENODEV;
520 }
521
522 return 0;
523}
524
525/**
526 * amdgpu_irq_remove_domain - remove the irq domain
527 *
528 * @adev: amdgpu device pointer
529 *
530 * Remove the irq domain for GPU interrupt sources
531 * that may be driven by another driver (e.g., ACP).
532 */
533void amdgpu_irq_remove_domain(struct amdgpu_device *adev)
534{
535 if (adev->irq.domain) {
536 irq_domain_remove(adev->irq.domain);
537 adev->irq.domain = NULL;
538 }
539}
540
541/**
542 * amdgpu_irq_create_mapping - create a mapping between a domain irq and a
543 * Linux irq
544 *
545 * @adev: amdgpu device pointer
546 * @src_id: IH source id
547 *
548 * Create a mapping between a domain irq (GPU IH src id) and a Linux irq
549 * Use this for components that generate a GPU interrupt, but are driven
550 * by a different driver (e.g., ACP).
551 * Returns the Linux irq.
552 */
553unsigned amdgpu_irq_create_mapping(struct amdgpu_device *adev, unsigned src_id)
554{
555 adev->irq.virq[src_id] = irq_create_mapping(adev->irq.domain, src_id);
556
557 return adev->irq.virq[src_id];
558}