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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * ZTE ZX296702 GPIO driver
4 *
5 * Author: Jun Nie <jun.nie@linaro.org>
6 *
7 * Copyright (C) 2015 Linaro Ltd.
8 */
9#include <linux/bitops.h>
10#include <linux/device.h>
11#include <linux/errno.h>
12#include <linux/gpio/driver.h>
13#include <linux/irqchip/chained_irq.h>
14#include <linux/init.h>
15#include <linux/of.h>
16#include <linux/pinctrl/consumer.h>
17#include <linux/platform_device.h>
18#include <linux/pm.h>
19#include <linux/slab.h>
20#include <linux/spinlock.h>
21
22#define ZX_GPIO_DIR 0x00
23#define ZX_GPIO_IVE 0x04
24#define ZX_GPIO_IV 0x08
25#define ZX_GPIO_IEP 0x0C
26#define ZX_GPIO_IEN 0x10
27#define ZX_GPIO_DI 0x14
28#define ZX_GPIO_DO1 0x18
29#define ZX_GPIO_DO0 0x1C
30#define ZX_GPIO_DO 0x20
31
32#define ZX_GPIO_IM 0x28
33#define ZX_GPIO_IE 0x2C
34
35#define ZX_GPIO_MIS 0x30
36#define ZX_GPIO_IC 0x34
37
38#define ZX_GPIO_NR 16
39
40struct zx_gpio {
41 raw_spinlock_t lock;
42
43 void __iomem *base;
44 struct gpio_chip gc;
45};
46
47static int zx_direction_input(struct gpio_chip *gc, unsigned offset)
48{
49 struct zx_gpio *chip = gpiochip_get_data(gc);
50 unsigned long flags;
51 u16 gpiodir;
52
53 if (offset >= gc->ngpio)
54 return -EINVAL;
55
56 raw_spin_lock_irqsave(&chip->lock, flags);
57 gpiodir = readw_relaxed(chip->base + ZX_GPIO_DIR);
58 gpiodir &= ~BIT(offset);
59 writew_relaxed(gpiodir, chip->base + ZX_GPIO_DIR);
60 raw_spin_unlock_irqrestore(&chip->lock, flags);
61
62 return 0;
63}
64
65static int zx_direction_output(struct gpio_chip *gc, unsigned offset,
66 int value)
67{
68 struct zx_gpio *chip = gpiochip_get_data(gc);
69 unsigned long flags;
70 u16 gpiodir;
71
72 if (offset >= gc->ngpio)
73 return -EINVAL;
74
75 raw_spin_lock_irqsave(&chip->lock, flags);
76 gpiodir = readw_relaxed(chip->base + ZX_GPIO_DIR);
77 gpiodir |= BIT(offset);
78 writew_relaxed(gpiodir, chip->base + ZX_GPIO_DIR);
79
80 if (value)
81 writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO1);
82 else
83 writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO0);
84 raw_spin_unlock_irqrestore(&chip->lock, flags);
85
86 return 0;
87}
88
89static int zx_get_value(struct gpio_chip *gc, unsigned offset)
90{
91 struct zx_gpio *chip = gpiochip_get_data(gc);
92
93 return !!(readw_relaxed(chip->base + ZX_GPIO_DI) & BIT(offset));
94}
95
96static void zx_set_value(struct gpio_chip *gc, unsigned offset, int value)
97{
98 struct zx_gpio *chip = gpiochip_get_data(gc);
99
100 if (value)
101 writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO1);
102 else
103 writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO0);
104}
105
106static int zx_irq_type(struct irq_data *d, unsigned trigger)
107{
108 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
109 struct zx_gpio *chip = gpiochip_get_data(gc);
110 int offset = irqd_to_hwirq(d);
111 unsigned long flags;
112 u16 gpiois, gpioi_epos, gpioi_eneg, gpioiev;
113 u16 bit = BIT(offset);
114
115 if (offset < 0 || offset >= ZX_GPIO_NR)
116 return -EINVAL;
117
118 raw_spin_lock_irqsave(&chip->lock, flags);
119
120 gpioiev = readw_relaxed(chip->base + ZX_GPIO_IV);
121 gpiois = readw_relaxed(chip->base + ZX_GPIO_IVE);
122 gpioi_epos = readw_relaxed(chip->base + ZX_GPIO_IEP);
123 gpioi_eneg = readw_relaxed(chip->base + ZX_GPIO_IEN);
124
125 if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
126 gpiois |= bit;
127 if (trigger & IRQ_TYPE_LEVEL_HIGH)
128 gpioiev |= bit;
129 else
130 gpioiev &= ~bit;
131 } else
132 gpiois &= ~bit;
133
134 if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
135 gpioi_epos |= bit;
136 gpioi_eneg |= bit;
137 } else {
138 if (trigger & IRQ_TYPE_EDGE_RISING) {
139 gpioi_epos |= bit;
140 gpioi_eneg &= ~bit;
141 } else if (trigger & IRQ_TYPE_EDGE_FALLING) {
142 gpioi_eneg |= bit;
143 gpioi_epos &= ~bit;
144 }
145 }
146
147 writew_relaxed(gpiois, chip->base + ZX_GPIO_IVE);
148 writew_relaxed(gpioi_epos, chip->base + ZX_GPIO_IEP);
149 writew_relaxed(gpioi_eneg, chip->base + ZX_GPIO_IEN);
150 writew_relaxed(gpioiev, chip->base + ZX_GPIO_IV);
151 raw_spin_unlock_irqrestore(&chip->lock, flags);
152
153 return 0;
154}
155
156static void zx_irq_handler(struct irq_desc *desc)
157{
158 unsigned long pending;
159 int offset;
160 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
161 struct zx_gpio *chip = gpiochip_get_data(gc);
162 struct irq_chip *irqchip = irq_desc_get_chip(desc);
163
164 chained_irq_enter(irqchip, desc);
165
166 pending = readw_relaxed(chip->base + ZX_GPIO_MIS);
167 writew_relaxed(pending, chip->base + ZX_GPIO_IC);
168 if (pending) {
169 for_each_set_bit(offset, &pending, ZX_GPIO_NR)
170 generic_handle_irq(irq_find_mapping(gc->irq.domain,
171 offset));
172 }
173
174 chained_irq_exit(irqchip, desc);
175}
176
177static void zx_irq_mask(struct irq_data *d)
178{
179 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
180 struct zx_gpio *chip = gpiochip_get_data(gc);
181 u16 mask = BIT(irqd_to_hwirq(d) % ZX_GPIO_NR);
182 u16 gpioie;
183
184 raw_spin_lock(&chip->lock);
185 gpioie = readw_relaxed(chip->base + ZX_GPIO_IM) | mask;
186 writew_relaxed(gpioie, chip->base + ZX_GPIO_IM);
187 gpioie = readw_relaxed(chip->base + ZX_GPIO_IE) & ~mask;
188 writew_relaxed(gpioie, chip->base + ZX_GPIO_IE);
189 raw_spin_unlock(&chip->lock);
190}
191
192static void zx_irq_unmask(struct irq_data *d)
193{
194 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
195 struct zx_gpio *chip = gpiochip_get_data(gc);
196 u16 mask = BIT(irqd_to_hwirq(d) % ZX_GPIO_NR);
197 u16 gpioie;
198
199 raw_spin_lock(&chip->lock);
200 gpioie = readw_relaxed(chip->base + ZX_GPIO_IM) & ~mask;
201 writew_relaxed(gpioie, chip->base + ZX_GPIO_IM);
202 gpioie = readw_relaxed(chip->base + ZX_GPIO_IE) | mask;
203 writew_relaxed(gpioie, chip->base + ZX_GPIO_IE);
204 raw_spin_unlock(&chip->lock);
205}
206
207static struct irq_chip zx_irqchip = {
208 .name = "zx-gpio",
209 .irq_mask = zx_irq_mask,
210 .irq_unmask = zx_irq_unmask,
211 .irq_set_type = zx_irq_type,
212};
213
214static int zx_gpio_probe(struct platform_device *pdev)
215{
216 struct device *dev = &pdev->dev;
217 struct zx_gpio *chip;
218 struct gpio_irq_chip *girq;
219 int irq, id, ret;
220
221 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
222 if (!chip)
223 return -ENOMEM;
224
225 chip->base = devm_platform_ioremap_resource(pdev, 0);
226 if (IS_ERR(chip->base))
227 return PTR_ERR(chip->base);
228
229 id = of_alias_get_id(dev->of_node, "gpio");
230
231 raw_spin_lock_init(&chip->lock);
232 chip->gc.request = gpiochip_generic_request;
233 chip->gc.free = gpiochip_generic_free;
234 chip->gc.direction_input = zx_direction_input;
235 chip->gc.direction_output = zx_direction_output;
236 chip->gc.get = zx_get_value;
237 chip->gc.set = zx_set_value;
238 chip->gc.base = ZX_GPIO_NR * id;
239 chip->gc.ngpio = ZX_GPIO_NR;
240 chip->gc.label = dev_name(dev);
241 chip->gc.parent = dev;
242 chip->gc.owner = THIS_MODULE;
243
244 /*
245 * irq_chip support
246 */
247 writew_relaxed(0xffff, chip->base + ZX_GPIO_IM);
248 writew_relaxed(0, chip->base + ZX_GPIO_IE);
249 irq = platform_get_irq(pdev, 0);
250 if (irq < 0)
251 return irq;
252 girq = &chip->gc.irq;
253 girq->chip = &zx_irqchip;
254 girq->parent_handler = zx_irq_handler;
255 girq->num_parents = 1;
256 girq->parents = devm_kcalloc(&pdev->dev, 1,
257 sizeof(*girq->parents),
258 GFP_KERNEL);
259 if (!girq->parents)
260 return -ENOMEM;
261 girq->parents[0] = irq;
262 girq->default_type = IRQ_TYPE_NONE;
263 girq->handler = handle_simple_irq;
264
265 ret = gpiochip_add_data(&chip->gc, chip);
266 if (ret)
267 return ret;
268
269 platform_set_drvdata(pdev, chip);
270 dev_info(dev, "ZX GPIO chip registered\n");
271
272 return 0;
273}
274
275static const struct of_device_id zx_gpio_match[] = {
276 {
277 .compatible = "zte,zx296702-gpio",
278 },
279 { },
280};
281
282static struct platform_driver zx_gpio_driver = {
283 .probe = zx_gpio_probe,
284 .driver = {
285 .name = "zx_gpio",
286 .of_match_table = of_match_ptr(zx_gpio_match),
287 },
288};
289builtin_platform_driver(zx_gpio_driver)
1/*
2 * Copyright (C) 2015 Linaro Ltd.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8#include <linux/bitops.h>
9#include <linux/device.h>
10#include <linux/errno.h>
11#include <linux/gpio/driver.h>
12#include <linux/irqchip/chained_irq.h>
13#include <linux/module.h>
14#include <linux/of.h>
15#include <linux/pinctrl/consumer.h>
16#include <linux/platform_device.h>
17#include <linux/pm.h>
18#include <linux/slab.h>
19#include <linux/spinlock.h>
20
21#define ZX_GPIO_DIR 0x00
22#define ZX_GPIO_IVE 0x04
23#define ZX_GPIO_IV 0x08
24#define ZX_GPIO_IEP 0x0C
25#define ZX_GPIO_IEN 0x10
26#define ZX_GPIO_DI 0x14
27#define ZX_GPIO_DO1 0x18
28#define ZX_GPIO_DO0 0x1C
29#define ZX_GPIO_DO 0x20
30
31#define ZX_GPIO_IM 0x28
32#define ZX_GPIO_IE 0x2C
33
34#define ZX_GPIO_MIS 0x30
35#define ZX_GPIO_IC 0x34
36
37#define ZX_GPIO_NR 16
38
39struct zx_gpio {
40 spinlock_t lock;
41
42 void __iomem *base;
43 struct gpio_chip gc;
44};
45
46static int zx_direction_input(struct gpio_chip *gc, unsigned offset)
47{
48 struct zx_gpio *chip = gpiochip_get_data(gc);
49 unsigned long flags;
50 u16 gpiodir;
51
52 if (offset >= gc->ngpio)
53 return -EINVAL;
54
55 spin_lock_irqsave(&chip->lock, flags);
56 gpiodir = readw_relaxed(chip->base + ZX_GPIO_DIR);
57 gpiodir &= ~BIT(offset);
58 writew_relaxed(gpiodir, chip->base + ZX_GPIO_DIR);
59 spin_unlock_irqrestore(&chip->lock, flags);
60
61 return 0;
62}
63
64static int zx_direction_output(struct gpio_chip *gc, unsigned offset,
65 int value)
66{
67 struct zx_gpio *chip = gpiochip_get_data(gc);
68 unsigned long flags;
69 u16 gpiodir;
70
71 if (offset >= gc->ngpio)
72 return -EINVAL;
73
74 spin_lock_irqsave(&chip->lock, flags);
75 gpiodir = readw_relaxed(chip->base + ZX_GPIO_DIR);
76 gpiodir |= BIT(offset);
77 writew_relaxed(gpiodir, chip->base + ZX_GPIO_DIR);
78
79 if (value)
80 writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO1);
81 else
82 writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO0);
83 spin_unlock_irqrestore(&chip->lock, flags);
84
85 return 0;
86}
87
88static int zx_get_value(struct gpio_chip *gc, unsigned offset)
89{
90 struct zx_gpio *chip = gpiochip_get_data(gc);
91
92 return !!(readw_relaxed(chip->base + ZX_GPIO_DI) & BIT(offset));
93}
94
95static void zx_set_value(struct gpio_chip *gc, unsigned offset, int value)
96{
97 struct zx_gpio *chip = gpiochip_get_data(gc);
98
99 if (value)
100 writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO1);
101 else
102 writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO0);
103}
104
105static int zx_irq_type(struct irq_data *d, unsigned trigger)
106{
107 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
108 struct zx_gpio *chip = gpiochip_get_data(gc);
109 int offset = irqd_to_hwirq(d);
110 unsigned long flags;
111 u16 gpiois, gpioi_epos, gpioi_eneg, gpioiev;
112 u16 bit = BIT(offset);
113
114 if (offset < 0 || offset >= ZX_GPIO_NR)
115 return -EINVAL;
116
117 spin_lock_irqsave(&chip->lock, flags);
118
119 gpioiev = readw_relaxed(chip->base + ZX_GPIO_IV);
120 gpiois = readw_relaxed(chip->base + ZX_GPIO_IVE);
121 gpioi_epos = readw_relaxed(chip->base + ZX_GPIO_IEP);
122 gpioi_eneg = readw_relaxed(chip->base + ZX_GPIO_IEN);
123
124 if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
125 gpiois |= bit;
126 if (trigger & IRQ_TYPE_LEVEL_HIGH)
127 gpioiev |= bit;
128 else
129 gpioiev &= ~bit;
130 } else
131 gpiois &= ~bit;
132
133 if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
134 gpioi_epos |= bit;
135 gpioi_eneg |= bit;
136 } else {
137 if (trigger & IRQ_TYPE_EDGE_RISING) {
138 gpioi_epos |= bit;
139 gpioi_eneg &= ~bit;
140 } else if (trigger & IRQ_TYPE_EDGE_FALLING) {
141 gpioi_eneg |= bit;
142 gpioi_epos &= ~bit;
143 }
144 }
145
146 writew_relaxed(gpiois, chip->base + ZX_GPIO_IVE);
147 writew_relaxed(gpioi_epos, chip->base + ZX_GPIO_IEP);
148 writew_relaxed(gpioi_eneg, chip->base + ZX_GPIO_IEN);
149 writew_relaxed(gpioiev, chip->base + ZX_GPIO_IV);
150 spin_unlock_irqrestore(&chip->lock, flags);
151
152 return 0;
153}
154
155static void zx_irq_handler(struct irq_desc *desc)
156{
157 unsigned long pending;
158 int offset;
159 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
160 struct zx_gpio *chip = gpiochip_get_data(gc);
161 struct irq_chip *irqchip = irq_desc_get_chip(desc);
162
163 chained_irq_enter(irqchip, desc);
164
165 pending = readw_relaxed(chip->base + ZX_GPIO_MIS);
166 writew_relaxed(pending, chip->base + ZX_GPIO_IC);
167 if (pending) {
168 for_each_set_bit(offset, &pending, ZX_GPIO_NR)
169 generic_handle_irq(irq_find_mapping(gc->irqdomain,
170 offset));
171 }
172
173 chained_irq_exit(irqchip, desc);
174}
175
176static void zx_irq_mask(struct irq_data *d)
177{
178 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
179 struct zx_gpio *chip = gpiochip_get_data(gc);
180 u16 mask = BIT(irqd_to_hwirq(d) % ZX_GPIO_NR);
181 u16 gpioie;
182
183 spin_lock(&chip->lock);
184 gpioie = readw_relaxed(chip->base + ZX_GPIO_IM) | mask;
185 writew_relaxed(gpioie, chip->base + ZX_GPIO_IM);
186 gpioie = readw_relaxed(chip->base + ZX_GPIO_IE) & ~mask;
187 writew_relaxed(gpioie, chip->base + ZX_GPIO_IE);
188 spin_unlock(&chip->lock);
189}
190
191static void zx_irq_unmask(struct irq_data *d)
192{
193 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
194 struct zx_gpio *chip = gpiochip_get_data(gc);
195 u16 mask = BIT(irqd_to_hwirq(d) % ZX_GPIO_NR);
196 u16 gpioie;
197
198 spin_lock(&chip->lock);
199 gpioie = readw_relaxed(chip->base + ZX_GPIO_IM) & ~mask;
200 writew_relaxed(gpioie, chip->base + ZX_GPIO_IM);
201 gpioie = readw_relaxed(chip->base + ZX_GPIO_IE) | mask;
202 writew_relaxed(gpioie, chip->base + ZX_GPIO_IE);
203 spin_unlock(&chip->lock);
204}
205
206static struct irq_chip zx_irqchip = {
207 .name = "zx-gpio",
208 .irq_mask = zx_irq_mask,
209 .irq_unmask = zx_irq_unmask,
210 .irq_set_type = zx_irq_type,
211};
212
213static int zx_gpio_probe(struct platform_device *pdev)
214{
215 struct device *dev = &pdev->dev;
216 struct zx_gpio *chip;
217 struct resource *res;
218 int irq, id, ret;
219
220 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
221 if (!chip)
222 return -ENOMEM;
223
224 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
225 chip->base = devm_ioremap_resource(dev, res);
226 if (IS_ERR(chip->base))
227 return PTR_ERR(chip->base);
228
229 spin_lock_init(&chip->lock);
230 if (of_property_read_bool(dev->of_node, "gpio-ranges")) {
231 chip->gc.request = gpiochip_generic_request;
232 chip->gc.free = gpiochip_generic_free;
233 }
234
235 id = of_alias_get_id(dev->of_node, "gpio");
236 chip->gc.direction_input = zx_direction_input;
237 chip->gc.direction_output = zx_direction_output;
238 chip->gc.get = zx_get_value;
239 chip->gc.set = zx_set_value;
240 chip->gc.base = ZX_GPIO_NR * id;
241 chip->gc.ngpio = ZX_GPIO_NR;
242 chip->gc.label = dev_name(dev);
243 chip->gc.parent = dev;
244 chip->gc.owner = THIS_MODULE;
245
246 ret = gpiochip_add_data(&chip->gc, chip);
247 if (ret)
248 return ret;
249
250 /*
251 * irq_chip support
252 */
253 writew_relaxed(0xffff, chip->base + ZX_GPIO_IM);
254 writew_relaxed(0, chip->base + ZX_GPIO_IE);
255 irq = platform_get_irq(pdev, 0);
256 if (irq < 0) {
257 dev_err(dev, "invalid IRQ\n");
258 gpiochip_remove(&chip->gc);
259 return -ENODEV;
260 }
261
262 ret = gpiochip_irqchip_add(&chip->gc, &zx_irqchip,
263 0, handle_simple_irq,
264 IRQ_TYPE_NONE);
265 if (ret) {
266 dev_err(dev, "could not add irqchip\n");
267 gpiochip_remove(&chip->gc);
268 return ret;
269 }
270 gpiochip_set_chained_irqchip(&chip->gc, &zx_irqchip,
271 irq, zx_irq_handler);
272
273 platform_set_drvdata(pdev, chip);
274 dev_info(dev, "ZX GPIO chip registered\n");
275
276 return 0;
277}
278
279static const struct of_device_id zx_gpio_match[] = {
280 {
281 .compatible = "zte,zx296702-gpio",
282 },
283 { },
284};
285MODULE_DEVICE_TABLE(of, zx_gpio_match);
286
287static struct platform_driver zx_gpio_driver = {
288 .probe = zx_gpio_probe,
289 .driver = {
290 .name = "zx_gpio",
291 .of_match_table = of_match_ptr(zx_gpio_match),
292 },
293};
294
295module_platform_driver(zx_gpio_driver)
296
297MODULE_AUTHOR("Jun Nie <jun.nie@linaro.org>");
298MODULE_DESCRIPTION("ZTE ZX296702 GPIO driver");
299MODULE_LICENSE("GPL");