1/* SPDX-License-Identifier: GPL-2.0-or-later */
   2/*
   3 *  Boot code and exception vectors for Book3E processors
   4 *
   5 *  Copyright (C) 2007 Ben. Herrenschmidt (benh@kernel.crashing.org), IBM Corp.
 
 
 
 
 
   6 */
   7
   8#include <linux/threads.h>
   9#include <asm/reg.h>
  10#include <asm/page.h>
  11#include <asm/ppc_asm.h>
  12#include <asm/asm-offsets.h>
  13#include <asm/cputable.h>
  14#include <asm/setup.h>
  15#include <asm/thread_info.h>
  16#include <asm/reg_a2.h>
  17#include <asm/exception-64e.h>
  18#include <asm/bug.h>
  19#include <asm/irqflags.h>
  20#include <asm/ptrace.h>
  21#include <asm/ppc-opcode.h>
  22#include <asm/mmu.h>
  23#include <asm/hw_irq.h>
  24#include <asm/kvm_asm.h>
  25#include <asm/kvm_booke_hv_asm.h>
  26#include <asm/feature-fixups.h>
  27#include <asm/context_tracking.h>
  28
  29/* XXX This will ultimately add space for a special exception save
  30 *     structure used to save things like SRR0/SRR1, SPRGs, MAS, etc...
  31 *     when taking special interrupts. For now we don't support that,
  32 *     special interrupts from within a non-standard level will probably
  33 *     blow you up
  34 */
  35#define SPECIAL_EXC_SRR0	0
  36#define SPECIAL_EXC_SRR1	1
  37#define SPECIAL_EXC_SPRG_GEN	2
  38#define SPECIAL_EXC_SPRG_TLB	3
  39#define SPECIAL_EXC_MAS0	4
  40#define SPECIAL_EXC_MAS1	5
  41#define SPECIAL_EXC_MAS2	6
  42#define SPECIAL_EXC_MAS3	7
  43#define SPECIAL_EXC_MAS6	8
  44#define SPECIAL_EXC_MAS7	9
  45#define SPECIAL_EXC_MAS5	10	/* E.HV only */
  46#define SPECIAL_EXC_MAS8	11	/* E.HV only */
  47#define SPECIAL_EXC_IRQHAPPENED	12
  48#define SPECIAL_EXC_DEAR	13
  49#define SPECIAL_EXC_ESR		14
  50#define SPECIAL_EXC_SOFTE	15
  51#define SPECIAL_EXC_CSRR0	16
  52#define SPECIAL_EXC_CSRR1	17
  53/* must be even to keep 16-byte stack alignment */
  54#define SPECIAL_EXC_END		18
  55
  56#define SPECIAL_EXC_FRAME_SIZE	(INT_FRAME_SIZE + SPECIAL_EXC_END * 8)
  57#define SPECIAL_EXC_FRAME_OFFS  (INT_FRAME_SIZE - 288)
  58
  59#define SPECIAL_EXC_STORE(reg, name) \
  60	std	reg, (SPECIAL_EXC_##name * 8 + SPECIAL_EXC_FRAME_OFFS)(r1)
  61
  62#define SPECIAL_EXC_LOAD(reg, name) \
  63	ld	reg, (SPECIAL_EXC_##name * 8 + SPECIAL_EXC_FRAME_OFFS)(r1)
  64
  65special_reg_save:
  66	lbz	r9,PACAIRQHAPPENED(r13)
  67	RECONCILE_IRQ_STATE(r3,r4)
  68
  69	/*
  70	 * We only need (or have stack space) to save this stuff if
  71	 * we interrupted the kernel.
  72	 */
  73	ld	r3,_MSR(r1)
  74	andi.	r3,r3,MSR_PR
  75	bnelr
  76
 
 
 
 
 
 
 
 
 
 
 
  77	/*
  78	 * Advance to the next TLB exception frame for handler
  79	 * types that don't do it automatically.
  80	 */
  81	LOAD_REG_ADDR(r11,extlb_level_exc)
  82	lwz	r12,0(r11)
  83	mfspr	r10,SPRN_SPRG_TLB_EXFRAME
  84	add	r10,r10,r12
  85	mtspr	SPRN_SPRG_TLB_EXFRAME,r10
  86
  87	/*
  88	 * Save registers needed to allow nesting of certain exceptions
  89	 * (such as TLB misses) inside special exception levels
  90	 */
  91	mfspr	r10,SPRN_SRR0
  92	SPECIAL_EXC_STORE(r10,SRR0)
  93	mfspr	r10,SPRN_SRR1
  94	SPECIAL_EXC_STORE(r10,SRR1)
  95	mfspr	r10,SPRN_SPRG_GEN_SCRATCH
  96	SPECIAL_EXC_STORE(r10,SPRG_GEN)
  97	mfspr	r10,SPRN_SPRG_TLB_SCRATCH
  98	SPECIAL_EXC_STORE(r10,SPRG_TLB)
  99	mfspr	r10,SPRN_MAS0
 100	SPECIAL_EXC_STORE(r10,MAS0)
 101	mfspr	r10,SPRN_MAS1
 102	SPECIAL_EXC_STORE(r10,MAS1)
 103	mfspr	r10,SPRN_MAS2
 104	SPECIAL_EXC_STORE(r10,MAS2)
 105	mfspr	r10,SPRN_MAS3
 106	SPECIAL_EXC_STORE(r10,MAS3)
 107	mfspr	r10,SPRN_MAS6
 108	SPECIAL_EXC_STORE(r10,MAS6)
 109	mfspr	r10,SPRN_MAS7
 110	SPECIAL_EXC_STORE(r10,MAS7)
 111BEGIN_FTR_SECTION
 112	mfspr	r10,SPRN_MAS5
 113	SPECIAL_EXC_STORE(r10,MAS5)
 114	mfspr	r10,SPRN_MAS8
 115	SPECIAL_EXC_STORE(r10,MAS8)
 116
 117	/* MAS5/8 could have inappropriate values if we interrupted KVM code */
 118	li	r10,0
 119	mtspr	SPRN_MAS5,r10
 120	mtspr	SPRN_MAS8,r10
 121END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
 122	SPECIAL_EXC_STORE(r9,IRQHAPPENED)
 123
 124	mfspr	r10,SPRN_DEAR
 125	SPECIAL_EXC_STORE(r10,DEAR)
 126	mfspr	r10,SPRN_ESR
 127	SPECIAL_EXC_STORE(r10,ESR)
 128
 129	lbz	r10,PACAIRQSOFTMASK(r13)
 130	SPECIAL_EXC_STORE(r10,SOFTE)
 131	ld	r10,_NIP(r1)
 132	SPECIAL_EXC_STORE(r10,CSRR0)
 133	ld	r10,_MSR(r1)
 134	SPECIAL_EXC_STORE(r10,CSRR1)
 135
 136	blr
 137
 138ret_from_level_except:
 139	ld	r3,_MSR(r1)
 140	andi.	r3,r3,MSR_PR
 141	beq	1f
 142	b	ret_from_except
 1431:
 144
 145	LOAD_REG_ADDR(r11,extlb_level_exc)
 146	lwz	r12,0(r11)
 147	mfspr	r10,SPRN_SPRG_TLB_EXFRAME
 148	sub	r10,r10,r12
 149	mtspr	SPRN_SPRG_TLB_EXFRAME,r10
 150
 151	/*
 152	 * It's possible that the special level exception interrupted a
 153	 * TLB miss handler, and inserted the same entry that the
 154	 * interrupted handler was about to insert.  On CPUs without TLB
 155	 * write conditional, this can result in a duplicate TLB entry.
 156	 * Wipe all non-bolted entries to be safe.
 157	 *
 158	 * Note that this doesn't protect against any TLB misses
 159	 * we may take accessing the stack from here to the end of
 160	 * the special level exception.  It's not clear how we can
 161	 * reasonably protect against that, but only CPUs with
 162	 * neither TLB write conditional nor bolted kernel memory
 163	 * are affected.  Do any such CPUs even exist?
 164	 */
 165	PPC_TLBILX_ALL(0,R0)
 166
 167	REST_NVGPRS(r1)
 168
 169	SPECIAL_EXC_LOAD(r10,SRR0)
 170	mtspr	SPRN_SRR0,r10
 171	SPECIAL_EXC_LOAD(r10,SRR1)
 172	mtspr	SPRN_SRR1,r10
 173	SPECIAL_EXC_LOAD(r10,SPRG_GEN)
 174	mtspr	SPRN_SPRG_GEN_SCRATCH,r10
 175	SPECIAL_EXC_LOAD(r10,SPRG_TLB)
 176	mtspr	SPRN_SPRG_TLB_SCRATCH,r10
 177	SPECIAL_EXC_LOAD(r10,MAS0)
 178	mtspr	SPRN_MAS0,r10
 179	SPECIAL_EXC_LOAD(r10,MAS1)
 180	mtspr	SPRN_MAS1,r10
 181	SPECIAL_EXC_LOAD(r10,MAS2)
 182	mtspr	SPRN_MAS2,r10
 183	SPECIAL_EXC_LOAD(r10,MAS3)
 184	mtspr	SPRN_MAS3,r10
 185	SPECIAL_EXC_LOAD(r10,MAS6)
 186	mtspr	SPRN_MAS6,r10
 187	SPECIAL_EXC_LOAD(r10,MAS7)
 188	mtspr	SPRN_MAS7,r10
 189BEGIN_FTR_SECTION
 190	SPECIAL_EXC_LOAD(r10,MAS5)
 191	mtspr	SPRN_MAS5,r10
 192	SPECIAL_EXC_LOAD(r10,MAS8)
 193	mtspr	SPRN_MAS8,r10
 194END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
 195
 196	lbz	r6,PACAIRQSOFTMASK(r13)
 197	ld	r5,SOFTE(r1)
 198
 199	/* Interrupts had better not already be enabled... */
 200	tweqi	r6,IRQS_ENABLED
 201
 202	andi.	r6,r5,IRQS_DISABLED
 203	bne	1f
 204
 205	TRACE_ENABLE_INTS
 206	stb	r5,PACAIRQSOFTMASK(r13)
 2071:
 208	/*
 209	 * Restore PACAIRQHAPPENED rather than setting it based on
 210	 * the return MSR[EE], since we could have interrupted
 211	 * __check_irq_replay() or other inconsistent transitory
 212	 * states that must remain that way.
 213	 */
 214	SPECIAL_EXC_LOAD(r10,IRQHAPPENED)
 215	stb	r10,PACAIRQHAPPENED(r13)
 216
 217	SPECIAL_EXC_LOAD(r10,DEAR)
 218	mtspr	SPRN_DEAR,r10
 219	SPECIAL_EXC_LOAD(r10,ESR)
 220	mtspr	SPRN_ESR,r10
 221
 222	stdcx.	r0,0,r1		/* to clear the reservation */
 223
 224	REST_4GPRS(2, r1)
 225	REST_4GPRS(6, r1)
 226
 227	ld	r10,_CTR(r1)
 228	ld	r11,_XER(r1)
 229	mtctr	r10
 230	mtxer	r11
 231
 232	blr
 233
 234.macro ret_from_level srr0 srr1 paca_ex scratch
 235	bl	ret_from_level_except
 236
 237	ld	r10,_LINK(r1)
 238	ld	r11,_CCR(r1)
 239	ld	r0,GPR13(r1)
 240	mtlr	r10
 241	mtcr	r11
 242
 243	ld	r10,GPR10(r1)
 244	ld	r11,GPR11(r1)
 245	ld	r12,GPR12(r1)
 246	mtspr	\scratch,r0
 247
 248	std	r10,\paca_ex+EX_R10(r13);
 249	std	r11,\paca_ex+EX_R11(r13);
 250	ld	r10,_NIP(r1)
 251	ld	r11,_MSR(r1)
 252	ld	r0,GPR0(r1)
 253	ld	r1,GPR1(r1)
 254	mtspr	\srr0,r10
 255	mtspr	\srr1,r11
 256	ld	r10,\paca_ex+EX_R10(r13)
 257	ld	r11,\paca_ex+EX_R11(r13)
 258	mfspr	r13,\scratch
 259.endm
 260
 261ret_from_crit_except:
 262	ret_from_level SPRN_CSRR0 SPRN_CSRR1 PACA_EXCRIT SPRN_SPRG_CRIT_SCRATCH
 263	rfci
 264
 265ret_from_mc_except:
 266	ret_from_level SPRN_MCSRR0 SPRN_MCSRR1 PACA_EXMC SPRN_SPRG_MC_SCRATCH
 267	rfmci
 268
 269/* Exception prolog code for all exceptions */
 270#define EXCEPTION_PROLOG(n, intnum, type, addition)	    		    \
 271	mtspr	SPRN_SPRG_##type##_SCRATCH,r13;	/* get spare registers */   \
 272	mfspr	r13,SPRN_SPRG_PACA;	/* get PACA */			    \
 273	std	r10,PACA_EX##type+EX_R10(r13);				    \
 274	std	r11,PACA_EX##type+EX_R11(r13);				    \
 275	mfcr	r10;			/* save CR */			    \
 276	mfspr	r11,SPRN_##type##_SRR1;/* what are we coming from */	    \
 277	DO_KVM	intnum,SPRN_##type##_SRR1;    /* KVM hook */		    \
 278	stw	r10,PACA_EX##type+EX_CR(r13); /* save old CR in the PACA */ \
 279	addition;			/* additional code for that exc. */ \
 280	std	r1,PACA_EX##type+EX_R1(r13); /* save old r1 in the PACA */  \
 281	type##_SET_KSTACK;		/* get special stack if necessary */\
 282	andi.	r10,r11,MSR_PR;		/* save stack pointer */	    \
 283	beq	1f;			/* branch around if supervisor */   \
 284	ld	r1,PACAKSAVE(r13);	/* get kernel stack coming from usr */\
 2851:	type##_BTB_FLUSH		\
 286	cmpdi	cr1,r1,0;		/* check if SP makes sense */	    \
 287	bge-	cr1,exc_##n##_bad_stack;/* bad stack (TODO: out of line) */ \
 288	mfspr	r10,SPRN_##type##_SRR0;	/* read SRR0 before touching stack */
 289
 290/* Exception type-specific macros */
 291#define	GEN_SET_KSTACK							    \
 292	subi	r1,r1,INT_FRAME_SIZE;	/* alloc frame on kernel stack */
 293#define SPRN_GEN_SRR0	SPRN_SRR0
 294#define SPRN_GEN_SRR1	SPRN_SRR1
 295
 296#define	GDBELL_SET_KSTACK	GEN_SET_KSTACK
 297#define SPRN_GDBELL_SRR0	SPRN_GSRR0
 298#define SPRN_GDBELL_SRR1	SPRN_GSRR1
 299
 300#define CRIT_SET_KSTACK						            \
 301	ld	r1,PACA_CRIT_STACK(r13);				    \
 302	subi	r1,r1,SPECIAL_EXC_FRAME_SIZE
 303#define SPRN_CRIT_SRR0	SPRN_CSRR0
 304#define SPRN_CRIT_SRR1	SPRN_CSRR1
 305
 306#define DBG_SET_KSTACK						            \
 307	ld	r1,PACA_DBG_STACK(r13);					    \
 308	subi	r1,r1,SPECIAL_EXC_FRAME_SIZE
 309#define SPRN_DBG_SRR0	SPRN_DSRR0
 310#define SPRN_DBG_SRR1	SPRN_DSRR1
 311
 312#define MC_SET_KSTACK						            \
 313	ld	r1,PACA_MC_STACK(r13);					    \
 314	subi	r1,r1,SPECIAL_EXC_FRAME_SIZE
 315#define SPRN_MC_SRR0	SPRN_MCSRR0
 316#define SPRN_MC_SRR1	SPRN_MCSRR1
 317
 318#ifdef CONFIG_PPC_FSL_BOOK3E
 319#define GEN_BTB_FLUSH			\
 320	START_BTB_FLUSH_SECTION		\
 321		beq 1f;			\
 322		BTB_FLUSH(r10)			\
 323		1:		\
 324	END_BTB_FLUSH_SECTION
 325
 326#define CRIT_BTB_FLUSH			\
 327	START_BTB_FLUSH_SECTION		\
 328		BTB_FLUSH(r10)		\
 329	END_BTB_FLUSH_SECTION
 330
 331#define DBG_BTB_FLUSH CRIT_BTB_FLUSH
 332#define MC_BTB_FLUSH CRIT_BTB_FLUSH
 333#define GDBELL_BTB_FLUSH GEN_BTB_FLUSH
 334#else
 335#define GEN_BTB_FLUSH
 336#define CRIT_BTB_FLUSH
 337#define DBG_BTB_FLUSH
 338#define MC_BTB_FLUSH
 339#define GDBELL_BTB_FLUSH
 340#endif
 341
 342#define NORMAL_EXCEPTION_PROLOG(n, intnum, addition)			    \
 343	EXCEPTION_PROLOG(n, intnum, GEN, addition##_GEN(n))
 344
 345#define CRIT_EXCEPTION_PROLOG(n, intnum, addition)			    \
 346	EXCEPTION_PROLOG(n, intnum, CRIT, addition##_CRIT(n))
 347
 348#define DBG_EXCEPTION_PROLOG(n, intnum, addition)			    \
 349	EXCEPTION_PROLOG(n, intnum, DBG, addition##_DBG(n))
 350
 351#define MC_EXCEPTION_PROLOG(n, intnum, addition)			    \
 352	EXCEPTION_PROLOG(n, intnum, MC, addition##_MC(n))
 353
 354#define GDBELL_EXCEPTION_PROLOG(n, intnum, addition)			    \
 355	EXCEPTION_PROLOG(n, intnum, GDBELL, addition##_GDBELL(n))
 356
 357/* Variants of the "addition" argument for the prolog
 358 */
 359#define PROLOG_ADDITION_NONE_GEN(n)
 360#define PROLOG_ADDITION_NONE_GDBELL(n)
 361#define PROLOG_ADDITION_NONE_CRIT(n)
 362#define PROLOG_ADDITION_NONE_DBG(n)
 363#define PROLOG_ADDITION_NONE_MC(n)
 364
 365#define PROLOG_ADDITION_MASKABLE_GEN(n)					    \
 366	lbz	r10,PACAIRQSOFTMASK(r13);	/* are irqs soft-masked? */ \
 367	andi.	r10,r10,IRQS_DISABLED;	/* yes -> go out of line */ \
 368	bne	masked_interrupt_book3e_##n
 369
 370#define PROLOG_ADDITION_2REGS_GEN(n)					    \
 371	std	r14,PACA_EXGEN+EX_R14(r13);				    \
 372	std	r15,PACA_EXGEN+EX_R15(r13)
 373
 374#define PROLOG_ADDITION_1REG_GEN(n)					    \
 375	std	r14,PACA_EXGEN+EX_R14(r13);
 376
 377#define PROLOG_ADDITION_2REGS_CRIT(n)					    \
 378	std	r14,PACA_EXCRIT+EX_R14(r13);				    \
 379	std	r15,PACA_EXCRIT+EX_R15(r13)
 380
 381#define PROLOG_ADDITION_2REGS_DBG(n)					    \
 382	std	r14,PACA_EXDBG+EX_R14(r13);				    \
 383	std	r15,PACA_EXDBG+EX_R15(r13)
 384
 385#define PROLOG_ADDITION_2REGS_MC(n)					    \
 386	std	r14,PACA_EXMC+EX_R14(r13);				    \
 387	std	r15,PACA_EXMC+EX_R15(r13)
 388
 389
 390/* Core exception code for all exceptions except TLB misses. */
 391#define EXCEPTION_COMMON_LVL(n, scratch, excf)				    \
 392exc_##n##_common:							    \
 393	std	r0,GPR0(r1);		/* save r0 in stackframe */	    \
 394	std	r2,GPR2(r1);		/* save r2 in stackframe */	    \
 395	SAVE_4GPRS(3, r1);		/* save r3 - r6 in stackframe */    \
 396	SAVE_2GPRS(7, r1);		/* save r7, r8 in stackframe */	    \
 397	std	r9,GPR9(r1);		/* save r9 in stackframe */	    \
 398	std	r10,_NIP(r1);		/* save SRR0 to stackframe */	    \
 399	std	r11,_MSR(r1);		/* save SRR1 to stackframe */	    \
 400	beq	2f;			/* if from kernel mode */	    \
 401	ACCOUNT_CPU_USER_ENTRY(r13,r10,r11);/* accounting (uses cr0+eq) */  \
 4022:	ld	r3,excf+EX_R10(r13);	/* get back r10 */		    \
 403	ld	r4,excf+EX_R11(r13);	/* get back r11 */		    \
 404	mfspr	r5,scratch;		/* get back r13 */		    \
 405	std	r12,GPR12(r1);		/* save r12 in stackframe */	    \
 406	ld	r2,PACATOC(r13);	/* get kernel TOC into r2 */	    \
 407	mflr	r6;			/* save LR in stackframe */	    \
 408	mfctr	r7;			/* save CTR in stackframe */	    \
 409	mfspr	r8,SPRN_XER;		/* save XER in stackframe */	    \
 410	ld	r9,excf+EX_R1(r13);	/* load orig r1 back from PACA */   \
 411	lwz	r10,excf+EX_CR(r13);	/* load orig CR back from PACA	*/  \
 412	lbz	r11,PACAIRQSOFTMASK(r13); /* get current IRQ softe */	    \
 413	ld	r12,exception_marker@toc(r2);				    \
 414	li	r0,0;							    \
 415	std	r3,GPR10(r1);		/* save r10 to stackframe */	    \
 416	std	r4,GPR11(r1);		/* save r11 to stackframe */	    \
 417	std	r5,GPR13(r1);		/* save it to stackframe */	    \
 418	std	r6,_LINK(r1);						    \
 419	std	r7,_CTR(r1);						    \
 420	std	r8,_XER(r1);						    \
 421	li	r3,(n)+1;		/* indicate partial regs in trap */ \
 422	std	r9,0(r1);		/* store stack frame back link */   \
 423	std	r10,_CCR(r1);		/* store orig CR in stackframe */   \
 424	std	r9,GPR1(r1);		/* store stack frame back link */   \
 425	std	r11,SOFTE(r1);		/* and save it to stackframe */     \
 426	std	r12,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */	    \
 427	std	r3,_TRAP(r1);		/* set trap number		*/  \
 428	std	r0,RESULT(r1);		/* clear regs->result */
 429
 430#define EXCEPTION_COMMON(n) \
 431	EXCEPTION_COMMON_LVL(n, SPRN_SPRG_GEN_SCRATCH, PACA_EXGEN)
 432#define EXCEPTION_COMMON_CRIT(n) \
 433	EXCEPTION_COMMON_LVL(n, SPRN_SPRG_CRIT_SCRATCH, PACA_EXCRIT)
 434#define EXCEPTION_COMMON_MC(n) \
 435	EXCEPTION_COMMON_LVL(n, SPRN_SPRG_MC_SCRATCH, PACA_EXMC)
 436#define EXCEPTION_COMMON_DBG(n) \
 437	EXCEPTION_COMMON_LVL(n, SPRN_SPRG_DBG_SCRATCH, PACA_EXDBG)
 438
 439/*
 440 * This is meant for exceptions that don't immediately hard-enable.  We
 441 * set a bit in paca->irq_happened to ensure that a subsequent call to
 442 * arch_local_irq_restore() will properly hard-enable and avoid the
 443 * fast-path, and then reconcile irq state.
 444 */
 445#define INTS_DISABLE	RECONCILE_IRQ_STATE(r3,r4)
 446
 447/*
 448 * This is called by exceptions that don't use INTS_DISABLE (that did not
 449 * touch irq indicators in the PACA).  This will restore MSR:EE to it's
 450 * previous value
 451 *
 452 * XXX In the long run, we may want to open-code it in order to separate the
 453 *     load from the wrtee, thus limiting the latency caused by the dependency
 454 *     but at this point, I'll favor code clarity until we have a near to final
 455 *     implementation
 456 */
 457#define INTS_RESTORE_HARD						    \
 458	ld	r11,_MSR(r1);						    \
 459	wrtee	r11;
 460
 461/* XXX FIXME: Restore r14/r15 when necessary */
 462#define BAD_STACK_TRAMPOLINE(n)						    \
 463exc_##n##_bad_stack:							    \
 464	li	r1,(n);			/* get exception number */	    \
 465	sth	r1,PACA_TRAP_SAVE(r13);	/* store trap */		    \
 466	b	bad_stack_book3e;	/* bad stack error */
 467
 468/* WARNING: If you change the layout of this stub, make sure you check
 469	*   the debug exception handler which handles single stepping
 470	*   into exceptions from userspace, and the MM code in
 471	*   arch/powerpc/mm/tlb_nohash.c which patches the branch here
 472	*   and would need to be updated if that branch is moved
 473	*/
 474#define	EXCEPTION_STUB(loc, label)					\
 475	. = interrupt_base_book3e + loc;				\
 476	nop;	/* To make debug interrupts happy */			\
 477	b	exc_##label##_book3e;
 478
 479#define ACK_NONE(r)
 480#define ACK_DEC(r)							\
 481	lis	r,TSR_DIS@h;						\
 482	mtspr	SPRN_TSR,r
 483#define ACK_FIT(r)							\
 484	lis	r,TSR_FIS@h;						\
 485	mtspr	SPRN_TSR,r
 486
 487/* Used by asynchronous interrupt that may happen in the idle loop.
 488 *
 489 * This check if the thread was in the idle loop, and if yes, returns
 490 * to the caller rather than the PC. This is to avoid a race if
 491 * interrupts happen before the wait instruction.
 492 */
 493#define CHECK_NAPPING()							\
 494	ld	r11, PACA_THREAD_INFO(r13);				\
 495	ld	r10,TI_LOCAL_FLAGS(r11);				\
 496	andi.	r9,r10,_TLF_NAPPING;					\
 497	beq+	1f;							\
 498	ld	r8,_LINK(r1);						\
 499	rlwinm	r7,r10,0,~_TLF_NAPPING;					\
 500	std	r8,_NIP(r1);						\
 501	std	r7,TI_LOCAL_FLAGS(r11);					\
 5021:
 503
 504
 505#define MASKABLE_EXCEPTION(trapnum, intnum, label, hdlr, ack)		\
 506	START_EXCEPTION(label);						\
 507	NORMAL_EXCEPTION_PROLOG(trapnum, intnum, PROLOG_ADDITION_MASKABLE)\
 508	EXCEPTION_COMMON(trapnum)					\
 509	INTS_DISABLE;							\
 510	ack(r8);							\
 511	CHECK_NAPPING();						\
 512	addi	r3,r1,STACK_FRAME_OVERHEAD;				\
 513	bl	hdlr;							\
 514	b	ret_from_except_lite;
 515
 516/* This value is used to mark exception frames on the stack. */
 517	.section	".toc","aw"
 518exception_marker:
 519	.tc	ID_EXC_MARKER[TC],STACK_FRAME_REGS_MARKER
 520
 521
 522/*
 523 * And here we have the exception vectors !
 524 */
 525
 526	.text
 527	.balign	0x1000
 528	.globl interrupt_base_book3e
 529interrupt_base_book3e:					/* fake trap */
 530	EXCEPTION_STUB(0x000, machine_check)
 531	EXCEPTION_STUB(0x020, critical_input)		/* 0x0100 */
 532	EXCEPTION_STUB(0x040, debug_crit)		/* 0x0d00 */
 533	EXCEPTION_STUB(0x060, data_storage)		/* 0x0300 */
 534	EXCEPTION_STUB(0x080, instruction_storage)	/* 0x0400 */
 535	EXCEPTION_STUB(0x0a0, external_input)		/* 0x0500 */
 536	EXCEPTION_STUB(0x0c0, alignment)		/* 0x0600 */
 537	EXCEPTION_STUB(0x0e0, program)			/* 0x0700 */
 538	EXCEPTION_STUB(0x100, fp_unavailable)		/* 0x0800 */
 539	EXCEPTION_STUB(0x120, system_call)		/* 0x0c00 */
 540	EXCEPTION_STUB(0x140, ap_unavailable)		/* 0x0f20 */
 541	EXCEPTION_STUB(0x160, decrementer)		/* 0x0900 */
 542	EXCEPTION_STUB(0x180, fixed_interval)		/* 0x0980 */
 543	EXCEPTION_STUB(0x1a0, watchdog)			/* 0x09f0 */
 544	EXCEPTION_STUB(0x1c0, data_tlb_miss)
 545	EXCEPTION_STUB(0x1e0, instruction_tlb_miss)
 546	EXCEPTION_STUB(0x200, altivec_unavailable)
 547	EXCEPTION_STUB(0x220, altivec_assist)
 548	EXCEPTION_STUB(0x260, perfmon)
 549	EXCEPTION_STUB(0x280, doorbell)
 550	EXCEPTION_STUB(0x2a0, doorbell_crit)
 551	EXCEPTION_STUB(0x2c0, guest_doorbell)
 552	EXCEPTION_STUB(0x2e0, guest_doorbell_crit)
 553	EXCEPTION_STUB(0x300, hypercall)
 554	EXCEPTION_STUB(0x320, ehpriv)
 555	EXCEPTION_STUB(0x340, lrat_error)
 556
 557	.globl __end_interrupts
 558__end_interrupts:
 559
 560/* Critical Input Interrupt */
 561	START_EXCEPTION(critical_input);
 562	CRIT_EXCEPTION_PROLOG(0x100, BOOKE_INTERRUPT_CRITICAL,
 563			      PROLOG_ADDITION_NONE)
 564	EXCEPTION_COMMON_CRIT(0x100)
 565	bl	save_nvgprs
 566	bl	special_reg_save
 567	CHECK_NAPPING();
 568	addi	r3,r1,STACK_FRAME_OVERHEAD
 569	bl	unknown_exception
 570	b	ret_from_crit_except
 571
 572/* Machine Check Interrupt */
 573	START_EXCEPTION(machine_check);
 574	MC_EXCEPTION_PROLOG(0x000, BOOKE_INTERRUPT_MACHINE_CHECK,
 575			    PROLOG_ADDITION_NONE)
 576	EXCEPTION_COMMON_MC(0x000)
 577	bl	save_nvgprs
 578	bl	special_reg_save
 579	CHECK_NAPPING();
 580	addi	r3,r1,STACK_FRAME_OVERHEAD
 581	bl	machine_check_exception
 582	b	ret_from_mc_except
 583
 584/* Data Storage Interrupt */
 585	START_EXCEPTION(data_storage)
 586	NORMAL_EXCEPTION_PROLOG(0x300, BOOKE_INTERRUPT_DATA_STORAGE,
 587				PROLOG_ADDITION_2REGS)
 588	mfspr	r14,SPRN_DEAR
 589	mfspr	r15,SPRN_ESR
 590	EXCEPTION_COMMON(0x300)
 591	INTS_DISABLE
 592	b	storage_fault_common
 593
 594/* Instruction Storage Interrupt */
 595	START_EXCEPTION(instruction_storage);
 596	NORMAL_EXCEPTION_PROLOG(0x400, BOOKE_INTERRUPT_INST_STORAGE,
 597				PROLOG_ADDITION_2REGS)
 598	li	r15,0
 599	mr	r14,r10
 600	EXCEPTION_COMMON(0x400)
 601	INTS_DISABLE
 602	b	storage_fault_common
 603
 604/* External Input Interrupt */
 605	MASKABLE_EXCEPTION(0x500, BOOKE_INTERRUPT_EXTERNAL,
 606			   external_input, do_IRQ, ACK_NONE)
 607
 608/* Alignment */
 609	START_EXCEPTION(alignment);
 610	NORMAL_EXCEPTION_PROLOG(0x600, BOOKE_INTERRUPT_ALIGNMENT,
 611				PROLOG_ADDITION_2REGS)
 612	mfspr	r14,SPRN_DEAR
 613	mfspr	r15,SPRN_ESR
 614	EXCEPTION_COMMON(0x600)
 615	b	alignment_more	/* no room, go out of line */
 616
 617/* Program Interrupt */
 618	START_EXCEPTION(program);
 619	NORMAL_EXCEPTION_PROLOG(0x700, BOOKE_INTERRUPT_PROGRAM,
 620				PROLOG_ADDITION_1REG)
 621	mfspr	r14,SPRN_ESR
 622	EXCEPTION_COMMON(0x700)
 623	INTS_DISABLE
 624	std	r14,_DSISR(r1)
 625	addi	r3,r1,STACK_FRAME_OVERHEAD
 626	ld	r14,PACA_EXGEN+EX_R14(r13)
 627	bl	save_nvgprs
 628	bl	program_check_exception
 629	b	ret_from_except
 630
 631/* Floating Point Unavailable Interrupt */
 632	START_EXCEPTION(fp_unavailable);
 633	NORMAL_EXCEPTION_PROLOG(0x800, BOOKE_INTERRUPT_FP_UNAVAIL,
 634				PROLOG_ADDITION_NONE)
 635	/* we can probably do a shorter exception entry for that one... */
 636	EXCEPTION_COMMON(0x800)
 637	ld	r12,_MSR(r1)
 638	andi.	r0,r12,MSR_PR;
 639	beq-	1f
 640	bl	load_up_fpu
 641	b	fast_exception_return
 6421:	INTS_DISABLE
 643	bl	save_nvgprs
 644	addi	r3,r1,STACK_FRAME_OVERHEAD
 645	bl	kernel_fp_unavailable_exception
 646	b	ret_from_except
 647
 648/* Altivec Unavailable Interrupt */
 649	START_EXCEPTION(altivec_unavailable);
 650	NORMAL_EXCEPTION_PROLOG(0x200, BOOKE_INTERRUPT_ALTIVEC_UNAVAIL,
 651				PROLOG_ADDITION_NONE)
 652	/* we can probably do a shorter exception entry for that one... */
 653	EXCEPTION_COMMON(0x200)
 654#ifdef CONFIG_ALTIVEC
 655BEGIN_FTR_SECTION
 656	ld	r12,_MSR(r1)
 657	andi.	r0,r12,MSR_PR;
 658	beq-	1f
 659	bl	load_up_altivec
 660	b	fast_exception_return
 6611:
 662END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
 663#endif
 664	INTS_DISABLE
 665	bl	save_nvgprs
 666	addi	r3,r1,STACK_FRAME_OVERHEAD
 667	bl	altivec_unavailable_exception
 668	b	ret_from_except
 669
 670/* AltiVec Assist */
 671	START_EXCEPTION(altivec_assist);
 672	NORMAL_EXCEPTION_PROLOG(0x220,
 673				BOOKE_INTERRUPT_ALTIVEC_ASSIST,
 674				PROLOG_ADDITION_NONE)
 675	EXCEPTION_COMMON(0x220)
 676	INTS_DISABLE
 677	bl	save_nvgprs
 678	addi	r3,r1,STACK_FRAME_OVERHEAD
 679#ifdef CONFIG_ALTIVEC
 680BEGIN_FTR_SECTION
 681	bl	altivec_assist_exception
 682END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
 683#else
 684	bl	unknown_exception
 685#endif
 686	b	ret_from_except
 687
 688
 689/* Decrementer Interrupt */
 690	MASKABLE_EXCEPTION(0x900, BOOKE_INTERRUPT_DECREMENTER,
 691			   decrementer, timer_interrupt, ACK_DEC)
 692
 693/* Fixed Interval Timer Interrupt */
 694	MASKABLE_EXCEPTION(0x980, BOOKE_INTERRUPT_FIT,
 695			   fixed_interval, unknown_exception, ACK_FIT)
 696
 697/* Watchdog Timer Interrupt */
 698	START_EXCEPTION(watchdog);
 699	CRIT_EXCEPTION_PROLOG(0x9f0, BOOKE_INTERRUPT_WATCHDOG,
 700			      PROLOG_ADDITION_NONE)
 701	EXCEPTION_COMMON_CRIT(0x9f0)
 702	bl	save_nvgprs
 703	bl	special_reg_save
 704	CHECK_NAPPING();
 705	addi	r3,r1,STACK_FRAME_OVERHEAD
 706#ifdef CONFIG_BOOKE_WDT
 707	bl	WatchdogException
 708#else
 709	bl	unknown_exception
 710#endif
 711	b	ret_from_crit_except
 712
 713/* System Call Interrupt */
 714	START_EXCEPTION(system_call)
 715	mr	r9,r13			/* keep a copy of userland r13 */
 716	mfspr	r11,SPRN_SRR0		/* get return address */
 717	mfspr	r12,SPRN_SRR1		/* get previous MSR */
 718	mfspr	r13,SPRN_SPRG_PACA	/* get our PACA */
 719	b	system_call_common
 720
 721/* Auxiliary Processor Unavailable Interrupt */
 722	START_EXCEPTION(ap_unavailable);
 723	NORMAL_EXCEPTION_PROLOG(0xf20, BOOKE_INTERRUPT_AP_UNAVAIL,
 724				PROLOG_ADDITION_NONE)
 725	EXCEPTION_COMMON(0xf20)
 726	INTS_DISABLE
 727	bl	save_nvgprs
 728	addi	r3,r1,STACK_FRAME_OVERHEAD
 729	bl	unknown_exception
 730	b	ret_from_except
 731
 732/* Debug exception as a critical interrupt*/
 733	START_EXCEPTION(debug_crit);
 734	CRIT_EXCEPTION_PROLOG(0xd00, BOOKE_INTERRUPT_DEBUG,
 735			      PROLOG_ADDITION_2REGS)
 736
 737	/*
 738	 * If there is a single step or branch-taken exception in an
 739	 * exception entry sequence, it was probably meant to apply to
 740	 * the code where the exception occurred (since exception entry
 741	 * doesn't turn off DE automatically).  We simulate the effect
 742	 * of turning off DE on entry to an exception handler by turning
 743	 * off DE in the CSRR1 value and clearing the debug status.
 744	 */
 745
 746	mfspr	r14,SPRN_DBSR		/* check single-step/branch taken */
 747	andis.	r15,r14,(DBSR_IC|DBSR_BT)@h
 748	beq+	1f
 749
 750#ifdef CONFIG_RELOCATABLE
 751	ld	r15,PACATOC(r13)
 752	ld	r14,interrupt_base_book3e@got(r15)
 753	ld	r15,__end_interrupts@got(r15)
 754	cmpld	cr0,r10,r14
 755	cmpld	cr1,r10,r15
 756#else
 757	LOAD_REG_IMMEDIATE_SYM(r14, r15, interrupt_base_book3e)
 758	cmpld	cr0, r10, r14
 759	LOAD_REG_IMMEDIATE_SYM(r14, r15, __end_interrupts)
 760	cmpld	cr1, r10, r14
 761#endif
 762	blt+	cr0,1f
 763	bge+	cr1,1f
 764
 765	/* here it looks like we got an inappropriate debug exception. */
 766	lis	r14,(DBSR_IC|DBSR_BT)@h		/* clear the event */
 767	rlwinm	r11,r11,0,~MSR_DE	/* clear DE in the CSRR1 value */
 768	mtspr	SPRN_DBSR,r14
 769	mtspr	SPRN_CSRR1,r11
 770	lwz	r10,PACA_EXCRIT+EX_CR(r13)	/* restore registers */
 771	ld	r1,PACA_EXCRIT+EX_R1(r13)
 772	ld	r14,PACA_EXCRIT+EX_R14(r13)
 773	ld	r15,PACA_EXCRIT+EX_R15(r13)
 774	mtcr	r10
 775	ld	r10,PACA_EXCRIT+EX_R10(r13)	/* restore registers */
 776	ld	r11,PACA_EXCRIT+EX_R11(r13)
 777	mfspr	r13,SPRN_SPRG_CRIT_SCRATCH
 778	rfci
 779
 780	/* Normal debug exception */
 781	/* XXX We only handle coming from userspace for now since we can't
 782	 *     quite save properly an interrupted kernel state yet
 783	 */
 7841:	andi.	r14,r11,MSR_PR;		/* check for userspace again */
 785	beq	kernel_dbg_exc;		/* if from kernel mode */
 786
 787	/* Now we mash up things to make it look like we are coming on a
 788	 * normal exception
 789	 */
 790	mfspr	r14,SPRN_DBSR
 791	EXCEPTION_COMMON_CRIT(0xd00)
 792	std	r14,_DSISR(r1)
 793	addi	r3,r1,STACK_FRAME_OVERHEAD
 794	mr	r4,r14
 795	ld	r14,PACA_EXCRIT+EX_R14(r13)
 796	ld	r15,PACA_EXCRIT+EX_R15(r13)
 797	bl	save_nvgprs
 798	bl	DebugException
 799	b	ret_from_except
 800
 801kernel_dbg_exc:
 802	b	.	/* NYI */
 803
 804/* Debug exception as a debug interrupt*/
 805	START_EXCEPTION(debug_debug);
 806	DBG_EXCEPTION_PROLOG(0xd00, BOOKE_INTERRUPT_DEBUG,
 807						 PROLOG_ADDITION_2REGS)
 808
 809	/*
 810	 * If there is a single step or branch-taken exception in an
 811	 * exception entry sequence, it was probably meant to apply to
 812	 * the code where the exception occurred (since exception entry
 813	 * doesn't turn off DE automatically).  We simulate the effect
 814	 * of turning off DE on entry to an exception handler by turning
 815	 * off DE in the DSRR1 value and clearing the debug status.
 816	 */
 817
 818	mfspr	r14,SPRN_DBSR		/* check single-step/branch taken */
 819	andis.	r15,r14,(DBSR_IC|DBSR_BT)@h
 820	beq+	1f
 821
 822#ifdef CONFIG_RELOCATABLE
 823	ld	r15,PACATOC(r13)
 824	ld	r14,interrupt_base_book3e@got(r15)
 825	ld	r15,__end_interrupts@got(r15)
 826	cmpld	cr0,r10,r14
 827	cmpld	cr1,r10,r15
 828#else
 829	LOAD_REG_IMMEDIATE_SYM(r14, r15, interrupt_base_book3e)
 830	cmpld	cr0, r10, r14
 831	LOAD_REG_IMMEDIATE_SYM(r14, r15,__end_interrupts)
 832	cmpld	cr1, r10, r14
 833#endif
 834	blt+	cr0,1f
 835	bge+	cr1,1f
 836
 837	/* here it looks like we got an inappropriate debug exception. */
 838	lis	r14,(DBSR_IC|DBSR_BT)@h		/* clear the event */
 839	rlwinm	r11,r11,0,~MSR_DE	/* clear DE in the DSRR1 value */
 840	mtspr	SPRN_DBSR,r14
 841	mtspr	SPRN_DSRR1,r11
 842	lwz	r10,PACA_EXDBG+EX_CR(r13)	/* restore registers */
 843	ld	r1,PACA_EXDBG+EX_R1(r13)
 844	ld	r14,PACA_EXDBG+EX_R14(r13)
 845	ld	r15,PACA_EXDBG+EX_R15(r13)
 846	mtcr	r10
 847	ld	r10,PACA_EXDBG+EX_R10(r13)	/* restore registers */
 848	ld	r11,PACA_EXDBG+EX_R11(r13)
 849	mfspr	r13,SPRN_SPRG_DBG_SCRATCH
 850	rfdi
 851
 852	/* Normal debug exception */
 853	/* XXX We only handle coming from userspace for now since we can't
 854	 *     quite save properly an interrupted kernel state yet
 855	 */
 8561:	andi.	r14,r11,MSR_PR;		/* check for userspace again */
 857	beq	kernel_dbg_exc;		/* if from kernel mode */
 858
 859	/* Now we mash up things to make it look like we are coming on a
 860	 * normal exception
 861	 */
 862	mfspr	r14,SPRN_DBSR
 863	EXCEPTION_COMMON_DBG(0xd08)
 864	INTS_DISABLE
 865	std	r14,_DSISR(r1)
 866	addi	r3,r1,STACK_FRAME_OVERHEAD
 867	mr	r4,r14
 868	ld	r14,PACA_EXDBG+EX_R14(r13)
 869	ld	r15,PACA_EXDBG+EX_R15(r13)
 870	bl	save_nvgprs
 871	bl	DebugException
 872	b	ret_from_except
 873
 874	START_EXCEPTION(perfmon);
 875	NORMAL_EXCEPTION_PROLOG(0x260, BOOKE_INTERRUPT_PERFORMANCE_MONITOR,
 876				PROLOG_ADDITION_NONE)
 877	EXCEPTION_COMMON(0x260)
 878	INTS_DISABLE
 879	CHECK_NAPPING()
 880	addi	r3,r1,STACK_FRAME_OVERHEAD
 881	bl	performance_monitor_exception
 882	b	ret_from_except_lite
 883
 884/* Doorbell interrupt */
 885	MASKABLE_EXCEPTION(0x280, BOOKE_INTERRUPT_DOORBELL,
 886			   doorbell, doorbell_exception, ACK_NONE)
 887
 888/* Doorbell critical Interrupt */
 889	START_EXCEPTION(doorbell_crit);
 890	CRIT_EXCEPTION_PROLOG(0x2a0, BOOKE_INTERRUPT_DOORBELL_CRITICAL,
 891			      PROLOG_ADDITION_NONE)
 892	EXCEPTION_COMMON_CRIT(0x2a0)
 893	bl	save_nvgprs
 894	bl	special_reg_save
 895	CHECK_NAPPING();
 896	addi	r3,r1,STACK_FRAME_OVERHEAD
 897	bl	unknown_exception
 898	b	ret_from_crit_except
 899
 900/*
 901 *	Guest doorbell interrupt
 902 *	This general exception use GSRRx save/restore registers
 903 */
 904	START_EXCEPTION(guest_doorbell);
 905	GDBELL_EXCEPTION_PROLOG(0x2c0, BOOKE_INTERRUPT_GUEST_DBELL,
 906			        PROLOG_ADDITION_NONE)
 907	EXCEPTION_COMMON(0x2c0)
 908	addi	r3,r1,STACK_FRAME_OVERHEAD
 909	bl	save_nvgprs
 910	INTS_RESTORE_HARD
 911	bl	unknown_exception
 912	b	ret_from_except
 913
 914/* Guest Doorbell critical Interrupt */
 915	START_EXCEPTION(guest_doorbell_crit);
 916	CRIT_EXCEPTION_PROLOG(0x2e0, BOOKE_INTERRUPT_GUEST_DBELL_CRIT,
 917			      PROLOG_ADDITION_NONE)
 918	EXCEPTION_COMMON_CRIT(0x2e0)
 919	bl	save_nvgprs
 920	bl	special_reg_save
 921	CHECK_NAPPING();
 922	addi	r3,r1,STACK_FRAME_OVERHEAD
 923	bl	unknown_exception
 924	b	ret_from_crit_except
 925
 926/* Hypervisor call */
 927	START_EXCEPTION(hypercall);
 928	NORMAL_EXCEPTION_PROLOG(0x310, BOOKE_INTERRUPT_HV_SYSCALL,
 929			        PROLOG_ADDITION_NONE)
 930	EXCEPTION_COMMON(0x310)
 931	addi	r3,r1,STACK_FRAME_OVERHEAD
 932	bl	save_nvgprs
 933	INTS_RESTORE_HARD
 934	bl	unknown_exception
 935	b	ret_from_except
 936
 937/* Embedded Hypervisor priviledged  */
 938	START_EXCEPTION(ehpriv);
 939	NORMAL_EXCEPTION_PROLOG(0x320, BOOKE_INTERRUPT_HV_PRIV,
 940			        PROLOG_ADDITION_NONE)
 941	EXCEPTION_COMMON(0x320)
 942	addi	r3,r1,STACK_FRAME_OVERHEAD
 943	bl	save_nvgprs
 944	INTS_RESTORE_HARD
 945	bl	unknown_exception
 946	b	ret_from_except
 947
 948/* LRAT Error interrupt */
 949	START_EXCEPTION(lrat_error);
 950	NORMAL_EXCEPTION_PROLOG(0x340, BOOKE_INTERRUPT_LRAT_ERROR,
 951			        PROLOG_ADDITION_NONE)
 952	EXCEPTION_COMMON(0x340)
 953	addi	r3,r1,STACK_FRAME_OVERHEAD
 954	bl	save_nvgprs
 955	INTS_RESTORE_HARD
 956	bl	unknown_exception
 957	b	ret_from_except
 958
 959/*
 960 * An interrupt came in while soft-disabled; We mark paca->irq_happened
 961 * accordingly and if the interrupt is level sensitive, we hard disable
 962 * hard disable (full_mask) corresponds to PACA_IRQ_MUST_HARD_MASK, so
 963 * keep these in synch.
 964 */
 965
 966.macro masked_interrupt_book3e paca_irq full_mask
 967	lbz	r10,PACAIRQHAPPENED(r13)
 968	.if \full_mask == 1
 969	ori	r10,r10,\paca_irq | PACA_IRQ_HARD_DIS
 970	.else
 971	ori	r10,r10,\paca_irq
 972	.endif
 973	stb	r10,PACAIRQHAPPENED(r13)
 974
 975	.if \full_mask == 1
 976	rldicl	r10,r11,48,1		/* clear MSR_EE */
 977	rotldi	r11,r10,16
 978	mtspr	SPRN_SRR1,r11
 979	.endif
 980
 981	lwz	r11,PACA_EXGEN+EX_CR(r13)
 982	mtcr	r11
 983	ld	r10,PACA_EXGEN+EX_R10(r13)
 984	ld	r11,PACA_EXGEN+EX_R11(r13)
 985	mfspr	r13,SPRN_SPRG_GEN_SCRATCH
 986	rfi
 987	b	.
 988.endm
 989
 990masked_interrupt_book3e_0x500:
 991	// XXX When adding support for EPR, use PACA_IRQ_EE_EDGE
 992	masked_interrupt_book3e PACA_IRQ_EE 1
 993
 994masked_interrupt_book3e_0x900:
 995	ACK_DEC(r10);
 996	masked_interrupt_book3e PACA_IRQ_DEC 0
 997
 998masked_interrupt_book3e_0x980:
 999	ACK_FIT(r10);
1000	masked_interrupt_book3e PACA_IRQ_DEC 0
1001
1002masked_interrupt_book3e_0x280:
1003masked_interrupt_book3e_0x2c0:
1004	masked_interrupt_book3e PACA_IRQ_DBELL 0
1005
1006/*
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1007 * This is called from 0x300 and 0x400 handlers after the prologs with
1008 * r14 and r15 containing the fault address and error code, with the
1009 * original values stashed away in the PACA
1010 */
1011storage_fault_common:
1012	std	r14,_DAR(r1)
1013	std	r15,_DSISR(r1)
1014	addi	r3,r1,STACK_FRAME_OVERHEAD
1015	mr	r4,r14
1016	mr	r5,r15
1017	ld	r14,PACA_EXGEN+EX_R14(r13)
1018	ld	r15,PACA_EXGEN+EX_R15(r13)
1019	bl	do_page_fault
1020	cmpdi	r3,0
1021	bne-	1f
1022	b	ret_from_except_lite
10231:	bl	save_nvgprs
1024	mr	r5,r3
1025	addi	r3,r1,STACK_FRAME_OVERHEAD
1026	ld	r4,_DAR(r1)
1027	bl	bad_page_fault
1028	b	ret_from_except
1029
1030/*
1031 * Alignment exception doesn't fit entirely in the 0x100 bytes so it
1032 * continues here.
1033 */
1034alignment_more:
1035	std	r14,_DAR(r1)
1036	std	r15,_DSISR(r1)
1037	addi	r3,r1,STACK_FRAME_OVERHEAD
1038	ld	r14,PACA_EXGEN+EX_R14(r13)
1039	ld	r15,PACA_EXGEN+EX_R15(r13)
1040	bl	save_nvgprs
1041	INTS_RESTORE_HARD
1042	bl	alignment_exception
1043	b	ret_from_except
1044
1045	.align	7
1046_GLOBAL(ret_from_except)
1047	ld	r11,_TRAP(r1)
1048	andi.	r0,r11,1
1049	bne	ret_from_except_lite
1050	REST_NVGPRS(r1)
1051
1052_GLOBAL(ret_from_except_lite)
1053	/*
1054	 * Disable interrupts so that current_thread_info()->flags
1055	 * can't change between when we test it and when we return
1056	 * from the interrupt.
1057	 */
1058	wrteei	0
1059
1060	ld	r9, PACA_THREAD_INFO(r13)
1061	ld	r3,_MSR(r1)
1062	ld	r10,PACACURRENT(r13)
1063	ld	r4,TI_FLAGS(r9)
1064	andi.	r3,r3,MSR_PR
1065	beq	resume_kernel
1066	lwz	r3,(THREAD+THREAD_DBCR0)(r10)
1067
1068	/* Check current_thread_info()->flags */
1069	andi.	r0,r4,_TIF_USER_WORK_MASK
1070	bne	1f
1071	/*
1072	 * Check to see if the dbcr0 register is set up to debug.
1073	 * Use the internal debug mode bit to do this.
1074	 */
1075	andis.	r0,r3,DBCR0_IDM@h
1076	beq	restore
1077	mfmsr	r0
1078	rlwinm	r0,r0,0,~MSR_DE	/* Clear MSR.DE */
1079	mtmsr	r0
1080	mtspr	SPRN_DBCR0,r3
1081	li	r10, -1
1082	mtspr	SPRN_DBSR,r10
1083	b	restore
10841:	andi.	r0,r4,_TIF_NEED_RESCHED
1085	beq	2f
1086	bl	restore_interrupts
1087	SCHEDULE_USER
1088	b	ret_from_except_lite
10892:
1090	bl	save_nvgprs
1091	/*
1092	 * Use a non volatile GPR to save and restore our thread_info flags
1093	 * across the call to restore_interrupts.
1094	 */
1095	mr	r30,r4
1096	bl	restore_interrupts
1097	mr	r4,r30
1098	addi	r3,r1,STACK_FRAME_OVERHEAD
1099	bl	do_notify_resume
1100	b	ret_from_except
1101
1102resume_kernel:
1103	/* check current_thread_info, _TIF_EMULATE_STACK_STORE */
1104	andis.	r8,r4,_TIF_EMULATE_STACK_STORE@h
1105	beq+	1f
1106
1107	addi	r8,r1,INT_FRAME_SIZE	/* Get the kprobed function entry */
1108
1109	ld	r3,GPR1(r1)
1110	subi	r3,r3,INT_FRAME_SIZE	/* dst: Allocate a trampoline exception frame */
1111	mr	r4,r1			/* src:  current exception frame */
1112	mr	r1,r3			/* Reroute the trampoline frame to r1 */
1113
1114	/* Copy from the original to the trampoline. */
1115	li	r5,INT_FRAME_SIZE/8	/* size: INT_FRAME_SIZE */
1116	li	r6,0			/* start offset: 0 */
1117	mtctr	r5
11182:	ldx	r0,r6,r4
1119	stdx	r0,r6,r3
1120	addi	r6,r6,8
1121	bdnz	2b
1122
1123	/* Do real store operation to complete stdu */
1124	ld	r5,GPR1(r1)
1125	std	r8,0(r5)
1126
1127	/* Clear _TIF_EMULATE_STACK_STORE flag */
1128	lis	r11,_TIF_EMULATE_STACK_STORE@h
1129	addi	r5,r9,TI_FLAGS
11300:	ldarx	r4,0,r5
1131	andc	r4,r4,r11
1132	stdcx.	r4,0,r5
1133	bne-	0b
11341:
1135
1136#ifdef CONFIG_PREEMPT
1137	/* Check if we need to preempt */
1138	andi.	r0,r4,_TIF_NEED_RESCHED
1139	beq+	restore
1140	/* Check that preempt_count() == 0 and interrupts are enabled */
1141	lwz	r8,TI_PREEMPT(r9)
1142	cmpwi	cr0,r8,0
1143	bne	restore
1144	ld	r0,SOFTE(r1)
1145	andi.	r0,r0,IRQS_DISABLED
1146	bne	restore
1147
1148	/*
1149	 * Here we are preempting the current task. We want to make
1150	 * sure we are soft-disabled first and reconcile irq state.
1151	 */
1152	RECONCILE_IRQ_STATE(r3,r4)
1153	bl	preempt_schedule_irq
1154
1155	/*
1156	 * arch_local_irq_restore() from preempt_schedule_irq above may
1157	 * enable hard interrupt but we really should disable interrupts
1158	 * when we return from the interrupt, and so that we don't get
1159	 * interrupted after loading SRR0/1.
1160	 */
1161	wrteei	0
1162#endif /* CONFIG_PREEMPT */
1163
1164restore:
1165	/*
1166	 * This is the main kernel exit path. First we check if we
1167	 * are about to re-enable interrupts
1168	 */
1169	ld	r5,SOFTE(r1)
1170	lbz	r6,PACAIRQSOFTMASK(r13)
1171	andi.	r5,r5,IRQS_DISABLED
1172	bne	.Lrestore_irq_off
1173
1174	/* We are enabling, were we already enabled ? Yes, just return */
1175	andi.	r6,r6,IRQS_DISABLED
1176	beq	cr0,fast_exception_return
1177
1178	/*
1179	 * We are about to soft-enable interrupts (we are hard disabled
1180	 * at this point). We check if there's anything that needs to
1181	 * be replayed first.
1182	 */
1183	lbz	r0,PACAIRQHAPPENED(r13)
1184	cmpwi	cr0,r0,0
1185	bne-	.Lrestore_check_irq_replay
1186
1187	/*
1188	 * Get here when nothing happened while soft-disabled, just
1189	 * soft-enable and move-on. We will hard-enable as a side
1190	 * effect of rfi
1191	 */
1192.Lrestore_no_replay:
1193	TRACE_ENABLE_INTS
1194	li	r0,IRQS_ENABLED
1195	stb	r0,PACAIRQSOFTMASK(r13);
1196
1197/* This is the return from load_up_fpu fast path which could do with
1198 * less GPR restores in fact, but for now we have a single return path
1199 */
 
1200fast_exception_return:
1201	wrteei	0
12021:	mr	r0,r13
1203	ld	r10,_MSR(r1)
1204	REST_4GPRS(2, r1)
1205	andi.	r6,r10,MSR_PR
1206	REST_2GPRS(6, r1)
1207	beq	1f
1208	ACCOUNT_CPU_USER_EXIT(r13, r10, r11)
1209	ld	r0,GPR13(r1)
1210
12111:	stdcx.	r0,0,r1		/* to clear the reservation */
1212
1213	ld	r8,_CCR(r1)
1214	ld	r9,_LINK(r1)
1215	ld	r10,_CTR(r1)
1216	ld	r11,_XER(r1)
1217	mtcr	r8
1218	mtlr	r9
1219	mtctr	r10
1220	mtxer	r11
1221	REST_2GPRS(8, r1)
1222	ld	r10,GPR10(r1)
1223	ld	r11,GPR11(r1)
1224	ld	r12,GPR12(r1)
1225	mtspr	SPRN_SPRG_GEN_SCRATCH,r0
1226
1227	std	r10,PACA_EXGEN+EX_R10(r13);
1228	std	r11,PACA_EXGEN+EX_R11(r13);
1229	ld	r10,_NIP(r1)
1230	ld	r11,_MSR(r1)
1231	ld	r0,GPR0(r1)
1232	ld	r1,GPR1(r1)
1233	mtspr	SPRN_SRR0,r10
1234	mtspr	SPRN_SRR1,r11
1235	ld	r10,PACA_EXGEN+EX_R10(r13)
1236	ld	r11,PACA_EXGEN+EX_R11(r13)
1237	mfspr	r13,SPRN_SPRG_GEN_SCRATCH
1238	rfi
1239
1240	/*
1241	 * We are returning to a context with interrupts soft disabled.
1242	 *
1243	 * However, we may also about to hard enable, so we need to
1244	 * make sure that in this case, we also clear PACA_IRQ_HARD_DIS
1245	 * or that bit can get out of sync and bad things will happen
1246	 */
1247.Lrestore_irq_off:
1248	ld	r3,_MSR(r1)
1249	lbz	r7,PACAIRQHAPPENED(r13)
1250	andi.	r0,r3,MSR_EE
1251	beq	1f
1252	rlwinm	r7,r7,0,~PACA_IRQ_HARD_DIS
1253	stb	r7,PACAIRQHAPPENED(r13)
12541:
1255#if defined(CONFIG_PPC_IRQ_SOFT_MASK_DEBUG) && defined(CONFIG_BUG)
1256	/* The interrupt should not have soft enabled. */
1257	lbz	r7,PACAIRQSOFTMASK(r13)
12581:	tdeqi	r7,IRQS_ENABLED
1259	EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,BUGFLAG_WARNING
1260#endif
1261	b	fast_exception_return
1262
1263	/*
1264	 * Something did happen, check if a re-emit is needed
1265	 * (this also clears paca->irq_happened)
1266	 */
1267.Lrestore_check_irq_replay:
1268	/* XXX: We could implement a fast path here where we check
1269	 * for irq_happened being just 0x01, in which case we can
1270	 * clear it and return. That means that we would potentially
1271	 * miss a decrementer having wrapped all the way around.
1272	 *
1273	 * Still, this might be useful for things like hash_page
1274	 */
1275	bl	__check_irq_replay
1276	cmpwi	cr0,r3,0
1277	beq	.Lrestore_no_replay
1278
1279	/*
1280	 * We need to re-emit an interrupt. We do so by re-using our
1281	 * existing exception frame. We first change the trap value,
1282	 * but we need to ensure we preserve the low nibble of it
1283	 */
1284	ld	r4,_TRAP(r1)
1285	clrldi	r4,r4,60
1286	or	r4,r4,r3
1287	std	r4,_TRAP(r1)
1288
1289	/*
1290	 * PACA_IRQ_HARD_DIS won't always be set here, so set it now
1291	 * to reconcile the IRQ state. Tracing is already accounted for.
1292	 */
1293	lbz	r4,PACAIRQHAPPENED(r13)
1294	ori	r4,r4,PACA_IRQ_HARD_DIS
1295	stb	r4,PACAIRQHAPPENED(r13)
1296
1297	/*
1298	 * Then find the right handler and call it. Interrupts are
1299	 * still soft-disabled and we keep them that way.
1300	*/
1301	cmpwi	cr0,r3,0x500
1302	bne	1f
1303	addi	r3,r1,STACK_FRAME_OVERHEAD;
1304	bl	do_IRQ
1305	b	ret_from_except
13061:	cmpwi	cr0,r3,0xf00
1307	bne	1f
1308	addi	r3,r1,STACK_FRAME_OVERHEAD;
1309	bl	performance_monitor_exception
1310	b	ret_from_except
13111:	cmpwi	cr0,r3,0xe60
1312	bne	1f
1313	addi	r3,r1,STACK_FRAME_OVERHEAD;
1314	bl	handle_hmi_exception
1315	b	ret_from_except
13161:	cmpwi	cr0,r3,0x900
1317	bne	1f
1318	addi	r3,r1,STACK_FRAME_OVERHEAD;
1319	bl	timer_interrupt
1320	b	ret_from_except
1321#ifdef CONFIG_PPC_DOORBELL
13221:
1323	cmpwi	cr0,r3,0x280
1324	bne	1f
1325	addi	r3,r1,STACK_FRAME_OVERHEAD;
1326	bl	doorbell_exception
1327#endif /* CONFIG_PPC_DOORBELL */
13281:	b	ret_from_except /* What else to do here ? */
1329
1330_ASM_NOKPROBE_SYMBOL(ret_from_except);
1331_ASM_NOKPROBE_SYMBOL(ret_from_except_lite);
1332_ASM_NOKPROBE_SYMBOL(resume_kernel);
1333_ASM_NOKPROBE_SYMBOL(restore);
1334_ASM_NOKPROBE_SYMBOL(fast_exception_return);
1335
1336/*
1337 * Trampolines used when spotting a bad kernel stack pointer in
1338 * the exception entry code.
1339 *
1340 * TODO: move some bits like SRR0 read to trampoline, pass PACA
1341 * index around, etc... to handle crit & mcheck
1342 */
1343BAD_STACK_TRAMPOLINE(0x000)
1344BAD_STACK_TRAMPOLINE(0x100)
1345BAD_STACK_TRAMPOLINE(0x200)
1346BAD_STACK_TRAMPOLINE(0x220)
1347BAD_STACK_TRAMPOLINE(0x260)
1348BAD_STACK_TRAMPOLINE(0x280)
1349BAD_STACK_TRAMPOLINE(0x2a0)
1350BAD_STACK_TRAMPOLINE(0x2c0)
1351BAD_STACK_TRAMPOLINE(0x2e0)
1352BAD_STACK_TRAMPOLINE(0x300)
1353BAD_STACK_TRAMPOLINE(0x310)
1354BAD_STACK_TRAMPOLINE(0x320)
1355BAD_STACK_TRAMPOLINE(0x340)
1356BAD_STACK_TRAMPOLINE(0x400)
1357BAD_STACK_TRAMPOLINE(0x500)
1358BAD_STACK_TRAMPOLINE(0x600)
1359BAD_STACK_TRAMPOLINE(0x700)
1360BAD_STACK_TRAMPOLINE(0x800)
1361BAD_STACK_TRAMPOLINE(0x900)
1362BAD_STACK_TRAMPOLINE(0x980)
1363BAD_STACK_TRAMPOLINE(0x9f0)
1364BAD_STACK_TRAMPOLINE(0xa00)
1365BAD_STACK_TRAMPOLINE(0xb00)
1366BAD_STACK_TRAMPOLINE(0xc00)
1367BAD_STACK_TRAMPOLINE(0xd00)
1368BAD_STACK_TRAMPOLINE(0xd08)
1369BAD_STACK_TRAMPOLINE(0xe00)
1370BAD_STACK_TRAMPOLINE(0xf00)
1371BAD_STACK_TRAMPOLINE(0xf20)
1372
1373	.globl	bad_stack_book3e
1374bad_stack_book3e:
1375	/* XXX: Needs to make SPRN_SPRG_GEN depend on exception type */
1376	mfspr	r10,SPRN_SRR0;		  /* read SRR0 before touching stack */
1377	ld	r1,PACAEMERGSP(r13)
1378	subi	r1,r1,64+INT_FRAME_SIZE
1379	std	r10,_NIP(r1)
1380	std	r11,_MSR(r1)
1381	ld	r10,PACA_EXGEN+EX_R1(r13) /* FIXME for crit & mcheck */
1382	lwz	r11,PACA_EXGEN+EX_CR(r13) /* FIXME for crit & mcheck */
1383	std	r10,GPR1(r1)
1384	std	r11,_CCR(r1)
1385	mfspr	r10,SPRN_DEAR
1386	mfspr	r11,SPRN_ESR
1387	std	r10,_DAR(r1)
1388	std	r11,_DSISR(r1)
1389	std	r0,GPR0(r1);		/* save r0 in stackframe */	    \
1390	std	r2,GPR2(r1);		/* save r2 in stackframe */	    \
1391	SAVE_4GPRS(3, r1);		/* save r3 - r6 in stackframe */    \
1392	SAVE_2GPRS(7, r1);		/* save r7, r8 in stackframe */	    \
1393	std	r9,GPR9(r1);		/* save r9 in stackframe */	    \
1394	ld	r3,PACA_EXGEN+EX_R10(r13);/* get back r10 */		    \
1395	ld	r4,PACA_EXGEN+EX_R11(r13);/* get back r11 */		    \
1396	mfspr	r5,SPRN_SPRG_GEN_SCRATCH;/* get back r13 XXX can be wrong */ \
1397	std	r3,GPR10(r1);		/* save r10 to stackframe */	    \
1398	std	r4,GPR11(r1);		/* save r11 to stackframe */	    \
1399	std	r12,GPR12(r1);		/* save r12 in stackframe */	    \
1400	std	r5,GPR13(r1);		/* save it to stackframe */	    \
1401	mflr	r10
1402	mfctr	r11
1403	mfxer	r12
1404	std	r10,_LINK(r1)
1405	std	r11,_CTR(r1)
1406	std	r12,_XER(r1)
1407	SAVE_10GPRS(14,r1)
1408	SAVE_8GPRS(24,r1)
1409	lhz	r12,PACA_TRAP_SAVE(r13)
1410	std	r12,_TRAP(r1)
1411	addi	r11,r1,INT_FRAME_SIZE
1412	std	r11,0(r1)
1413	li	r12,0
1414	std	r12,0(r11)
1415	ld	r2,PACATOC(r13)
14161:	addi	r3,r1,STACK_FRAME_OVERHEAD
1417	bl	kernel_bad_stack
1418	b	1b
1419
1420/*
1421 * Setup the initial TLB for a core. This current implementation
1422 * assume that whatever we are running off will not conflict with
1423 * the new mapping at PAGE_OFFSET.
1424 */
1425_GLOBAL(initial_tlb_book3e)
1426
1427	/* Look for the first TLB with IPROT set */
1428	mfspr	r4,SPRN_TLB0CFG
1429	andi.	r3,r4,TLBnCFG_IPROT
1430	lis	r3,MAS0_TLBSEL(0)@h
1431	bne	found_iprot
1432
1433	mfspr	r4,SPRN_TLB1CFG
1434	andi.	r3,r4,TLBnCFG_IPROT
1435	lis	r3,MAS0_TLBSEL(1)@h
1436	bne	found_iprot
1437
1438	mfspr	r4,SPRN_TLB2CFG
1439	andi.	r3,r4,TLBnCFG_IPROT
1440	lis	r3,MAS0_TLBSEL(2)@h
1441	bne	found_iprot
1442
1443	lis	r3,MAS0_TLBSEL(3)@h
1444	mfspr	r4,SPRN_TLB3CFG
1445	/* fall through */
1446
1447found_iprot:
1448	andi.	r5,r4,TLBnCFG_HES
1449	bne	have_hes
1450
1451	mflr	r8				/* save LR */
1452/* 1. Find the index of the entry we're executing in
1453 *
1454 * r3 = MAS0_TLBSEL (for the iprot array)
1455 * r4 = SPRN_TLBnCFG
1456 */
1457	bl	invstr				/* Find our address */
1458invstr:	mflr	r6				/* Make it accessible */
1459	mfmsr	r7
1460	rlwinm	r5,r7,27,31,31			/* extract MSR[IS] */
1461	mfspr	r7,SPRN_PID
1462	slwi	r7,r7,16
1463	or	r7,r7,r5
1464	mtspr	SPRN_MAS6,r7
1465	tlbsx	0,r6				/* search MSR[IS], SPID=PID */
1466
1467	mfspr	r3,SPRN_MAS0
1468	rlwinm	r5,r3,16,20,31			/* Extract MAS0(Entry) */
1469
1470	mfspr	r7,SPRN_MAS1			/* Insure IPROT set */
1471	oris	r7,r7,MAS1_IPROT@h
1472	mtspr	SPRN_MAS1,r7
1473	tlbwe
1474
1475/* 2. Invalidate all entries except the entry we're executing in
1476 *
1477 * r3 = MAS0 w/TLBSEL & ESEL for the entry we are running in
1478 * r4 = SPRN_TLBnCFG
1479 * r5 = ESEL of entry we are running in
1480 */
1481	andi.	r4,r4,TLBnCFG_N_ENTRY		/* Extract # entries */
1482	li	r6,0				/* Set Entry counter to 0 */
14831:	mr	r7,r3				/* Set MAS0(TLBSEL) */
1484	rlwimi	r7,r6,16,4,15			/* Setup MAS0 = TLBSEL | ESEL(r6) */
1485	mtspr	SPRN_MAS0,r7
1486	tlbre
1487	mfspr	r7,SPRN_MAS1
1488	rlwinm	r7,r7,0,2,31			/* Clear MAS1 Valid and IPROT */
1489	cmpw	r5,r6
1490	beq	skpinv				/* Dont update the current execution TLB */
1491	mtspr	SPRN_MAS1,r7
1492	tlbwe
1493	isync
1494skpinv:	addi	r6,r6,1				/* Increment */
1495	cmpw	r6,r4				/* Are we done? */
1496	bne	1b				/* If not, repeat */
1497
1498	/* Invalidate all TLBs */
1499	PPC_TLBILX_ALL(0,R0)
1500	sync
1501	isync
1502
1503/* 3. Setup a temp mapping and jump to it
1504 *
1505 * r3 = MAS0 w/TLBSEL & ESEL for the entry we are running in
1506 * r5 = ESEL of entry we are running in
1507 */
1508	andi.	r7,r5,0x1	/* Find an entry not used and is non-zero */
1509	addi	r7,r7,0x1
1510	mr	r4,r3		/* Set MAS0(TLBSEL) = 1 */
1511	mtspr	SPRN_MAS0,r4
1512	tlbre
1513
1514	rlwimi	r4,r7,16,4,15	/* Setup MAS0 = TLBSEL | ESEL(r7) */
1515	mtspr	SPRN_MAS0,r4
1516
1517	mfspr	r7,SPRN_MAS1
1518	xori	r6,r7,MAS1_TS		/* Setup TMP mapping in the other Address space */
1519	mtspr	SPRN_MAS1,r6
1520
1521	tlbwe
1522
1523	mfmsr	r6
1524	xori	r6,r6,MSR_IS
1525	mtspr	SPRN_SRR1,r6
1526	bl	1f		/* Find our address */
15271:	mflr	r6
1528	addi	r6,r6,(2f - 1b)
1529	mtspr	SPRN_SRR0,r6
1530	rfi
15312:
1532
1533/* 4. Clear out PIDs & Search info
1534 *
1535 * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in
1536 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping
1537 * r5 = MAS3
1538 */
1539	li	r6,0
1540	mtspr   SPRN_MAS6,r6
1541	mtspr	SPRN_PID,r6
1542
1543/* 5. Invalidate mapping we started in
1544 *
1545 * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in
1546 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping
1547 * r5 = MAS3
1548 */
1549	mtspr	SPRN_MAS0,r3
1550	tlbre
1551	mfspr	r6,SPRN_MAS1
1552	rlwinm	r6,r6,0,2,31	/* clear IPROT and VALID */
1553	mtspr	SPRN_MAS1,r6
1554	tlbwe
1555	sync
1556	isync
1557
 
 
 
 
 
 
 
 
 
 
1558/* 6. Setup KERNELBASE mapping in TLB[0]
1559 *
1560 * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in
1561 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping
1562 * r5 = MAS3
1563 */
1564	rlwinm	r3,r3,0,16,3	/* clear ESEL */
1565	mtspr	SPRN_MAS0,r3
1566	lis	r6,(MAS1_VALID|MAS1_IPROT)@h
1567	ori	r6,r6,(MAS1_TSIZE(BOOK3E_PAGESZ_1GB))@l
1568	mtspr	SPRN_MAS1,r6
1569
1570	LOAD_REG_IMMEDIATE(r6, PAGE_OFFSET | MAS2_M_IF_NEEDED)
1571	mtspr	SPRN_MAS2,r6
1572
1573	rlwinm	r5,r5,0,0,25
1574	ori	r5,r5,MAS3_SR | MAS3_SW | MAS3_SX
1575	mtspr	SPRN_MAS3,r5
1576	li	r5,-1
1577	rlwinm	r5,r5,0,0,25
1578
1579	tlbwe
1580
1581/* 7. Jump to KERNELBASE mapping
1582 *
1583 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping
1584 */
1585	/* Now we branch the new virtual address mapped by this entry */
1586	bl	1f		/* Find our address */
15871:	mflr	r6
1588	addi	r6,r6,(2f - 1b)
1589	tovirt(r6,r6)
1590	lis	r7,MSR_KERNEL@h
1591	ori	r7,r7,MSR_KERNEL@l
1592	mtspr	SPRN_SRR0,r6
1593	mtspr	SPRN_SRR1,r7
1594	rfi				/* start execution out of TLB1[0] entry */
15952:
1596
1597/* 8. Clear out the temp mapping
1598 *
1599 * r4 = MAS0 w/TLBSEL & ESEL for the entry we are running in
1600 */
1601	mtspr	SPRN_MAS0,r4
1602	tlbre
1603	mfspr	r5,SPRN_MAS1
1604	rlwinm	r5,r5,0,2,31	/* clear IPROT and VALID */
1605	mtspr	SPRN_MAS1,r5
1606	tlbwe
1607	sync
1608	isync
1609
1610	/* We translate LR and return */
1611	tovirt(r8,r8)
1612	mtlr	r8
1613	blr
1614
1615have_hes:
1616	/* Setup MAS 0,1,2,3 and 7 for tlbwe of a 1G entry that maps the
1617	 * kernel linear mapping. We also set MAS8 once for all here though
1618	 * that will have to be made dependent on whether we are running under
1619	 * a hypervisor I suppose.
1620	 */
1621
1622	/* BEWARE, MAGIC
1623	 * This code is called as an ordinary function on the boot CPU. But to
1624	 * avoid duplication, this code is also used in SCOM bringup of
1625	 * secondary CPUs. We read the code between the initial_tlb_code_start
1626	 * and initial_tlb_code_end labels one instruction at a time and RAM it
1627	 * into the new core via SCOM. That doesn't process branches, so there
1628	 * must be none between those two labels. It also means if this code
1629	 * ever takes any parameters, the SCOM code must also be updated to
1630	 * provide them.
1631	 */
1632	.globl a2_tlbinit_code_start
1633a2_tlbinit_code_start:
1634
1635	ori	r11,r3,MAS0_WQ_ALLWAYS
1636	oris	r11,r11,MAS0_ESEL(3)@h /* Use way 3: workaround A2 erratum 376 */
1637	mtspr	SPRN_MAS0,r11
1638	lis	r3,(MAS1_VALID | MAS1_IPROT)@h
1639	ori	r3,r3,BOOK3E_PAGESZ_1GB << MAS1_TSIZE_SHIFT
1640	mtspr	SPRN_MAS1,r3
1641	LOAD_REG_IMMEDIATE(r3, PAGE_OFFSET | MAS2_M)
1642	mtspr	SPRN_MAS2,r3
1643	li	r3,MAS3_SR | MAS3_SW | MAS3_SX
1644	mtspr	SPRN_MAS7_MAS3,r3
1645	li	r3,0
1646	mtspr	SPRN_MAS8,r3
1647
1648	/* Write the TLB entry */
1649	tlbwe
1650
1651	.globl a2_tlbinit_after_linear_map
1652a2_tlbinit_after_linear_map:
1653
1654	/* Now we branch the new virtual address mapped by this entry */
1655	LOAD_REG_IMMEDIATE_SYM(r3, r5, 1f)
1656	mtctr	r3
1657	bctr
1658
16591:	/* We are now running at PAGE_OFFSET, clean the TLB of everything
1660	 * else (including IPROTed things left by firmware)
1661	 * r4 = TLBnCFG
1662	 * r3 = current address (more or less)
1663	 */
1664
1665	li	r5,0
1666	mtspr	SPRN_MAS6,r5
1667	tlbsx	0,r3
1668
1669	rlwinm	r9,r4,0,TLBnCFG_N_ENTRY
1670	rlwinm	r10,r4,8,0xff
1671	addi	r10,r10,-1	/* Get inner loop mask */
1672
1673	li	r3,1
1674
1675	mfspr	r5,SPRN_MAS1
1676	rlwinm	r5,r5,0,(~(MAS1_VALID|MAS1_IPROT))
1677
1678	mfspr	r6,SPRN_MAS2
1679	rldicr	r6,r6,0,51		/* Extract EPN */
1680
1681	mfspr	r7,SPRN_MAS0
1682	rlwinm	r7,r7,0,0xffff0fff	/* Clear HES and WQ */
1683
1684	rlwinm	r8,r7,16,0xfff		/* Extract ESEL */
1685
16862:	add	r4,r3,r8
1687	and	r4,r4,r10
1688
1689	rlwimi	r7,r4,16,MAS0_ESEL_MASK
1690
1691	mtspr	SPRN_MAS0,r7
1692	mtspr	SPRN_MAS1,r5
1693	mtspr	SPRN_MAS2,r6
1694	tlbwe
1695
1696	addi	r3,r3,1
1697	and.	r4,r3,r10
1698
1699	bne	3f
1700	addis	r6,r6,(1<<30)@h
17013:
1702	cmpw	r3,r9
1703	blt	2b
1704
1705	.globl  a2_tlbinit_after_iprot_flush
1706a2_tlbinit_after_iprot_flush:
1707
1708	PPC_TLBILX(0,0,R0)
1709	sync
1710	isync
1711
1712	.globl a2_tlbinit_code_end
1713a2_tlbinit_code_end:
1714
1715	/* We translate LR and return */
1716	mflr	r3
1717	tovirt(r3,r3)
1718	mtlr	r3
1719	blr
1720
1721/*
1722 * Main entry (boot CPU, thread 0)
1723 *
1724 * We enter here from head_64.S, possibly after the prom_init trampoline
1725 * with r3 and r4 already saved to r31 and 30 respectively and in 64 bits
1726 * mode. Anything else is as it was left by the bootloader
1727 *
1728 * Initial requirements of this port:
1729 *
1730 * - Kernel loaded at 0 physical
1731 * - A good lump of memory mapped 0:0 by UTLB entry 0
1732 * - MSR:IS & MSR:DS set to 0
1733 *
1734 * Note that some of the above requirements will be relaxed in the future
1735 * as the kernel becomes smarter at dealing with different initial conditions
1736 * but for now you have to be careful
1737 */
1738_GLOBAL(start_initialization_book3e)
1739	mflr	r28
1740
1741	/* First, we need to setup some initial TLBs to map the kernel
1742	 * text, data and bss at PAGE_OFFSET. We don't have a real mode
1743	 * and always use AS 0, so we just set it up to match our link
1744	 * address and never use 0 based addresses.
1745	 */
1746	bl	initial_tlb_book3e
1747
1748	/* Init global core bits */
1749	bl	init_core_book3e
1750
1751	/* Init per-thread bits */
1752	bl	init_thread_book3e
1753
1754	/* Return to common init code */
1755	tovirt(r28,r28)
1756	mtlr	r28
1757	blr
1758
1759
1760/*
1761 * Secondary core/processor entry
1762 *
1763 * This is entered for thread 0 of a secondary core, all other threads
1764 * are expected to be stopped. It's similar to start_initialization_book3e
1765 * except that it's generally entered from the holding loop in head_64.S
1766 * after CPUs have been gathered by Open Firmware.
1767 *
1768 * We assume we are in 32 bits mode running with whatever TLB entry was
1769 * set for us by the firmware or POR engine.
1770 */
1771_GLOBAL(book3e_secondary_core_init_tlb_set)
1772	li	r4,1
1773	b	generic_secondary_smp_init
1774
1775_GLOBAL(book3e_secondary_core_init)
1776	mflr	r28
1777
1778	/* Do we need to setup initial TLB entry ? */
1779	cmplwi	r4,0
1780	bne	2f
1781
1782	/* Setup TLB for this core */
1783	bl	initial_tlb_book3e
1784
1785	/* We can return from the above running at a different
1786	 * address, so recalculate r2 (TOC)
1787	 */
1788	bl	relative_toc
1789
1790	/* Init global core bits */
17912:	bl	init_core_book3e
1792
1793	/* Init per-thread bits */
17943:	bl	init_thread_book3e
1795
1796	/* Return to common init code at proper virtual address.
1797	 *
1798	 * Due to various previous assumptions, we know we entered this
1799	 * function at either the final PAGE_OFFSET mapping or using a
1800	 * 1:1 mapping at 0, so we don't bother doing a complicated check
1801	 * here, we just ensure the return address has the right top bits.
1802	 *
1803	 * Note that if we ever want to be smarter about where we can be
1804	 * started from, we have to be careful that by the time we reach
1805	 * the code below we may already be running at a different location
1806	 * than the one we were called from since initial_tlb_book3e can
1807	 * have moved us already.
1808	 */
1809	cmpdi	cr0,r28,0
1810	blt	1f
1811	lis	r3,PAGE_OFFSET@highest
1812	sldi	r3,r3,32
1813	or	r28,r28,r3
18141:	mtlr	r28
1815	blr
1816
1817_GLOBAL(book3e_secondary_thread_init)
1818	mflr	r28
1819	b	3b
1820
1821	.globl init_core_book3e
1822init_core_book3e:
1823	/* Establish the interrupt vector base */
1824	tovirt(r2,r2)
1825	LOAD_REG_ADDR(r3, interrupt_base_book3e)
1826	mtspr	SPRN_IVPR,r3
1827	sync
1828	blr
1829
1830init_thread_book3e:
1831	lis	r3,(SPRN_EPCR_ICM | SPRN_EPCR_GICM)@h
1832	mtspr	SPRN_EPCR,r3
1833
1834	/* Make sure interrupts are off */
1835	wrteei	0
1836
1837	/* disable all timers and clear out status */
1838	li	r3,0
1839	mtspr	SPRN_TCR,r3
1840	mfspr	r3,SPRN_TSR
1841	mtspr	SPRN_TSR,r3
1842
1843	blr
1844
1845_GLOBAL(__setup_base_ivors)
1846	SET_IVOR(0, 0x020) /* Critical Input */
1847	SET_IVOR(1, 0x000) /* Machine Check */
1848	SET_IVOR(2, 0x060) /* Data Storage */ 
1849	SET_IVOR(3, 0x080) /* Instruction Storage */
1850	SET_IVOR(4, 0x0a0) /* External Input */ 
1851	SET_IVOR(5, 0x0c0) /* Alignment */ 
1852	SET_IVOR(6, 0x0e0) /* Program */ 
1853	SET_IVOR(7, 0x100) /* FP Unavailable */ 
1854	SET_IVOR(8, 0x120) /* System Call */ 
1855	SET_IVOR(9, 0x140) /* Auxiliary Processor Unavailable */ 
1856	SET_IVOR(10, 0x160) /* Decrementer */ 
1857	SET_IVOR(11, 0x180) /* Fixed Interval Timer */ 
1858	SET_IVOR(12, 0x1a0) /* Watchdog Timer */ 
1859	SET_IVOR(13, 0x1c0) /* Data TLB Error */ 
1860	SET_IVOR(14, 0x1e0) /* Instruction TLB Error */
1861	SET_IVOR(15, 0x040) /* Debug */
1862
1863	sync
1864
1865	blr
1866
1867_GLOBAL(setup_altivec_ivors)
1868	SET_IVOR(32, 0x200) /* AltiVec Unavailable */
1869	SET_IVOR(33, 0x220) /* AltiVec Assist */
1870	blr
1871
1872_GLOBAL(setup_perfmon_ivor)
1873	SET_IVOR(35, 0x260) /* Performance Monitor */
1874	blr
1875
1876_GLOBAL(setup_doorbell_ivors)
1877	SET_IVOR(36, 0x280) /* Processor Doorbell */
1878	SET_IVOR(37, 0x2a0) /* Processor Doorbell Crit */
1879	blr
1880
1881_GLOBAL(setup_ehv_ivors)
1882	SET_IVOR(40, 0x300) /* Embedded Hypervisor System Call */
1883	SET_IVOR(41, 0x320) /* Embedded Hypervisor Privilege */
1884	SET_IVOR(38, 0x2c0) /* Guest Processor Doorbell */
1885	SET_IVOR(39, 0x2e0) /* Guest Processor Doorbell Crit/MC */
1886	blr
1887
1888_GLOBAL(setup_lrat_ivor)
1889	SET_IVOR(42, 0x340) /* LRAT Error */
1890	blr