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1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * This file contains low level CPU setup functions.
4 * Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org)
5 */
6
7#include <asm/processor.h>
8#include <asm/page.h>
9#include <asm/cputable.h>
10#include <asm/ppc_asm.h>
11#include <asm/asm-offsets.h>
12#include <asm/cache.h>
13#include <asm/book3s/64/mmu-hash.h>
14
15/* Entry: r3 = crap, r4 = ptr to cputable entry
16 *
17 * Note that we can be called twice for pseudo-PVRs
18 */
19_GLOBAL(__setup_cpu_power7)
20 mflr r11
21 bl __init_hvmode_206
22 mtlr r11
23 beqlr
24 li r0,0
25 mtspr SPRN_LPID,r0
26 LOAD_REG_IMMEDIATE(r0, PCR_MASK)
27 mtspr SPRN_PCR,r0
28 mfspr r3,SPRN_LPCR
29 li r4,(LPCR_LPES1 >> LPCR_LPES_SH)
30 bl __init_LPCR_ISA206
31 mtlr r11
32 blr
33
34_GLOBAL(__restore_cpu_power7)
35 mflr r11
36 mfmsr r3
37 rldicl. r0,r3,4,63
38 beqlr
39 li r0,0
40 mtspr SPRN_LPID,r0
41 LOAD_REG_IMMEDIATE(r0, PCR_MASK)
42 mtspr SPRN_PCR,r0
43 mfspr r3,SPRN_LPCR
44 li r4,(LPCR_LPES1 >> LPCR_LPES_SH)
45 bl __init_LPCR_ISA206
46 mtlr r11
47 blr
48
49_GLOBAL(__setup_cpu_power8)
50 mflr r11
51 bl __init_FSCR
52 bl __init_PMU
53 bl __init_PMU_ISA207
54 bl __init_hvmode_206
55 mtlr r11
56 beqlr
57 li r0,0
58 mtspr SPRN_LPID,r0
59 LOAD_REG_IMMEDIATE(r0, PCR_MASK)
60 mtspr SPRN_PCR,r0
61 mfspr r3,SPRN_LPCR
62 ori r3, r3, LPCR_PECEDH
63 li r4,0 /* LPES = 0 */
64 bl __init_LPCR_ISA206
65 bl __init_HFSCR
66 bl __init_PMU_HV
67 bl __init_PMU_HV_ISA207
68 mtlr r11
69 blr
70
71_GLOBAL(__restore_cpu_power8)
72 mflr r11
73 bl __init_FSCR
74 bl __init_PMU
75 bl __init_PMU_ISA207
76 mfmsr r3
77 rldicl. r0,r3,4,63
78 mtlr r11
79 beqlr
80 li r0,0
81 mtspr SPRN_LPID,r0
82 LOAD_REG_IMMEDIATE(r0, PCR_MASK)
83 mtspr SPRN_PCR,r0
84 mfspr r3,SPRN_LPCR
85 ori r3, r3, LPCR_PECEDH
86 li r4,0 /* LPES = 0 */
87 bl __init_LPCR_ISA206
88 bl __init_HFSCR
89 bl __init_PMU_HV
90 bl __init_PMU_HV_ISA207
91 mtlr r11
92 blr
93
94_GLOBAL(__setup_cpu_power10)
95 mflr r11
96 bl __init_FSCR_power10
97 bl __init_PMU
98 bl __init_PMU_ISA31
99 b 1f
100
101_GLOBAL(__setup_cpu_power9)
102 mflr r11
103 bl __init_FSCR_power9
104 bl __init_PMU
1051: bl __init_hvmode_206
106 mtlr r11
107 beqlr
108 li r0,0
109 mtspr SPRN_PSSCR,r0
110 mtspr SPRN_LPID,r0
111 mtspr SPRN_PID,r0
112 LOAD_REG_IMMEDIATE(r0, PCR_MASK)
113 mtspr SPRN_PCR,r0
114 mfspr r3,SPRN_LPCR
115 LOAD_REG_IMMEDIATE(r4, LPCR_PECEDH | LPCR_PECE_HVEE | LPCR_HVICE | LPCR_HEIC)
116 or r3, r3, r4
117 LOAD_REG_IMMEDIATE(r4, LPCR_UPRT | LPCR_HR)
118 andc r3, r3, r4
119 li r4,0 /* LPES = 0 */
120 bl __init_LPCR_ISA300
121 bl __init_HFSCR
122 bl __init_PMU_HV
123 mtlr r11
124 blr
125
126_GLOBAL(__restore_cpu_power10)
127 mflr r11
128 bl __init_FSCR_power10
129 bl __init_PMU
130 bl __init_PMU_ISA31
131 b 1f
132
133_GLOBAL(__restore_cpu_power9)
134 mflr r11
135 bl __init_FSCR_power9
136 bl __init_PMU
1371: mfmsr r3
138 rldicl. r0,r3,4,63
139 mtlr r11
140 beqlr
141 li r0,0
142 mtspr SPRN_PSSCR,r0
143 mtspr SPRN_LPID,r0
144 mtspr SPRN_PID,r0
145 LOAD_REG_IMMEDIATE(r0, PCR_MASK)
146 mtspr SPRN_PCR,r0
147 mfspr r3,SPRN_LPCR
148 LOAD_REG_IMMEDIATE(r4, LPCR_PECEDH | LPCR_PECE_HVEE | LPCR_HVICE | LPCR_HEIC)
149 or r3, r3, r4
150 LOAD_REG_IMMEDIATE(r4, LPCR_UPRT | LPCR_HR)
151 andc r3, r3, r4
152 li r4,0 /* LPES = 0 */
153 bl __init_LPCR_ISA300
154 bl __init_HFSCR
155 bl __init_PMU_HV
156 mtlr r11
157 blr
158
159__init_hvmode_206:
160 /* Disable CPU_FTR_HVMODE and exit if MSR:HV is not set */
161 mfmsr r3
162 rldicl. r0,r3,4,63
163 bnelr
164 ld r5,CPU_SPEC_FEATURES(r4)
165 LOAD_REG_IMMEDIATE(r6,CPU_FTR_HVMODE | CPU_FTR_P9_TM_HV_ASSIST)
166 andc r5,r5,r6
167 std r5,CPU_SPEC_FEATURES(r4)
168 blr
169
170__init_LPCR_ISA206:
171 /* Setup a sane LPCR:
172 * Called with initial LPCR in R3 and desired LPES 2-bit value in R4
173 *
174 * LPES = 0b01 (HSRR0/1 used for 0x500)
175 * PECE = 0b111
176 * DPFD = 4
177 * HDICE = 0
178 * VC = 0b100 (VPM0=1, VPM1=0, ISL=0)
179 * VRMASD = 0b10000 (L=1, LP=00)
180 *
181 * Other bits untouched for now
182 */
183 li r5,0x10
184 rldimi r3,r5, LPCR_VRMASD_SH, 64-LPCR_VRMASD_SH-5
185
186 /* POWER9 has no VRMASD */
187__init_LPCR_ISA300:
188 rldimi r3,r4, LPCR_LPES_SH, 64-LPCR_LPES_SH-2
189 ori r3,r3,(LPCR_PECE0|LPCR_PECE1|LPCR_PECE2)
190 li r5,4
191 rldimi r3,r5, LPCR_DPFD_SH, 64-LPCR_DPFD_SH-3
192 clrrdi r3,r3,1 /* clear HDICE */
193 li r5,4
194 rldimi r3,r5, LPCR_VC_SH, 0
195 mtspr SPRN_LPCR,r3
196 isync
197 blr
198
199__init_FSCR_power10:
200 mfspr r3, SPRN_FSCR
201 ori r3, r3, FSCR_PREFIX
202 mtspr SPRN_FSCR, r3
203 // fall through
204
205__init_FSCR_power9:
206 mfspr r3, SPRN_FSCR
207 ori r3, r3, FSCR_SCV
208 mtspr SPRN_FSCR, r3
209 // fall through
210
211__init_FSCR:
212 mfspr r3,SPRN_FSCR
213 ori r3,r3,FSCR_TAR|FSCR_EBB
214 mtspr SPRN_FSCR,r3
215 blr
216
217__init_HFSCR:
218 mfspr r3,SPRN_HFSCR
219 ori r3,r3,HFSCR_TAR|HFSCR_TM|HFSCR_BHRB|HFSCR_PM|\
220 HFSCR_DSCR|HFSCR_VECVSX|HFSCR_FP|HFSCR_EBB|HFSCR_MSGP
221 mtspr SPRN_HFSCR,r3
222 blr
223
224__init_PMU_HV:
225 li r5,0
226 mtspr SPRN_MMCRC,r5
227 blr
228
229__init_PMU_HV_ISA207:
230 li r5,0
231 mtspr SPRN_MMCRH,r5
232 blr
233
234__init_PMU:
235 li r5,0
236 mtspr SPRN_MMCRA,r5
237 mtspr SPRN_MMCR0,r5
238 mtspr SPRN_MMCR1,r5
239 mtspr SPRN_MMCR2,r5
240 blr
241
242__init_PMU_ISA207:
243 li r5,0
244 mtspr SPRN_MMCRS,r5
245 blr
246
247__init_PMU_ISA31:
248 li r5,0
249 mtspr SPRN_MMCR3,r5
250 LOAD_REG_IMMEDIATE(r5, MMCRA_BHRB_DISABLE)
251 mtspr SPRN_MMCRA,r5
252 blr
1/*
2 * This file contains low level CPU setup functions.
3 * Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org)
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
9 *
10 */
11
12#include <asm/processor.h>
13#include <asm/page.h>
14#include <asm/cputable.h>
15#include <asm/ppc_asm.h>
16#include <asm/asm-offsets.h>
17#include <asm/cache.h>
18#include <asm/book3s/64/mmu-hash.h>
19
20/* Entry: r3 = crap, r4 = ptr to cputable entry
21 *
22 * Note that we can be called twice for pseudo-PVRs
23 */
24_GLOBAL(__setup_cpu_power7)
25 mflr r11
26 bl __init_hvmode_206
27 mtlr r11
28 beqlr
29 li r0,0
30 mtspr SPRN_LPID,r0
31 mfspr r3,SPRN_LPCR
32 bl __init_LPCR
33 bl __init_tlb_power7
34 mtlr r11
35 blr
36
37_GLOBAL(__restore_cpu_power7)
38 mflr r11
39 mfmsr r3
40 rldicl. r0,r3,4,63
41 beqlr
42 li r0,0
43 mtspr SPRN_LPID,r0
44 mfspr r3,SPRN_LPCR
45 bl __init_LPCR
46 bl __init_tlb_power7
47 mtlr r11
48 blr
49
50_GLOBAL(__setup_cpu_power8)
51 mflr r11
52 bl __init_FSCR
53 bl __init_PMU
54 bl __init_hvmode_206
55 mtlr r11
56 beqlr
57 li r0,0
58 mtspr SPRN_LPID,r0
59 mfspr r3,SPRN_LPCR
60 ori r3, r3, LPCR_PECEDH
61 bl __init_LPCR
62 bl __init_HFSCR
63 bl __init_tlb_power8
64 bl __init_PMU_HV
65 mtlr r11
66 blr
67
68_GLOBAL(__restore_cpu_power8)
69 mflr r11
70 bl __init_FSCR
71 bl __init_PMU
72 mfmsr r3
73 rldicl. r0,r3,4,63
74 mtlr r11
75 beqlr
76 li r0,0
77 mtspr SPRN_LPID,r0
78 mfspr r3,SPRN_LPCR
79 ori r3, r3, LPCR_PECEDH
80 bl __init_LPCR
81 bl __init_HFSCR
82 bl __init_tlb_power8
83 bl __init_PMU_HV
84 mtlr r11
85 blr
86
87_GLOBAL(__setup_cpu_power9)
88 mflr r11
89 bl __init_FSCR
90 bl __init_hvmode_206
91 mtlr r11
92 beqlr
93 li r0,0
94 mtspr SPRN_LPID,r0
95 mfspr r3,SPRN_LPCR
96 ori r3, r3, LPCR_PECEDH
97 bl __init_LPCR
98 bl __init_HFSCR
99 bl __init_tlb_power9
100 mtlr r11
101 blr
102
103_GLOBAL(__restore_cpu_power9)
104 mflr r11
105 bl __init_FSCR
106 mfmsr r3
107 rldicl. r0,r3,4,63
108 mtlr r11
109 beqlr
110 li r0,0
111 mtspr SPRN_LPID,r0
112 mfspr r3,SPRN_LPCR
113 ori r3, r3, LPCR_PECEDH
114 bl __init_LPCR
115 bl __init_HFSCR
116 bl __init_tlb_power9
117 mtlr r11
118 blr
119
120__init_hvmode_206:
121 /* Disable CPU_FTR_HVMODE and exit if MSR:HV is not set */
122 mfmsr r3
123 rldicl. r0,r3,4,63
124 bnelr
125 ld r5,CPU_SPEC_FEATURES(r4)
126 LOAD_REG_IMMEDIATE(r6,CPU_FTR_HVMODE)
127 xor r5,r5,r6
128 std r5,CPU_SPEC_FEATURES(r4)
129 blr
130
131__init_LPCR:
132 /* Setup a sane LPCR:
133 * Called with initial LPCR in R3
134 *
135 * LPES = 0b01 (HSRR0/1 used for 0x500)
136 * PECE = 0b111
137 * DPFD = 4
138 * HDICE = 0
139 * VC = 0b100 (VPM0=1, VPM1=0, ISL=0)
140 * VRMASD = 0b10000 (L=1, LP=00)
141 *
142 * Other bits untouched for now
143 */
144 li r5,1
145 rldimi r3,r5, LPCR_LPES_SH, 64-LPCR_LPES_SH-2
146 ori r3,r3,(LPCR_PECE0|LPCR_PECE1|LPCR_PECE2)
147 li r5,4
148 rldimi r3,r5, LPCR_DPFD_SH, 64-LPCR_DPFD_SH-3
149 clrrdi r3,r3,1 /* clear HDICE */
150 li r5,4
151 rldimi r3,r5, LPCR_VC_SH, 0
152 li r5,0x10
153 rldimi r3,r5, LPCR_VRMASD_SH, 64-LPCR_VRMASD_SH-5
154 mtspr SPRN_LPCR,r3
155 isync
156 blr
157
158__init_FSCR:
159 mfspr r3,SPRN_FSCR
160 ori r3,r3,FSCR_TAR|FSCR_DSCR|FSCR_EBB
161 mtspr SPRN_FSCR,r3
162 blr
163
164__init_HFSCR:
165 mfspr r3,SPRN_HFSCR
166 ori r3,r3,HFSCR_TAR|HFSCR_TM|HFSCR_BHRB|HFSCR_PM|\
167 HFSCR_DSCR|HFSCR_VECVSX|HFSCR_FP|HFSCR_EBB
168 mtspr SPRN_HFSCR,r3
169 blr
170
171/*
172 * Clear the TLB using the specified IS form of tlbiel instruction
173 * (invalidate by congruence class). P7 has 128 CCs., P8 has 512.
174 */
175__init_tlb_power7:
176 li r6,POWER7_TLB_SETS
177 mtctr r6
178 li r7,0xc00 /* IS field = 0b11 */
179 ptesync
1802: tlbiel r7
181 addi r7,r7,0x1000
182 bdnz 2b
183 ptesync
1841: blr
185
186__init_tlb_power8:
187 li r6,POWER8_TLB_SETS
188 mtctr r6
189 li r7,0xc00 /* IS field = 0b11 */
190 ptesync
1912: tlbiel r7
192 addi r7,r7,0x1000
193 bdnz 2b
194 ptesync
1951: blr
196
197__init_tlb_power9:
198 li r6,POWER9_TLB_SETS_HASH
199 mtctr r6
200 li r7,0xc00 /* IS field = 0b11 */
201 ptesync
2022: tlbiel r7
203 addi r7,r7,0x1000
204 bdnz 2b
205 ptesync
2061: blr
207
208__init_PMU_HV:
209 li r5,0
210 mtspr SPRN_MMCRC,r5
211 mtspr SPRN_MMCRH,r5
212 blr
213
214__init_PMU:
215 li r5,0
216 mtspr SPRN_MMCRS,r5
217 mtspr SPRN_MMCRA,r5
218 mtspr SPRN_MMCR0,r5
219 mtspr SPRN_MMCR1,r5
220 mtspr SPRN_MMCR2,r5
221 blr