Loading...
1/*
2 * Nios2 TLB handling
3 *
4 * Copyright (C) 2009, Wind River Systems Inc
5 * Implemented by fredrik.markstrom@gmail.com and ivarholmqvist@gmail.com
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 */
11
12#include <linux/init.h>
13#include <linux/sched.h>
14#include <linux/mm.h>
15#include <linux/pagemap.h>
16
17#include <asm/tlb.h>
18#include <asm/mmu_context.h>
19#include <asm/cpuinfo.h>
20
21#define TLB_INDEX_MASK \
22 ((((1UL << (cpuinfo.tlb_ptr_sz - cpuinfo.tlb_num_ways_log2))) - 1) \
23 << PAGE_SHIFT)
24
25static void get_misc_and_pid(unsigned long *misc, unsigned long *pid)
26{
27 *misc = RDCTL(CTL_TLBMISC);
28 *misc &= (TLBMISC_PID | TLBMISC_WAY);
29 *pid = *misc & TLBMISC_PID;
30}
31
32/*
33 * This provides a PTEADDR value for addr that will cause a TLB miss
34 * (fast TLB miss). TLB invalidation replaces entries with this value.
35 */
36static unsigned long pteaddr_invalid(unsigned long addr)
37{
38 return ((addr | 0xC0000000UL) >> PAGE_SHIFT) << 2;
39}
40
41/*
42 * This one is only used for pages with the global bit set so we don't care
43 * much about the ASID.
44 */
45static void replace_tlb_one_pid(unsigned long addr, unsigned long mmu_pid, unsigned long tlbacc)
46{
47 unsigned int way;
48 unsigned long org_misc, pid_misc;
49
50 /* remember pid/way until we return. */
51 get_misc_and_pid(&org_misc, &pid_misc);
52
53 WRCTL(CTL_PTEADDR, (addr >> PAGE_SHIFT) << 2);
54
55 for (way = 0; way < cpuinfo.tlb_num_ways; way++) {
56 unsigned long pteaddr;
57 unsigned long tlbmisc;
58 unsigned long pid;
59
60 tlbmisc = TLBMISC_RD | (way << TLBMISC_WAY_SHIFT);
61 WRCTL(CTL_TLBMISC, tlbmisc);
62
63 pteaddr = RDCTL(CTL_PTEADDR);
64 if (((pteaddr >> 2) & 0xfffff) != (addr >> PAGE_SHIFT))
65 continue;
66
67 tlbmisc = RDCTL(CTL_TLBMISC);
68 pid = (tlbmisc >> TLBMISC_PID_SHIFT) & TLBMISC_PID_MASK;
69 if (pid != mmu_pid)
70 continue;
71
72 tlbmisc = (mmu_pid << TLBMISC_PID_SHIFT) | TLBMISC_WE |
73 (way << TLBMISC_WAY_SHIFT);
74 WRCTL(CTL_TLBMISC, tlbmisc);
75 if (tlbacc == 0)
76 WRCTL(CTL_PTEADDR, pteaddr_invalid(addr));
77 WRCTL(CTL_TLBACC, tlbacc);
78 /*
79 * There should be only a single entry that maps a
80 * particular {address,pid} so break after a match.
81 */
82 break;
83 }
84
85 WRCTL(CTL_TLBMISC, org_misc);
86}
87
88static void flush_tlb_one_pid(unsigned long addr, unsigned long mmu_pid)
89{
90 pr_debug("Flush tlb-entry for vaddr=%#lx\n", addr);
91
92 replace_tlb_one_pid(addr, mmu_pid, 0);
93}
94
95static void reload_tlb_one_pid(unsigned long addr, unsigned long mmu_pid, pte_t pte)
96{
97 pr_debug("Reload tlb-entry for vaddr=%#lx\n", addr);
98
99 replace_tlb_one_pid(addr, mmu_pid, pte_val(pte));
100}
101
102void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
103 unsigned long end)
104{
105 unsigned long mmu_pid = get_pid_from_context(&vma->vm_mm->context);
106
107 while (start < end) {
108 flush_tlb_one_pid(start, mmu_pid);
109 start += PAGE_SIZE;
110 }
111}
112
113void reload_tlb_page(struct vm_area_struct *vma, unsigned long addr, pte_t pte)
114{
115 unsigned long mmu_pid = get_pid_from_context(&vma->vm_mm->context);
116
117 reload_tlb_one_pid(addr, mmu_pid, pte);
118}
119
120/*
121 * This one is only used for pages with the global bit set so we don't care
122 * much about the ASID.
123 */
124static void flush_tlb_one(unsigned long addr)
125{
126 unsigned int way;
127 unsigned long org_misc, pid_misc;
128
129 pr_debug("Flush tlb-entry for vaddr=%#lx\n", addr);
130
131 /* remember pid/way until we return. */
132 get_misc_and_pid(&org_misc, &pid_misc);
133
134 WRCTL(CTL_PTEADDR, (addr >> PAGE_SHIFT) << 2);
135
136 for (way = 0; way < cpuinfo.tlb_num_ways; way++) {
137 unsigned long pteaddr;
138 unsigned long tlbmisc;
139
140 tlbmisc = TLBMISC_RD | (way << TLBMISC_WAY_SHIFT);
141 WRCTL(CTL_TLBMISC, tlbmisc);
142
143 pteaddr = RDCTL(CTL_PTEADDR);
144 if (((pteaddr >> 2) & 0xfffff) != (addr >> PAGE_SHIFT))
145 continue;
146
147 pr_debug("Flush entry by writing way=%dl pid=%ld\n",
148 way, (pid_misc >> TLBMISC_PID_SHIFT));
149
150 tlbmisc = TLBMISC_WE | (way << TLBMISC_WAY_SHIFT);
151 WRCTL(CTL_TLBMISC, tlbmisc);
152 WRCTL(CTL_PTEADDR, pteaddr_invalid(addr));
153 WRCTL(CTL_TLBACC, 0);
154 }
155
156 WRCTL(CTL_TLBMISC, org_misc);
157}
158
159void flush_tlb_kernel_range(unsigned long start, unsigned long end)
160{
161 while (start < end) {
162 flush_tlb_one(start);
163 start += PAGE_SIZE;
164 }
165}
166
167void dump_tlb_line(unsigned long line)
168{
169 unsigned int way;
170 unsigned long org_misc;
171
172 pr_debug("dump tlb-entries for line=%#lx (addr %08lx)\n", line,
173 line << (PAGE_SHIFT + cpuinfo.tlb_num_ways_log2));
174
175 /* remember pid/way until we return */
176 org_misc = (RDCTL(CTL_TLBMISC) & (TLBMISC_PID | TLBMISC_WAY));
177
178 WRCTL(CTL_PTEADDR, line << 2);
179
180 for (way = 0; way < cpuinfo.tlb_num_ways; way++) {
181 unsigned long pteaddr;
182 unsigned long tlbmisc;
183 unsigned long tlbacc;
184
185 WRCTL(CTL_TLBMISC, TLBMISC_RD | (way << TLBMISC_WAY_SHIFT));
186 pteaddr = RDCTL(CTL_PTEADDR);
187 tlbmisc = RDCTL(CTL_TLBMISC);
188 tlbacc = RDCTL(CTL_TLBACC);
189
190 if ((tlbacc << PAGE_SHIFT) != 0) {
191 pr_debug("-- way:%02x vpn:0x%08lx phys:0x%08lx pid:0x%02lx flags:%c%c%c%c%c\n",
192 way,
193 (pteaddr << (PAGE_SHIFT-2)),
194 (tlbacc << PAGE_SHIFT),
195 ((tlbmisc >> TLBMISC_PID_SHIFT) &
196 TLBMISC_PID_MASK),
197 (tlbacc & _PAGE_READ ? 'r' : '-'),
198 (tlbacc & _PAGE_WRITE ? 'w' : '-'),
199 (tlbacc & _PAGE_EXEC ? 'x' : '-'),
200 (tlbacc & _PAGE_GLOBAL ? 'g' : '-'),
201 (tlbacc & _PAGE_CACHED ? 'c' : '-'));
202 }
203 }
204
205 WRCTL(CTL_TLBMISC, org_misc);
206}
207
208void dump_tlb(void)
209{
210 unsigned int i;
211
212 for (i = 0; i < cpuinfo.tlb_num_lines; i++)
213 dump_tlb_line(i);
214}
215
216void flush_tlb_pid(unsigned long mmu_pid)
217{
218 unsigned long addr = 0;
219 unsigned int line;
220 unsigned int way;
221 unsigned long org_misc, pid_misc;
222
223 /* remember pid/way until we return */
224 get_misc_and_pid(&org_misc, &pid_misc);
225
226 for (line = 0; line < cpuinfo.tlb_num_lines; line++) {
227 WRCTL(CTL_PTEADDR, pteaddr_invalid(addr));
228
229 for (way = 0; way < cpuinfo.tlb_num_ways; way++) {
230 unsigned long tlbmisc;
231 unsigned long pid;
232
233 tlbmisc = TLBMISC_RD | (way << TLBMISC_WAY_SHIFT);
234 WRCTL(CTL_TLBMISC, tlbmisc);
235 tlbmisc = RDCTL(CTL_TLBMISC);
236 pid = (tlbmisc >> TLBMISC_PID_SHIFT) & TLBMISC_PID_MASK;
237 if (pid != mmu_pid)
238 continue;
239
240 tlbmisc = TLBMISC_WE | (way << TLBMISC_WAY_SHIFT);
241 WRCTL(CTL_TLBMISC, tlbmisc);
242 WRCTL(CTL_TLBACC, 0);
243 }
244
245 addr += PAGE_SIZE;
246 }
247
248 WRCTL(CTL_TLBMISC, org_misc);
249}
250
251/*
252 * All entries common to a mm share an asid. To effectively flush these
253 * entries, we just bump the asid.
254 */
255void flush_tlb_mm(struct mm_struct *mm)
256{
257 if (current->mm == mm) {
258 unsigned long mmu_pid = get_pid_from_context(&mm->context);
259 flush_tlb_pid(mmu_pid);
260 } else {
261 memset(&mm->context, 0, sizeof(mm_context_t));
262 }
263}
264
265void flush_tlb_all(void)
266{
267 unsigned long addr = 0;
268 unsigned int line;
269 unsigned int way;
270 unsigned long org_misc, pid_misc;
271
272 /* remember pid/way until we return */
273 get_misc_and_pid(&org_misc, &pid_misc);
274
275 /* Start at way 0, way is auto-incremented after each TLBACC write */
276 WRCTL(CTL_TLBMISC, TLBMISC_WE);
277
278 /* Map each TLB entry to physcal address 0 with no-access and a
279 bad ptbase */
280 for (line = 0; line < cpuinfo.tlb_num_lines; line++) {
281 WRCTL(CTL_PTEADDR, pteaddr_invalid(addr));
282 for (way = 0; way < cpuinfo.tlb_num_ways; way++)
283 WRCTL(CTL_TLBACC, 0);
284
285 addr += PAGE_SIZE;
286 }
287
288 /* restore pid/way */
289 WRCTL(CTL_TLBMISC, org_misc);
290}
291
292void set_mmu_pid(unsigned long pid)
293{
294 unsigned long tlbmisc;
295
296 tlbmisc = RDCTL(CTL_TLBMISC);
297 tlbmisc = (tlbmisc & TLBMISC_WAY);
298 tlbmisc |= (pid & TLBMISC_PID_MASK) << TLBMISC_PID_SHIFT;
299 WRCTL(CTL_TLBMISC, tlbmisc);
300}
1/*
2 * Nios2 TLB handling
3 *
4 * Copyright (C) 2009, Wind River Systems Inc
5 * Implemented by fredrik.markstrom@gmail.com and ivarholmqvist@gmail.com
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 */
11
12#include <linux/init.h>
13#include <linux/sched.h>
14#include <linux/mm.h>
15#include <linux/pagemap.h>
16
17#include <asm/tlb.h>
18#include <asm/mmu_context.h>
19#include <asm/pgtable.h>
20#include <asm/cpuinfo.h>
21
22#define TLB_INDEX_MASK \
23 ((((1UL << (cpuinfo.tlb_ptr_sz - cpuinfo.tlb_num_ways_log2))) - 1) \
24 << PAGE_SHIFT)
25
26/* Used as illegal PHYS_ADDR for TLB mappings
27 */
28#define MAX_PHYS_ADDR 0
29
30static void get_misc_and_pid(unsigned long *misc, unsigned long *pid)
31{
32 *misc = RDCTL(CTL_TLBMISC);
33 *misc &= (TLBMISC_PID | TLBMISC_WAY);
34 *pid = *misc & TLBMISC_PID;
35}
36
37/*
38 * All entries common to a mm share an asid. To effectively flush these
39 * entries, we just bump the asid.
40 */
41void flush_tlb_mm(struct mm_struct *mm)
42{
43 if (current->mm == mm)
44 flush_tlb_all();
45 else
46 memset(&mm->context, 0, sizeof(mm_context_t));
47}
48
49/*
50 * This one is only used for pages with the global bit set so we don't care
51 * much about the ASID.
52 */
53void flush_tlb_one_pid(unsigned long addr, unsigned long mmu_pid)
54{
55 unsigned int way;
56 unsigned long org_misc, pid_misc;
57
58 pr_debug("Flush tlb-entry for vaddr=%#lx\n", addr);
59
60 /* remember pid/way until we return. */
61 get_misc_and_pid(&org_misc, &pid_misc);
62
63 WRCTL(CTL_PTEADDR, (addr >> PAGE_SHIFT) << 2);
64
65 for (way = 0; way < cpuinfo.tlb_num_ways; way++) {
66 unsigned long pteaddr;
67 unsigned long tlbmisc;
68 unsigned long pid;
69
70 tlbmisc = pid_misc | TLBMISC_RD | (way << TLBMISC_WAY_SHIFT);
71 WRCTL(CTL_TLBMISC, tlbmisc);
72 pteaddr = RDCTL(CTL_PTEADDR);
73 tlbmisc = RDCTL(CTL_TLBMISC);
74 pid = (tlbmisc >> TLBMISC_PID_SHIFT) & TLBMISC_PID_MASK;
75 if (((((pteaddr >> 2) & 0xfffff)) == (addr >> PAGE_SHIFT)) &&
76 pid == mmu_pid) {
77 unsigned long vaddr = CONFIG_NIOS2_IO_REGION_BASE +
78 ((PAGE_SIZE * cpuinfo.tlb_num_lines) * way) +
79 (addr & TLB_INDEX_MASK);
80 pr_debug("Flush entry by writing %#lx way=%dl pid=%ld\n",
81 vaddr, way, (pid_misc >> TLBMISC_PID_SHIFT));
82
83 WRCTL(CTL_PTEADDR, (vaddr >> 12) << 2);
84 tlbmisc = pid_misc | TLBMISC_WE |
85 (way << TLBMISC_WAY_SHIFT);
86 WRCTL(CTL_TLBMISC, tlbmisc);
87 WRCTL(CTL_TLBACC, (MAX_PHYS_ADDR >> PAGE_SHIFT));
88 }
89 }
90
91 WRCTL(CTL_TLBMISC, org_misc);
92}
93
94void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
95 unsigned long end)
96{
97 unsigned long mmu_pid = get_pid_from_context(&vma->vm_mm->context);
98
99 while (start < end) {
100 flush_tlb_one_pid(start, mmu_pid);
101 start += PAGE_SIZE;
102 }
103}
104
105void flush_tlb_kernel_range(unsigned long start, unsigned long end)
106{
107 while (start < end) {
108 flush_tlb_one(start);
109 start += PAGE_SIZE;
110 }
111}
112
113/*
114 * This one is only used for pages with the global bit set so we don't care
115 * much about the ASID.
116 */
117void flush_tlb_one(unsigned long addr)
118{
119 unsigned int way;
120 unsigned long org_misc, pid_misc;
121
122 pr_debug("Flush tlb-entry for vaddr=%#lx\n", addr);
123
124 /* remember pid/way until we return. */
125 get_misc_and_pid(&org_misc, &pid_misc);
126
127 WRCTL(CTL_PTEADDR, (addr >> PAGE_SHIFT) << 2);
128
129 for (way = 0; way < cpuinfo.tlb_num_ways; way++) {
130 unsigned long pteaddr;
131 unsigned long tlbmisc;
132
133 tlbmisc = pid_misc | TLBMISC_RD | (way << TLBMISC_WAY_SHIFT);
134 WRCTL(CTL_TLBMISC, tlbmisc);
135 pteaddr = RDCTL(CTL_PTEADDR);
136 tlbmisc = RDCTL(CTL_TLBMISC);
137
138 if ((((pteaddr >> 2) & 0xfffff)) == (addr >> PAGE_SHIFT)) {
139 unsigned long vaddr = CONFIG_NIOS2_IO_REGION_BASE +
140 ((PAGE_SIZE * cpuinfo.tlb_num_lines) * way) +
141 (addr & TLB_INDEX_MASK);
142
143 pr_debug("Flush entry by writing %#lx way=%dl pid=%ld\n",
144 vaddr, way, (pid_misc >> TLBMISC_PID_SHIFT));
145
146 tlbmisc = pid_misc | TLBMISC_WE |
147 (way << TLBMISC_WAY_SHIFT);
148 WRCTL(CTL_PTEADDR, (vaddr >> 12) << 2);
149 WRCTL(CTL_TLBMISC, tlbmisc);
150 WRCTL(CTL_TLBACC, (MAX_PHYS_ADDR >> PAGE_SHIFT));
151 }
152 }
153
154 WRCTL(CTL_TLBMISC, org_misc);
155}
156
157void dump_tlb_line(unsigned long line)
158{
159 unsigned int way;
160 unsigned long org_misc;
161
162 pr_debug("dump tlb-entries for line=%#lx (addr %08lx)\n", line,
163 line << (PAGE_SHIFT + cpuinfo.tlb_num_ways_log2));
164
165 /* remember pid/way until we return */
166 org_misc = (RDCTL(CTL_TLBMISC) & (TLBMISC_PID | TLBMISC_WAY));
167
168 WRCTL(CTL_PTEADDR, line << 2);
169
170 for (way = 0; way < cpuinfo.tlb_num_ways; way++) {
171 unsigned long pteaddr;
172 unsigned long tlbmisc;
173 unsigned long tlbacc;
174
175 WRCTL(CTL_TLBMISC, TLBMISC_RD | (way << TLBMISC_WAY_SHIFT));
176 pteaddr = RDCTL(CTL_PTEADDR);
177 tlbmisc = RDCTL(CTL_TLBMISC);
178 tlbacc = RDCTL(CTL_TLBACC);
179
180 if ((tlbacc << PAGE_SHIFT) != (MAX_PHYS_ADDR & PAGE_MASK)) {
181 pr_debug("-- way:%02x vpn:0x%08lx phys:0x%08lx pid:0x%02lx flags:%c%c%c%c%c\n",
182 way,
183 (pteaddr << (PAGE_SHIFT-2)),
184 (tlbacc << PAGE_SHIFT),
185 ((tlbmisc >> TLBMISC_PID_SHIFT) &
186 TLBMISC_PID_MASK),
187 (tlbacc & _PAGE_READ ? 'r' : '-'),
188 (tlbacc & _PAGE_WRITE ? 'w' : '-'),
189 (tlbacc & _PAGE_EXEC ? 'x' : '-'),
190 (tlbacc & _PAGE_GLOBAL ? 'g' : '-'),
191 (tlbacc & _PAGE_CACHED ? 'c' : '-'));
192 }
193 }
194
195 WRCTL(CTL_TLBMISC, org_misc);
196}
197
198void dump_tlb(void)
199{
200 unsigned int i;
201
202 for (i = 0; i < cpuinfo.tlb_num_lines; i++)
203 dump_tlb_line(i);
204}
205
206void flush_tlb_pid(unsigned long pid)
207{
208 unsigned int line;
209 unsigned int way;
210 unsigned long org_misc, pid_misc;
211
212 /* remember pid/way until we return */
213 get_misc_and_pid(&org_misc, &pid_misc);
214
215 for (line = 0; line < cpuinfo.tlb_num_lines; line++) {
216 WRCTL(CTL_PTEADDR, line << 2);
217
218 for (way = 0; way < cpuinfo.tlb_num_ways; way++) {
219 unsigned long pteaddr;
220 unsigned long tlbmisc;
221 unsigned long tlbacc;
222
223 tlbmisc = pid_misc | TLBMISC_RD |
224 (way << TLBMISC_WAY_SHIFT);
225 WRCTL(CTL_TLBMISC, tlbmisc);
226 pteaddr = RDCTL(CTL_PTEADDR);
227 tlbmisc = RDCTL(CTL_TLBMISC);
228 tlbacc = RDCTL(CTL_TLBACC);
229
230 if (((tlbmisc>>TLBMISC_PID_SHIFT) & TLBMISC_PID_MASK)
231 == pid) {
232 tlbmisc = pid_misc | TLBMISC_WE |
233 (way << TLBMISC_WAY_SHIFT);
234 WRCTL(CTL_TLBMISC, tlbmisc);
235 WRCTL(CTL_TLBACC,
236 (MAX_PHYS_ADDR >> PAGE_SHIFT));
237 }
238 }
239
240 WRCTL(CTL_TLBMISC, org_misc);
241 }
242}
243
244void flush_tlb_all(void)
245{
246 int i;
247 unsigned long vaddr = CONFIG_NIOS2_IO_REGION_BASE;
248 unsigned int way;
249 unsigned long org_misc, pid_misc, tlbmisc;
250
251 /* remember pid/way until we return */
252 get_misc_and_pid(&org_misc, &pid_misc);
253 pid_misc |= TLBMISC_WE;
254
255 /* Map each TLB entry to physcal address 0 with no-access and a
256 bad ptbase */
257 for (way = 0; way < cpuinfo.tlb_num_ways; way++) {
258 tlbmisc = pid_misc | (way << TLBMISC_WAY_SHIFT);
259 for (i = 0; i < cpuinfo.tlb_num_lines; i++) {
260 WRCTL(CTL_PTEADDR, ((vaddr) >> PAGE_SHIFT) << 2);
261 WRCTL(CTL_TLBMISC, tlbmisc);
262 WRCTL(CTL_TLBACC, (MAX_PHYS_ADDR >> PAGE_SHIFT));
263 vaddr += 1UL << 12;
264 }
265 }
266
267 /* restore pid/way */
268 WRCTL(CTL_TLBMISC, org_misc);
269}
270
271void set_mmu_pid(unsigned long pid)
272{
273 WRCTL(CTL_TLBMISC, (RDCTL(CTL_TLBMISC) & TLBMISC_WAY) |
274 ((pid & TLBMISC_PID_MASK) << TLBMISC_PID_SHIFT));
275}