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1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 */
6#ifndef _ASM_PCI_H
7#define _ASM_PCI_H
8
9#include <linux/mm.h>
10
11#ifdef __KERNEL__
12
13/*
14 * This file essentially defines the interface between board
15 * specific PCI code and MIPS common PCI code. Should potentially put
16 * into include/asm/pci.h file.
17 */
18
19#include <linux/ioport.h>
20#include <linux/list.h>
21#include <linux/of.h>
22
23#ifdef CONFIG_PCI_DRIVERS_LEGACY
24
25/*
26 * Each pci channel is a top-level PCI bus seem by CPU. A machine with
27 * multiple PCI channels may have multiple PCI host controllers or a
28 * single controller supporting multiple channels.
29 */
30struct pci_controller {
31 struct list_head list;
32 struct pci_bus *bus;
33 struct device_node *of_node;
34
35 struct pci_ops *pci_ops;
36 struct resource *mem_resource;
37 unsigned long mem_offset;
38 struct resource *io_resource;
39 unsigned long io_offset;
40 unsigned long io_map_base;
41 struct resource *busn_resource;
42
43#ifndef CONFIG_PCI_DOMAINS_GENERIC
44 unsigned int index;
45 /* For compatibility with current (as of July 2003) pciutils
46 and XFree86. Eventually will be removed. */
47 unsigned int need_domain_info;
48#endif
49
50 /* Optional access methods for reading/writing the bus number
51 of the PCI controller */
52 int (*get_busno)(void);
53 void (*set_busno)(int busno);
54};
55
56/*
57 * Used by boards to register their PCI busses before the actual scanning.
58 */
59extern void register_pci_controller(struct pci_controller *hose);
60
61/*
62 * board supplied pci irq fixup routine
63 */
64extern int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
65
66/* Do platform specific device initialization at pci_enable_device() time */
67extern int pcibios_plat_dev_init(struct pci_dev *dev);
68
69extern char * (*pcibios_plat_setup)(char *str);
70
71#ifdef CONFIG_OF
72/* this function parses memory ranges from a device node */
73extern void pci_load_of_ranges(struct pci_controller *hose,
74 struct device_node *node);
75#else
76static inline void pci_load_of_ranges(struct pci_controller *hose,
77 struct device_node *node) {}
78#endif
79
80#ifdef CONFIG_PCI_DOMAINS_GENERIC
81static inline void set_pci_need_domain_info(struct pci_controller *hose,
82 int need_domain_info)
83{
84 /* nothing to do */
85}
86#elif defined(CONFIG_PCI_DOMAINS)
87static inline void set_pci_need_domain_info(struct pci_controller *hose,
88 int need_domain_info)
89{
90 hose->need_domain_info = need_domain_info;
91}
92#endif /* CONFIG_PCI_DOMAINS */
93
94#endif
95
96/* Can be used to override the logic in pci_scan_bus for skipping
97 already-configured bus numbers - to be used for buggy BIOSes
98 or architectures with incomplete PCI setup by the loader */
99static inline unsigned int pcibios_assign_all_busses(void)
100{
101 return 1;
102}
103
104extern unsigned long PCIBIOS_MIN_IO;
105extern unsigned long PCIBIOS_MIN_MEM;
106
107#define PCIBIOS_MIN_CARDBUS_IO 0x4000
108
109#define HAVE_PCI_MMAP
110#define ARCH_GENERIC_PCI_MMAP_RESOURCE
111
112/*
113 * Dynamic DMA mapping stuff.
114 * MIPS has everything mapped statically.
115 */
116
117#include <linux/types.h>
118#include <linux/slab.h>
119#include <linux/scatterlist.h>
120#include <linux/string.h>
121#include <asm/io.h>
122
123#ifdef CONFIG_PCI_DOMAINS_GENERIC
124static inline int pci_proc_domain(struct pci_bus *bus)
125{
126 return pci_domain_nr(bus);
127}
128#elif defined(CONFIG_PCI_DOMAINS)
129#define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index
130
131static inline int pci_proc_domain(struct pci_bus *bus)
132{
133 struct pci_controller *hose = bus->sysdata;
134 return hose->need_domain_info;
135}
136#endif /* CONFIG_PCI_DOMAINS */
137
138#endif /* __KERNEL__ */
139
140/* Do platform specific device initialization at pci_enable_device() time */
141extern int pcibios_plat_dev_init(struct pci_dev *dev);
142
143/* Chances are this interrupt is wired PC-style ... */
144static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
145{
146 return channel ? 15 : 14;
147}
148
149#endif /* _ASM_PCI_H */
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 */
6#ifndef _ASM_PCI_H
7#define _ASM_PCI_H
8
9#include <linux/mm.h>
10
11#ifdef __KERNEL__
12
13/*
14 * This file essentially defines the interface between board
15 * specific PCI code and MIPS common PCI code. Should potentially put
16 * into include/asm/pci.h file.
17 */
18
19#include <linux/ioport.h>
20#include <linux/of.h>
21
22/*
23 * Each pci channel is a top-level PCI bus seem by CPU. A machine with
24 * multiple PCI channels may have multiple PCI host controllers or a
25 * single controller supporting multiple channels.
26 */
27struct pci_controller {
28 struct pci_controller *next;
29 struct pci_bus *bus;
30 struct device_node *of_node;
31
32 struct pci_ops *pci_ops;
33 struct resource *mem_resource;
34 unsigned long mem_offset;
35 struct resource *io_resource;
36 unsigned long io_offset;
37 unsigned long io_map_base;
38 struct resource *busn_resource;
39 unsigned long busn_offset;
40
41 unsigned int index;
42 /* For compatibility with current (as of July 2003) pciutils
43 and XFree86. Eventually will be removed. */
44 unsigned int need_domain_info;
45
46 int iommu;
47
48 /* Optional access methods for reading/writing the bus number
49 of the PCI controller */
50 int (*get_busno)(void);
51 void (*set_busno)(int busno);
52};
53
54/*
55 * Used by boards to register their PCI busses before the actual scanning.
56 */
57extern void register_pci_controller(struct pci_controller *hose);
58
59/*
60 * board supplied pci irq fixup routine
61 */
62extern int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
63
64
65/* Can be used to override the logic in pci_scan_bus for skipping
66 already-configured bus numbers - to be used for buggy BIOSes
67 or architectures with incomplete PCI setup by the loader */
68
69extern unsigned int pcibios_assign_all_busses(void);
70
71extern unsigned long PCIBIOS_MIN_IO;
72extern unsigned long PCIBIOS_MIN_MEM;
73
74#define PCIBIOS_MIN_CARDBUS_IO 0x4000
75
76extern void pcibios_set_master(struct pci_dev *dev);
77
78#define HAVE_PCI_MMAP
79
80extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
81 enum pci_mmap_state mmap_state, int write_combine);
82
83#define HAVE_ARCH_PCI_RESOURCE_TO_USER
84
85static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
86 const struct resource *rsrc, resource_size_t *start,
87 resource_size_t *end)
88{
89 phys_addr_t size = resource_size(rsrc);
90
91 *start = fixup_bigphys_addr(rsrc->start, size);
92 *end = rsrc->start + size;
93}
94
95/*
96 * Dynamic DMA mapping stuff.
97 * MIPS has everything mapped statically.
98 */
99
100#include <linux/types.h>
101#include <linux/slab.h>
102#include <linux/scatterlist.h>
103#include <linux/string.h>
104#include <asm/io.h>
105
106struct pci_dev;
107
108/*
109 * The PCI address space does equal the physical memory address space. The
110 * networking and block device layers use this boolean for bounce buffer
111 * decisions. This is set if any hose does not have an IOMMU.
112 */
113extern unsigned int PCI_DMA_BUS_IS_PHYS;
114
115#ifdef CONFIG_PCI_DOMAINS
116#define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index
117
118static inline int pci_proc_domain(struct pci_bus *bus)
119{
120 struct pci_controller *hose = bus->sysdata;
121 return hose->need_domain_info;
122}
123#endif /* CONFIG_PCI_DOMAINS */
124
125#endif /* __KERNEL__ */
126
127/* Do platform specific device initialization at pci_enable_device() time */
128extern int pcibios_plat_dev_init(struct pci_dev *dev);
129
130/* Chances are this interrupt is wired PC-style ... */
131static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
132{
133 return channel ? 15 : 14;
134}
135
136extern char * (*pcibios_plat_setup)(char *str);
137
138#ifdef CONFIG_OF
139/* this function parses memory ranges from a device node */
140extern void pci_load_of_ranges(struct pci_controller *hose,
141 struct device_node *node);
142#else
143static inline void pci_load_of_ranges(struct pci_controller *hose,
144 struct device_node *node) {}
145#endif
146
147#endif /* _ASM_PCI_H */