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1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003, 06, 07 by Ralf Baechle (ralf@linux-mips.org)
7 */
8#ifndef __ASM_CMPXCHG_H
9#define __ASM_CMPXCHG_H
10
11#include <linux/bug.h>
12#include <linux/irqflags.h>
13#include <asm/compiler.h>
14#include <asm/llsc.h>
15#include <asm/sync.h>
16#include <asm/war.h>
17
18/*
19 * These functions doesn't exist, so if they are called you'll either:
20 *
21 * - Get an error at compile-time due to __compiletime_error, if supported by
22 * your compiler.
23 *
24 * or:
25 *
26 * - Get an error at link-time due to the call to the missing function.
27 */
28extern unsigned long __cmpxchg_called_with_bad_pointer(void)
29 __compiletime_error("Bad argument size for cmpxchg");
30extern unsigned long __cmpxchg64_unsupported(void)
31 __compiletime_error("cmpxchg64 not available; cpu_has_64bits may be false");
32extern unsigned long __xchg_called_with_bad_pointer(void)
33 __compiletime_error("Bad argument size for xchg");
34
35#define __xchg_asm(ld, st, m, val) \
36({ \
37 __typeof(*(m)) __ret; \
38 \
39 if (kernel_uses_llsc) { \
40 __asm__ __volatile__( \
41 " .set push \n" \
42 " .set noat \n" \
43 " .set push \n" \
44 " .set " MIPS_ISA_ARCH_LEVEL " \n" \
45 " " __SYNC(full, loongson3_war) " \n" \
46 "1: " ld " %0, %2 # __xchg_asm \n" \
47 " .set pop \n" \
48 " move $1, %z3 \n" \
49 " .set " MIPS_ISA_ARCH_LEVEL " \n" \
50 " " st " $1, %1 \n" \
51 "\t" __SC_BEQZ "$1, 1b \n" \
52 " .set pop \n" \
53 : "=&r" (__ret), "=" GCC_OFF_SMALL_ASM() (*m) \
54 : GCC_OFF_SMALL_ASM() (*m), "Jr" (val) \
55 : __LLSC_CLOBBER); \
56 } else { \
57 unsigned long __flags; \
58 \
59 raw_local_irq_save(__flags); \
60 __ret = *m; \
61 *m = val; \
62 raw_local_irq_restore(__flags); \
63 } \
64 \
65 __ret; \
66})
67
68extern unsigned long __xchg_small(volatile void *ptr, unsigned long val,
69 unsigned int size);
70
71static __always_inline
72unsigned long __xchg(volatile void *ptr, unsigned long x, int size)
73{
74 switch (size) {
75 case 1:
76 case 2:
77 return __xchg_small(ptr, x, size);
78
79 case 4:
80 return __xchg_asm("ll", "sc", (volatile u32 *)ptr, x);
81
82 case 8:
83 if (!IS_ENABLED(CONFIG_64BIT))
84 return __xchg_called_with_bad_pointer();
85
86 return __xchg_asm("lld", "scd", (volatile u64 *)ptr, x);
87
88 default:
89 return __xchg_called_with_bad_pointer();
90 }
91}
92
93#define xchg(ptr, x) \
94({ \
95 __typeof__(*(ptr)) __res; \
96 \
97 /* \
98 * In the Loongson3 workaround case __xchg_asm() already \
99 * contains a completion barrier prior to the LL, so we don't \
100 * need to emit an extra one here. \
101 */ \
102 if (!__SYNC_loongson3_war) \
103 smp_mb__before_llsc(); \
104 \
105 __res = (__typeof__(*(ptr))) \
106 __xchg((ptr), (unsigned long)(x), sizeof(*(ptr))); \
107 \
108 smp_llsc_mb(); \
109 \
110 __res; \
111})
112
113#define __cmpxchg_asm(ld, st, m, old, new) \
114({ \
115 __typeof(*(m)) __ret; \
116 \
117 if (kernel_uses_llsc) { \
118 __asm__ __volatile__( \
119 " .set push \n" \
120 " .set noat \n" \
121 " .set push \n" \
122 " .set "MIPS_ISA_ARCH_LEVEL" \n" \
123 " " __SYNC(full, loongson3_war) " \n" \
124 "1: " ld " %0, %2 # __cmpxchg_asm \n" \
125 " bne %0, %z3, 2f \n" \
126 " .set pop \n" \
127 " move $1, %z4 \n" \
128 " .set "MIPS_ISA_ARCH_LEVEL" \n" \
129 " " st " $1, %1 \n" \
130 "\t" __SC_BEQZ "$1, 1b \n" \
131 " .set pop \n" \
132 "2: " __SYNC(full, loongson3_war) " \n" \
133 : "=&r" (__ret), "=" GCC_OFF_SMALL_ASM() (*m) \
134 : GCC_OFF_SMALL_ASM() (*m), "Jr" (old), "Jr" (new) \
135 : __LLSC_CLOBBER); \
136 } else { \
137 unsigned long __flags; \
138 \
139 raw_local_irq_save(__flags); \
140 __ret = *m; \
141 if (__ret == old) \
142 *m = new; \
143 raw_local_irq_restore(__flags); \
144 } \
145 \
146 __ret; \
147})
148
149extern unsigned long __cmpxchg_small(volatile void *ptr, unsigned long old,
150 unsigned long new, unsigned int size);
151
152static __always_inline
153unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
154 unsigned long new, unsigned int size)
155{
156 switch (size) {
157 case 1:
158 case 2:
159 return __cmpxchg_small(ptr, old, new, size);
160
161 case 4:
162 return __cmpxchg_asm("ll", "sc", (volatile u32 *)ptr,
163 (u32)old, new);
164
165 case 8:
166 /* lld/scd are only available for MIPS64 */
167 if (!IS_ENABLED(CONFIG_64BIT))
168 return __cmpxchg_called_with_bad_pointer();
169
170 return __cmpxchg_asm("lld", "scd", (volatile u64 *)ptr,
171 (u64)old, new);
172
173 default:
174 return __cmpxchg_called_with_bad_pointer();
175 }
176}
177
178#define cmpxchg_local(ptr, old, new) \
179 ((__typeof__(*(ptr))) \
180 __cmpxchg((ptr), \
181 (unsigned long)(__typeof__(*(ptr)))(old), \
182 (unsigned long)(__typeof__(*(ptr)))(new), \
183 sizeof(*(ptr))))
184
185#define cmpxchg(ptr, old, new) \
186({ \
187 __typeof__(*(ptr)) __res; \
188 \
189 /* \
190 * In the Loongson3 workaround case __cmpxchg_asm() already \
191 * contains a completion barrier prior to the LL, so we don't \
192 * need to emit an extra one here. \
193 */ \
194 if (!__SYNC_loongson3_war) \
195 smp_mb__before_llsc(); \
196 \
197 __res = cmpxchg_local((ptr), (old), (new)); \
198 \
199 /* \
200 * In the Loongson3 workaround case __cmpxchg_asm() already \
201 * contains a completion barrier after the SC, so we don't \
202 * need to emit an extra one here. \
203 */ \
204 if (!__SYNC_loongson3_war) \
205 smp_llsc_mb(); \
206 \
207 __res; \
208})
209
210#ifdef CONFIG_64BIT
211#define cmpxchg64_local(ptr, o, n) \
212 ({ \
213 BUILD_BUG_ON(sizeof(*(ptr)) != 8); \
214 cmpxchg_local((ptr), (o), (n)); \
215 })
216
217#define cmpxchg64(ptr, o, n) \
218 ({ \
219 BUILD_BUG_ON(sizeof(*(ptr)) != 8); \
220 cmpxchg((ptr), (o), (n)); \
221 })
222#else
223
224# include <asm-generic/cmpxchg-local.h>
225# define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
226
227# ifdef CONFIG_SMP
228
229static inline unsigned long __cmpxchg64(volatile void *ptr,
230 unsigned long long old,
231 unsigned long long new)
232{
233 unsigned long long tmp, ret;
234 unsigned long flags;
235
236 /*
237 * The assembly below has to combine 32 bit values into a 64 bit
238 * register, and split 64 bit values from one register into two. If we
239 * were to take an interrupt in the middle of this we'd only save the
240 * least significant 32 bits of each register & probably clobber the
241 * most significant 32 bits of the 64 bit values we're using. In order
242 * to avoid this we must disable interrupts.
243 */
244 local_irq_save(flags);
245
246 asm volatile(
247 " .set push \n"
248 " .set " MIPS_ISA_ARCH_LEVEL " \n"
249 /* Load 64 bits from ptr */
250 " " __SYNC(full, loongson3_war) " \n"
251 "1: lld %L0, %3 # __cmpxchg64 \n"
252 /*
253 * Split the 64 bit value we loaded into the 2 registers that hold the
254 * ret variable.
255 */
256 " dsra %M0, %L0, 32 \n"
257 " sll %L0, %L0, 0 \n"
258 /*
259 * Compare ret against old, breaking out of the loop if they don't
260 * match.
261 */
262 " bne %M0, %M4, 2f \n"
263 " bne %L0, %L4, 2f \n"
264 /*
265 * Combine the 32 bit halves from the 2 registers that hold the new
266 * variable into a single 64 bit register.
267 */
268# if MIPS_ISA_REV >= 2
269 " move %L1, %L5 \n"
270 " dins %L1, %M5, 32, 32 \n"
271# else
272 " dsll %L1, %L5, 32 \n"
273 " dsrl %L1, %L1, 32 \n"
274 " .set noat \n"
275 " dsll $at, %M5, 32 \n"
276 " or %L1, %L1, $at \n"
277 " .set at \n"
278# endif
279 /* Attempt to store new at ptr */
280 " scd %L1, %2 \n"
281 /* If we failed, loop! */
282 "\t" __SC_BEQZ "%L1, 1b \n"
283 " .set pop \n"
284 "2: " __SYNC(full, loongson3_war) " \n"
285 : "=&r"(ret),
286 "=&r"(tmp),
287 "=" GCC_OFF_SMALL_ASM() (*(unsigned long long *)ptr)
288 : GCC_OFF_SMALL_ASM() (*(unsigned long long *)ptr),
289 "r" (old),
290 "r" (new)
291 : "memory");
292
293 local_irq_restore(flags);
294 return ret;
295}
296
297# define cmpxchg64(ptr, o, n) ({ \
298 unsigned long long __old = (__typeof__(*(ptr)))(o); \
299 unsigned long long __new = (__typeof__(*(ptr)))(n); \
300 __typeof__(*(ptr)) __res; \
301 \
302 /* \
303 * We can only use cmpxchg64 if we know that the CPU supports \
304 * 64-bits, ie. lld & scd. Our call to __cmpxchg64_unsupported \
305 * will cause a build error unless cpu_has_64bits is a \
306 * compile-time constant 1. \
307 */ \
308 if (cpu_has_64bits && kernel_uses_llsc) { \
309 smp_mb__before_llsc(); \
310 __res = __cmpxchg64((ptr), __old, __new); \
311 smp_llsc_mb(); \
312 } else { \
313 __res = __cmpxchg64_unsupported(); \
314 } \
315 \
316 __res; \
317})
318
319# else /* !CONFIG_SMP */
320# define cmpxchg64(ptr, o, n) cmpxchg64_local((ptr), (o), (n))
321# endif /* !CONFIG_SMP */
322#endif /* !CONFIG_64BIT */
323
324#endif /* __ASM_CMPXCHG_H */
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003, 06, 07 by Ralf Baechle (ralf@linux-mips.org)
7 */
8#ifndef __ASM_CMPXCHG_H
9#define __ASM_CMPXCHG_H
10
11#include <linux/bug.h>
12#include <linux/irqflags.h>
13#include <asm/compiler.h>
14#include <asm/war.h>
15
16static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
17{
18 __u32 retval;
19
20 smp_mb__before_llsc();
21
22 if (kernel_uses_llsc && R10000_LLSC_WAR) {
23 unsigned long dummy;
24
25 __asm__ __volatile__(
26 " .set arch=r4000 \n"
27 "1: ll %0, %3 # xchg_u32 \n"
28 " .set mips0 \n"
29 " move %2, %z4 \n"
30 " .set arch=r4000 \n"
31 " sc %2, %1 \n"
32 " beqzl %2, 1b \n"
33 " .set mips0 \n"
34 : "=&r" (retval), "=" GCC_OFF_SMALL_ASM() (*m), "=&r" (dummy)
35 : GCC_OFF_SMALL_ASM() (*m), "Jr" (val)
36 : "memory");
37 } else if (kernel_uses_llsc) {
38 unsigned long dummy;
39
40 do {
41 __asm__ __volatile__(
42 " .set "MIPS_ISA_ARCH_LEVEL" \n"
43 " ll %0, %3 # xchg_u32 \n"
44 " .set mips0 \n"
45 " move %2, %z4 \n"
46 " .set "MIPS_ISA_ARCH_LEVEL" \n"
47 " sc %2, %1 \n"
48 " .set mips0 \n"
49 : "=&r" (retval), "=" GCC_OFF_SMALL_ASM() (*m),
50 "=&r" (dummy)
51 : GCC_OFF_SMALL_ASM() (*m), "Jr" (val)
52 : "memory");
53 } while (unlikely(!dummy));
54 } else {
55 unsigned long flags;
56
57 raw_local_irq_save(flags);
58 retval = *m;
59 *m = val;
60 raw_local_irq_restore(flags); /* implies memory barrier */
61 }
62
63 smp_llsc_mb();
64
65 return retval;
66}
67
68#ifdef CONFIG_64BIT
69static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val)
70{
71 __u64 retval;
72
73 smp_mb__before_llsc();
74
75 if (kernel_uses_llsc && R10000_LLSC_WAR) {
76 unsigned long dummy;
77
78 __asm__ __volatile__(
79 " .set arch=r4000 \n"
80 "1: lld %0, %3 # xchg_u64 \n"
81 " move %2, %z4 \n"
82 " scd %2, %1 \n"
83 " beqzl %2, 1b \n"
84 " .set mips0 \n"
85 : "=&r" (retval), "=" GCC_OFF_SMALL_ASM() (*m), "=&r" (dummy)
86 : GCC_OFF_SMALL_ASM() (*m), "Jr" (val)
87 : "memory");
88 } else if (kernel_uses_llsc) {
89 unsigned long dummy;
90
91 do {
92 __asm__ __volatile__(
93 " .set "MIPS_ISA_ARCH_LEVEL" \n"
94 " lld %0, %3 # xchg_u64 \n"
95 " move %2, %z4 \n"
96 " scd %2, %1 \n"
97 " .set mips0 \n"
98 : "=&r" (retval), "=" GCC_OFF_SMALL_ASM() (*m),
99 "=&r" (dummy)
100 : GCC_OFF_SMALL_ASM() (*m), "Jr" (val)
101 : "memory");
102 } while (unlikely(!dummy));
103 } else {
104 unsigned long flags;
105
106 raw_local_irq_save(flags);
107 retval = *m;
108 *m = val;
109 raw_local_irq_restore(flags); /* implies memory barrier */
110 }
111
112 smp_llsc_mb();
113
114 return retval;
115}
116#else
117extern __u64 __xchg_u64_unsupported_on_32bit_kernels(volatile __u64 * m, __u64 val);
118#define __xchg_u64 __xchg_u64_unsupported_on_32bit_kernels
119#endif
120
121static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
122{
123 switch (size) {
124 case 4:
125 return __xchg_u32(ptr, x);
126 case 8:
127 return __xchg_u64(ptr, x);
128 }
129
130 return x;
131}
132
133#define xchg(ptr, x) \
134({ \
135 BUILD_BUG_ON(sizeof(*(ptr)) & ~0xc); \
136 \
137 ((__typeof__(*(ptr))) \
138 __xchg((unsigned long)(x), (ptr), sizeof(*(ptr)))); \
139})
140
141#define __cmpxchg_asm(ld, st, m, old, new) \
142({ \
143 __typeof(*(m)) __ret; \
144 \
145 if (kernel_uses_llsc && R10000_LLSC_WAR) { \
146 __asm__ __volatile__( \
147 " .set push \n" \
148 " .set noat \n" \
149 " .set arch=r4000 \n" \
150 "1: " ld " %0, %2 # __cmpxchg_asm \n" \
151 " bne %0, %z3, 2f \n" \
152 " .set mips0 \n" \
153 " move $1, %z4 \n" \
154 " .set arch=r4000 \n" \
155 " " st " $1, %1 \n" \
156 " beqzl $1, 1b \n" \
157 "2: \n" \
158 " .set pop \n" \
159 : "=&r" (__ret), "=" GCC_OFF_SMALL_ASM() (*m) \
160 : GCC_OFF_SMALL_ASM() (*m), "Jr" (old), "Jr" (new) \
161 : "memory"); \
162 } else if (kernel_uses_llsc) { \
163 __asm__ __volatile__( \
164 " .set push \n" \
165 " .set noat \n" \
166 " .set "MIPS_ISA_ARCH_LEVEL" \n" \
167 "1: " ld " %0, %2 # __cmpxchg_asm \n" \
168 " bne %0, %z3, 2f \n" \
169 " .set mips0 \n" \
170 " move $1, %z4 \n" \
171 " .set "MIPS_ISA_ARCH_LEVEL" \n" \
172 " " st " $1, %1 \n" \
173 " beqz $1, 1b \n" \
174 " .set pop \n" \
175 "2: \n" \
176 : "=&r" (__ret), "=" GCC_OFF_SMALL_ASM() (*m) \
177 : GCC_OFF_SMALL_ASM() (*m), "Jr" (old), "Jr" (new) \
178 : "memory"); \
179 } else { \
180 unsigned long __flags; \
181 \
182 raw_local_irq_save(__flags); \
183 __ret = *m; \
184 if (__ret == old) \
185 *m = new; \
186 raw_local_irq_restore(__flags); \
187 } \
188 \
189 __ret; \
190})
191
192/*
193 * This function doesn't exist, so you'll get a linker error
194 * if something tries to do an invalid cmpxchg().
195 */
196extern void __cmpxchg_called_with_bad_pointer(void);
197
198#define __cmpxchg(ptr, old, new, pre_barrier, post_barrier) \
199({ \
200 __typeof__(ptr) __ptr = (ptr); \
201 __typeof__(*(ptr)) __old = (old); \
202 __typeof__(*(ptr)) __new = (new); \
203 __typeof__(*(ptr)) __res = 0; \
204 \
205 pre_barrier; \
206 \
207 switch (sizeof(*(__ptr))) { \
208 case 4: \
209 __res = __cmpxchg_asm("ll", "sc", __ptr, __old, __new); \
210 break; \
211 case 8: \
212 if (sizeof(long) == 8) { \
213 __res = __cmpxchg_asm("lld", "scd", __ptr, \
214 __old, __new); \
215 break; \
216 } \
217 default: \
218 __cmpxchg_called_with_bad_pointer(); \
219 break; \
220 } \
221 \
222 post_barrier; \
223 \
224 __res; \
225})
226
227#define cmpxchg(ptr, old, new) __cmpxchg(ptr, old, new, smp_mb__before_llsc(), smp_llsc_mb())
228#define cmpxchg_local(ptr, old, new) __cmpxchg(ptr, old, new, , )
229
230#ifdef CONFIG_64BIT
231#define cmpxchg64_local(ptr, o, n) \
232 ({ \
233 BUILD_BUG_ON(sizeof(*(ptr)) != 8); \
234 cmpxchg_local((ptr), (o), (n)); \
235 })
236
237#define cmpxchg64(ptr, o, n) \
238 ({ \
239 BUILD_BUG_ON(sizeof(*(ptr)) != 8); \
240 cmpxchg((ptr), (o), (n)); \
241 })
242#else
243#include <asm-generic/cmpxchg-local.h>
244#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
245#define cmpxchg64(ptr, o, n) cmpxchg64_local((ptr), (o), (n))
246#endif
247
248#endif /* __ASM_CMPXCHG_H */