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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * ALSA driver for RME Digi32, Digi32/8 and Digi32 PRO audio interfaces
4 *
5 * Copyright (c) 2002-2004 Martin Langer <martin-langer@gmx.de>,
6 * Pilo Chambert <pilo.c@wanadoo.fr>
7 *
8 * Thanks to : Anders Torger <torger@ludd.luth.se>,
9 * Henk Hesselink <henk@anda.nl>
10 * for writing the digi96-driver
11 * and RME for all informations.
12 *
13 * ****************************************************************************
14 *
15 * Note #1 "Sek'd models" ................................... martin 2002-12-07
16 *
17 * Identical soundcards by Sek'd were labeled:
18 * RME Digi 32 = Sek'd Prodif 32
19 * RME Digi 32 Pro = Sek'd Prodif 96
20 * RME Digi 32/8 = Sek'd Prodif Gold
21 *
22 * ****************************************************************************
23 *
24 * Note #2 "full duplex mode" ............................... martin 2002-12-07
25 *
26 * Full duplex doesn't work. All cards (32, 32/8, 32Pro) are working identical
27 * in this mode. Rec data and play data are using the same buffer therefore. At
28 * first you have got the playing bits in the buffer and then (after playing
29 * them) they were overwitten by the captured sound of the CS8412/14. Both
30 * modes (play/record) are running harmonically hand in hand in the same buffer
31 * and you have only one start bit plus one interrupt bit to control this
32 * paired action.
33 * This is opposite to the latter rme96 where playing and capturing is totally
34 * separated and so their full duplex mode is supported by alsa (using two
35 * start bits and two interrupts for two different buffers).
36 * But due to the wrong sequence of playing and capturing ALSA shows no solved
37 * full duplex support for the rme32 at the moment. That's bad, but I'm not
38 * able to solve it. Are you motivated enough to solve this problem now? Your
39 * patch would be welcome!
40 *
41 * ****************************************************************************
42 *
43 * "The story after the long seeking" -- tiwai
44 *
45 * Ok, the situation regarding the full duplex is now improved a bit.
46 * In the fullduplex mode (given by the module parameter), the hardware buffer
47 * is split to halves for read and write directions at the DMA pointer.
48 * That is, the half above the current DMA pointer is used for write, and
49 * the half below is used for read. To mangle this strange behavior, an
50 * software intermediate buffer is introduced. This is, of course, not good
51 * from the viewpoint of the data transfer efficiency. However, this allows
52 * you to use arbitrary buffer sizes, instead of the fixed I/O buffer size.
53 *
54 * ****************************************************************************
55 */
56
57
58#include <linux/delay.h>
59#include <linux/gfp.h>
60#include <linux/init.h>
61#include <linux/interrupt.h>
62#include <linux/pci.h>
63#include <linux/module.h>
64#include <linux/io.h>
65
66#include <sound/core.h>
67#include <sound/info.h>
68#include <sound/control.h>
69#include <sound/pcm.h>
70#include <sound/pcm_params.h>
71#include <sound/pcm-indirect.h>
72#include <sound/asoundef.h>
73#include <sound/initval.h>
74
75static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
76static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
77static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
78static bool fullduplex[SNDRV_CARDS]; // = {[0 ... (SNDRV_CARDS - 1)] = 1};
79
80module_param_array(index, int, NULL, 0444);
81MODULE_PARM_DESC(index, "Index value for RME Digi32 soundcard.");
82module_param_array(id, charp, NULL, 0444);
83MODULE_PARM_DESC(id, "ID string for RME Digi32 soundcard.");
84module_param_array(enable, bool, NULL, 0444);
85MODULE_PARM_DESC(enable, "Enable RME Digi32 soundcard.");
86module_param_array(fullduplex, bool, NULL, 0444);
87MODULE_PARM_DESC(fullduplex, "Support full-duplex mode.");
88MODULE_AUTHOR("Martin Langer <martin-langer@gmx.de>, Pilo Chambert <pilo.c@wanadoo.fr>");
89MODULE_DESCRIPTION("RME Digi32, Digi32/8, Digi32 PRO");
90MODULE_LICENSE("GPL");
91MODULE_SUPPORTED_DEVICE("{{RME,Digi32}," "{RME,Digi32/8}," "{RME,Digi32 PRO}}");
92
93/* Defines for RME Digi32 series */
94#define RME32_SPDIF_NCHANNELS 2
95
96/* Playback and capture buffer size */
97#define RME32_BUFFER_SIZE 0x20000
98
99/* IO area size */
100#define RME32_IO_SIZE 0x30000
101
102/* IO area offsets */
103#define RME32_IO_DATA_BUFFER 0x0
104#define RME32_IO_CONTROL_REGISTER 0x20000
105#define RME32_IO_GET_POS 0x20000
106#define RME32_IO_CONFIRM_ACTION_IRQ 0x20004
107#define RME32_IO_RESET_POS 0x20100
108
109/* Write control register bits */
110#define RME32_WCR_START (1 << 0) /* startbit */
111#define RME32_WCR_MONO (1 << 1) /* 0=stereo, 1=mono
112 Setting the whole card to mono
113 doesn't seem to be very useful.
114 A software-solution can handle
115 full-duplex with one direction in
116 stereo and the other way in mono.
117 So, the hardware should work all
118 the time in stereo! */
119#define RME32_WCR_MODE24 (1 << 2) /* 0=16bit, 1=32bit */
120#define RME32_WCR_SEL (1 << 3) /* 0=input on output, 1=normal playback/capture */
121#define RME32_WCR_FREQ_0 (1 << 4) /* frequency (play) */
122#define RME32_WCR_FREQ_1 (1 << 5)
123#define RME32_WCR_INP_0 (1 << 6) /* input switch */
124#define RME32_WCR_INP_1 (1 << 7)
125#define RME32_WCR_RESET (1 << 8) /* Reset address */
126#define RME32_WCR_MUTE (1 << 9) /* digital mute for output */
127#define RME32_WCR_PRO (1 << 10) /* 1=professional, 0=consumer */
128#define RME32_WCR_DS_BM (1 << 11) /* 1=DoubleSpeed (only PRO-Version); 1=BlockMode (only Adat-Version) */
129#define RME32_WCR_ADAT (1 << 12) /* Adat Mode (only Adat-Version) */
130#define RME32_WCR_AUTOSYNC (1 << 13) /* AutoSync */
131#define RME32_WCR_PD (1 << 14) /* DAC Reset (only PRO-Version) */
132#define RME32_WCR_EMP (1 << 15) /* 1=Emphasis on (only PRO-Version) */
133
134#define RME32_WCR_BITPOS_FREQ_0 4
135#define RME32_WCR_BITPOS_FREQ_1 5
136#define RME32_WCR_BITPOS_INP_0 6
137#define RME32_WCR_BITPOS_INP_1 7
138
139/* Read control register bits */
140#define RME32_RCR_AUDIO_ADDR_MASK 0x1ffff
141#define RME32_RCR_LOCK (1 << 23) /* 1=locked, 0=not locked */
142#define RME32_RCR_ERF (1 << 26) /* 1=Error, 0=no Error */
143#define RME32_RCR_FREQ_0 (1 << 27) /* CS841x frequency (record) */
144#define RME32_RCR_FREQ_1 (1 << 28)
145#define RME32_RCR_FREQ_2 (1 << 29)
146#define RME32_RCR_KMODE (1 << 30) /* card mode: 1=PLL, 0=quartz */
147#define RME32_RCR_IRQ (1 << 31) /* interrupt */
148
149#define RME32_RCR_BITPOS_F0 27
150#define RME32_RCR_BITPOS_F1 28
151#define RME32_RCR_BITPOS_F2 29
152
153/* Input types */
154#define RME32_INPUT_OPTICAL 0
155#define RME32_INPUT_COAXIAL 1
156#define RME32_INPUT_INTERNAL 2
157#define RME32_INPUT_XLR 3
158
159/* Clock modes */
160#define RME32_CLOCKMODE_SLAVE 0
161#define RME32_CLOCKMODE_MASTER_32 1
162#define RME32_CLOCKMODE_MASTER_44 2
163#define RME32_CLOCKMODE_MASTER_48 3
164
165/* Block sizes in bytes */
166#define RME32_BLOCK_SIZE 8192
167
168/* Software intermediate buffer (max) size */
169#define RME32_MID_BUFFER_SIZE (1024*1024)
170
171/* Hardware revisions */
172#define RME32_32_REVISION 192
173#define RME32_328_REVISION_OLD 100
174#define RME32_328_REVISION_NEW 101
175#define RME32_PRO_REVISION_WITH_8412 192
176#define RME32_PRO_REVISION_WITH_8414 150
177
178
179struct rme32 {
180 spinlock_t lock;
181 int irq;
182 unsigned long port;
183 void __iomem *iobase;
184
185 u32 wcreg; /* cached write control register value */
186 u32 wcreg_spdif; /* S/PDIF setup */
187 u32 wcreg_spdif_stream; /* S/PDIF setup (temporary) */
188 u32 rcreg; /* cached read control register value */
189
190 u8 rev; /* card revision number */
191
192 struct snd_pcm_substream *playback_substream;
193 struct snd_pcm_substream *capture_substream;
194
195 int playback_frlog; /* log2 of framesize */
196 int capture_frlog;
197
198 size_t playback_periodsize; /* in bytes, zero if not used */
199 size_t capture_periodsize; /* in bytes, zero if not used */
200
201 unsigned int fullduplex_mode;
202 int running;
203
204 struct snd_pcm_indirect playback_pcm;
205 struct snd_pcm_indirect capture_pcm;
206
207 struct snd_card *card;
208 struct snd_pcm *spdif_pcm;
209 struct snd_pcm *adat_pcm;
210 struct pci_dev *pci;
211 struct snd_kcontrol *spdif_ctl;
212};
213
214static const struct pci_device_id snd_rme32_ids[] = {
215 {PCI_VDEVICE(XILINX_RME, PCI_DEVICE_ID_RME_DIGI32), 0,},
216 {PCI_VDEVICE(XILINX_RME, PCI_DEVICE_ID_RME_DIGI32_8), 0,},
217 {PCI_VDEVICE(XILINX_RME, PCI_DEVICE_ID_RME_DIGI32_PRO), 0,},
218 {0,}
219};
220
221MODULE_DEVICE_TABLE(pci, snd_rme32_ids);
222
223#define RME32_ISWORKING(rme32) ((rme32)->wcreg & RME32_WCR_START)
224#define RME32_PRO_WITH_8414(rme32) ((rme32)->pci->device == PCI_DEVICE_ID_RME_DIGI32_PRO && (rme32)->rev == RME32_PRO_REVISION_WITH_8414)
225
226static int snd_rme32_playback_prepare(struct snd_pcm_substream *substream);
227
228static int snd_rme32_capture_prepare(struct snd_pcm_substream *substream);
229
230static int snd_rme32_pcm_trigger(struct snd_pcm_substream *substream, int cmd);
231
232static void snd_rme32_proc_init(struct rme32 * rme32);
233
234static int snd_rme32_create_switches(struct snd_card *card, struct rme32 * rme32);
235
236static inline unsigned int snd_rme32_pcm_byteptr(struct rme32 * rme32)
237{
238 return (readl(rme32->iobase + RME32_IO_GET_POS)
239 & RME32_RCR_AUDIO_ADDR_MASK);
240}
241
242/* silence callback for halfduplex mode */
243static int snd_rme32_playback_silence(struct snd_pcm_substream *substream,
244 int channel, unsigned long pos,
245 unsigned long count)
246{
247 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
248
249 memset_io(rme32->iobase + RME32_IO_DATA_BUFFER + pos, 0, count);
250 return 0;
251}
252
253/* copy callback for halfduplex mode */
254static int snd_rme32_playback_copy(struct snd_pcm_substream *substream,
255 int channel, unsigned long pos,
256 void __user *src, unsigned long count)
257{
258 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
259
260 if (copy_from_user_toio(rme32->iobase + RME32_IO_DATA_BUFFER + pos,
261 src, count))
262 return -EFAULT;
263 return 0;
264}
265
266static int snd_rme32_playback_copy_kernel(struct snd_pcm_substream *substream,
267 int channel, unsigned long pos,
268 void *src, unsigned long count)
269{
270 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
271
272 memcpy_toio(rme32->iobase + RME32_IO_DATA_BUFFER + pos, src, count);
273 return 0;
274}
275
276/* copy callback for halfduplex mode */
277static int snd_rme32_capture_copy(struct snd_pcm_substream *substream,
278 int channel, unsigned long pos,
279 void __user *dst, unsigned long count)
280{
281 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
282
283 if (copy_to_user_fromio(dst,
284 rme32->iobase + RME32_IO_DATA_BUFFER + pos,
285 count))
286 return -EFAULT;
287 return 0;
288}
289
290static int snd_rme32_capture_copy_kernel(struct snd_pcm_substream *substream,
291 int channel, unsigned long pos,
292 void *dst, unsigned long count)
293{
294 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
295
296 memcpy_fromio(dst, rme32->iobase + RME32_IO_DATA_BUFFER + pos, count);
297 return 0;
298}
299
300/*
301 * SPDIF I/O capabilities (half-duplex mode)
302 */
303static const struct snd_pcm_hardware snd_rme32_spdif_info = {
304 .info = (SNDRV_PCM_INFO_MMAP_IOMEM |
305 SNDRV_PCM_INFO_MMAP_VALID |
306 SNDRV_PCM_INFO_INTERLEAVED |
307 SNDRV_PCM_INFO_PAUSE |
308 SNDRV_PCM_INFO_SYNC_START |
309 SNDRV_PCM_INFO_SYNC_APPLPTR),
310 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
311 SNDRV_PCM_FMTBIT_S32_LE),
312 .rates = (SNDRV_PCM_RATE_32000 |
313 SNDRV_PCM_RATE_44100 |
314 SNDRV_PCM_RATE_48000),
315 .rate_min = 32000,
316 .rate_max = 48000,
317 .channels_min = 2,
318 .channels_max = 2,
319 .buffer_bytes_max = RME32_BUFFER_SIZE,
320 .period_bytes_min = RME32_BLOCK_SIZE,
321 .period_bytes_max = RME32_BLOCK_SIZE,
322 .periods_min = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE,
323 .periods_max = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE,
324 .fifo_size = 0,
325};
326
327/*
328 * ADAT I/O capabilities (half-duplex mode)
329 */
330static const struct snd_pcm_hardware snd_rme32_adat_info =
331{
332 .info = (SNDRV_PCM_INFO_MMAP_IOMEM |
333 SNDRV_PCM_INFO_MMAP_VALID |
334 SNDRV_PCM_INFO_INTERLEAVED |
335 SNDRV_PCM_INFO_PAUSE |
336 SNDRV_PCM_INFO_SYNC_START |
337 SNDRV_PCM_INFO_SYNC_APPLPTR),
338 .formats= SNDRV_PCM_FMTBIT_S16_LE,
339 .rates = (SNDRV_PCM_RATE_44100 |
340 SNDRV_PCM_RATE_48000),
341 .rate_min = 44100,
342 .rate_max = 48000,
343 .channels_min = 8,
344 .channels_max = 8,
345 .buffer_bytes_max = RME32_BUFFER_SIZE,
346 .period_bytes_min = RME32_BLOCK_SIZE,
347 .period_bytes_max = RME32_BLOCK_SIZE,
348 .periods_min = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE,
349 .periods_max = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE,
350 .fifo_size = 0,
351};
352
353/*
354 * SPDIF I/O capabilities (full-duplex mode)
355 */
356static const struct snd_pcm_hardware snd_rme32_spdif_fd_info = {
357 .info = (SNDRV_PCM_INFO_MMAP |
358 SNDRV_PCM_INFO_MMAP_VALID |
359 SNDRV_PCM_INFO_INTERLEAVED |
360 SNDRV_PCM_INFO_PAUSE |
361 SNDRV_PCM_INFO_SYNC_START |
362 SNDRV_PCM_INFO_SYNC_APPLPTR),
363 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
364 SNDRV_PCM_FMTBIT_S32_LE),
365 .rates = (SNDRV_PCM_RATE_32000 |
366 SNDRV_PCM_RATE_44100 |
367 SNDRV_PCM_RATE_48000),
368 .rate_min = 32000,
369 .rate_max = 48000,
370 .channels_min = 2,
371 .channels_max = 2,
372 .buffer_bytes_max = RME32_MID_BUFFER_SIZE,
373 .period_bytes_min = RME32_BLOCK_SIZE,
374 .period_bytes_max = RME32_BLOCK_SIZE,
375 .periods_min = 2,
376 .periods_max = RME32_MID_BUFFER_SIZE / RME32_BLOCK_SIZE,
377 .fifo_size = 0,
378};
379
380/*
381 * ADAT I/O capabilities (full-duplex mode)
382 */
383static const struct snd_pcm_hardware snd_rme32_adat_fd_info =
384{
385 .info = (SNDRV_PCM_INFO_MMAP |
386 SNDRV_PCM_INFO_MMAP_VALID |
387 SNDRV_PCM_INFO_INTERLEAVED |
388 SNDRV_PCM_INFO_PAUSE |
389 SNDRV_PCM_INFO_SYNC_START |
390 SNDRV_PCM_INFO_SYNC_APPLPTR),
391 .formats= SNDRV_PCM_FMTBIT_S16_LE,
392 .rates = (SNDRV_PCM_RATE_44100 |
393 SNDRV_PCM_RATE_48000),
394 .rate_min = 44100,
395 .rate_max = 48000,
396 .channels_min = 8,
397 .channels_max = 8,
398 .buffer_bytes_max = RME32_MID_BUFFER_SIZE,
399 .period_bytes_min = RME32_BLOCK_SIZE,
400 .period_bytes_max = RME32_BLOCK_SIZE,
401 .periods_min = 2,
402 .periods_max = RME32_MID_BUFFER_SIZE / RME32_BLOCK_SIZE,
403 .fifo_size = 0,
404};
405
406static void snd_rme32_reset_dac(struct rme32 *rme32)
407{
408 writel(rme32->wcreg | RME32_WCR_PD,
409 rme32->iobase + RME32_IO_CONTROL_REGISTER);
410 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
411}
412
413static int snd_rme32_playback_getrate(struct rme32 * rme32)
414{
415 int rate;
416
417 rate = ((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_0) & 1) +
418 (((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_1) & 1) << 1);
419 switch (rate) {
420 case 1:
421 rate = 32000;
422 break;
423 case 2:
424 rate = 44100;
425 break;
426 case 3:
427 rate = 48000;
428 break;
429 default:
430 return -1;
431 }
432 return (rme32->wcreg & RME32_WCR_DS_BM) ? rate << 1 : rate;
433}
434
435static int snd_rme32_capture_getrate(struct rme32 * rme32, int *is_adat)
436{
437 int n;
438
439 *is_adat = 0;
440 if (rme32->rcreg & RME32_RCR_LOCK) {
441 /* ADAT rate */
442 *is_adat = 1;
443 }
444 if (rme32->rcreg & RME32_RCR_ERF) {
445 return -1;
446 }
447
448 /* S/PDIF rate */
449 n = ((rme32->rcreg >> RME32_RCR_BITPOS_F0) & 1) +
450 (((rme32->rcreg >> RME32_RCR_BITPOS_F1) & 1) << 1) +
451 (((rme32->rcreg >> RME32_RCR_BITPOS_F2) & 1) << 2);
452
453 if (RME32_PRO_WITH_8414(rme32))
454 switch (n) { /* supporting the CS8414 */
455 case 0:
456 case 1:
457 case 2:
458 return -1;
459 case 3:
460 return 96000;
461 case 4:
462 return 88200;
463 case 5:
464 return 48000;
465 case 6:
466 return 44100;
467 case 7:
468 return 32000;
469 default:
470 return -1;
471 break;
472 }
473 else
474 switch (n) { /* supporting the CS8412 */
475 case 0:
476 return -1;
477 case 1:
478 return 48000;
479 case 2:
480 return 44100;
481 case 3:
482 return 32000;
483 case 4:
484 return 48000;
485 case 5:
486 return 44100;
487 case 6:
488 return 44056;
489 case 7:
490 return 32000;
491 default:
492 break;
493 }
494 return -1;
495}
496
497static int snd_rme32_playback_setrate(struct rme32 * rme32, int rate)
498{
499 int ds;
500
501 ds = rme32->wcreg & RME32_WCR_DS_BM;
502 switch (rate) {
503 case 32000:
504 rme32->wcreg &= ~RME32_WCR_DS_BM;
505 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) &
506 ~RME32_WCR_FREQ_1;
507 break;
508 case 44100:
509 rme32->wcreg &= ~RME32_WCR_DS_BM;
510 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_1) &
511 ~RME32_WCR_FREQ_0;
512 break;
513 case 48000:
514 rme32->wcreg &= ~RME32_WCR_DS_BM;
515 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) |
516 RME32_WCR_FREQ_1;
517 break;
518 case 64000:
519 if (rme32->pci->device != PCI_DEVICE_ID_RME_DIGI32_PRO)
520 return -EINVAL;
521 rme32->wcreg |= RME32_WCR_DS_BM;
522 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) &
523 ~RME32_WCR_FREQ_1;
524 break;
525 case 88200:
526 if (rme32->pci->device != PCI_DEVICE_ID_RME_DIGI32_PRO)
527 return -EINVAL;
528 rme32->wcreg |= RME32_WCR_DS_BM;
529 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_1) &
530 ~RME32_WCR_FREQ_0;
531 break;
532 case 96000:
533 if (rme32->pci->device != PCI_DEVICE_ID_RME_DIGI32_PRO)
534 return -EINVAL;
535 rme32->wcreg |= RME32_WCR_DS_BM;
536 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) |
537 RME32_WCR_FREQ_1;
538 break;
539 default:
540 return -EINVAL;
541 }
542 if ((!ds && rme32->wcreg & RME32_WCR_DS_BM) ||
543 (ds && !(rme32->wcreg & RME32_WCR_DS_BM)))
544 {
545 /* change to/from double-speed: reset the DAC (if available) */
546 snd_rme32_reset_dac(rme32);
547 } else {
548 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
549 }
550 return 0;
551}
552
553static int snd_rme32_setclockmode(struct rme32 * rme32, int mode)
554{
555 switch (mode) {
556 case RME32_CLOCKMODE_SLAVE:
557 /* AutoSync */
558 rme32->wcreg = (rme32->wcreg & ~RME32_WCR_FREQ_0) &
559 ~RME32_WCR_FREQ_1;
560 break;
561 case RME32_CLOCKMODE_MASTER_32:
562 /* Internal 32.0kHz */
563 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) &
564 ~RME32_WCR_FREQ_1;
565 break;
566 case RME32_CLOCKMODE_MASTER_44:
567 /* Internal 44.1kHz */
568 rme32->wcreg = (rme32->wcreg & ~RME32_WCR_FREQ_0) |
569 RME32_WCR_FREQ_1;
570 break;
571 case RME32_CLOCKMODE_MASTER_48:
572 /* Internal 48.0kHz */
573 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) |
574 RME32_WCR_FREQ_1;
575 break;
576 default:
577 return -EINVAL;
578 }
579 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
580 return 0;
581}
582
583static int snd_rme32_getclockmode(struct rme32 * rme32)
584{
585 return ((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_0) & 1) +
586 (((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_1) & 1) << 1);
587}
588
589static int snd_rme32_setinputtype(struct rme32 * rme32, int type)
590{
591 switch (type) {
592 case RME32_INPUT_OPTICAL:
593 rme32->wcreg = (rme32->wcreg & ~RME32_WCR_INP_0) &
594 ~RME32_WCR_INP_1;
595 break;
596 case RME32_INPUT_COAXIAL:
597 rme32->wcreg = (rme32->wcreg | RME32_WCR_INP_0) &
598 ~RME32_WCR_INP_1;
599 break;
600 case RME32_INPUT_INTERNAL:
601 rme32->wcreg = (rme32->wcreg & ~RME32_WCR_INP_0) |
602 RME32_WCR_INP_1;
603 break;
604 case RME32_INPUT_XLR:
605 rme32->wcreg = (rme32->wcreg | RME32_WCR_INP_0) |
606 RME32_WCR_INP_1;
607 break;
608 default:
609 return -EINVAL;
610 }
611 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
612 return 0;
613}
614
615static int snd_rme32_getinputtype(struct rme32 * rme32)
616{
617 return ((rme32->wcreg >> RME32_WCR_BITPOS_INP_0) & 1) +
618 (((rme32->wcreg >> RME32_WCR_BITPOS_INP_1) & 1) << 1);
619}
620
621static void
622snd_rme32_setframelog(struct rme32 * rme32, int n_channels, int is_playback)
623{
624 int frlog;
625
626 if (n_channels == 2) {
627 frlog = 1;
628 } else {
629 /* assume 8 channels */
630 frlog = 3;
631 }
632 if (is_playback) {
633 frlog += (rme32->wcreg & RME32_WCR_MODE24) ? 2 : 1;
634 rme32->playback_frlog = frlog;
635 } else {
636 frlog += (rme32->wcreg & RME32_WCR_MODE24) ? 2 : 1;
637 rme32->capture_frlog = frlog;
638 }
639}
640
641static int snd_rme32_setformat(struct rme32 *rme32, snd_pcm_format_t format)
642{
643 switch (format) {
644 case SNDRV_PCM_FORMAT_S16_LE:
645 rme32->wcreg &= ~RME32_WCR_MODE24;
646 break;
647 case SNDRV_PCM_FORMAT_S32_LE:
648 rme32->wcreg |= RME32_WCR_MODE24;
649 break;
650 default:
651 return -EINVAL;
652 }
653 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
654 return 0;
655}
656
657static int
658snd_rme32_playback_hw_params(struct snd_pcm_substream *substream,
659 struct snd_pcm_hw_params *params)
660{
661 int err, rate, dummy;
662 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
663 struct snd_pcm_runtime *runtime = substream->runtime;
664
665 if (!rme32->fullduplex_mode) {
666 runtime->dma_area = (void __force *)(rme32->iobase +
667 RME32_IO_DATA_BUFFER);
668 runtime->dma_addr = rme32->port + RME32_IO_DATA_BUFFER;
669 runtime->dma_bytes = RME32_BUFFER_SIZE;
670 }
671
672 spin_lock_irq(&rme32->lock);
673 if ((rme32->rcreg & RME32_RCR_KMODE) &&
674 (rate = snd_rme32_capture_getrate(rme32, &dummy)) > 0) {
675 /* AutoSync */
676 if ((int)params_rate(params) != rate) {
677 spin_unlock_irq(&rme32->lock);
678 return -EIO;
679 }
680 } else if ((err = snd_rme32_playback_setrate(rme32, params_rate(params))) < 0) {
681 spin_unlock_irq(&rme32->lock);
682 return err;
683 }
684 if ((err = snd_rme32_setformat(rme32, params_format(params))) < 0) {
685 spin_unlock_irq(&rme32->lock);
686 return err;
687 }
688
689 snd_rme32_setframelog(rme32, params_channels(params), 1);
690 if (rme32->capture_periodsize != 0) {
691 if (params_period_size(params) << rme32->playback_frlog != rme32->capture_periodsize) {
692 spin_unlock_irq(&rme32->lock);
693 return -EBUSY;
694 }
695 }
696 rme32->playback_periodsize = params_period_size(params) << rme32->playback_frlog;
697 /* S/PDIF setup */
698 if ((rme32->wcreg & RME32_WCR_ADAT) == 0) {
699 rme32->wcreg &= ~(RME32_WCR_PRO | RME32_WCR_EMP);
700 rme32->wcreg |= rme32->wcreg_spdif_stream;
701 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
702 }
703 spin_unlock_irq(&rme32->lock);
704
705 return 0;
706}
707
708static int
709snd_rme32_capture_hw_params(struct snd_pcm_substream *substream,
710 struct snd_pcm_hw_params *params)
711{
712 int err, isadat, rate;
713 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
714 struct snd_pcm_runtime *runtime = substream->runtime;
715
716 if (!rme32->fullduplex_mode) {
717 runtime->dma_area = (void __force *)rme32->iobase +
718 RME32_IO_DATA_BUFFER;
719 runtime->dma_addr = rme32->port + RME32_IO_DATA_BUFFER;
720 runtime->dma_bytes = RME32_BUFFER_SIZE;
721 }
722
723 spin_lock_irq(&rme32->lock);
724 /* enable AutoSync for record-preparing */
725 rme32->wcreg |= RME32_WCR_AUTOSYNC;
726 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
727
728 if ((err = snd_rme32_setformat(rme32, params_format(params))) < 0) {
729 spin_unlock_irq(&rme32->lock);
730 return err;
731 }
732 if ((err = snd_rme32_playback_setrate(rme32, params_rate(params))) < 0) {
733 spin_unlock_irq(&rme32->lock);
734 return err;
735 }
736 if ((rate = snd_rme32_capture_getrate(rme32, &isadat)) > 0) {
737 if ((int)params_rate(params) != rate) {
738 spin_unlock_irq(&rme32->lock);
739 return -EIO;
740 }
741 if ((isadat && runtime->hw.channels_min == 2) ||
742 (!isadat && runtime->hw.channels_min == 8)) {
743 spin_unlock_irq(&rme32->lock);
744 return -EIO;
745 }
746 }
747 /* AutoSync off for recording */
748 rme32->wcreg &= ~RME32_WCR_AUTOSYNC;
749 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
750
751 snd_rme32_setframelog(rme32, params_channels(params), 0);
752 if (rme32->playback_periodsize != 0) {
753 if (params_period_size(params) << rme32->capture_frlog !=
754 rme32->playback_periodsize) {
755 spin_unlock_irq(&rme32->lock);
756 return -EBUSY;
757 }
758 }
759 rme32->capture_periodsize =
760 params_period_size(params) << rme32->capture_frlog;
761 spin_unlock_irq(&rme32->lock);
762
763 return 0;
764}
765
766static void snd_rme32_pcm_start(struct rme32 * rme32, int from_pause)
767{
768 if (!from_pause) {
769 writel(0, rme32->iobase + RME32_IO_RESET_POS);
770 }
771
772 rme32->wcreg |= RME32_WCR_START;
773 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
774}
775
776static void snd_rme32_pcm_stop(struct rme32 * rme32, int to_pause)
777{
778 /*
779 * Check if there is an unconfirmed IRQ, if so confirm it, or else
780 * the hardware will not stop generating interrupts
781 */
782 rme32->rcreg = readl(rme32->iobase + RME32_IO_CONTROL_REGISTER);
783 if (rme32->rcreg & RME32_RCR_IRQ) {
784 writel(0, rme32->iobase + RME32_IO_CONFIRM_ACTION_IRQ);
785 }
786 rme32->wcreg &= ~RME32_WCR_START;
787 if (rme32->wcreg & RME32_WCR_SEL)
788 rme32->wcreg |= RME32_WCR_MUTE;
789 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
790 if (! to_pause)
791 writel(0, rme32->iobase + RME32_IO_RESET_POS);
792}
793
794static irqreturn_t snd_rme32_interrupt(int irq, void *dev_id)
795{
796 struct rme32 *rme32 = (struct rme32 *) dev_id;
797
798 rme32->rcreg = readl(rme32->iobase + RME32_IO_CONTROL_REGISTER);
799 if (!(rme32->rcreg & RME32_RCR_IRQ)) {
800 return IRQ_NONE;
801 } else {
802 if (rme32->capture_substream) {
803 snd_pcm_period_elapsed(rme32->capture_substream);
804 }
805 if (rme32->playback_substream) {
806 snd_pcm_period_elapsed(rme32->playback_substream);
807 }
808 writel(0, rme32->iobase + RME32_IO_CONFIRM_ACTION_IRQ);
809 }
810 return IRQ_HANDLED;
811}
812
813static const unsigned int period_bytes[] = { RME32_BLOCK_SIZE };
814
815static const struct snd_pcm_hw_constraint_list hw_constraints_period_bytes = {
816 .count = ARRAY_SIZE(period_bytes),
817 .list = period_bytes,
818 .mask = 0
819};
820
821static void snd_rme32_set_buffer_constraint(struct rme32 *rme32, struct snd_pcm_runtime *runtime)
822{
823 if (! rme32->fullduplex_mode) {
824 snd_pcm_hw_constraint_single(runtime,
825 SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
826 RME32_BUFFER_SIZE);
827 snd_pcm_hw_constraint_list(runtime, 0,
828 SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
829 &hw_constraints_period_bytes);
830 }
831}
832
833static int snd_rme32_playback_spdif_open(struct snd_pcm_substream *substream)
834{
835 int rate, dummy;
836 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
837 struct snd_pcm_runtime *runtime = substream->runtime;
838
839 snd_pcm_set_sync(substream);
840
841 spin_lock_irq(&rme32->lock);
842 if (rme32->playback_substream != NULL) {
843 spin_unlock_irq(&rme32->lock);
844 return -EBUSY;
845 }
846 rme32->wcreg &= ~RME32_WCR_ADAT;
847 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
848 rme32->playback_substream = substream;
849 spin_unlock_irq(&rme32->lock);
850
851 if (rme32->fullduplex_mode)
852 runtime->hw = snd_rme32_spdif_fd_info;
853 else
854 runtime->hw = snd_rme32_spdif_info;
855 if (rme32->pci->device == PCI_DEVICE_ID_RME_DIGI32_PRO) {
856 runtime->hw.rates |= SNDRV_PCM_RATE_64000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000;
857 runtime->hw.rate_max = 96000;
858 }
859 if ((rme32->rcreg & RME32_RCR_KMODE) &&
860 (rate = snd_rme32_capture_getrate(rme32, &dummy)) > 0) {
861 /* AutoSync */
862 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
863 runtime->hw.rate_min = rate;
864 runtime->hw.rate_max = rate;
865 }
866
867 snd_rme32_set_buffer_constraint(rme32, runtime);
868
869 rme32->wcreg_spdif_stream = rme32->wcreg_spdif;
870 rme32->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
871 snd_ctl_notify(rme32->card, SNDRV_CTL_EVENT_MASK_VALUE |
872 SNDRV_CTL_EVENT_MASK_INFO, &rme32->spdif_ctl->id);
873 return 0;
874}
875
876static int snd_rme32_capture_spdif_open(struct snd_pcm_substream *substream)
877{
878 int isadat, rate;
879 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
880 struct snd_pcm_runtime *runtime = substream->runtime;
881
882 snd_pcm_set_sync(substream);
883
884 spin_lock_irq(&rme32->lock);
885 if (rme32->capture_substream != NULL) {
886 spin_unlock_irq(&rme32->lock);
887 return -EBUSY;
888 }
889 rme32->capture_substream = substream;
890 spin_unlock_irq(&rme32->lock);
891
892 if (rme32->fullduplex_mode)
893 runtime->hw = snd_rme32_spdif_fd_info;
894 else
895 runtime->hw = snd_rme32_spdif_info;
896 if (RME32_PRO_WITH_8414(rme32)) {
897 runtime->hw.rates |= SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000;
898 runtime->hw.rate_max = 96000;
899 }
900 if ((rate = snd_rme32_capture_getrate(rme32, &isadat)) > 0) {
901 if (isadat) {
902 return -EIO;
903 }
904 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
905 runtime->hw.rate_min = rate;
906 runtime->hw.rate_max = rate;
907 }
908
909 snd_rme32_set_buffer_constraint(rme32, runtime);
910
911 return 0;
912}
913
914static int
915snd_rme32_playback_adat_open(struct snd_pcm_substream *substream)
916{
917 int rate, dummy;
918 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
919 struct snd_pcm_runtime *runtime = substream->runtime;
920
921 snd_pcm_set_sync(substream);
922
923 spin_lock_irq(&rme32->lock);
924 if (rme32->playback_substream != NULL) {
925 spin_unlock_irq(&rme32->lock);
926 return -EBUSY;
927 }
928 rme32->wcreg |= RME32_WCR_ADAT;
929 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
930 rme32->playback_substream = substream;
931 spin_unlock_irq(&rme32->lock);
932
933 if (rme32->fullduplex_mode)
934 runtime->hw = snd_rme32_adat_fd_info;
935 else
936 runtime->hw = snd_rme32_adat_info;
937 if ((rme32->rcreg & RME32_RCR_KMODE) &&
938 (rate = snd_rme32_capture_getrate(rme32, &dummy)) > 0) {
939 /* AutoSync */
940 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
941 runtime->hw.rate_min = rate;
942 runtime->hw.rate_max = rate;
943 }
944
945 snd_rme32_set_buffer_constraint(rme32, runtime);
946 return 0;
947}
948
949static int
950snd_rme32_capture_adat_open(struct snd_pcm_substream *substream)
951{
952 int isadat, rate;
953 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
954 struct snd_pcm_runtime *runtime = substream->runtime;
955
956 if (rme32->fullduplex_mode)
957 runtime->hw = snd_rme32_adat_fd_info;
958 else
959 runtime->hw = snd_rme32_adat_info;
960 if ((rate = snd_rme32_capture_getrate(rme32, &isadat)) > 0) {
961 if (!isadat) {
962 return -EIO;
963 }
964 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
965 runtime->hw.rate_min = rate;
966 runtime->hw.rate_max = rate;
967 }
968
969 snd_pcm_set_sync(substream);
970
971 spin_lock_irq(&rme32->lock);
972 if (rme32->capture_substream != NULL) {
973 spin_unlock_irq(&rme32->lock);
974 return -EBUSY;
975 }
976 rme32->capture_substream = substream;
977 spin_unlock_irq(&rme32->lock);
978
979 snd_rme32_set_buffer_constraint(rme32, runtime);
980 return 0;
981}
982
983static int snd_rme32_playback_close(struct snd_pcm_substream *substream)
984{
985 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
986 int spdif = 0;
987
988 spin_lock_irq(&rme32->lock);
989 rme32->playback_substream = NULL;
990 rme32->playback_periodsize = 0;
991 spdif = (rme32->wcreg & RME32_WCR_ADAT) == 0;
992 spin_unlock_irq(&rme32->lock);
993 if (spdif) {
994 rme32->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
995 snd_ctl_notify(rme32->card, SNDRV_CTL_EVENT_MASK_VALUE |
996 SNDRV_CTL_EVENT_MASK_INFO,
997 &rme32->spdif_ctl->id);
998 }
999 return 0;
1000}
1001
1002static int snd_rme32_capture_close(struct snd_pcm_substream *substream)
1003{
1004 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1005
1006 spin_lock_irq(&rme32->lock);
1007 rme32->capture_substream = NULL;
1008 rme32->capture_periodsize = 0;
1009 spin_unlock_irq(&rme32->lock);
1010 return 0;
1011}
1012
1013static int snd_rme32_playback_prepare(struct snd_pcm_substream *substream)
1014{
1015 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1016
1017 spin_lock_irq(&rme32->lock);
1018 if (rme32->fullduplex_mode) {
1019 memset(&rme32->playback_pcm, 0, sizeof(rme32->playback_pcm));
1020 rme32->playback_pcm.hw_buffer_size = RME32_BUFFER_SIZE;
1021 rme32->playback_pcm.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
1022 } else {
1023 writel(0, rme32->iobase + RME32_IO_RESET_POS);
1024 }
1025 if (rme32->wcreg & RME32_WCR_SEL)
1026 rme32->wcreg &= ~RME32_WCR_MUTE;
1027 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
1028 spin_unlock_irq(&rme32->lock);
1029 return 0;
1030}
1031
1032static int snd_rme32_capture_prepare(struct snd_pcm_substream *substream)
1033{
1034 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1035
1036 spin_lock_irq(&rme32->lock);
1037 if (rme32->fullduplex_mode) {
1038 memset(&rme32->capture_pcm, 0, sizeof(rme32->capture_pcm));
1039 rme32->capture_pcm.hw_buffer_size = RME32_BUFFER_SIZE;
1040 rme32->capture_pcm.hw_queue_size = RME32_BUFFER_SIZE / 2;
1041 rme32->capture_pcm.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
1042 } else {
1043 writel(0, rme32->iobase + RME32_IO_RESET_POS);
1044 }
1045 spin_unlock_irq(&rme32->lock);
1046 return 0;
1047}
1048
1049static int
1050snd_rme32_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1051{
1052 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1053 struct snd_pcm_substream *s;
1054
1055 spin_lock(&rme32->lock);
1056 snd_pcm_group_for_each_entry(s, substream) {
1057 if (s != rme32->playback_substream &&
1058 s != rme32->capture_substream)
1059 continue;
1060 switch (cmd) {
1061 case SNDRV_PCM_TRIGGER_START:
1062 rme32->running |= (1 << s->stream);
1063 if (rme32->fullduplex_mode) {
1064 /* remember the current DMA position */
1065 if (s == rme32->playback_substream) {
1066 rme32->playback_pcm.hw_io =
1067 rme32->playback_pcm.hw_data = snd_rme32_pcm_byteptr(rme32);
1068 } else {
1069 rme32->capture_pcm.hw_io =
1070 rme32->capture_pcm.hw_data = snd_rme32_pcm_byteptr(rme32);
1071 }
1072 }
1073 break;
1074 case SNDRV_PCM_TRIGGER_STOP:
1075 rme32->running &= ~(1 << s->stream);
1076 break;
1077 }
1078 snd_pcm_trigger_done(s, substream);
1079 }
1080
1081 switch (cmd) {
1082 case SNDRV_PCM_TRIGGER_START:
1083 if (rme32->running && ! RME32_ISWORKING(rme32))
1084 snd_rme32_pcm_start(rme32, 0);
1085 break;
1086 case SNDRV_PCM_TRIGGER_STOP:
1087 if (! rme32->running && RME32_ISWORKING(rme32))
1088 snd_rme32_pcm_stop(rme32, 0);
1089 break;
1090 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1091 if (rme32->running && RME32_ISWORKING(rme32))
1092 snd_rme32_pcm_stop(rme32, 1);
1093 break;
1094 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1095 if (rme32->running && ! RME32_ISWORKING(rme32))
1096 snd_rme32_pcm_start(rme32, 1);
1097 break;
1098 }
1099 spin_unlock(&rme32->lock);
1100 return 0;
1101}
1102
1103/* pointer callback for halfduplex mode */
1104static snd_pcm_uframes_t
1105snd_rme32_playback_pointer(struct snd_pcm_substream *substream)
1106{
1107 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1108 return snd_rme32_pcm_byteptr(rme32) >> rme32->playback_frlog;
1109}
1110
1111static snd_pcm_uframes_t
1112snd_rme32_capture_pointer(struct snd_pcm_substream *substream)
1113{
1114 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1115 return snd_rme32_pcm_byteptr(rme32) >> rme32->capture_frlog;
1116}
1117
1118
1119/* ack and pointer callbacks for fullduplex mode */
1120static void snd_rme32_pb_trans_copy(struct snd_pcm_substream *substream,
1121 struct snd_pcm_indirect *rec, size_t bytes)
1122{
1123 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1124 memcpy_toio(rme32->iobase + RME32_IO_DATA_BUFFER + rec->hw_data,
1125 substream->runtime->dma_area + rec->sw_data, bytes);
1126}
1127
1128static int snd_rme32_playback_fd_ack(struct snd_pcm_substream *substream)
1129{
1130 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1131 struct snd_pcm_indirect *rec, *cprec;
1132
1133 rec = &rme32->playback_pcm;
1134 cprec = &rme32->capture_pcm;
1135 spin_lock(&rme32->lock);
1136 rec->hw_queue_size = RME32_BUFFER_SIZE;
1137 if (rme32->running & (1 << SNDRV_PCM_STREAM_CAPTURE))
1138 rec->hw_queue_size -= cprec->hw_ready;
1139 spin_unlock(&rme32->lock);
1140 return snd_pcm_indirect_playback_transfer(substream, rec,
1141 snd_rme32_pb_trans_copy);
1142}
1143
1144static void snd_rme32_cp_trans_copy(struct snd_pcm_substream *substream,
1145 struct snd_pcm_indirect *rec, size_t bytes)
1146{
1147 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1148 memcpy_fromio(substream->runtime->dma_area + rec->sw_data,
1149 rme32->iobase + RME32_IO_DATA_BUFFER + rec->hw_data,
1150 bytes);
1151}
1152
1153static int snd_rme32_capture_fd_ack(struct snd_pcm_substream *substream)
1154{
1155 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1156 return snd_pcm_indirect_capture_transfer(substream, &rme32->capture_pcm,
1157 snd_rme32_cp_trans_copy);
1158}
1159
1160static snd_pcm_uframes_t
1161snd_rme32_playback_fd_pointer(struct snd_pcm_substream *substream)
1162{
1163 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1164 return snd_pcm_indirect_playback_pointer(substream, &rme32->playback_pcm,
1165 snd_rme32_pcm_byteptr(rme32));
1166}
1167
1168static snd_pcm_uframes_t
1169snd_rme32_capture_fd_pointer(struct snd_pcm_substream *substream)
1170{
1171 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1172 return snd_pcm_indirect_capture_pointer(substream, &rme32->capture_pcm,
1173 snd_rme32_pcm_byteptr(rme32));
1174}
1175
1176/* for halfduplex mode */
1177static const struct snd_pcm_ops snd_rme32_playback_spdif_ops = {
1178 .open = snd_rme32_playback_spdif_open,
1179 .close = snd_rme32_playback_close,
1180 .hw_params = snd_rme32_playback_hw_params,
1181 .prepare = snd_rme32_playback_prepare,
1182 .trigger = snd_rme32_pcm_trigger,
1183 .pointer = snd_rme32_playback_pointer,
1184 .copy_user = snd_rme32_playback_copy,
1185 .copy_kernel = snd_rme32_playback_copy_kernel,
1186 .fill_silence = snd_rme32_playback_silence,
1187 .mmap = snd_pcm_lib_mmap_iomem,
1188};
1189
1190static const struct snd_pcm_ops snd_rme32_capture_spdif_ops = {
1191 .open = snd_rme32_capture_spdif_open,
1192 .close = snd_rme32_capture_close,
1193 .hw_params = snd_rme32_capture_hw_params,
1194 .prepare = snd_rme32_capture_prepare,
1195 .trigger = snd_rme32_pcm_trigger,
1196 .pointer = snd_rme32_capture_pointer,
1197 .copy_user = snd_rme32_capture_copy,
1198 .copy_kernel = snd_rme32_capture_copy_kernel,
1199 .mmap = snd_pcm_lib_mmap_iomem,
1200};
1201
1202static const struct snd_pcm_ops snd_rme32_playback_adat_ops = {
1203 .open = snd_rme32_playback_adat_open,
1204 .close = snd_rme32_playback_close,
1205 .hw_params = snd_rme32_playback_hw_params,
1206 .prepare = snd_rme32_playback_prepare,
1207 .trigger = snd_rme32_pcm_trigger,
1208 .pointer = snd_rme32_playback_pointer,
1209 .copy_user = snd_rme32_playback_copy,
1210 .copy_kernel = snd_rme32_playback_copy_kernel,
1211 .fill_silence = snd_rme32_playback_silence,
1212 .mmap = snd_pcm_lib_mmap_iomem,
1213};
1214
1215static const struct snd_pcm_ops snd_rme32_capture_adat_ops = {
1216 .open = snd_rme32_capture_adat_open,
1217 .close = snd_rme32_capture_close,
1218 .hw_params = snd_rme32_capture_hw_params,
1219 .prepare = snd_rme32_capture_prepare,
1220 .trigger = snd_rme32_pcm_trigger,
1221 .pointer = snd_rme32_capture_pointer,
1222 .copy_user = snd_rme32_capture_copy,
1223 .copy_kernel = snd_rme32_capture_copy_kernel,
1224 .mmap = snd_pcm_lib_mmap_iomem,
1225};
1226
1227/* for fullduplex mode */
1228static const struct snd_pcm_ops snd_rme32_playback_spdif_fd_ops = {
1229 .open = snd_rme32_playback_spdif_open,
1230 .close = snd_rme32_playback_close,
1231 .hw_params = snd_rme32_playback_hw_params,
1232 .prepare = snd_rme32_playback_prepare,
1233 .trigger = snd_rme32_pcm_trigger,
1234 .pointer = snd_rme32_playback_fd_pointer,
1235 .ack = snd_rme32_playback_fd_ack,
1236};
1237
1238static const struct snd_pcm_ops snd_rme32_capture_spdif_fd_ops = {
1239 .open = snd_rme32_capture_spdif_open,
1240 .close = snd_rme32_capture_close,
1241 .hw_params = snd_rme32_capture_hw_params,
1242 .prepare = snd_rme32_capture_prepare,
1243 .trigger = snd_rme32_pcm_trigger,
1244 .pointer = snd_rme32_capture_fd_pointer,
1245 .ack = snd_rme32_capture_fd_ack,
1246};
1247
1248static const struct snd_pcm_ops snd_rme32_playback_adat_fd_ops = {
1249 .open = snd_rme32_playback_adat_open,
1250 .close = snd_rme32_playback_close,
1251 .hw_params = snd_rme32_playback_hw_params,
1252 .prepare = snd_rme32_playback_prepare,
1253 .trigger = snd_rme32_pcm_trigger,
1254 .pointer = snd_rme32_playback_fd_pointer,
1255 .ack = snd_rme32_playback_fd_ack,
1256};
1257
1258static const struct snd_pcm_ops snd_rme32_capture_adat_fd_ops = {
1259 .open = snd_rme32_capture_adat_open,
1260 .close = snd_rme32_capture_close,
1261 .hw_params = snd_rme32_capture_hw_params,
1262 .prepare = snd_rme32_capture_prepare,
1263 .trigger = snd_rme32_pcm_trigger,
1264 .pointer = snd_rme32_capture_fd_pointer,
1265 .ack = snd_rme32_capture_fd_ack,
1266};
1267
1268static void snd_rme32_free(void *private_data)
1269{
1270 struct rme32 *rme32 = (struct rme32 *) private_data;
1271
1272 if (rme32 == NULL) {
1273 return;
1274 }
1275 if (rme32->irq >= 0) {
1276 snd_rme32_pcm_stop(rme32, 0);
1277 free_irq(rme32->irq, (void *) rme32);
1278 rme32->irq = -1;
1279 }
1280 if (rme32->iobase) {
1281 iounmap(rme32->iobase);
1282 rme32->iobase = NULL;
1283 }
1284 if (rme32->port) {
1285 pci_release_regions(rme32->pci);
1286 rme32->port = 0;
1287 }
1288 pci_disable_device(rme32->pci);
1289}
1290
1291static void snd_rme32_free_spdif_pcm(struct snd_pcm *pcm)
1292{
1293 struct rme32 *rme32 = (struct rme32 *) pcm->private_data;
1294 rme32->spdif_pcm = NULL;
1295}
1296
1297static void
1298snd_rme32_free_adat_pcm(struct snd_pcm *pcm)
1299{
1300 struct rme32 *rme32 = (struct rme32 *) pcm->private_data;
1301 rme32->adat_pcm = NULL;
1302}
1303
1304static int snd_rme32_create(struct rme32 *rme32)
1305{
1306 struct pci_dev *pci = rme32->pci;
1307 int err;
1308
1309 rme32->irq = -1;
1310 spin_lock_init(&rme32->lock);
1311
1312 if ((err = pci_enable_device(pci)) < 0)
1313 return err;
1314
1315 if ((err = pci_request_regions(pci, "RME32")) < 0)
1316 return err;
1317 rme32->port = pci_resource_start(rme32->pci, 0);
1318
1319 rme32->iobase = ioremap(rme32->port, RME32_IO_SIZE);
1320 if (!rme32->iobase) {
1321 dev_err(rme32->card->dev,
1322 "unable to remap memory region 0x%lx-0x%lx\n",
1323 rme32->port, rme32->port + RME32_IO_SIZE - 1);
1324 return -ENOMEM;
1325 }
1326
1327 if (request_irq(pci->irq, snd_rme32_interrupt, IRQF_SHARED,
1328 KBUILD_MODNAME, rme32)) {
1329 dev_err(rme32->card->dev, "unable to grab IRQ %d\n", pci->irq);
1330 return -EBUSY;
1331 }
1332 rme32->irq = pci->irq;
1333 rme32->card->sync_irq = rme32->irq;
1334
1335 /* read the card's revision number */
1336 pci_read_config_byte(pci, 8, &rme32->rev);
1337
1338 /* set up ALSA pcm device for S/PDIF */
1339 if ((err = snd_pcm_new(rme32->card, "Digi32 IEC958", 0, 1, 1, &rme32->spdif_pcm)) < 0) {
1340 return err;
1341 }
1342 rme32->spdif_pcm->private_data = rme32;
1343 rme32->spdif_pcm->private_free = snd_rme32_free_spdif_pcm;
1344 strcpy(rme32->spdif_pcm->name, "Digi32 IEC958");
1345 if (rme32->fullduplex_mode) {
1346 snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK,
1347 &snd_rme32_playback_spdif_fd_ops);
1348 snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE,
1349 &snd_rme32_capture_spdif_fd_ops);
1350 snd_pcm_set_managed_buffer_all(rme32->spdif_pcm, SNDRV_DMA_TYPE_CONTINUOUS,
1351 NULL, 0, RME32_MID_BUFFER_SIZE);
1352 rme32->spdif_pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
1353 } else {
1354 snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK,
1355 &snd_rme32_playback_spdif_ops);
1356 snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE,
1357 &snd_rme32_capture_spdif_ops);
1358 rme32->spdif_pcm->info_flags = SNDRV_PCM_INFO_HALF_DUPLEX;
1359 }
1360
1361 /* set up ALSA pcm device for ADAT */
1362 if ((pci->device == PCI_DEVICE_ID_RME_DIGI32) ||
1363 (pci->device == PCI_DEVICE_ID_RME_DIGI32_PRO)) {
1364 /* ADAT is not available on DIGI32 and DIGI32 Pro */
1365 rme32->adat_pcm = NULL;
1366 }
1367 else {
1368 if ((err = snd_pcm_new(rme32->card, "Digi32 ADAT", 1,
1369 1, 1, &rme32->adat_pcm)) < 0)
1370 {
1371 return err;
1372 }
1373 rme32->adat_pcm->private_data = rme32;
1374 rme32->adat_pcm->private_free = snd_rme32_free_adat_pcm;
1375 strcpy(rme32->adat_pcm->name, "Digi32 ADAT");
1376 if (rme32->fullduplex_mode) {
1377 snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK,
1378 &snd_rme32_playback_adat_fd_ops);
1379 snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_CAPTURE,
1380 &snd_rme32_capture_adat_fd_ops);
1381 snd_pcm_set_managed_buffer_all(rme32->adat_pcm, SNDRV_DMA_TYPE_CONTINUOUS,
1382 NULL,
1383 0, RME32_MID_BUFFER_SIZE);
1384 rme32->adat_pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
1385 } else {
1386 snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK,
1387 &snd_rme32_playback_adat_ops);
1388 snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_CAPTURE,
1389 &snd_rme32_capture_adat_ops);
1390 rme32->adat_pcm->info_flags = SNDRV_PCM_INFO_HALF_DUPLEX;
1391 }
1392 }
1393
1394
1395 rme32->playback_periodsize = 0;
1396 rme32->capture_periodsize = 0;
1397
1398 /* make sure playback/capture is stopped, if by some reason active */
1399 snd_rme32_pcm_stop(rme32, 0);
1400
1401 /* reset DAC */
1402 snd_rme32_reset_dac(rme32);
1403
1404 /* reset buffer pointer */
1405 writel(0, rme32->iobase + RME32_IO_RESET_POS);
1406
1407 /* set default values in registers */
1408 rme32->wcreg = RME32_WCR_SEL | /* normal playback */
1409 RME32_WCR_INP_0 | /* input select */
1410 RME32_WCR_MUTE; /* muting on */
1411 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
1412
1413
1414 /* init switch interface */
1415 if ((err = snd_rme32_create_switches(rme32->card, rme32)) < 0) {
1416 return err;
1417 }
1418
1419 /* init proc interface */
1420 snd_rme32_proc_init(rme32);
1421
1422 rme32->capture_substream = NULL;
1423 rme32->playback_substream = NULL;
1424
1425 return 0;
1426}
1427
1428/*
1429 * proc interface
1430 */
1431
1432static void
1433snd_rme32_proc_read(struct snd_info_entry * entry, struct snd_info_buffer *buffer)
1434{
1435 int n;
1436 struct rme32 *rme32 = (struct rme32 *) entry->private_data;
1437
1438 rme32->rcreg = readl(rme32->iobase + RME32_IO_CONTROL_REGISTER);
1439
1440 snd_iprintf(buffer, rme32->card->longname);
1441 snd_iprintf(buffer, " (index #%d)\n", rme32->card->number + 1);
1442
1443 snd_iprintf(buffer, "\nGeneral settings\n");
1444 if (rme32->fullduplex_mode)
1445 snd_iprintf(buffer, " Full-duplex mode\n");
1446 else
1447 snd_iprintf(buffer, " Half-duplex mode\n");
1448 if (RME32_PRO_WITH_8414(rme32)) {
1449 snd_iprintf(buffer, " receiver: CS8414\n");
1450 } else {
1451 snd_iprintf(buffer, " receiver: CS8412\n");
1452 }
1453 if (rme32->wcreg & RME32_WCR_MODE24) {
1454 snd_iprintf(buffer, " format: 24 bit");
1455 } else {
1456 snd_iprintf(buffer, " format: 16 bit");
1457 }
1458 if (rme32->wcreg & RME32_WCR_MONO) {
1459 snd_iprintf(buffer, ", Mono\n");
1460 } else {
1461 snd_iprintf(buffer, ", Stereo\n");
1462 }
1463
1464 snd_iprintf(buffer, "\nInput settings\n");
1465 switch (snd_rme32_getinputtype(rme32)) {
1466 case RME32_INPUT_OPTICAL:
1467 snd_iprintf(buffer, " input: optical");
1468 break;
1469 case RME32_INPUT_COAXIAL:
1470 snd_iprintf(buffer, " input: coaxial");
1471 break;
1472 case RME32_INPUT_INTERNAL:
1473 snd_iprintf(buffer, " input: internal");
1474 break;
1475 case RME32_INPUT_XLR:
1476 snd_iprintf(buffer, " input: XLR");
1477 break;
1478 }
1479 if (snd_rme32_capture_getrate(rme32, &n) < 0) {
1480 snd_iprintf(buffer, "\n sample rate: no valid signal\n");
1481 } else {
1482 if (n) {
1483 snd_iprintf(buffer, " (8 channels)\n");
1484 } else {
1485 snd_iprintf(buffer, " (2 channels)\n");
1486 }
1487 snd_iprintf(buffer, " sample rate: %d Hz\n",
1488 snd_rme32_capture_getrate(rme32, &n));
1489 }
1490
1491 snd_iprintf(buffer, "\nOutput settings\n");
1492 if (rme32->wcreg & RME32_WCR_SEL) {
1493 snd_iprintf(buffer, " output signal: normal playback");
1494 } else {
1495 snd_iprintf(buffer, " output signal: same as input");
1496 }
1497 if (rme32->wcreg & RME32_WCR_MUTE) {
1498 snd_iprintf(buffer, " (muted)\n");
1499 } else {
1500 snd_iprintf(buffer, "\n");
1501 }
1502
1503 /* master output frequency */
1504 if (!
1505 ((!(rme32->wcreg & RME32_WCR_FREQ_0))
1506 && (!(rme32->wcreg & RME32_WCR_FREQ_1)))) {
1507 snd_iprintf(buffer, " sample rate: %d Hz\n",
1508 snd_rme32_playback_getrate(rme32));
1509 }
1510 if (rme32->rcreg & RME32_RCR_KMODE) {
1511 snd_iprintf(buffer, " sample clock source: AutoSync\n");
1512 } else {
1513 snd_iprintf(buffer, " sample clock source: Internal\n");
1514 }
1515 if (rme32->wcreg & RME32_WCR_PRO) {
1516 snd_iprintf(buffer, " format: AES/EBU (professional)\n");
1517 } else {
1518 snd_iprintf(buffer, " format: IEC958 (consumer)\n");
1519 }
1520 if (rme32->wcreg & RME32_WCR_EMP) {
1521 snd_iprintf(buffer, " emphasis: on\n");
1522 } else {
1523 snd_iprintf(buffer, " emphasis: off\n");
1524 }
1525}
1526
1527static void snd_rme32_proc_init(struct rme32 *rme32)
1528{
1529 snd_card_ro_proc_new(rme32->card, "rme32", rme32, snd_rme32_proc_read);
1530}
1531
1532/*
1533 * control interface
1534 */
1535
1536#define snd_rme32_info_loopback_control snd_ctl_boolean_mono_info
1537
1538static int
1539snd_rme32_get_loopback_control(struct snd_kcontrol *kcontrol,
1540 struct snd_ctl_elem_value *ucontrol)
1541{
1542 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1543
1544 spin_lock_irq(&rme32->lock);
1545 ucontrol->value.integer.value[0] =
1546 rme32->wcreg & RME32_WCR_SEL ? 0 : 1;
1547 spin_unlock_irq(&rme32->lock);
1548 return 0;
1549}
1550static int
1551snd_rme32_put_loopback_control(struct snd_kcontrol *kcontrol,
1552 struct snd_ctl_elem_value *ucontrol)
1553{
1554 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1555 unsigned int val;
1556 int change;
1557
1558 val = ucontrol->value.integer.value[0] ? 0 : RME32_WCR_SEL;
1559 spin_lock_irq(&rme32->lock);
1560 val = (rme32->wcreg & ~RME32_WCR_SEL) | val;
1561 change = val != rme32->wcreg;
1562 if (ucontrol->value.integer.value[0])
1563 val &= ~RME32_WCR_MUTE;
1564 else
1565 val |= RME32_WCR_MUTE;
1566 rme32->wcreg = val;
1567 writel(val, rme32->iobase + RME32_IO_CONTROL_REGISTER);
1568 spin_unlock_irq(&rme32->lock);
1569 return change;
1570}
1571
1572static int
1573snd_rme32_info_inputtype_control(struct snd_kcontrol *kcontrol,
1574 struct snd_ctl_elem_info *uinfo)
1575{
1576 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1577 static const char * const texts[4] = {
1578 "Optical", "Coaxial", "Internal", "XLR"
1579 };
1580 int num_items;
1581
1582 switch (rme32->pci->device) {
1583 case PCI_DEVICE_ID_RME_DIGI32:
1584 case PCI_DEVICE_ID_RME_DIGI32_8:
1585 num_items = 3;
1586 break;
1587 case PCI_DEVICE_ID_RME_DIGI32_PRO:
1588 num_items = 4;
1589 break;
1590 default:
1591 snd_BUG();
1592 return -EINVAL;
1593 }
1594 return snd_ctl_enum_info(uinfo, 1, num_items, texts);
1595}
1596static int
1597snd_rme32_get_inputtype_control(struct snd_kcontrol *kcontrol,
1598 struct snd_ctl_elem_value *ucontrol)
1599{
1600 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1601 unsigned int items = 3;
1602
1603 spin_lock_irq(&rme32->lock);
1604 ucontrol->value.enumerated.item[0] = snd_rme32_getinputtype(rme32);
1605
1606 switch (rme32->pci->device) {
1607 case PCI_DEVICE_ID_RME_DIGI32:
1608 case PCI_DEVICE_ID_RME_DIGI32_8:
1609 items = 3;
1610 break;
1611 case PCI_DEVICE_ID_RME_DIGI32_PRO:
1612 items = 4;
1613 break;
1614 default:
1615 snd_BUG();
1616 break;
1617 }
1618 if (ucontrol->value.enumerated.item[0] >= items) {
1619 ucontrol->value.enumerated.item[0] = items - 1;
1620 }
1621
1622 spin_unlock_irq(&rme32->lock);
1623 return 0;
1624}
1625static int
1626snd_rme32_put_inputtype_control(struct snd_kcontrol *kcontrol,
1627 struct snd_ctl_elem_value *ucontrol)
1628{
1629 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1630 unsigned int val;
1631 int change, items = 3;
1632
1633 switch (rme32->pci->device) {
1634 case PCI_DEVICE_ID_RME_DIGI32:
1635 case PCI_DEVICE_ID_RME_DIGI32_8:
1636 items = 3;
1637 break;
1638 case PCI_DEVICE_ID_RME_DIGI32_PRO:
1639 items = 4;
1640 break;
1641 default:
1642 snd_BUG();
1643 break;
1644 }
1645 val = ucontrol->value.enumerated.item[0] % items;
1646
1647 spin_lock_irq(&rme32->lock);
1648 change = val != (unsigned int)snd_rme32_getinputtype(rme32);
1649 snd_rme32_setinputtype(rme32, val);
1650 spin_unlock_irq(&rme32->lock);
1651 return change;
1652}
1653
1654static int
1655snd_rme32_info_clockmode_control(struct snd_kcontrol *kcontrol,
1656 struct snd_ctl_elem_info *uinfo)
1657{
1658 static const char * const texts[4] = { "AutoSync",
1659 "Internal 32.0kHz",
1660 "Internal 44.1kHz",
1661 "Internal 48.0kHz" };
1662
1663 return snd_ctl_enum_info(uinfo, 1, 4, texts);
1664}
1665static int
1666snd_rme32_get_clockmode_control(struct snd_kcontrol *kcontrol,
1667 struct snd_ctl_elem_value *ucontrol)
1668{
1669 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1670
1671 spin_lock_irq(&rme32->lock);
1672 ucontrol->value.enumerated.item[0] = snd_rme32_getclockmode(rme32);
1673 spin_unlock_irq(&rme32->lock);
1674 return 0;
1675}
1676static int
1677snd_rme32_put_clockmode_control(struct snd_kcontrol *kcontrol,
1678 struct snd_ctl_elem_value *ucontrol)
1679{
1680 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1681 unsigned int val;
1682 int change;
1683
1684 val = ucontrol->value.enumerated.item[0] % 3;
1685 spin_lock_irq(&rme32->lock);
1686 change = val != (unsigned int)snd_rme32_getclockmode(rme32);
1687 snd_rme32_setclockmode(rme32, val);
1688 spin_unlock_irq(&rme32->lock);
1689 return change;
1690}
1691
1692static u32 snd_rme32_convert_from_aes(struct snd_aes_iec958 * aes)
1693{
1694 u32 val = 0;
1695 val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? RME32_WCR_PRO : 0;
1696 if (val & RME32_WCR_PRO)
1697 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? RME32_WCR_EMP : 0;
1698 else
1699 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? RME32_WCR_EMP : 0;
1700 return val;
1701}
1702
1703static void snd_rme32_convert_to_aes(struct snd_aes_iec958 * aes, u32 val)
1704{
1705 aes->status[0] = ((val & RME32_WCR_PRO) ? IEC958_AES0_PROFESSIONAL : 0);
1706 if (val & RME32_WCR_PRO)
1707 aes->status[0] |= (val & RME32_WCR_EMP) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
1708 else
1709 aes->status[0] |= (val & RME32_WCR_EMP) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
1710}
1711
1712static int snd_rme32_control_spdif_info(struct snd_kcontrol *kcontrol,
1713 struct snd_ctl_elem_info *uinfo)
1714{
1715 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1716 uinfo->count = 1;
1717 return 0;
1718}
1719
1720static int snd_rme32_control_spdif_get(struct snd_kcontrol *kcontrol,
1721 struct snd_ctl_elem_value *ucontrol)
1722{
1723 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1724
1725 snd_rme32_convert_to_aes(&ucontrol->value.iec958,
1726 rme32->wcreg_spdif);
1727 return 0;
1728}
1729
1730static int snd_rme32_control_spdif_put(struct snd_kcontrol *kcontrol,
1731 struct snd_ctl_elem_value *ucontrol)
1732{
1733 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1734 int change;
1735 u32 val;
1736
1737 val = snd_rme32_convert_from_aes(&ucontrol->value.iec958);
1738 spin_lock_irq(&rme32->lock);
1739 change = val != rme32->wcreg_spdif;
1740 rme32->wcreg_spdif = val;
1741 spin_unlock_irq(&rme32->lock);
1742 return change;
1743}
1744
1745static int snd_rme32_control_spdif_stream_info(struct snd_kcontrol *kcontrol,
1746 struct snd_ctl_elem_info *uinfo)
1747{
1748 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1749 uinfo->count = 1;
1750 return 0;
1751}
1752
1753static int snd_rme32_control_spdif_stream_get(struct snd_kcontrol *kcontrol,
1754 struct snd_ctl_elem_value *
1755 ucontrol)
1756{
1757 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1758
1759 snd_rme32_convert_to_aes(&ucontrol->value.iec958,
1760 rme32->wcreg_spdif_stream);
1761 return 0;
1762}
1763
1764static int snd_rme32_control_spdif_stream_put(struct snd_kcontrol *kcontrol,
1765 struct snd_ctl_elem_value *
1766 ucontrol)
1767{
1768 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1769 int change;
1770 u32 val;
1771
1772 val = snd_rme32_convert_from_aes(&ucontrol->value.iec958);
1773 spin_lock_irq(&rme32->lock);
1774 change = val != rme32->wcreg_spdif_stream;
1775 rme32->wcreg_spdif_stream = val;
1776 rme32->wcreg &= ~(RME32_WCR_PRO | RME32_WCR_EMP);
1777 rme32->wcreg |= val;
1778 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
1779 spin_unlock_irq(&rme32->lock);
1780 return change;
1781}
1782
1783static int snd_rme32_control_spdif_mask_info(struct snd_kcontrol *kcontrol,
1784 struct snd_ctl_elem_info *uinfo)
1785{
1786 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1787 uinfo->count = 1;
1788 return 0;
1789}
1790
1791static int snd_rme32_control_spdif_mask_get(struct snd_kcontrol *kcontrol,
1792 struct snd_ctl_elem_value *
1793 ucontrol)
1794{
1795 ucontrol->value.iec958.status[0] = kcontrol->private_value;
1796 return 0;
1797}
1798
1799static const struct snd_kcontrol_new snd_rme32_controls[] = {
1800 {
1801 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1802 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
1803 .info = snd_rme32_control_spdif_info,
1804 .get = snd_rme32_control_spdif_get,
1805 .put = snd_rme32_control_spdif_put
1806 },
1807 {
1808 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
1809 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1810 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, PCM_STREAM),
1811 .info = snd_rme32_control_spdif_stream_info,
1812 .get = snd_rme32_control_spdif_stream_get,
1813 .put = snd_rme32_control_spdif_stream_put
1814 },
1815 {
1816 .access = SNDRV_CTL_ELEM_ACCESS_READ,
1817 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1818 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, CON_MASK),
1819 .info = snd_rme32_control_spdif_mask_info,
1820 .get = snd_rme32_control_spdif_mask_get,
1821 .private_value = IEC958_AES0_PROFESSIONAL | IEC958_AES0_CON_EMPHASIS
1822 },
1823 {
1824 .access = SNDRV_CTL_ELEM_ACCESS_READ,
1825 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1826 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, PRO_MASK),
1827 .info = snd_rme32_control_spdif_mask_info,
1828 .get = snd_rme32_control_spdif_mask_get,
1829 .private_value = IEC958_AES0_PROFESSIONAL | IEC958_AES0_PRO_EMPHASIS
1830 },
1831 {
1832 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1833 .name = "Input Connector",
1834 .info = snd_rme32_info_inputtype_control,
1835 .get = snd_rme32_get_inputtype_control,
1836 .put = snd_rme32_put_inputtype_control
1837 },
1838 {
1839 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1840 .name = "Loopback Input",
1841 .info = snd_rme32_info_loopback_control,
1842 .get = snd_rme32_get_loopback_control,
1843 .put = snd_rme32_put_loopback_control
1844 },
1845 {
1846 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1847 .name = "Sample Clock Source",
1848 .info = snd_rme32_info_clockmode_control,
1849 .get = snd_rme32_get_clockmode_control,
1850 .put = snd_rme32_put_clockmode_control
1851 }
1852};
1853
1854static int snd_rme32_create_switches(struct snd_card *card, struct rme32 * rme32)
1855{
1856 int idx, err;
1857 struct snd_kcontrol *kctl;
1858
1859 for (idx = 0; idx < (int)ARRAY_SIZE(snd_rme32_controls); idx++) {
1860 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_rme32_controls[idx], rme32))) < 0)
1861 return err;
1862 if (idx == 1) /* IEC958 (S/PDIF) Stream */
1863 rme32->spdif_ctl = kctl;
1864 }
1865
1866 return 0;
1867}
1868
1869/*
1870 * Card initialisation
1871 */
1872
1873static void snd_rme32_card_free(struct snd_card *card)
1874{
1875 snd_rme32_free(card->private_data);
1876}
1877
1878static int
1879snd_rme32_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
1880{
1881 static int dev;
1882 struct rme32 *rme32;
1883 struct snd_card *card;
1884 int err;
1885
1886 if (dev >= SNDRV_CARDS) {
1887 return -ENODEV;
1888 }
1889 if (!enable[dev]) {
1890 dev++;
1891 return -ENOENT;
1892 }
1893
1894 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
1895 sizeof(struct rme32), &card);
1896 if (err < 0)
1897 return err;
1898 card->private_free = snd_rme32_card_free;
1899 rme32 = (struct rme32 *) card->private_data;
1900 rme32->card = card;
1901 rme32->pci = pci;
1902 if (fullduplex[dev])
1903 rme32->fullduplex_mode = 1;
1904 if ((err = snd_rme32_create(rme32)) < 0) {
1905 snd_card_free(card);
1906 return err;
1907 }
1908
1909 strcpy(card->driver, "Digi32");
1910 switch (rme32->pci->device) {
1911 case PCI_DEVICE_ID_RME_DIGI32:
1912 strcpy(card->shortname, "RME Digi32");
1913 break;
1914 case PCI_DEVICE_ID_RME_DIGI32_8:
1915 strcpy(card->shortname, "RME Digi32/8");
1916 break;
1917 case PCI_DEVICE_ID_RME_DIGI32_PRO:
1918 strcpy(card->shortname, "RME Digi32 PRO");
1919 break;
1920 }
1921 sprintf(card->longname, "%s (Rev. %d) at 0x%lx, irq %d",
1922 card->shortname, rme32->rev, rme32->port, rme32->irq);
1923
1924 if ((err = snd_card_register(card)) < 0) {
1925 snd_card_free(card);
1926 return err;
1927 }
1928 pci_set_drvdata(pci, card);
1929 dev++;
1930 return 0;
1931}
1932
1933static void snd_rme32_remove(struct pci_dev *pci)
1934{
1935 snd_card_free(pci_get_drvdata(pci));
1936}
1937
1938static struct pci_driver rme32_driver = {
1939 .name = KBUILD_MODNAME,
1940 .id_table = snd_rme32_ids,
1941 .probe = snd_rme32_probe,
1942 .remove = snd_rme32_remove,
1943};
1944
1945module_pci_driver(rme32_driver);
1/*
2 * ALSA driver for RME Digi32, Digi32/8 and Digi32 PRO audio interfaces
3 *
4 * Copyright (c) 2002-2004 Martin Langer <martin-langer@gmx.de>,
5 * Pilo Chambert <pilo.c@wanadoo.fr>
6 *
7 * Thanks to : Anders Torger <torger@ludd.luth.se>,
8 * Henk Hesselink <henk@anda.nl>
9 * for writing the digi96-driver
10 * and RME for all informations.
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 *
27 * ****************************************************************************
28 *
29 * Note #1 "Sek'd models" ................................... martin 2002-12-07
30 *
31 * Identical soundcards by Sek'd were labeled:
32 * RME Digi 32 = Sek'd Prodif 32
33 * RME Digi 32 Pro = Sek'd Prodif 96
34 * RME Digi 32/8 = Sek'd Prodif Gold
35 *
36 * ****************************************************************************
37 *
38 * Note #2 "full duplex mode" ............................... martin 2002-12-07
39 *
40 * Full duplex doesn't work. All cards (32, 32/8, 32Pro) are working identical
41 * in this mode. Rec data and play data are using the same buffer therefore. At
42 * first you have got the playing bits in the buffer and then (after playing
43 * them) they were overwitten by the captured sound of the CS8412/14. Both
44 * modes (play/record) are running harmonically hand in hand in the same buffer
45 * and you have only one start bit plus one interrupt bit to control this
46 * paired action.
47 * This is opposite to the latter rme96 where playing and capturing is totally
48 * separated and so their full duplex mode is supported by alsa (using two
49 * start bits and two interrupts for two different buffers).
50 * But due to the wrong sequence of playing and capturing ALSA shows no solved
51 * full duplex support for the rme32 at the moment. That's bad, but I'm not
52 * able to solve it. Are you motivated enough to solve this problem now? Your
53 * patch would be welcome!
54 *
55 * ****************************************************************************
56 *
57 * "The story after the long seeking" -- tiwai
58 *
59 * Ok, the situation regarding the full duplex is now improved a bit.
60 * In the fullduplex mode (given by the module parameter), the hardware buffer
61 * is split to halves for read and write directions at the DMA pointer.
62 * That is, the half above the current DMA pointer is used for write, and
63 * the half below is used for read. To mangle this strange behavior, an
64 * software intermediate buffer is introduced. This is, of course, not good
65 * from the viewpoint of the data transfer efficiency. However, this allows
66 * you to use arbitrary buffer sizes, instead of the fixed I/O buffer size.
67 *
68 * ****************************************************************************
69 */
70
71
72#include <linux/delay.h>
73#include <linux/gfp.h>
74#include <linux/init.h>
75#include <linux/interrupt.h>
76#include <linux/pci.h>
77#include <linux/module.h>
78#include <linux/io.h>
79
80#include <sound/core.h>
81#include <sound/info.h>
82#include <sound/control.h>
83#include <sound/pcm.h>
84#include <sound/pcm_params.h>
85#include <sound/pcm-indirect.h>
86#include <sound/asoundef.h>
87#include <sound/initval.h>
88
89static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
90static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
91static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
92static bool fullduplex[SNDRV_CARDS]; // = {[0 ... (SNDRV_CARDS - 1)] = 1};
93
94module_param_array(index, int, NULL, 0444);
95MODULE_PARM_DESC(index, "Index value for RME Digi32 soundcard.");
96module_param_array(id, charp, NULL, 0444);
97MODULE_PARM_DESC(id, "ID string for RME Digi32 soundcard.");
98module_param_array(enable, bool, NULL, 0444);
99MODULE_PARM_DESC(enable, "Enable RME Digi32 soundcard.");
100module_param_array(fullduplex, bool, NULL, 0444);
101MODULE_PARM_DESC(fullduplex, "Support full-duplex mode.");
102MODULE_AUTHOR("Martin Langer <martin-langer@gmx.de>, Pilo Chambert <pilo.c@wanadoo.fr>");
103MODULE_DESCRIPTION("RME Digi32, Digi32/8, Digi32 PRO");
104MODULE_LICENSE("GPL");
105MODULE_SUPPORTED_DEVICE("{{RME,Digi32}," "{RME,Digi32/8}," "{RME,Digi32 PRO}}");
106
107/* Defines for RME Digi32 series */
108#define RME32_SPDIF_NCHANNELS 2
109
110/* Playback and capture buffer size */
111#define RME32_BUFFER_SIZE 0x20000
112
113/* IO area size */
114#define RME32_IO_SIZE 0x30000
115
116/* IO area offsets */
117#define RME32_IO_DATA_BUFFER 0x0
118#define RME32_IO_CONTROL_REGISTER 0x20000
119#define RME32_IO_GET_POS 0x20000
120#define RME32_IO_CONFIRM_ACTION_IRQ 0x20004
121#define RME32_IO_RESET_POS 0x20100
122
123/* Write control register bits */
124#define RME32_WCR_START (1 << 0) /* startbit */
125#define RME32_WCR_MONO (1 << 1) /* 0=stereo, 1=mono
126 Setting the whole card to mono
127 doesn't seem to be very useful.
128 A software-solution can handle
129 full-duplex with one direction in
130 stereo and the other way in mono.
131 So, the hardware should work all
132 the time in stereo! */
133#define RME32_WCR_MODE24 (1 << 2) /* 0=16bit, 1=32bit */
134#define RME32_WCR_SEL (1 << 3) /* 0=input on output, 1=normal playback/capture */
135#define RME32_WCR_FREQ_0 (1 << 4) /* frequency (play) */
136#define RME32_WCR_FREQ_1 (1 << 5)
137#define RME32_WCR_INP_0 (1 << 6) /* input switch */
138#define RME32_WCR_INP_1 (1 << 7)
139#define RME32_WCR_RESET (1 << 8) /* Reset address */
140#define RME32_WCR_MUTE (1 << 9) /* digital mute for output */
141#define RME32_WCR_PRO (1 << 10) /* 1=professional, 0=consumer */
142#define RME32_WCR_DS_BM (1 << 11) /* 1=DoubleSpeed (only PRO-Version); 1=BlockMode (only Adat-Version) */
143#define RME32_WCR_ADAT (1 << 12) /* Adat Mode (only Adat-Version) */
144#define RME32_WCR_AUTOSYNC (1 << 13) /* AutoSync */
145#define RME32_WCR_PD (1 << 14) /* DAC Reset (only PRO-Version) */
146#define RME32_WCR_EMP (1 << 15) /* 1=Emphasis on (only PRO-Version) */
147
148#define RME32_WCR_BITPOS_FREQ_0 4
149#define RME32_WCR_BITPOS_FREQ_1 5
150#define RME32_WCR_BITPOS_INP_0 6
151#define RME32_WCR_BITPOS_INP_1 7
152
153/* Read control register bits */
154#define RME32_RCR_AUDIO_ADDR_MASK 0x1ffff
155#define RME32_RCR_LOCK (1 << 23) /* 1=locked, 0=not locked */
156#define RME32_RCR_ERF (1 << 26) /* 1=Error, 0=no Error */
157#define RME32_RCR_FREQ_0 (1 << 27) /* CS841x frequency (record) */
158#define RME32_RCR_FREQ_1 (1 << 28)
159#define RME32_RCR_FREQ_2 (1 << 29)
160#define RME32_RCR_KMODE (1 << 30) /* card mode: 1=PLL, 0=quartz */
161#define RME32_RCR_IRQ (1 << 31) /* interrupt */
162
163#define RME32_RCR_BITPOS_F0 27
164#define RME32_RCR_BITPOS_F1 28
165#define RME32_RCR_BITPOS_F2 29
166
167/* Input types */
168#define RME32_INPUT_OPTICAL 0
169#define RME32_INPUT_COAXIAL 1
170#define RME32_INPUT_INTERNAL 2
171#define RME32_INPUT_XLR 3
172
173/* Clock modes */
174#define RME32_CLOCKMODE_SLAVE 0
175#define RME32_CLOCKMODE_MASTER_32 1
176#define RME32_CLOCKMODE_MASTER_44 2
177#define RME32_CLOCKMODE_MASTER_48 3
178
179/* Block sizes in bytes */
180#define RME32_BLOCK_SIZE 8192
181
182/* Software intermediate buffer (max) size */
183#define RME32_MID_BUFFER_SIZE (1024*1024)
184
185/* Hardware revisions */
186#define RME32_32_REVISION 192
187#define RME32_328_REVISION_OLD 100
188#define RME32_328_REVISION_NEW 101
189#define RME32_PRO_REVISION_WITH_8412 192
190#define RME32_PRO_REVISION_WITH_8414 150
191
192
193struct rme32 {
194 spinlock_t lock;
195 int irq;
196 unsigned long port;
197 void __iomem *iobase;
198
199 u32 wcreg; /* cached write control register value */
200 u32 wcreg_spdif; /* S/PDIF setup */
201 u32 wcreg_spdif_stream; /* S/PDIF setup (temporary) */
202 u32 rcreg; /* cached read control register value */
203
204 u8 rev; /* card revision number */
205
206 struct snd_pcm_substream *playback_substream;
207 struct snd_pcm_substream *capture_substream;
208
209 int playback_frlog; /* log2 of framesize */
210 int capture_frlog;
211
212 size_t playback_periodsize; /* in bytes, zero if not used */
213 size_t capture_periodsize; /* in bytes, zero if not used */
214
215 unsigned int fullduplex_mode;
216 int running;
217
218 struct snd_pcm_indirect playback_pcm;
219 struct snd_pcm_indirect capture_pcm;
220
221 struct snd_card *card;
222 struct snd_pcm *spdif_pcm;
223 struct snd_pcm *adat_pcm;
224 struct pci_dev *pci;
225 struct snd_kcontrol *spdif_ctl;
226};
227
228static const struct pci_device_id snd_rme32_ids[] = {
229 {PCI_VDEVICE(XILINX_RME, PCI_DEVICE_ID_RME_DIGI32), 0,},
230 {PCI_VDEVICE(XILINX_RME, PCI_DEVICE_ID_RME_DIGI32_8), 0,},
231 {PCI_VDEVICE(XILINX_RME, PCI_DEVICE_ID_RME_DIGI32_PRO), 0,},
232 {0,}
233};
234
235MODULE_DEVICE_TABLE(pci, snd_rme32_ids);
236
237#define RME32_ISWORKING(rme32) ((rme32)->wcreg & RME32_WCR_START)
238#define RME32_PRO_WITH_8414(rme32) ((rme32)->pci->device == PCI_DEVICE_ID_RME_DIGI32_PRO && (rme32)->rev == RME32_PRO_REVISION_WITH_8414)
239
240static int snd_rme32_playback_prepare(struct snd_pcm_substream *substream);
241
242static int snd_rme32_capture_prepare(struct snd_pcm_substream *substream);
243
244static int snd_rme32_pcm_trigger(struct snd_pcm_substream *substream, int cmd);
245
246static void snd_rme32_proc_init(struct rme32 * rme32);
247
248static int snd_rme32_create_switches(struct snd_card *card, struct rme32 * rme32);
249
250static inline unsigned int snd_rme32_pcm_byteptr(struct rme32 * rme32)
251{
252 return (readl(rme32->iobase + RME32_IO_GET_POS)
253 & RME32_RCR_AUDIO_ADDR_MASK);
254}
255
256/* silence callback for halfduplex mode */
257static int snd_rme32_playback_silence(struct snd_pcm_substream *substream, int channel, /* not used (interleaved data) */
258 snd_pcm_uframes_t pos,
259 snd_pcm_uframes_t count)
260{
261 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
262 count <<= rme32->playback_frlog;
263 pos <<= rme32->playback_frlog;
264 memset_io(rme32->iobase + RME32_IO_DATA_BUFFER + pos, 0, count);
265 return 0;
266}
267
268/* copy callback for halfduplex mode */
269static int snd_rme32_playback_copy(struct snd_pcm_substream *substream, int channel, /* not used (interleaved data) */
270 snd_pcm_uframes_t pos,
271 void __user *src, snd_pcm_uframes_t count)
272{
273 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
274 count <<= rme32->playback_frlog;
275 pos <<= rme32->playback_frlog;
276 if (copy_from_user_toio(rme32->iobase + RME32_IO_DATA_BUFFER + pos,
277 src, count))
278 return -EFAULT;
279 return 0;
280}
281
282/* copy callback for halfduplex mode */
283static int snd_rme32_capture_copy(struct snd_pcm_substream *substream, int channel, /* not used (interleaved data) */
284 snd_pcm_uframes_t pos,
285 void __user *dst, snd_pcm_uframes_t count)
286{
287 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
288 count <<= rme32->capture_frlog;
289 pos <<= rme32->capture_frlog;
290 if (copy_to_user_fromio(dst,
291 rme32->iobase + RME32_IO_DATA_BUFFER + pos,
292 count))
293 return -EFAULT;
294 return 0;
295}
296
297/*
298 * SPDIF I/O capabilities (half-duplex mode)
299 */
300static struct snd_pcm_hardware snd_rme32_spdif_info = {
301 .info = (SNDRV_PCM_INFO_MMAP_IOMEM |
302 SNDRV_PCM_INFO_MMAP_VALID |
303 SNDRV_PCM_INFO_INTERLEAVED |
304 SNDRV_PCM_INFO_PAUSE |
305 SNDRV_PCM_INFO_SYNC_START),
306 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
307 SNDRV_PCM_FMTBIT_S32_LE),
308 .rates = (SNDRV_PCM_RATE_32000 |
309 SNDRV_PCM_RATE_44100 |
310 SNDRV_PCM_RATE_48000),
311 .rate_min = 32000,
312 .rate_max = 48000,
313 .channels_min = 2,
314 .channels_max = 2,
315 .buffer_bytes_max = RME32_BUFFER_SIZE,
316 .period_bytes_min = RME32_BLOCK_SIZE,
317 .period_bytes_max = RME32_BLOCK_SIZE,
318 .periods_min = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE,
319 .periods_max = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE,
320 .fifo_size = 0,
321};
322
323/*
324 * ADAT I/O capabilities (half-duplex mode)
325 */
326static struct snd_pcm_hardware snd_rme32_adat_info =
327{
328 .info = (SNDRV_PCM_INFO_MMAP_IOMEM |
329 SNDRV_PCM_INFO_MMAP_VALID |
330 SNDRV_PCM_INFO_INTERLEAVED |
331 SNDRV_PCM_INFO_PAUSE |
332 SNDRV_PCM_INFO_SYNC_START),
333 .formats= SNDRV_PCM_FMTBIT_S16_LE,
334 .rates = (SNDRV_PCM_RATE_44100 |
335 SNDRV_PCM_RATE_48000),
336 .rate_min = 44100,
337 .rate_max = 48000,
338 .channels_min = 8,
339 .channels_max = 8,
340 .buffer_bytes_max = RME32_BUFFER_SIZE,
341 .period_bytes_min = RME32_BLOCK_SIZE,
342 .period_bytes_max = RME32_BLOCK_SIZE,
343 .periods_min = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE,
344 .periods_max = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE,
345 .fifo_size = 0,
346};
347
348/*
349 * SPDIF I/O capabilities (full-duplex mode)
350 */
351static struct snd_pcm_hardware snd_rme32_spdif_fd_info = {
352 .info = (SNDRV_PCM_INFO_MMAP |
353 SNDRV_PCM_INFO_MMAP_VALID |
354 SNDRV_PCM_INFO_INTERLEAVED |
355 SNDRV_PCM_INFO_PAUSE |
356 SNDRV_PCM_INFO_SYNC_START),
357 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
358 SNDRV_PCM_FMTBIT_S32_LE),
359 .rates = (SNDRV_PCM_RATE_32000 |
360 SNDRV_PCM_RATE_44100 |
361 SNDRV_PCM_RATE_48000),
362 .rate_min = 32000,
363 .rate_max = 48000,
364 .channels_min = 2,
365 .channels_max = 2,
366 .buffer_bytes_max = RME32_MID_BUFFER_SIZE,
367 .period_bytes_min = RME32_BLOCK_SIZE,
368 .period_bytes_max = RME32_BLOCK_SIZE,
369 .periods_min = 2,
370 .periods_max = RME32_MID_BUFFER_SIZE / RME32_BLOCK_SIZE,
371 .fifo_size = 0,
372};
373
374/*
375 * ADAT I/O capabilities (full-duplex mode)
376 */
377static struct snd_pcm_hardware snd_rme32_adat_fd_info =
378{
379 .info = (SNDRV_PCM_INFO_MMAP |
380 SNDRV_PCM_INFO_MMAP_VALID |
381 SNDRV_PCM_INFO_INTERLEAVED |
382 SNDRV_PCM_INFO_PAUSE |
383 SNDRV_PCM_INFO_SYNC_START),
384 .formats= SNDRV_PCM_FMTBIT_S16_LE,
385 .rates = (SNDRV_PCM_RATE_44100 |
386 SNDRV_PCM_RATE_48000),
387 .rate_min = 44100,
388 .rate_max = 48000,
389 .channels_min = 8,
390 .channels_max = 8,
391 .buffer_bytes_max = RME32_MID_BUFFER_SIZE,
392 .period_bytes_min = RME32_BLOCK_SIZE,
393 .period_bytes_max = RME32_BLOCK_SIZE,
394 .periods_min = 2,
395 .periods_max = RME32_MID_BUFFER_SIZE / RME32_BLOCK_SIZE,
396 .fifo_size = 0,
397};
398
399static void snd_rme32_reset_dac(struct rme32 *rme32)
400{
401 writel(rme32->wcreg | RME32_WCR_PD,
402 rme32->iobase + RME32_IO_CONTROL_REGISTER);
403 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
404}
405
406static int snd_rme32_playback_getrate(struct rme32 * rme32)
407{
408 int rate;
409
410 rate = ((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_0) & 1) +
411 (((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_1) & 1) << 1);
412 switch (rate) {
413 case 1:
414 rate = 32000;
415 break;
416 case 2:
417 rate = 44100;
418 break;
419 case 3:
420 rate = 48000;
421 break;
422 default:
423 return -1;
424 }
425 return (rme32->wcreg & RME32_WCR_DS_BM) ? rate << 1 : rate;
426}
427
428static int snd_rme32_capture_getrate(struct rme32 * rme32, int *is_adat)
429{
430 int n;
431
432 *is_adat = 0;
433 if (rme32->rcreg & RME32_RCR_LOCK) {
434 /* ADAT rate */
435 *is_adat = 1;
436 }
437 if (rme32->rcreg & RME32_RCR_ERF) {
438 return -1;
439 }
440
441 /* S/PDIF rate */
442 n = ((rme32->rcreg >> RME32_RCR_BITPOS_F0) & 1) +
443 (((rme32->rcreg >> RME32_RCR_BITPOS_F1) & 1) << 1) +
444 (((rme32->rcreg >> RME32_RCR_BITPOS_F2) & 1) << 2);
445
446 if (RME32_PRO_WITH_8414(rme32))
447 switch (n) { /* supporting the CS8414 */
448 case 0:
449 case 1:
450 case 2:
451 return -1;
452 case 3:
453 return 96000;
454 case 4:
455 return 88200;
456 case 5:
457 return 48000;
458 case 6:
459 return 44100;
460 case 7:
461 return 32000;
462 default:
463 return -1;
464 break;
465 }
466 else
467 switch (n) { /* supporting the CS8412 */
468 case 0:
469 return -1;
470 case 1:
471 return 48000;
472 case 2:
473 return 44100;
474 case 3:
475 return 32000;
476 case 4:
477 return 48000;
478 case 5:
479 return 44100;
480 case 6:
481 return 44056;
482 case 7:
483 return 32000;
484 default:
485 break;
486 }
487 return -1;
488}
489
490static int snd_rme32_playback_setrate(struct rme32 * rme32, int rate)
491{
492 int ds;
493
494 ds = rme32->wcreg & RME32_WCR_DS_BM;
495 switch (rate) {
496 case 32000:
497 rme32->wcreg &= ~RME32_WCR_DS_BM;
498 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) &
499 ~RME32_WCR_FREQ_1;
500 break;
501 case 44100:
502 rme32->wcreg &= ~RME32_WCR_DS_BM;
503 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_1) &
504 ~RME32_WCR_FREQ_0;
505 break;
506 case 48000:
507 rme32->wcreg &= ~RME32_WCR_DS_BM;
508 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) |
509 RME32_WCR_FREQ_1;
510 break;
511 case 64000:
512 if (rme32->pci->device != PCI_DEVICE_ID_RME_DIGI32_PRO)
513 return -EINVAL;
514 rme32->wcreg |= RME32_WCR_DS_BM;
515 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) &
516 ~RME32_WCR_FREQ_1;
517 break;
518 case 88200:
519 if (rme32->pci->device != PCI_DEVICE_ID_RME_DIGI32_PRO)
520 return -EINVAL;
521 rme32->wcreg |= RME32_WCR_DS_BM;
522 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_1) &
523 ~RME32_WCR_FREQ_0;
524 break;
525 case 96000:
526 if (rme32->pci->device != PCI_DEVICE_ID_RME_DIGI32_PRO)
527 return -EINVAL;
528 rme32->wcreg |= RME32_WCR_DS_BM;
529 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) |
530 RME32_WCR_FREQ_1;
531 break;
532 default:
533 return -EINVAL;
534 }
535 if ((!ds && rme32->wcreg & RME32_WCR_DS_BM) ||
536 (ds && !(rme32->wcreg & RME32_WCR_DS_BM)))
537 {
538 /* change to/from double-speed: reset the DAC (if available) */
539 snd_rme32_reset_dac(rme32);
540 } else {
541 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
542 }
543 return 0;
544}
545
546static int snd_rme32_setclockmode(struct rme32 * rme32, int mode)
547{
548 switch (mode) {
549 case RME32_CLOCKMODE_SLAVE:
550 /* AutoSync */
551 rme32->wcreg = (rme32->wcreg & ~RME32_WCR_FREQ_0) &
552 ~RME32_WCR_FREQ_1;
553 break;
554 case RME32_CLOCKMODE_MASTER_32:
555 /* Internal 32.0kHz */
556 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) &
557 ~RME32_WCR_FREQ_1;
558 break;
559 case RME32_CLOCKMODE_MASTER_44:
560 /* Internal 44.1kHz */
561 rme32->wcreg = (rme32->wcreg & ~RME32_WCR_FREQ_0) |
562 RME32_WCR_FREQ_1;
563 break;
564 case RME32_CLOCKMODE_MASTER_48:
565 /* Internal 48.0kHz */
566 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) |
567 RME32_WCR_FREQ_1;
568 break;
569 default:
570 return -EINVAL;
571 }
572 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
573 return 0;
574}
575
576static int snd_rme32_getclockmode(struct rme32 * rme32)
577{
578 return ((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_0) & 1) +
579 (((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_1) & 1) << 1);
580}
581
582static int snd_rme32_setinputtype(struct rme32 * rme32, int type)
583{
584 switch (type) {
585 case RME32_INPUT_OPTICAL:
586 rme32->wcreg = (rme32->wcreg & ~RME32_WCR_INP_0) &
587 ~RME32_WCR_INP_1;
588 break;
589 case RME32_INPUT_COAXIAL:
590 rme32->wcreg = (rme32->wcreg | RME32_WCR_INP_0) &
591 ~RME32_WCR_INP_1;
592 break;
593 case RME32_INPUT_INTERNAL:
594 rme32->wcreg = (rme32->wcreg & ~RME32_WCR_INP_0) |
595 RME32_WCR_INP_1;
596 break;
597 case RME32_INPUT_XLR:
598 rme32->wcreg = (rme32->wcreg | RME32_WCR_INP_0) |
599 RME32_WCR_INP_1;
600 break;
601 default:
602 return -EINVAL;
603 }
604 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
605 return 0;
606}
607
608static int snd_rme32_getinputtype(struct rme32 * rme32)
609{
610 return ((rme32->wcreg >> RME32_WCR_BITPOS_INP_0) & 1) +
611 (((rme32->wcreg >> RME32_WCR_BITPOS_INP_1) & 1) << 1);
612}
613
614static void
615snd_rme32_setframelog(struct rme32 * rme32, int n_channels, int is_playback)
616{
617 int frlog;
618
619 if (n_channels == 2) {
620 frlog = 1;
621 } else {
622 /* assume 8 channels */
623 frlog = 3;
624 }
625 if (is_playback) {
626 frlog += (rme32->wcreg & RME32_WCR_MODE24) ? 2 : 1;
627 rme32->playback_frlog = frlog;
628 } else {
629 frlog += (rme32->wcreg & RME32_WCR_MODE24) ? 2 : 1;
630 rme32->capture_frlog = frlog;
631 }
632}
633
634static int snd_rme32_setformat(struct rme32 *rme32, snd_pcm_format_t format)
635{
636 switch (format) {
637 case SNDRV_PCM_FORMAT_S16_LE:
638 rme32->wcreg &= ~RME32_WCR_MODE24;
639 break;
640 case SNDRV_PCM_FORMAT_S32_LE:
641 rme32->wcreg |= RME32_WCR_MODE24;
642 break;
643 default:
644 return -EINVAL;
645 }
646 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
647 return 0;
648}
649
650static int
651snd_rme32_playback_hw_params(struct snd_pcm_substream *substream,
652 struct snd_pcm_hw_params *params)
653{
654 int err, rate, dummy;
655 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
656 struct snd_pcm_runtime *runtime = substream->runtime;
657
658 if (rme32->fullduplex_mode) {
659 err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(params));
660 if (err < 0)
661 return err;
662 } else {
663 runtime->dma_area = (void __force *)(rme32->iobase +
664 RME32_IO_DATA_BUFFER);
665 runtime->dma_addr = rme32->port + RME32_IO_DATA_BUFFER;
666 runtime->dma_bytes = RME32_BUFFER_SIZE;
667 }
668
669 spin_lock_irq(&rme32->lock);
670 if ((rme32->rcreg & RME32_RCR_KMODE) &&
671 (rate = snd_rme32_capture_getrate(rme32, &dummy)) > 0) {
672 /* AutoSync */
673 if ((int)params_rate(params) != rate) {
674 spin_unlock_irq(&rme32->lock);
675 return -EIO;
676 }
677 } else if ((err = snd_rme32_playback_setrate(rme32, params_rate(params))) < 0) {
678 spin_unlock_irq(&rme32->lock);
679 return err;
680 }
681 if ((err = snd_rme32_setformat(rme32, params_format(params))) < 0) {
682 spin_unlock_irq(&rme32->lock);
683 return err;
684 }
685
686 snd_rme32_setframelog(rme32, params_channels(params), 1);
687 if (rme32->capture_periodsize != 0) {
688 if (params_period_size(params) << rme32->playback_frlog != rme32->capture_periodsize) {
689 spin_unlock_irq(&rme32->lock);
690 return -EBUSY;
691 }
692 }
693 rme32->playback_periodsize = params_period_size(params) << rme32->playback_frlog;
694 /* S/PDIF setup */
695 if ((rme32->wcreg & RME32_WCR_ADAT) == 0) {
696 rme32->wcreg &= ~(RME32_WCR_PRO | RME32_WCR_EMP);
697 rme32->wcreg |= rme32->wcreg_spdif_stream;
698 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
699 }
700 spin_unlock_irq(&rme32->lock);
701
702 return 0;
703}
704
705static int
706snd_rme32_capture_hw_params(struct snd_pcm_substream *substream,
707 struct snd_pcm_hw_params *params)
708{
709 int err, isadat, rate;
710 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
711 struct snd_pcm_runtime *runtime = substream->runtime;
712
713 if (rme32->fullduplex_mode) {
714 err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(params));
715 if (err < 0)
716 return err;
717 } else {
718 runtime->dma_area = (void __force *)rme32->iobase +
719 RME32_IO_DATA_BUFFER;
720 runtime->dma_addr = rme32->port + RME32_IO_DATA_BUFFER;
721 runtime->dma_bytes = RME32_BUFFER_SIZE;
722 }
723
724 spin_lock_irq(&rme32->lock);
725 /* enable AutoSync for record-preparing */
726 rme32->wcreg |= RME32_WCR_AUTOSYNC;
727 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
728
729 if ((err = snd_rme32_setformat(rme32, params_format(params))) < 0) {
730 spin_unlock_irq(&rme32->lock);
731 return err;
732 }
733 if ((err = snd_rme32_playback_setrate(rme32, params_rate(params))) < 0) {
734 spin_unlock_irq(&rme32->lock);
735 return err;
736 }
737 if ((rate = snd_rme32_capture_getrate(rme32, &isadat)) > 0) {
738 if ((int)params_rate(params) != rate) {
739 spin_unlock_irq(&rme32->lock);
740 return -EIO;
741 }
742 if ((isadat && runtime->hw.channels_min == 2) ||
743 (!isadat && runtime->hw.channels_min == 8)) {
744 spin_unlock_irq(&rme32->lock);
745 return -EIO;
746 }
747 }
748 /* AutoSync off for recording */
749 rme32->wcreg &= ~RME32_WCR_AUTOSYNC;
750 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
751
752 snd_rme32_setframelog(rme32, params_channels(params), 0);
753 if (rme32->playback_periodsize != 0) {
754 if (params_period_size(params) << rme32->capture_frlog !=
755 rme32->playback_periodsize) {
756 spin_unlock_irq(&rme32->lock);
757 return -EBUSY;
758 }
759 }
760 rme32->capture_periodsize =
761 params_period_size(params) << rme32->capture_frlog;
762 spin_unlock_irq(&rme32->lock);
763
764 return 0;
765}
766
767static int snd_rme32_pcm_hw_free(struct snd_pcm_substream *substream)
768{
769 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
770 if (! rme32->fullduplex_mode)
771 return 0;
772 return snd_pcm_lib_free_pages(substream);
773}
774
775static void snd_rme32_pcm_start(struct rme32 * rme32, int from_pause)
776{
777 if (!from_pause) {
778 writel(0, rme32->iobase + RME32_IO_RESET_POS);
779 }
780
781 rme32->wcreg |= RME32_WCR_START;
782 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
783}
784
785static void snd_rme32_pcm_stop(struct rme32 * rme32, int to_pause)
786{
787 /*
788 * Check if there is an unconfirmed IRQ, if so confirm it, or else
789 * the hardware will not stop generating interrupts
790 */
791 rme32->rcreg = readl(rme32->iobase + RME32_IO_CONTROL_REGISTER);
792 if (rme32->rcreg & RME32_RCR_IRQ) {
793 writel(0, rme32->iobase + RME32_IO_CONFIRM_ACTION_IRQ);
794 }
795 rme32->wcreg &= ~RME32_WCR_START;
796 if (rme32->wcreg & RME32_WCR_SEL)
797 rme32->wcreg |= RME32_WCR_MUTE;
798 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
799 if (! to_pause)
800 writel(0, rme32->iobase + RME32_IO_RESET_POS);
801}
802
803static irqreturn_t snd_rme32_interrupt(int irq, void *dev_id)
804{
805 struct rme32 *rme32 = (struct rme32 *) dev_id;
806
807 rme32->rcreg = readl(rme32->iobase + RME32_IO_CONTROL_REGISTER);
808 if (!(rme32->rcreg & RME32_RCR_IRQ)) {
809 return IRQ_NONE;
810 } else {
811 if (rme32->capture_substream) {
812 snd_pcm_period_elapsed(rme32->capture_substream);
813 }
814 if (rme32->playback_substream) {
815 snd_pcm_period_elapsed(rme32->playback_substream);
816 }
817 writel(0, rme32->iobase + RME32_IO_CONFIRM_ACTION_IRQ);
818 }
819 return IRQ_HANDLED;
820}
821
822static unsigned int period_bytes[] = { RME32_BLOCK_SIZE };
823
824
825static struct snd_pcm_hw_constraint_list hw_constraints_period_bytes = {
826 .count = ARRAY_SIZE(period_bytes),
827 .list = period_bytes,
828 .mask = 0
829};
830
831static void snd_rme32_set_buffer_constraint(struct rme32 *rme32, struct snd_pcm_runtime *runtime)
832{
833 if (! rme32->fullduplex_mode) {
834 snd_pcm_hw_constraint_single(runtime,
835 SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
836 RME32_BUFFER_SIZE);
837 snd_pcm_hw_constraint_list(runtime, 0,
838 SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
839 &hw_constraints_period_bytes);
840 }
841}
842
843static int snd_rme32_playback_spdif_open(struct snd_pcm_substream *substream)
844{
845 int rate, dummy;
846 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
847 struct snd_pcm_runtime *runtime = substream->runtime;
848
849 snd_pcm_set_sync(substream);
850
851 spin_lock_irq(&rme32->lock);
852 if (rme32->playback_substream != NULL) {
853 spin_unlock_irq(&rme32->lock);
854 return -EBUSY;
855 }
856 rme32->wcreg &= ~RME32_WCR_ADAT;
857 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
858 rme32->playback_substream = substream;
859 spin_unlock_irq(&rme32->lock);
860
861 if (rme32->fullduplex_mode)
862 runtime->hw = snd_rme32_spdif_fd_info;
863 else
864 runtime->hw = snd_rme32_spdif_info;
865 if (rme32->pci->device == PCI_DEVICE_ID_RME_DIGI32_PRO) {
866 runtime->hw.rates |= SNDRV_PCM_RATE_64000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000;
867 runtime->hw.rate_max = 96000;
868 }
869 if ((rme32->rcreg & RME32_RCR_KMODE) &&
870 (rate = snd_rme32_capture_getrate(rme32, &dummy)) > 0) {
871 /* AutoSync */
872 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
873 runtime->hw.rate_min = rate;
874 runtime->hw.rate_max = rate;
875 }
876
877 snd_rme32_set_buffer_constraint(rme32, runtime);
878
879 rme32->wcreg_spdif_stream = rme32->wcreg_spdif;
880 rme32->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
881 snd_ctl_notify(rme32->card, SNDRV_CTL_EVENT_MASK_VALUE |
882 SNDRV_CTL_EVENT_MASK_INFO, &rme32->spdif_ctl->id);
883 return 0;
884}
885
886static int snd_rme32_capture_spdif_open(struct snd_pcm_substream *substream)
887{
888 int isadat, rate;
889 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
890 struct snd_pcm_runtime *runtime = substream->runtime;
891
892 snd_pcm_set_sync(substream);
893
894 spin_lock_irq(&rme32->lock);
895 if (rme32->capture_substream != NULL) {
896 spin_unlock_irq(&rme32->lock);
897 return -EBUSY;
898 }
899 rme32->capture_substream = substream;
900 spin_unlock_irq(&rme32->lock);
901
902 if (rme32->fullduplex_mode)
903 runtime->hw = snd_rme32_spdif_fd_info;
904 else
905 runtime->hw = snd_rme32_spdif_info;
906 if (RME32_PRO_WITH_8414(rme32)) {
907 runtime->hw.rates |= SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000;
908 runtime->hw.rate_max = 96000;
909 }
910 if ((rate = snd_rme32_capture_getrate(rme32, &isadat)) > 0) {
911 if (isadat) {
912 return -EIO;
913 }
914 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
915 runtime->hw.rate_min = rate;
916 runtime->hw.rate_max = rate;
917 }
918
919 snd_rme32_set_buffer_constraint(rme32, runtime);
920
921 return 0;
922}
923
924static int
925snd_rme32_playback_adat_open(struct snd_pcm_substream *substream)
926{
927 int rate, dummy;
928 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
929 struct snd_pcm_runtime *runtime = substream->runtime;
930
931 snd_pcm_set_sync(substream);
932
933 spin_lock_irq(&rme32->lock);
934 if (rme32->playback_substream != NULL) {
935 spin_unlock_irq(&rme32->lock);
936 return -EBUSY;
937 }
938 rme32->wcreg |= RME32_WCR_ADAT;
939 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
940 rme32->playback_substream = substream;
941 spin_unlock_irq(&rme32->lock);
942
943 if (rme32->fullduplex_mode)
944 runtime->hw = snd_rme32_adat_fd_info;
945 else
946 runtime->hw = snd_rme32_adat_info;
947 if ((rme32->rcreg & RME32_RCR_KMODE) &&
948 (rate = snd_rme32_capture_getrate(rme32, &dummy)) > 0) {
949 /* AutoSync */
950 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
951 runtime->hw.rate_min = rate;
952 runtime->hw.rate_max = rate;
953 }
954
955 snd_rme32_set_buffer_constraint(rme32, runtime);
956 return 0;
957}
958
959static int
960snd_rme32_capture_adat_open(struct snd_pcm_substream *substream)
961{
962 int isadat, rate;
963 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
964 struct snd_pcm_runtime *runtime = substream->runtime;
965
966 if (rme32->fullduplex_mode)
967 runtime->hw = snd_rme32_adat_fd_info;
968 else
969 runtime->hw = snd_rme32_adat_info;
970 if ((rate = snd_rme32_capture_getrate(rme32, &isadat)) > 0) {
971 if (!isadat) {
972 return -EIO;
973 }
974 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
975 runtime->hw.rate_min = rate;
976 runtime->hw.rate_max = rate;
977 }
978
979 snd_pcm_set_sync(substream);
980
981 spin_lock_irq(&rme32->lock);
982 if (rme32->capture_substream != NULL) {
983 spin_unlock_irq(&rme32->lock);
984 return -EBUSY;
985 }
986 rme32->capture_substream = substream;
987 spin_unlock_irq(&rme32->lock);
988
989 snd_rme32_set_buffer_constraint(rme32, runtime);
990 return 0;
991}
992
993static int snd_rme32_playback_close(struct snd_pcm_substream *substream)
994{
995 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
996 int spdif = 0;
997
998 spin_lock_irq(&rme32->lock);
999 rme32->playback_substream = NULL;
1000 rme32->playback_periodsize = 0;
1001 spdif = (rme32->wcreg & RME32_WCR_ADAT) == 0;
1002 spin_unlock_irq(&rme32->lock);
1003 if (spdif) {
1004 rme32->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1005 snd_ctl_notify(rme32->card, SNDRV_CTL_EVENT_MASK_VALUE |
1006 SNDRV_CTL_EVENT_MASK_INFO,
1007 &rme32->spdif_ctl->id);
1008 }
1009 return 0;
1010}
1011
1012static int snd_rme32_capture_close(struct snd_pcm_substream *substream)
1013{
1014 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1015
1016 spin_lock_irq(&rme32->lock);
1017 rme32->capture_substream = NULL;
1018 rme32->capture_periodsize = 0;
1019 spin_unlock_irq(&rme32->lock);
1020 return 0;
1021}
1022
1023static int snd_rme32_playback_prepare(struct snd_pcm_substream *substream)
1024{
1025 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1026
1027 spin_lock_irq(&rme32->lock);
1028 if (rme32->fullduplex_mode) {
1029 memset(&rme32->playback_pcm, 0, sizeof(rme32->playback_pcm));
1030 rme32->playback_pcm.hw_buffer_size = RME32_BUFFER_SIZE;
1031 rme32->playback_pcm.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
1032 } else {
1033 writel(0, rme32->iobase + RME32_IO_RESET_POS);
1034 }
1035 if (rme32->wcreg & RME32_WCR_SEL)
1036 rme32->wcreg &= ~RME32_WCR_MUTE;
1037 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
1038 spin_unlock_irq(&rme32->lock);
1039 return 0;
1040}
1041
1042static int snd_rme32_capture_prepare(struct snd_pcm_substream *substream)
1043{
1044 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1045
1046 spin_lock_irq(&rme32->lock);
1047 if (rme32->fullduplex_mode) {
1048 memset(&rme32->capture_pcm, 0, sizeof(rme32->capture_pcm));
1049 rme32->capture_pcm.hw_buffer_size = RME32_BUFFER_SIZE;
1050 rme32->capture_pcm.hw_queue_size = RME32_BUFFER_SIZE / 2;
1051 rme32->capture_pcm.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
1052 } else {
1053 writel(0, rme32->iobase + RME32_IO_RESET_POS);
1054 }
1055 spin_unlock_irq(&rme32->lock);
1056 return 0;
1057}
1058
1059static int
1060snd_rme32_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1061{
1062 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1063 struct snd_pcm_substream *s;
1064
1065 spin_lock(&rme32->lock);
1066 snd_pcm_group_for_each_entry(s, substream) {
1067 if (s != rme32->playback_substream &&
1068 s != rme32->capture_substream)
1069 continue;
1070 switch (cmd) {
1071 case SNDRV_PCM_TRIGGER_START:
1072 rme32->running |= (1 << s->stream);
1073 if (rme32->fullduplex_mode) {
1074 /* remember the current DMA position */
1075 if (s == rme32->playback_substream) {
1076 rme32->playback_pcm.hw_io =
1077 rme32->playback_pcm.hw_data = snd_rme32_pcm_byteptr(rme32);
1078 } else {
1079 rme32->capture_pcm.hw_io =
1080 rme32->capture_pcm.hw_data = snd_rme32_pcm_byteptr(rme32);
1081 }
1082 }
1083 break;
1084 case SNDRV_PCM_TRIGGER_STOP:
1085 rme32->running &= ~(1 << s->stream);
1086 break;
1087 }
1088 snd_pcm_trigger_done(s, substream);
1089 }
1090
1091 /* prefill playback buffer */
1092 if (cmd == SNDRV_PCM_TRIGGER_START && rme32->fullduplex_mode) {
1093 snd_pcm_group_for_each_entry(s, substream) {
1094 if (s == rme32->playback_substream) {
1095 s->ops->ack(s);
1096 break;
1097 }
1098 }
1099 }
1100
1101 switch (cmd) {
1102 case SNDRV_PCM_TRIGGER_START:
1103 if (rme32->running && ! RME32_ISWORKING(rme32))
1104 snd_rme32_pcm_start(rme32, 0);
1105 break;
1106 case SNDRV_PCM_TRIGGER_STOP:
1107 if (! rme32->running && RME32_ISWORKING(rme32))
1108 snd_rme32_pcm_stop(rme32, 0);
1109 break;
1110 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1111 if (rme32->running && RME32_ISWORKING(rme32))
1112 snd_rme32_pcm_stop(rme32, 1);
1113 break;
1114 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1115 if (rme32->running && ! RME32_ISWORKING(rme32))
1116 snd_rme32_pcm_start(rme32, 1);
1117 break;
1118 }
1119 spin_unlock(&rme32->lock);
1120 return 0;
1121}
1122
1123/* pointer callback for halfduplex mode */
1124static snd_pcm_uframes_t
1125snd_rme32_playback_pointer(struct snd_pcm_substream *substream)
1126{
1127 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1128 return snd_rme32_pcm_byteptr(rme32) >> rme32->playback_frlog;
1129}
1130
1131static snd_pcm_uframes_t
1132snd_rme32_capture_pointer(struct snd_pcm_substream *substream)
1133{
1134 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1135 return snd_rme32_pcm_byteptr(rme32) >> rme32->capture_frlog;
1136}
1137
1138
1139/* ack and pointer callbacks for fullduplex mode */
1140static void snd_rme32_pb_trans_copy(struct snd_pcm_substream *substream,
1141 struct snd_pcm_indirect *rec, size_t bytes)
1142{
1143 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1144 memcpy_toio(rme32->iobase + RME32_IO_DATA_BUFFER + rec->hw_data,
1145 substream->runtime->dma_area + rec->sw_data, bytes);
1146}
1147
1148static int snd_rme32_playback_fd_ack(struct snd_pcm_substream *substream)
1149{
1150 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1151 struct snd_pcm_indirect *rec, *cprec;
1152
1153 rec = &rme32->playback_pcm;
1154 cprec = &rme32->capture_pcm;
1155 spin_lock(&rme32->lock);
1156 rec->hw_queue_size = RME32_BUFFER_SIZE;
1157 if (rme32->running & (1 << SNDRV_PCM_STREAM_CAPTURE))
1158 rec->hw_queue_size -= cprec->hw_ready;
1159 spin_unlock(&rme32->lock);
1160 snd_pcm_indirect_playback_transfer(substream, rec,
1161 snd_rme32_pb_trans_copy);
1162 return 0;
1163}
1164
1165static void snd_rme32_cp_trans_copy(struct snd_pcm_substream *substream,
1166 struct snd_pcm_indirect *rec, size_t bytes)
1167{
1168 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1169 memcpy_fromio(substream->runtime->dma_area + rec->sw_data,
1170 rme32->iobase + RME32_IO_DATA_BUFFER + rec->hw_data,
1171 bytes);
1172}
1173
1174static int snd_rme32_capture_fd_ack(struct snd_pcm_substream *substream)
1175{
1176 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1177 snd_pcm_indirect_capture_transfer(substream, &rme32->capture_pcm,
1178 snd_rme32_cp_trans_copy);
1179 return 0;
1180}
1181
1182static snd_pcm_uframes_t
1183snd_rme32_playback_fd_pointer(struct snd_pcm_substream *substream)
1184{
1185 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1186 return snd_pcm_indirect_playback_pointer(substream, &rme32->playback_pcm,
1187 snd_rme32_pcm_byteptr(rme32));
1188}
1189
1190static snd_pcm_uframes_t
1191snd_rme32_capture_fd_pointer(struct snd_pcm_substream *substream)
1192{
1193 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1194 return snd_pcm_indirect_capture_pointer(substream, &rme32->capture_pcm,
1195 snd_rme32_pcm_byteptr(rme32));
1196}
1197
1198/* for halfduplex mode */
1199static struct snd_pcm_ops snd_rme32_playback_spdif_ops = {
1200 .open = snd_rme32_playback_spdif_open,
1201 .close = snd_rme32_playback_close,
1202 .ioctl = snd_pcm_lib_ioctl,
1203 .hw_params = snd_rme32_playback_hw_params,
1204 .hw_free = snd_rme32_pcm_hw_free,
1205 .prepare = snd_rme32_playback_prepare,
1206 .trigger = snd_rme32_pcm_trigger,
1207 .pointer = snd_rme32_playback_pointer,
1208 .copy = snd_rme32_playback_copy,
1209 .silence = snd_rme32_playback_silence,
1210 .mmap = snd_pcm_lib_mmap_iomem,
1211};
1212
1213static struct snd_pcm_ops snd_rme32_capture_spdif_ops = {
1214 .open = snd_rme32_capture_spdif_open,
1215 .close = snd_rme32_capture_close,
1216 .ioctl = snd_pcm_lib_ioctl,
1217 .hw_params = snd_rme32_capture_hw_params,
1218 .hw_free = snd_rme32_pcm_hw_free,
1219 .prepare = snd_rme32_capture_prepare,
1220 .trigger = snd_rme32_pcm_trigger,
1221 .pointer = snd_rme32_capture_pointer,
1222 .copy = snd_rme32_capture_copy,
1223 .mmap = snd_pcm_lib_mmap_iomem,
1224};
1225
1226static struct snd_pcm_ops snd_rme32_playback_adat_ops = {
1227 .open = snd_rme32_playback_adat_open,
1228 .close = snd_rme32_playback_close,
1229 .ioctl = snd_pcm_lib_ioctl,
1230 .hw_params = snd_rme32_playback_hw_params,
1231 .prepare = snd_rme32_playback_prepare,
1232 .trigger = snd_rme32_pcm_trigger,
1233 .pointer = snd_rme32_playback_pointer,
1234 .copy = snd_rme32_playback_copy,
1235 .silence = snd_rme32_playback_silence,
1236 .mmap = snd_pcm_lib_mmap_iomem,
1237};
1238
1239static struct snd_pcm_ops snd_rme32_capture_adat_ops = {
1240 .open = snd_rme32_capture_adat_open,
1241 .close = snd_rme32_capture_close,
1242 .ioctl = snd_pcm_lib_ioctl,
1243 .hw_params = snd_rme32_capture_hw_params,
1244 .prepare = snd_rme32_capture_prepare,
1245 .trigger = snd_rme32_pcm_trigger,
1246 .pointer = snd_rme32_capture_pointer,
1247 .copy = snd_rme32_capture_copy,
1248 .mmap = snd_pcm_lib_mmap_iomem,
1249};
1250
1251/* for fullduplex mode */
1252static struct snd_pcm_ops snd_rme32_playback_spdif_fd_ops = {
1253 .open = snd_rme32_playback_spdif_open,
1254 .close = snd_rme32_playback_close,
1255 .ioctl = snd_pcm_lib_ioctl,
1256 .hw_params = snd_rme32_playback_hw_params,
1257 .hw_free = snd_rme32_pcm_hw_free,
1258 .prepare = snd_rme32_playback_prepare,
1259 .trigger = snd_rme32_pcm_trigger,
1260 .pointer = snd_rme32_playback_fd_pointer,
1261 .ack = snd_rme32_playback_fd_ack,
1262};
1263
1264static struct snd_pcm_ops snd_rme32_capture_spdif_fd_ops = {
1265 .open = snd_rme32_capture_spdif_open,
1266 .close = snd_rme32_capture_close,
1267 .ioctl = snd_pcm_lib_ioctl,
1268 .hw_params = snd_rme32_capture_hw_params,
1269 .hw_free = snd_rme32_pcm_hw_free,
1270 .prepare = snd_rme32_capture_prepare,
1271 .trigger = snd_rme32_pcm_trigger,
1272 .pointer = snd_rme32_capture_fd_pointer,
1273 .ack = snd_rme32_capture_fd_ack,
1274};
1275
1276static struct snd_pcm_ops snd_rme32_playback_adat_fd_ops = {
1277 .open = snd_rme32_playback_adat_open,
1278 .close = snd_rme32_playback_close,
1279 .ioctl = snd_pcm_lib_ioctl,
1280 .hw_params = snd_rme32_playback_hw_params,
1281 .prepare = snd_rme32_playback_prepare,
1282 .trigger = snd_rme32_pcm_trigger,
1283 .pointer = snd_rme32_playback_fd_pointer,
1284 .ack = snd_rme32_playback_fd_ack,
1285};
1286
1287static struct snd_pcm_ops snd_rme32_capture_adat_fd_ops = {
1288 .open = snd_rme32_capture_adat_open,
1289 .close = snd_rme32_capture_close,
1290 .ioctl = snd_pcm_lib_ioctl,
1291 .hw_params = snd_rme32_capture_hw_params,
1292 .prepare = snd_rme32_capture_prepare,
1293 .trigger = snd_rme32_pcm_trigger,
1294 .pointer = snd_rme32_capture_fd_pointer,
1295 .ack = snd_rme32_capture_fd_ack,
1296};
1297
1298static void snd_rme32_free(void *private_data)
1299{
1300 struct rme32 *rme32 = (struct rme32 *) private_data;
1301
1302 if (rme32 == NULL) {
1303 return;
1304 }
1305 if (rme32->irq >= 0) {
1306 snd_rme32_pcm_stop(rme32, 0);
1307 free_irq(rme32->irq, (void *) rme32);
1308 rme32->irq = -1;
1309 }
1310 if (rme32->iobase) {
1311 iounmap(rme32->iobase);
1312 rme32->iobase = NULL;
1313 }
1314 if (rme32->port) {
1315 pci_release_regions(rme32->pci);
1316 rme32->port = 0;
1317 }
1318 pci_disable_device(rme32->pci);
1319}
1320
1321static void snd_rme32_free_spdif_pcm(struct snd_pcm *pcm)
1322{
1323 struct rme32 *rme32 = (struct rme32 *) pcm->private_data;
1324 rme32->spdif_pcm = NULL;
1325}
1326
1327static void
1328snd_rme32_free_adat_pcm(struct snd_pcm *pcm)
1329{
1330 struct rme32 *rme32 = (struct rme32 *) pcm->private_data;
1331 rme32->adat_pcm = NULL;
1332}
1333
1334static int snd_rme32_create(struct rme32 *rme32)
1335{
1336 struct pci_dev *pci = rme32->pci;
1337 int err;
1338
1339 rme32->irq = -1;
1340 spin_lock_init(&rme32->lock);
1341
1342 if ((err = pci_enable_device(pci)) < 0)
1343 return err;
1344
1345 if ((err = pci_request_regions(pci, "RME32")) < 0)
1346 return err;
1347 rme32->port = pci_resource_start(rme32->pci, 0);
1348
1349 rme32->iobase = ioremap_nocache(rme32->port, RME32_IO_SIZE);
1350 if (!rme32->iobase) {
1351 dev_err(rme32->card->dev,
1352 "unable to remap memory region 0x%lx-0x%lx\n",
1353 rme32->port, rme32->port + RME32_IO_SIZE - 1);
1354 return -ENOMEM;
1355 }
1356
1357 if (request_irq(pci->irq, snd_rme32_interrupt, IRQF_SHARED,
1358 KBUILD_MODNAME, rme32)) {
1359 dev_err(rme32->card->dev, "unable to grab IRQ %d\n", pci->irq);
1360 return -EBUSY;
1361 }
1362 rme32->irq = pci->irq;
1363
1364 /* read the card's revision number */
1365 pci_read_config_byte(pci, 8, &rme32->rev);
1366
1367 /* set up ALSA pcm device for S/PDIF */
1368 if ((err = snd_pcm_new(rme32->card, "Digi32 IEC958", 0, 1, 1, &rme32->spdif_pcm)) < 0) {
1369 return err;
1370 }
1371 rme32->spdif_pcm->private_data = rme32;
1372 rme32->spdif_pcm->private_free = snd_rme32_free_spdif_pcm;
1373 strcpy(rme32->spdif_pcm->name, "Digi32 IEC958");
1374 if (rme32->fullduplex_mode) {
1375 snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK,
1376 &snd_rme32_playback_spdif_fd_ops);
1377 snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE,
1378 &snd_rme32_capture_spdif_fd_ops);
1379 snd_pcm_lib_preallocate_pages_for_all(rme32->spdif_pcm, SNDRV_DMA_TYPE_CONTINUOUS,
1380 snd_dma_continuous_data(GFP_KERNEL),
1381 0, RME32_MID_BUFFER_SIZE);
1382 rme32->spdif_pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
1383 } else {
1384 snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK,
1385 &snd_rme32_playback_spdif_ops);
1386 snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE,
1387 &snd_rme32_capture_spdif_ops);
1388 rme32->spdif_pcm->info_flags = SNDRV_PCM_INFO_HALF_DUPLEX;
1389 }
1390
1391 /* set up ALSA pcm device for ADAT */
1392 if ((pci->device == PCI_DEVICE_ID_RME_DIGI32) ||
1393 (pci->device == PCI_DEVICE_ID_RME_DIGI32_PRO)) {
1394 /* ADAT is not available on DIGI32 and DIGI32 Pro */
1395 rme32->adat_pcm = NULL;
1396 }
1397 else {
1398 if ((err = snd_pcm_new(rme32->card, "Digi32 ADAT", 1,
1399 1, 1, &rme32->adat_pcm)) < 0)
1400 {
1401 return err;
1402 }
1403 rme32->adat_pcm->private_data = rme32;
1404 rme32->adat_pcm->private_free = snd_rme32_free_adat_pcm;
1405 strcpy(rme32->adat_pcm->name, "Digi32 ADAT");
1406 if (rme32->fullduplex_mode) {
1407 snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK,
1408 &snd_rme32_playback_adat_fd_ops);
1409 snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_CAPTURE,
1410 &snd_rme32_capture_adat_fd_ops);
1411 snd_pcm_lib_preallocate_pages_for_all(rme32->adat_pcm, SNDRV_DMA_TYPE_CONTINUOUS,
1412 snd_dma_continuous_data(GFP_KERNEL),
1413 0, RME32_MID_BUFFER_SIZE);
1414 rme32->adat_pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
1415 } else {
1416 snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK,
1417 &snd_rme32_playback_adat_ops);
1418 snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_CAPTURE,
1419 &snd_rme32_capture_adat_ops);
1420 rme32->adat_pcm->info_flags = SNDRV_PCM_INFO_HALF_DUPLEX;
1421 }
1422 }
1423
1424
1425 rme32->playback_periodsize = 0;
1426 rme32->capture_periodsize = 0;
1427
1428 /* make sure playback/capture is stopped, if by some reason active */
1429 snd_rme32_pcm_stop(rme32, 0);
1430
1431 /* reset DAC */
1432 snd_rme32_reset_dac(rme32);
1433
1434 /* reset buffer pointer */
1435 writel(0, rme32->iobase + RME32_IO_RESET_POS);
1436
1437 /* set default values in registers */
1438 rme32->wcreg = RME32_WCR_SEL | /* normal playback */
1439 RME32_WCR_INP_0 | /* input select */
1440 RME32_WCR_MUTE; /* muting on */
1441 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
1442
1443
1444 /* init switch interface */
1445 if ((err = snd_rme32_create_switches(rme32->card, rme32)) < 0) {
1446 return err;
1447 }
1448
1449 /* init proc interface */
1450 snd_rme32_proc_init(rme32);
1451
1452 rme32->capture_substream = NULL;
1453 rme32->playback_substream = NULL;
1454
1455 return 0;
1456}
1457
1458/*
1459 * proc interface
1460 */
1461
1462static void
1463snd_rme32_proc_read(struct snd_info_entry * entry, struct snd_info_buffer *buffer)
1464{
1465 int n;
1466 struct rme32 *rme32 = (struct rme32 *) entry->private_data;
1467
1468 rme32->rcreg = readl(rme32->iobase + RME32_IO_CONTROL_REGISTER);
1469
1470 snd_iprintf(buffer, rme32->card->longname);
1471 snd_iprintf(buffer, " (index #%d)\n", rme32->card->number + 1);
1472
1473 snd_iprintf(buffer, "\nGeneral settings\n");
1474 if (rme32->fullduplex_mode)
1475 snd_iprintf(buffer, " Full-duplex mode\n");
1476 else
1477 snd_iprintf(buffer, " Half-duplex mode\n");
1478 if (RME32_PRO_WITH_8414(rme32)) {
1479 snd_iprintf(buffer, " receiver: CS8414\n");
1480 } else {
1481 snd_iprintf(buffer, " receiver: CS8412\n");
1482 }
1483 if (rme32->wcreg & RME32_WCR_MODE24) {
1484 snd_iprintf(buffer, " format: 24 bit");
1485 } else {
1486 snd_iprintf(buffer, " format: 16 bit");
1487 }
1488 if (rme32->wcreg & RME32_WCR_MONO) {
1489 snd_iprintf(buffer, ", Mono\n");
1490 } else {
1491 snd_iprintf(buffer, ", Stereo\n");
1492 }
1493
1494 snd_iprintf(buffer, "\nInput settings\n");
1495 switch (snd_rme32_getinputtype(rme32)) {
1496 case RME32_INPUT_OPTICAL:
1497 snd_iprintf(buffer, " input: optical");
1498 break;
1499 case RME32_INPUT_COAXIAL:
1500 snd_iprintf(buffer, " input: coaxial");
1501 break;
1502 case RME32_INPUT_INTERNAL:
1503 snd_iprintf(buffer, " input: internal");
1504 break;
1505 case RME32_INPUT_XLR:
1506 snd_iprintf(buffer, " input: XLR");
1507 break;
1508 }
1509 if (snd_rme32_capture_getrate(rme32, &n) < 0) {
1510 snd_iprintf(buffer, "\n sample rate: no valid signal\n");
1511 } else {
1512 if (n) {
1513 snd_iprintf(buffer, " (8 channels)\n");
1514 } else {
1515 snd_iprintf(buffer, " (2 channels)\n");
1516 }
1517 snd_iprintf(buffer, " sample rate: %d Hz\n",
1518 snd_rme32_capture_getrate(rme32, &n));
1519 }
1520
1521 snd_iprintf(buffer, "\nOutput settings\n");
1522 if (rme32->wcreg & RME32_WCR_SEL) {
1523 snd_iprintf(buffer, " output signal: normal playback");
1524 } else {
1525 snd_iprintf(buffer, " output signal: same as input");
1526 }
1527 if (rme32->wcreg & RME32_WCR_MUTE) {
1528 snd_iprintf(buffer, " (muted)\n");
1529 } else {
1530 snd_iprintf(buffer, "\n");
1531 }
1532
1533 /* master output frequency */
1534 if (!
1535 ((!(rme32->wcreg & RME32_WCR_FREQ_0))
1536 && (!(rme32->wcreg & RME32_WCR_FREQ_1)))) {
1537 snd_iprintf(buffer, " sample rate: %d Hz\n",
1538 snd_rme32_playback_getrate(rme32));
1539 }
1540 if (rme32->rcreg & RME32_RCR_KMODE) {
1541 snd_iprintf(buffer, " sample clock source: AutoSync\n");
1542 } else {
1543 snd_iprintf(buffer, " sample clock source: Internal\n");
1544 }
1545 if (rme32->wcreg & RME32_WCR_PRO) {
1546 snd_iprintf(buffer, " format: AES/EBU (professional)\n");
1547 } else {
1548 snd_iprintf(buffer, " format: IEC958 (consumer)\n");
1549 }
1550 if (rme32->wcreg & RME32_WCR_EMP) {
1551 snd_iprintf(buffer, " emphasis: on\n");
1552 } else {
1553 snd_iprintf(buffer, " emphasis: off\n");
1554 }
1555}
1556
1557static void snd_rme32_proc_init(struct rme32 *rme32)
1558{
1559 struct snd_info_entry *entry;
1560
1561 if (! snd_card_proc_new(rme32->card, "rme32", &entry))
1562 snd_info_set_text_ops(entry, rme32, snd_rme32_proc_read);
1563}
1564
1565/*
1566 * control interface
1567 */
1568
1569#define snd_rme32_info_loopback_control snd_ctl_boolean_mono_info
1570
1571static int
1572snd_rme32_get_loopback_control(struct snd_kcontrol *kcontrol,
1573 struct snd_ctl_elem_value *ucontrol)
1574{
1575 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1576
1577 spin_lock_irq(&rme32->lock);
1578 ucontrol->value.integer.value[0] =
1579 rme32->wcreg & RME32_WCR_SEL ? 0 : 1;
1580 spin_unlock_irq(&rme32->lock);
1581 return 0;
1582}
1583static int
1584snd_rme32_put_loopback_control(struct snd_kcontrol *kcontrol,
1585 struct snd_ctl_elem_value *ucontrol)
1586{
1587 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1588 unsigned int val;
1589 int change;
1590
1591 val = ucontrol->value.integer.value[0] ? 0 : RME32_WCR_SEL;
1592 spin_lock_irq(&rme32->lock);
1593 val = (rme32->wcreg & ~RME32_WCR_SEL) | val;
1594 change = val != rme32->wcreg;
1595 if (ucontrol->value.integer.value[0])
1596 val &= ~RME32_WCR_MUTE;
1597 else
1598 val |= RME32_WCR_MUTE;
1599 rme32->wcreg = val;
1600 writel(val, rme32->iobase + RME32_IO_CONTROL_REGISTER);
1601 spin_unlock_irq(&rme32->lock);
1602 return change;
1603}
1604
1605static int
1606snd_rme32_info_inputtype_control(struct snd_kcontrol *kcontrol,
1607 struct snd_ctl_elem_info *uinfo)
1608{
1609 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1610 static const char * const texts[4] = {
1611 "Optical", "Coaxial", "Internal", "XLR"
1612 };
1613 int num_items;
1614
1615 switch (rme32->pci->device) {
1616 case PCI_DEVICE_ID_RME_DIGI32:
1617 case PCI_DEVICE_ID_RME_DIGI32_8:
1618 num_items = 3;
1619 break;
1620 case PCI_DEVICE_ID_RME_DIGI32_PRO:
1621 num_items = 4;
1622 break;
1623 default:
1624 snd_BUG();
1625 return -EINVAL;
1626 }
1627 return snd_ctl_enum_info(uinfo, 1, num_items, texts);
1628}
1629static int
1630snd_rme32_get_inputtype_control(struct snd_kcontrol *kcontrol,
1631 struct snd_ctl_elem_value *ucontrol)
1632{
1633 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1634 unsigned int items = 3;
1635
1636 spin_lock_irq(&rme32->lock);
1637 ucontrol->value.enumerated.item[0] = snd_rme32_getinputtype(rme32);
1638
1639 switch (rme32->pci->device) {
1640 case PCI_DEVICE_ID_RME_DIGI32:
1641 case PCI_DEVICE_ID_RME_DIGI32_8:
1642 items = 3;
1643 break;
1644 case PCI_DEVICE_ID_RME_DIGI32_PRO:
1645 items = 4;
1646 break;
1647 default:
1648 snd_BUG();
1649 break;
1650 }
1651 if (ucontrol->value.enumerated.item[0] >= items) {
1652 ucontrol->value.enumerated.item[0] = items - 1;
1653 }
1654
1655 spin_unlock_irq(&rme32->lock);
1656 return 0;
1657}
1658static int
1659snd_rme32_put_inputtype_control(struct snd_kcontrol *kcontrol,
1660 struct snd_ctl_elem_value *ucontrol)
1661{
1662 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1663 unsigned int val;
1664 int change, items = 3;
1665
1666 switch (rme32->pci->device) {
1667 case PCI_DEVICE_ID_RME_DIGI32:
1668 case PCI_DEVICE_ID_RME_DIGI32_8:
1669 items = 3;
1670 break;
1671 case PCI_DEVICE_ID_RME_DIGI32_PRO:
1672 items = 4;
1673 break;
1674 default:
1675 snd_BUG();
1676 break;
1677 }
1678 val = ucontrol->value.enumerated.item[0] % items;
1679
1680 spin_lock_irq(&rme32->lock);
1681 change = val != (unsigned int)snd_rme32_getinputtype(rme32);
1682 snd_rme32_setinputtype(rme32, val);
1683 spin_unlock_irq(&rme32->lock);
1684 return change;
1685}
1686
1687static int
1688snd_rme32_info_clockmode_control(struct snd_kcontrol *kcontrol,
1689 struct snd_ctl_elem_info *uinfo)
1690{
1691 static const char * const texts[4] = { "AutoSync",
1692 "Internal 32.0kHz",
1693 "Internal 44.1kHz",
1694 "Internal 48.0kHz" };
1695
1696 return snd_ctl_enum_info(uinfo, 1, 4, texts);
1697}
1698static int
1699snd_rme32_get_clockmode_control(struct snd_kcontrol *kcontrol,
1700 struct snd_ctl_elem_value *ucontrol)
1701{
1702 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1703
1704 spin_lock_irq(&rme32->lock);
1705 ucontrol->value.enumerated.item[0] = snd_rme32_getclockmode(rme32);
1706 spin_unlock_irq(&rme32->lock);
1707 return 0;
1708}
1709static int
1710snd_rme32_put_clockmode_control(struct snd_kcontrol *kcontrol,
1711 struct snd_ctl_elem_value *ucontrol)
1712{
1713 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1714 unsigned int val;
1715 int change;
1716
1717 val = ucontrol->value.enumerated.item[0] % 3;
1718 spin_lock_irq(&rme32->lock);
1719 change = val != (unsigned int)snd_rme32_getclockmode(rme32);
1720 snd_rme32_setclockmode(rme32, val);
1721 spin_unlock_irq(&rme32->lock);
1722 return change;
1723}
1724
1725static u32 snd_rme32_convert_from_aes(struct snd_aes_iec958 * aes)
1726{
1727 u32 val = 0;
1728 val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? RME32_WCR_PRO : 0;
1729 if (val & RME32_WCR_PRO)
1730 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? RME32_WCR_EMP : 0;
1731 else
1732 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? RME32_WCR_EMP : 0;
1733 return val;
1734}
1735
1736static void snd_rme32_convert_to_aes(struct snd_aes_iec958 * aes, u32 val)
1737{
1738 aes->status[0] = ((val & RME32_WCR_PRO) ? IEC958_AES0_PROFESSIONAL : 0);
1739 if (val & RME32_WCR_PRO)
1740 aes->status[0] |= (val & RME32_WCR_EMP) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
1741 else
1742 aes->status[0] |= (val & RME32_WCR_EMP) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
1743}
1744
1745static int snd_rme32_control_spdif_info(struct snd_kcontrol *kcontrol,
1746 struct snd_ctl_elem_info *uinfo)
1747{
1748 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1749 uinfo->count = 1;
1750 return 0;
1751}
1752
1753static int snd_rme32_control_spdif_get(struct snd_kcontrol *kcontrol,
1754 struct snd_ctl_elem_value *ucontrol)
1755{
1756 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1757
1758 snd_rme32_convert_to_aes(&ucontrol->value.iec958,
1759 rme32->wcreg_spdif);
1760 return 0;
1761}
1762
1763static int snd_rme32_control_spdif_put(struct snd_kcontrol *kcontrol,
1764 struct snd_ctl_elem_value *ucontrol)
1765{
1766 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1767 int change;
1768 u32 val;
1769
1770 val = snd_rme32_convert_from_aes(&ucontrol->value.iec958);
1771 spin_lock_irq(&rme32->lock);
1772 change = val != rme32->wcreg_spdif;
1773 rme32->wcreg_spdif = val;
1774 spin_unlock_irq(&rme32->lock);
1775 return change;
1776}
1777
1778static int snd_rme32_control_spdif_stream_info(struct snd_kcontrol *kcontrol,
1779 struct snd_ctl_elem_info *uinfo)
1780{
1781 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1782 uinfo->count = 1;
1783 return 0;
1784}
1785
1786static int snd_rme32_control_spdif_stream_get(struct snd_kcontrol *kcontrol,
1787 struct snd_ctl_elem_value *
1788 ucontrol)
1789{
1790 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1791
1792 snd_rme32_convert_to_aes(&ucontrol->value.iec958,
1793 rme32->wcreg_spdif_stream);
1794 return 0;
1795}
1796
1797static int snd_rme32_control_spdif_stream_put(struct snd_kcontrol *kcontrol,
1798 struct snd_ctl_elem_value *
1799 ucontrol)
1800{
1801 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1802 int change;
1803 u32 val;
1804
1805 val = snd_rme32_convert_from_aes(&ucontrol->value.iec958);
1806 spin_lock_irq(&rme32->lock);
1807 change = val != rme32->wcreg_spdif_stream;
1808 rme32->wcreg_spdif_stream = val;
1809 rme32->wcreg &= ~(RME32_WCR_PRO | RME32_WCR_EMP);
1810 rme32->wcreg |= val;
1811 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
1812 spin_unlock_irq(&rme32->lock);
1813 return change;
1814}
1815
1816static int snd_rme32_control_spdif_mask_info(struct snd_kcontrol *kcontrol,
1817 struct snd_ctl_elem_info *uinfo)
1818{
1819 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1820 uinfo->count = 1;
1821 return 0;
1822}
1823
1824static int snd_rme32_control_spdif_mask_get(struct snd_kcontrol *kcontrol,
1825 struct snd_ctl_elem_value *
1826 ucontrol)
1827{
1828 ucontrol->value.iec958.status[0] = kcontrol->private_value;
1829 return 0;
1830}
1831
1832static struct snd_kcontrol_new snd_rme32_controls[] = {
1833 {
1834 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1835 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
1836 .info = snd_rme32_control_spdif_info,
1837 .get = snd_rme32_control_spdif_get,
1838 .put = snd_rme32_control_spdif_put
1839 },
1840 {
1841 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
1842 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1843 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, PCM_STREAM),
1844 .info = snd_rme32_control_spdif_stream_info,
1845 .get = snd_rme32_control_spdif_stream_get,
1846 .put = snd_rme32_control_spdif_stream_put
1847 },
1848 {
1849 .access = SNDRV_CTL_ELEM_ACCESS_READ,
1850 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1851 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, CON_MASK),
1852 .info = snd_rme32_control_spdif_mask_info,
1853 .get = snd_rme32_control_spdif_mask_get,
1854 .private_value = IEC958_AES0_PROFESSIONAL | IEC958_AES0_CON_EMPHASIS
1855 },
1856 {
1857 .access = SNDRV_CTL_ELEM_ACCESS_READ,
1858 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1859 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, PRO_MASK),
1860 .info = snd_rme32_control_spdif_mask_info,
1861 .get = snd_rme32_control_spdif_mask_get,
1862 .private_value = IEC958_AES0_PROFESSIONAL | IEC958_AES0_PRO_EMPHASIS
1863 },
1864 {
1865 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1866 .name = "Input Connector",
1867 .info = snd_rme32_info_inputtype_control,
1868 .get = snd_rme32_get_inputtype_control,
1869 .put = snd_rme32_put_inputtype_control
1870 },
1871 {
1872 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1873 .name = "Loopback Input",
1874 .info = snd_rme32_info_loopback_control,
1875 .get = snd_rme32_get_loopback_control,
1876 .put = snd_rme32_put_loopback_control
1877 },
1878 {
1879 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1880 .name = "Sample Clock Source",
1881 .info = snd_rme32_info_clockmode_control,
1882 .get = snd_rme32_get_clockmode_control,
1883 .put = snd_rme32_put_clockmode_control
1884 }
1885};
1886
1887static int snd_rme32_create_switches(struct snd_card *card, struct rme32 * rme32)
1888{
1889 int idx, err;
1890 struct snd_kcontrol *kctl;
1891
1892 for (idx = 0; idx < (int)ARRAY_SIZE(snd_rme32_controls); idx++) {
1893 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_rme32_controls[idx], rme32))) < 0)
1894 return err;
1895 if (idx == 1) /* IEC958 (S/PDIF) Stream */
1896 rme32->spdif_ctl = kctl;
1897 }
1898
1899 return 0;
1900}
1901
1902/*
1903 * Card initialisation
1904 */
1905
1906static void snd_rme32_card_free(struct snd_card *card)
1907{
1908 snd_rme32_free(card->private_data);
1909}
1910
1911static int
1912snd_rme32_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
1913{
1914 static int dev;
1915 struct rme32 *rme32;
1916 struct snd_card *card;
1917 int err;
1918
1919 if (dev >= SNDRV_CARDS) {
1920 return -ENODEV;
1921 }
1922 if (!enable[dev]) {
1923 dev++;
1924 return -ENOENT;
1925 }
1926
1927 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
1928 sizeof(struct rme32), &card);
1929 if (err < 0)
1930 return err;
1931 card->private_free = snd_rme32_card_free;
1932 rme32 = (struct rme32 *) card->private_data;
1933 rme32->card = card;
1934 rme32->pci = pci;
1935 if (fullduplex[dev])
1936 rme32->fullduplex_mode = 1;
1937 if ((err = snd_rme32_create(rme32)) < 0) {
1938 snd_card_free(card);
1939 return err;
1940 }
1941
1942 strcpy(card->driver, "Digi32");
1943 switch (rme32->pci->device) {
1944 case PCI_DEVICE_ID_RME_DIGI32:
1945 strcpy(card->shortname, "RME Digi32");
1946 break;
1947 case PCI_DEVICE_ID_RME_DIGI32_8:
1948 strcpy(card->shortname, "RME Digi32/8");
1949 break;
1950 case PCI_DEVICE_ID_RME_DIGI32_PRO:
1951 strcpy(card->shortname, "RME Digi32 PRO");
1952 break;
1953 }
1954 sprintf(card->longname, "%s (Rev. %d) at 0x%lx, irq %d",
1955 card->shortname, rme32->rev, rme32->port, rme32->irq);
1956
1957 if ((err = snd_card_register(card)) < 0) {
1958 snd_card_free(card);
1959 return err;
1960 }
1961 pci_set_drvdata(pci, card);
1962 dev++;
1963 return 0;
1964}
1965
1966static void snd_rme32_remove(struct pci_dev *pci)
1967{
1968 snd_card_free(pci_get_drvdata(pci));
1969}
1970
1971static struct pci_driver rme32_driver = {
1972 .name = KBUILD_MODNAME,
1973 .id_table = snd_rme32_ids,
1974 .probe = snd_rme32_probe,
1975 .remove = snd_rme32_remove,
1976};
1977
1978module_pci_driver(rme32_driver);