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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Thunderbolt driver - eeprom access
4 *
5 * Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com>
6 * Copyright (C) 2018, Intel Corporation
7 */
8
9#include <linux/crc32.h>
10#include <linux/delay.h>
11#include <linux/property.h>
12#include <linux/slab.h>
13#include "tb.h"
14
15/**
16 * tb_eeprom_ctl_write() - write control word
17 */
18static int tb_eeprom_ctl_write(struct tb_switch *sw, struct tb_eeprom_ctl *ctl)
19{
20 return tb_sw_write(sw, ctl, TB_CFG_SWITCH, sw->cap_plug_events + 4, 1);
21}
22
23/**
24 * tb_eeprom_ctl_write() - read control word
25 */
26static int tb_eeprom_ctl_read(struct tb_switch *sw, struct tb_eeprom_ctl *ctl)
27{
28 return tb_sw_read(sw, ctl, TB_CFG_SWITCH, sw->cap_plug_events + 4, 1);
29}
30
31enum tb_eeprom_transfer {
32 TB_EEPROM_IN,
33 TB_EEPROM_OUT,
34};
35
36/**
37 * tb_eeprom_active - enable rom access
38 *
39 * WARNING: Always disable access after usage. Otherwise the controller will
40 * fail to reprobe.
41 */
42static int tb_eeprom_active(struct tb_switch *sw, bool enable)
43{
44 struct tb_eeprom_ctl ctl;
45 int res = tb_eeprom_ctl_read(sw, &ctl);
46 if (res)
47 return res;
48 if (enable) {
49 ctl.access_high = 1;
50 res = tb_eeprom_ctl_write(sw, &ctl);
51 if (res)
52 return res;
53 ctl.access_low = 0;
54 return tb_eeprom_ctl_write(sw, &ctl);
55 } else {
56 ctl.access_low = 1;
57 res = tb_eeprom_ctl_write(sw, &ctl);
58 if (res)
59 return res;
60 ctl.access_high = 0;
61 return tb_eeprom_ctl_write(sw, &ctl);
62 }
63}
64
65/**
66 * tb_eeprom_transfer - transfer one bit
67 *
68 * If TB_EEPROM_IN is passed, then the bit can be retrieved from ctl->data_in.
69 * If TB_EEPROM_OUT is passed, then ctl->data_out will be written.
70 */
71static int tb_eeprom_transfer(struct tb_switch *sw, struct tb_eeprom_ctl *ctl,
72 enum tb_eeprom_transfer direction)
73{
74 int res;
75 if (direction == TB_EEPROM_OUT) {
76 res = tb_eeprom_ctl_write(sw, ctl);
77 if (res)
78 return res;
79 }
80 ctl->clock = 1;
81 res = tb_eeprom_ctl_write(sw, ctl);
82 if (res)
83 return res;
84 if (direction == TB_EEPROM_IN) {
85 res = tb_eeprom_ctl_read(sw, ctl);
86 if (res)
87 return res;
88 }
89 ctl->clock = 0;
90 return tb_eeprom_ctl_write(sw, ctl);
91}
92
93/**
94 * tb_eeprom_out - write one byte to the bus
95 */
96static int tb_eeprom_out(struct tb_switch *sw, u8 val)
97{
98 struct tb_eeprom_ctl ctl;
99 int i;
100 int res = tb_eeprom_ctl_read(sw, &ctl);
101 if (res)
102 return res;
103 for (i = 0; i < 8; i++) {
104 ctl.data_out = val & 0x80;
105 res = tb_eeprom_transfer(sw, &ctl, TB_EEPROM_OUT);
106 if (res)
107 return res;
108 val <<= 1;
109 }
110 return 0;
111}
112
113/**
114 * tb_eeprom_in - read one byte from the bus
115 */
116static int tb_eeprom_in(struct tb_switch *sw, u8 *val)
117{
118 struct tb_eeprom_ctl ctl;
119 int i;
120 int res = tb_eeprom_ctl_read(sw, &ctl);
121 if (res)
122 return res;
123 *val = 0;
124 for (i = 0; i < 8; i++) {
125 *val <<= 1;
126 res = tb_eeprom_transfer(sw, &ctl, TB_EEPROM_IN);
127 if (res)
128 return res;
129 *val |= ctl.data_in;
130 }
131 return 0;
132}
133
134/**
135 * tb_eeprom_get_drom_offset - get drom offset within eeprom
136 */
137static int tb_eeprom_get_drom_offset(struct tb_switch *sw, u16 *offset)
138{
139 struct tb_cap_plug_events cap;
140 int res;
141
142 if (!sw->cap_plug_events) {
143 tb_sw_warn(sw, "no TB_CAP_PLUG_EVENTS, cannot read eeprom\n");
144 return -ENODEV;
145 }
146 res = tb_sw_read(sw, &cap, TB_CFG_SWITCH, sw->cap_plug_events,
147 sizeof(cap) / 4);
148 if (res)
149 return res;
150
151 if (!cap.eeprom_ctl.present || cap.eeprom_ctl.not_present) {
152 tb_sw_warn(sw, "no NVM\n");
153 return -ENODEV;
154 }
155
156 if (cap.drom_offset > 0xffff) {
157 tb_sw_warn(sw, "drom offset is larger than 0xffff: %#x\n",
158 cap.drom_offset);
159 return -ENXIO;
160 }
161 *offset = cap.drom_offset;
162 return 0;
163}
164
165/**
166 * tb_eeprom_read_n - read count bytes from offset into val
167 */
168static int tb_eeprom_read_n(struct tb_switch *sw, u16 offset, u8 *val,
169 size_t count)
170{
171 u16 drom_offset;
172 int i, res;
173
174 res = tb_eeprom_get_drom_offset(sw, &drom_offset);
175 if (res)
176 return res;
177
178 offset += drom_offset;
179
180 res = tb_eeprom_active(sw, true);
181 if (res)
182 return res;
183 res = tb_eeprom_out(sw, 3);
184 if (res)
185 return res;
186 res = tb_eeprom_out(sw, offset >> 8);
187 if (res)
188 return res;
189 res = tb_eeprom_out(sw, offset);
190 if (res)
191 return res;
192 for (i = 0; i < count; i++) {
193 res = tb_eeprom_in(sw, val + i);
194 if (res)
195 return res;
196 }
197 return tb_eeprom_active(sw, false);
198}
199
200static u8 tb_crc8(u8 *data, int len)
201{
202 int i, j;
203 u8 val = 0xff;
204 for (i = 0; i < len; i++) {
205 val ^= data[i];
206 for (j = 0; j < 8; j++)
207 val = (val << 1) ^ ((val & 0x80) ? 7 : 0);
208 }
209 return val;
210}
211
212static u32 tb_crc32(void *data, size_t len)
213{
214 return ~__crc32c_le(~0, data, len);
215}
216
217#define TB_DROM_DATA_START 13
218struct tb_drom_header {
219 /* BYTE 0 */
220 u8 uid_crc8; /* checksum for uid */
221 /* BYTES 1-8 */
222 u64 uid;
223 /* BYTES 9-12 */
224 u32 data_crc32; /* checksum for data_len bytes starting at byte 13 */
225 /* BYTE 13 */
226 u8 device_rom_revision; /* should be <= 1 */
227 u16 data_len:10;
228 u8 __unknown1:6;
229 /* BYTES 16-21 */
230 u16 vendor_id;
231 u16 model_id;
232 u8 model_rev;
233 u8 eeprom_rev;
234} __packed;
235
236enum tb_drom_entry_type {
237 /* force unsigned to prevent "one-bit signed bitfield" warning */
238 TB_DROM_ENTRY_GENERIC = 0U,
239 TB_DROM_ENTRY_PORT,
240};
241
242struct tb_drom_entry_header {
243 u8 len;
244 u8 index:6;
245 bool port_disabled:1; /* only valid if type is TB_DROM_ENTRY_PORT */
246 enum tb_drom_entry_type type:1;
247} __packed;
248
249struct tb_drom_entry_generic {
250 struct tb_drom_entry_header header;
251 u8 data[];
252} __packed;
253
254struct tb_drom_entry_port {
255 /* BYTES 0-1 */
256 struct tb_drom_entry_header header;
257 /* BYTE 2 */
258 u8 dual_link_port_rid:4;
259 u8 link_nr:1;
260 u8 unknown1:2;
261 bool has_dual_link_port:1;
262
263 /* BYTE 3 */
264 u8 dual_link_port_nr:6;
265 u8 unknown2:2;
266
267 /* BYTES 4 - 5 TODO decode */
268 u8 micro2:4;
269 u8 micro1:4;
270 u8 micro3;
271
272 /* BYTES 6-7, TODO: verify (find hardware that has these set) */
273 u8 peer_port_rid:4;
274 u8 unknown3:3;
275 bool has_peer_port:1;
276 u8 peer_port_nr:6;
277 u8 unknown4:2;
278} __packed;
279
280
281/**
282 * tb_drom_read_uid_only - read uid directly from drom
283 *
284 * Does not use the cached copy in sw->drom. Used during resume to check switch
285 * identity.
286 */
287int tb_drom_read_uid_only(struct tb_switch *sw, u64 *uid)
288{
289 u8 data[9];
290 u8 crc;
291 int res;
292
293 /* read uid */
294 res = tb_eeprom_read_n(sw, 0, data, 9);
295 if (res)
296 return res;
297
298 crc = tb_crc8(data + 1, 8);
299 if (crc != data[0]) {
300 tb_sw_warn(sw, "uid crc8 mismatch (expected: %#x, got: %#x)\n",
301 data[0], crc);
302 return -EIO;
303 }
304
305 *uid = *(u64 *)(data+1);
306 return 0;
307}
308
309static int tb_drom_parse_entry_generic(struct tb_switch *sw,
310 struct tb_drom_entry_header *header)
311{
312 const struct tb_drom_entry_generic *entry =
313 (const struct tb_drom_entry_generic *)header;
314
315 switch (header->index) {
316 case 1:
317 /* Length includes 2 bytes header so remove it before copy */
318 sw->vendor_name = kstrndup(entry->data,
319 header->len - sizeof(*header), GFP_KERNEL);
320 if (!sw->vendor_name)
321 return -ENOMEM;
322 break;
323
324 case 2:
325 sw->device_name = kstrndup(entry->data,
326 header->len - sizeof(*header), GFP_KERNEL);
327 if (!sw->device_name)
328 return -ENOMEM;
329 break;
330 }
331
332 return 0;
333}
334
335static int tb_drom_parse_entry_port(struct tb_switch *sw,
336 struct tb_drom_entry_header *header)
337{
338 struct tb_port *port;
339 int res;
340 enum tb_port_type type;
341
342 /*
343 * Some DROMs list more ports than the controller actually has
344 * so we skip those but allow the parser to continue.
345 */
346 if (header->index > sw->config.max_port_number) {
347 dev_info_once(&sw->dev, "ignoring unnecessary extra entries in DROM\n");
348 return 0;
349 }
350
351 port = &sw->ports[header->index];
352 port->disabled = header->port_disabled;
353 if (port->disabled)
354 return 0;
355
356 res = tb_port_read(port, &type, TB_CFG_PORT, 2, 1);
357 if (res)
358 return res;
359 type &= 0xffffff;
360
361 if (type == TB_TYPE_PORT) {
362 struct tb_drom_entry_port *entry = (void *) header;
363 if (header->len != sizeof(*entry)) {
364 tb_sw_warn(sw,
365 "port entry has size %#x (expected %#zx)\n",
366 header->len, sizeof(struct tb_drom_entry_port));
367 return -EIO;
368 }
369 port->link_nr = entry->link_nr;
370 if (entry->has_dual_link_port)
371 port->dual_link_port =
372 &port->sw->ports[entry->dual_link_port_nr];
373 }
374 return 0;
375}
376
377/**
378 * tb_drom_parse_entries - parse the linked list of drom entries
379 *
380 * Drom must have been copied to sw->drom.
381 */
382static int tb_drom_parse_entries(struct tb_switch *sw)
383{
384 struct tb_drom_header *header = (void *) sw->drom;
385 u16 pos = sizeof(*header);
386 u16 drom_size = header->data_len + TB_DROM_DATA_START;
387 int res;
388
389 while (pos < drom_size) {
390 struct tb_drom_entry_header *entry = (void *) (sw->drom + pos);
391 if (pos + 1 == drom_size || pos + entry->len > drom_size
392 || !entry->len) {
393 tb_sw_warn(sw, "DROM buffer overrun\n");
394 return -EILSEQ;
395 }
396
397 switch (entry->type) {
398 case TB_DROM_ENTRY_GENERIC:
399 res = tb_drom_parse_entry_generic(sw, entry);
400 break;
401 case TB_DROM_ENTRY_PORT:
402 res = tb_drom_parse_entry_port(sw, entry);
403 break;
404 }
405 if (res)
406 return res;
407
408 pos += entry->len;
409 }
410 return 0;
411}
412
413/**
414 * tb_drom_copy_efi - copy drom supplied by EFI to sw->drom if present
415 */
416static int tb_drom_copy_efi(struct tb_switch *sw, u16 *size)
417{
418 struct device *dev = &sw->tb->nhi->pdev->dev;
419 int len, res;
420
421 len = device_property_count_u8(dev, "ThunderboltDROM");
422 if (len < 0 || len < sizeof(struct tb_drom_header))
423 return -EINVAL;
424
425 sw->drom = kmalloc(len, GFP_KERNEL);
426 if (!sw->drom)
427 return -ENOMEM;
428
429 res = device_property_read_u8_array(dev, "ThunderboltDROM", sw->drom,
430 len);
431 if (res)
432 goto err;
433
434 *size = ((struct tb_drom_header *)sw->drom)->data_len +
435 TB_DROM_DATA_START;
436 if (*size > len)
437 goto err;
438
439 return 0;
440
441err:
442 kfree(sw->drom);
443 sw->drom = NULL;
444 return -EINVAL;
445}
446
447static int tb_drom_copy_nvm(struct tb_switch *sw, u16 *size)
448{
449 u32 drom_offset;
450 int ret;
451
452 if (!sw->dma_port)
453 return -ENODEV;
454
455 ret = tb_sw_read(sw, &drom_offset, TB_CFG_SWITCH,
456 sw->cap_plug_events + 12, 1);
457 if (ret)
458 return ret;
459
460 if (!drom_offset)
461 return -ENODEV;
462
463 ret = dma_port_flash_read(sw->dma_port, drom_offset + 14, size,
464 sizeof(*size));
465 if (ret)
466 return ret;
467
468 /* Size includes CRC8 + UID + CRC32 */
469 *size += 1 + 8 + 4;
470 sw->drom = kzalloc(*size, GFP_KERNEL);
471 if (!sw->drom)
472 return -ENOMEM;
473
474 ret = dma_port_flash_read(sw->dma_port, drom_offset, sw->drom, *size);
475 if (ret)
476 goto err_free;
477
478 /*
479 * Read UID from the minimal DROM because the one in NVM is just
480 * a placeholder.
481 */
482 tb_drom_read_uid_only(sw, &sw->uid);
483 return 0;
484
485err_free:
486 kfree(sw->drom);
487 sw->drom = NULL;
488 return ret;
489}
490
491static int usb4_copy_host_drom(struct tb_switch *sw, u16 *size)
492{
493 int ret;
494
495 ret = usb4_switch_drom_read(sw, 14, size, sizeof(*size));
496 if (ret)
497 return ret;
498
499 /* Size includes CRC8 + UID + CRC32 */
500 *size += 1 + 8 + 4;
501 sw->drom = kzalloc(*size, GFP_KERNEL);
502 if (!sw->drom)
503 return -ENOMEM;
504
505 ret = usb4_switch_drom_read(sw, 0, sw->drom, *size);
506 if (ret) {
507 kfree(sw->drom);
508 sw->drom = NULL;
509 }
510
511 return ret;
512}
513
514static int tb_drom_read_n(struct tb_switch *sw, u16 offset, u8 *val,
515 size_t count)
516{
517 if (tb_switch_is_usb4(sw))
518 return usb4_switch_drom_read(sw, offset, val, count);
519 return tb_eeprom_read_n(sw, offset, val, count);
520}
521
522/**
523 * tb_drom_read - copy drom to sw->drom and parse it
524 */
525int tb_drom_read(struct tb_switch *sw)
526{
527 u16 size;
528 u32 crc;
529 struct tb_drom_header *header;
530 int res, retries = 1;
531
532 if (sw->drom)
533 return 0;
534
535 if (tb_route(sw) == 0) {
536 /*
537 * Apple's NHI EFI driver supplies a DROM for the root switch
538 * in a device property. Use it if available.
539 */
540 if (tb_drom_copy_efi(sw, &size) == 0)
541 goto parse;
542
543 /* Non-Apple hardware has the DROM as part of NVM */
544 if (tb_drom_copy_nvm(sw, &size) == 0)
545 goto parse;
546
547 /*
548 * USB4 hosts may support reading DROM through router
549 * operations.
550 */
551 if (tb_switch_is_usb4(sw)) {
552 usb4_switch_read_uid(sw, &sw->uid);
553 if (!usb4_copy_host_drom(sw, &size))
554 goto parse;
555 } else {
556 /*
557 * The root switch contains only a dummy drom
558 * (header only, no entries). Hardcode the
559 * configuration here.
560 */
561 tb_drom_read_uid_only(sw, &sw->uid);
562 }
563
564 return 0;
565 }
566
567 res = tb_drom_read_n(sw, 14, (u8 *) &size, 2);
568 if (res)
569 return res;
570 size &= 0x3ff;
571 size += TB_DROM_DATA_START;
572 tb_sw_dbg(sw, "reading drom (length: %#x)\n", size);
573 if (size < sizeof(*header)) {
574 tb_sw_warn(sw, "drom too small, aborting\n");
575 return -EIO;
576 }
577
578 sw->drom = kzalloc(size, GFP_KERNEL);
579 if (!sw->drom)
580 return -ENOMEM;
581 res = tb_drom_read_n(sw, 0, sw->drom, size);
582 if (res)
583 goto err;
584
585parse:
586 header = (void *) sw->drom;
587
588 if (header->data_len + TB_DROM_DATA_START != size) {
589 tb_sw_warn(sw, "drom size mismatch, aborting\n");
590 goto err;
591 }
592
593 crc = tb_crc8((u8 *) &header->uid, 8);
594 if (crc != header->uid_crc8) {
595 tb_sw_warn(sw,
596 "drom uid crc8 mismatch (expected: %#x, got: %#x), aborting\n",
597 header->uid_crc8, crc);
598 goto err;
599 }
600 if (!sw->uid)
601 sw->uid = header->uid;
602 sw->vendor = header->vendor_id;
603 sw->device = header->model_id;
604 tb_check_quirks(sw);
605
606 crc = tb_crc32(sw->drom + TB_DROM_DATA_START, header->data_len);
607 if (crc != header->data_crc32) {
608 tb_sw_warn(sw,
609 "drom data crc32 mismatch (expected: %#x, got: %#x), continuing\n",
610 header->data_crc32, crc);
611 }
612
613 if (header->device_rom_revision > 2)
614 tb_sw_warn(sw, "drom device_rom_revision %#x unknown\n",
615 header->device_rom_revision);
616
617 res = tb_drom_parse_entries(sw);
618 /* If the DROM parsing fails, wait a moment and retry once */
619 if (res == -EILSEQ && retries--) {
620 tb_sw_warn(sw, "parsing DROM failed, retrying\n");
621 msleep(100);
622 res = tb_drom_read_n(sw, 0, sw->drom, size);
623 if (!res)
624 goto parse;
625 }
626
627 return res;
628err:
629 kfree(sw->drom);
630 sw->drom = NULL;
631 return -EIO;
632
633}
1/*
2 * Thunderbolt Cactus Ridge driver - eeprom access
3 *
4 * Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com>
5 */
6
7#include <linux/crc32.h>
8#include <linux/slab.h>
9#include "tb.h"
10
11/**
12 * tb_eeprom_ctl_write() - write control word
13 */
14static int tb_eeprom_ctl_write(struct tb_switch *sw, struct tb_eeprom_ctl *ctl)
15{
16 return tb_sw_write(sw, ctl, TB_CFG_SWITCH, sw->cap_plug_events + 4, 1);
17}
18
19/**
20 * tb_eeprom_ctl_write() - read control word
21 */
22static int tb_eeprom_ctl_read(struct tb_switch *sw, struct tb_eeprom_ctl *ctl)
23{
24 return tb_sw_read(sw, ctl, TB_CFG_SWITCH, sw->cap_plug_events + 4, 1);
25}
26
27enum tb_eeprom_transfer {
28 TB_EEPROM_IN,
29 TB_EEPROM_OUT,
30};
31
32/**
33 * tb_eeprom_active - enable rom access
34 *
35 * WARNING: Always disable access after usage. Otherwise the controller will
36 * fail to reprobe.
37 */
38static int tb_eeprom_active(struct tb_switch *sw, bool enable)
39{
40 struct tb_eeprom_ctl ctl;
41 int res = tb_eeprom_ctl_read(sw, &ctl);
42 if (res)
43 return res;
44 if (enable) {
45 ctl.access_high = 1;
46 res = tb_eeprom_ctl_write(sw, &ctl);
47 if (res)
48 return res;
49 ctl.access_low = 0;
50 return tb_eeprom_ctl_write(sw, &ctl);
51 } else {
52 ctl.access_low = 1;
53 res = tb_eeprom_ctl_write(sw, &ctl);
54 if (res)
55 return res;
56 ctl.access_high = 0;
57 return tb_eeprom_ctl_write(sw, &ctl);
58 }
59}
60
61/**
62 * tb_eeprom_transfer - transfer one bit
63 *
64 * If TB_EEPROM_IN is passed, then the bit can be retrieved from ctl->data_in.
65 * If TB_EEPROM_OUT is passed, then ctl->data_out will be written.
66 */
67static int tb_eeprom_transfer(struct tb_switch *sw, struct tb_eeprom_ctl *ctl,
68 enum tb_eeprom_transfer direction)
69{
70 int res;
71 if (direction == TB_EEPROM_OUT) {
72 res = tb_eeprom_ctl_write(sw, ctl);
73 if (res)
74 return res;
75 }
76 ctl->clock = 1;
77 res = tb_eeprom_ctl_write(sw, ctl);
78 if (res)
79 return res;
80 if (direction == TB_EEPROM_IN) {
81 res = tb_eeprom_ctl_read(sw, ctl);
82 if (res)
83 return res;
84 }
85 ctl->clock = 0;
86 return tb_eeprom_ctl_write(sw, ctl);
87}
88
89/**
90 * tb_eeprom_out - write one byte to the bus
91 */
92static int tb_eeprom_out(struct tb_switch *sw, u8 val)
93{
94 struct tb_eeprom_ctl ctl;
95 int i;
96 int res = tb_eeprom_ctl_read(sw, &ctl);
97 if (res)
98 return res;
99 for (i = 0; i < 8; i++) {
100 ctl.data_out = val & 0x80;
101 res = tb_eeprom_transfer(sw, &ctl, TB_EEPROM_OUT);
102 if (res)
103 return res;
104 val <<= 1;
105 }
106 return 0;
107}
108
109/**
110 * tb_eeprom_in - read one byte from the bus
111 */
112static int tb_eeprom_in(struct tb_switch *sw, u8 *val)
113{
114 struct tb_eeprom_ctl ctl;
115 int i;
116 int res = tb_eeprom_ctl_read(sw, &ctl);
117 if (res)
118 return res;
119 *val = 0;
120 for (i = 0; i < 8; i++) {
121 *val <<= 1;
122 res = tb_eeprom_transfer(sw, &ctl, TB_EEPROM_IN);
123 if (res)
124 return res;
125 *val |= ctl.data_in;
126 }
127 return 0;
128}
129
130/**
131 * tb_eeprom_read_n - read count bytes from offset into val
132 */
133static int tb_eeprom_read_n(struct tb_switch *sw, u16 offset, u8 *val,
134 size_t count)
135{
136 int i, res;
137 res = tb_eeprom_active(sw, true);
138 if (res)
139 return res;
140 res = tb_eeprom_out(sw, 3);
141 if (res)
142 return res;
143 res = tb_eeprom_out(sw, offset >> 8);
144 if (res)
145 return res;
146 res = tb_eeprom_out(sw, offset);
147 if (res)
148 return res;
149 for (i = 0; i < count; i++) {
150 res = tb_eeprom_in(sw, val + i);
151 if (res)
152 return res;
153 }
154 return tb_eeprom_active(sw, false);
155}
156
157static u8 tb_crc8(u8 *data, int len)
158{
159 int i, j;
160 u8 val = 0xff;
161 for (i = 0; i < len; i++) {
162 val ^= data[i];
163 for (j = 0; j < 8; j++)
164 val = (val << 1) ^ ((val & 0x80) ? 7 : 0);
165 }
166 return val;
167}
168
169static u32 tb_crc32(void *data, size_t len)
170{
171 return ~__crc32c_le(~0, data, len);
172}
173
174#define TB_DROM_DATA_START 13
175struct tb_drom_header {
176 /* BYTE 0 */
177 u8 uid_crc8; /* checksum for uid */
178 /* BYTES 1-8 */
179 u64 uid;
180 /* BYTES 9-12 */
181 u32 data_crc32; /* checksum for data_len bytes starting at byte 13 */
182 /* BYTE 13 */
183 u8 device_rom_revision; /* should be <= 1 */
184 u16 data_len:10;
185 u8 __unknown1:6;
186 /* BYTES 16-21 */
187 u16 vendor_id;
188 u16 model_id;
189 u8 model_rev;
190 u8 eeprom_rev;
191} __packed;
192
193enum tb_drom_entry_type {
194 /* force unsigned to prevent "one-bit signed bitfield" warning */
195 TB_DROM_ENTRY_GENERIC = 0U,
196 TB_DROM_ENTRY_PORT,
197};
198
199struct tb_drom_entry_header {
200 u8 len;
201 u8 index:6;
202 bool port_disabled:1; /* only valid if type is TB_DROM_ENTRY_PORT */
203 enum tb_drom_entry_type type:1;
204} __packed;
205
206struct tb_drom_entry_port {
207 /* BYTES 0-1 */
208 struct tb_drom_entry_header header;
209 /* BYTE 2 */
210 u8 dual_link_port_rid:4;
211 u8 link_nr:1;
212 u8 unknown1:2;
213 bool has_dual_link_port:1;
214
215 /* BYTE 3 */
216 u8 dual_link_port_nr:6;
217 u8 unknown2:2;
218
219 /* BYTES 4 - 5 TODO decode */
220 u8 micro2:4;
221 u8 micro1:4;
222 u8 micro3;
223
224 /* BYTES 5-6, TODO: verify (find hardware that has these set) */
225 u8 peer_port_rid:4;
226 u8 unknown3:3;
227 bool has_peer_port:1;
228 u8 peer_port_nr:6;
229 u8 unknown4:2;
230} __packed;
231
232
233/**
234 * tb_eeprom_get_drom_offset - get drom offset within eeprom
235 */
236static int tb_eeprom_get_drom_offset(struct tb_switch *sw, u16 *offset)
237{
238 struct tb_cap_plug_events cap;
239 int res;
240 if (!sw->cap_plug_events) {
241 tb_sw_warn(sw, "no TB_CAP_PLUG_EVENTS, cannot read eeprom\n");
242 return -ENOSYS;
243 }
244 res = tb_sw_read(sw, &cap, TB_CFG_SWITCH, sw->cap_plug_events,
245 sizeof(cap) / 4);
246 if (res)
247 return res;
248
249 if (!cap.eeprom_ctl.present || cap.eeprom_ctl.not_present) {
250 tb_sw_warn(sw, "no NVM\n");
251 return -ENOSYS;
252 }
253
254 if (cap.drom_offset > 0xffff) {
255 tb_sw_warn(sw, "drom offset is larger than 0xffff: %#x\n",
256 cap.drom_offset);
257 return -ENXIO;
258 }
259 *offset = cap.drom_offset;
260 return 0;
261}
262
263/**
264 * tb_drom_read_uid_only - read uid directly from drom
265 *
266 * Does not use the cached copy in sw->drom. Used during resume to check switch
267 * identity.
268 */
269int tb_drom_read_uid_only(struct tb_switch *sw, u64 *uid)
270{
271 u8 data[9];
272 u16 drom_offset;
273 u8 crc;
274 int res = tb_eeprom_get_drom_offset(sw, &drom_offset);
275 if (res)
276 return res;
277
278 /* read uid */
279 res = tb_eeprom_read_n(sw, drom_offset, data, 9);
280 if (res)
281 return res;
282
283 crc = tb_crc8(data + 1, 8);
284 if (crc != data[0]) {
285 tb_sw_warn(sw, "uid crc8 missmatch (expected: %#x, got: %#x)\n",
286 data[0], crc);
287 return -EIO;
288 }
289
290 *uid = *(u64 *)(data+1);
291 return 0;
292}
293
294static void tb_drom_parse_port_entry(struct tb_port *port,
295 struct tb_drom_entry_port *entry)
296{
297 port->link_nr = entry->link_nr;
298 if (entry->has_dual_link_port)
299 port->dual_link_port =
300 &port->sw->ports[entry->dual_link_port_nr];
301}
302
303static int tb_drom_parse_entry(struct tb_switch *sw,
304 struct tb_drom_entry_header *header)
305{
306 struct tb_port *port;
307 int res;
308 enum tb_port_type type;
309
310 if (header->type != TB_DROM_ENTRY_PORT)
311 return 0;
312
313 port = &sw->ports[header->index];
314 port->disabled = header->port_disabled;
315 if (port->disabled)
316 return 0;
317
318 res = tb_port_read(port, &type, TB_CFG_PORT, 2, 1);
319 if (res)
320 return res;
321 type &= 0xffffff;
322
323 if (type == TB_TYPE_PORT) {
324 struct tb_drom_entry_port *entry = (void *) header;
325 if (header->len != sizeof(*entry)) {
326 tb_sw_warn(sw,
327 "port entry has size %#x (expected %#zx)\n",
328 header->len, sizeof(struct tb_drom_entry_port));
329 return -EIO;
330 }
331 tb_drom_parse_port_entry(port, entry);
332 }
333 return 0;
334}
335
336/**
337 * tb_drom_parse_entries - parse the linked list of drom entries
338 *
339 * Drom must have been copied to sw->drom.
340 */
341static int tb_drom_parse_entries(struct tb_switch *sw)
342{
343 struct tb_drom_header *header = (void *) sw->drom;
344 u16 pos = sizeof(*header);
345 u16 drom_size = header->data_len + TB_DROM_DATA_START;
346
347 while (pos < drom_size) {
348 struct tb_drom_entry_header *entry = (void *) (sw->drom + pos);
349 if (pos + 1 == drom_size || pos + entry->len > drom_size
350 || !entry->len) {
351 tb_sw_warn(sw, "drom buffer overrun, aborting\n");
352 return -EIO;
353 }
354
355 tb_drom_parse_entry(sw, entry);
356
357 pos += entry->len;
358 }
359 return 0;
360}
361
362/**
363 * tb_drom_read - copy drom to sw->drom and parse it
364 */
365int tb_drom_read(struct tb_switch *sw)
366{
367 u16 drom_offset;
368 u16 size;
369 u32 crc;
370 struct tb_drom_header *header;
371 int res;
372 if (sw->drom)
373 return 0;
374
375 if (tb_route(sw) == 0) {
376 /*
377 * The root switch contains only a dummy drom (header only,
378 * no entries). Hardcode the configuration here.
379 */
380 tb_drom_read_uid_only(sw, &sw->uid);
381
382 sw->ports[1].link_nr = 0;
383 sw->ports[2].link_nr = 1;
384 sw->ports[1].dual_link_port = &sw->ports[2];
385 sw->ports[2].dual_link_port = &sw->ports[1];
386
387 sw->ports[3].link_nr = 0;
388 sw->ports[4].link_nr = 1;
389 sw->ports[3].dual_link_port = &sw->ports[4];
390 sw->ports[4].dual_link_port = &sw->ports[3];
391 return 0;
392 }
393
394 res = tb_eeprom_get_drom_offset(sw, &drom_offset);
395 if (res)
396 return res;
397
398 res = tb_eeprom_read_n(sw, drom_offset + 14, (u8 *) &size, 2);
399 if (res)
400 return res;
401 size &= 0x3ff;
402 size += TB_DROM_DATA_START;
403 tb_sw_info(sw, "reading drom (length: %#x)\n", size);
404 if (size < sizeof(*header)) {
405 tb_sw_warn(sw, "drom too small, aborting\n");
406 return -EIO;
407 }
408
409 sw->drom = kzalloc(size, GFP_KERNEL);
410 if (!sw->drom)
411 return -ENOMEM;
412 res = tb_eeprom_read_n(sw, drom_offset, sw->drom, size);
413 if (res)
414 goto err;
415
416 header = (void *) sw->drom;
417
418 if (header->data_len + TB_DROM_DATA_START != size) {
419 tb_sw_warn(sw, "drom size mismatch, aborting\n");
420 goto err;
421 }
422
423 crc = tb_crc8((u8 *) &header->uid, 8);
424 if (crc != header->uid_crc8) {
425 tb_sw_warn(sw,
426 "drom uid crc8 mismatch (expected: %#x, got: %#x), aborting\n",
427 header->uid_crc8, crc);
428 goto err;
429 }
430 sw->uid = header->uid;
431
432 crc = tb_crc32(sw->drom + TB_DROM_DATA_START, header->data_len);
433 if (crc != header->data_crc32) {
434 tb_sw_warn(sw,
435 "drom data crc32 mismatch (expected: %#x, got: %#x), aborting\n",
436 header->data_crc32, crc);
437 goto err;
438 }
439
440 if (header->device_rom_revision > 1)
441 tb_sw_warn(sw, "drom device_rom_revision %#x unknown\n",
442 header->device_rom_revision);
443
444 return tb_drom_parse_entries(sw);
445err:
446 kfree(sw->drom);
447 return -EIO;
448
449}