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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2018, Intel Corporation
4 * Copied from reset-sunxi.c
5 */
6
7#include <linux/err.h>
8#include <linux/io.h>
9#include <linux/init.h>
10#include <linux/of.h>
11#include <linux/of_address.h>
12#include <linux/platform_device.h>
13#include <linux/reset-controller.h>
14#include <linux/reset/reset-simple.h>
15#include <linux/reset/socfpga.h>
16#include <linux/slab.h>
17#include <linux/spinlock.h>
18#include <linux/types.h>
19
20#define SOCFPGA_NR_BANKS 8
21
22static int a10_reset_init(struct device_node *np)
23{
24 struct reset_simple_data *data;
25 struct resource res;
26 resource_size_t size;
27 int ret;
28 u32 reg_offset = 0x10;
29
30 data = kzalloc(sizeof(*data), GFP_KERNEL);
31 if (!data)
32 return -ENOMEM;
33
34 ret = of_address_to_resource(np, 0, &res);
35 if (ret)
36 goto err_alloc;
37
38 size = resource_size(&res);
39 if (!request_mem_region(res.start, size, np->name)) {
40 ret = -EBUSY;
41 goto err_alloc;
42 }
43
44 data->membase = ioremap(res.start, size);
45 if (!data->membase) {
46 ret = -ENOMEM;
47 goto err_alloc;
48 }
49
50 if (of_property_read_u32(np, "altr,modrst-offset", ®_offset))
51 pr_warn("missing altr,modrst-offset property, assuming 0x10\n");
52 data->membase += reg_offset;
53
54 spin_lock_init(&data->lock);
55
56 data->rcdev.owner = THIS_MODULE;
57 data->rcdev.nr_resets = SOCFPGA_NR_BANKS * 32;
58 data->rcdev.ops = &reset_simple_ops;
59 data->rcdev.of_node = np;
60 data->status_active_low = true;
61
62 return reset_controller_register(&data->rcdev);
63
64err_alloc:
65 kfree(data);
66 return ret;
67};
68
69/*
70 * These are the reset controller we need to initialize early on in
71 * our system, before we can even think of using a regular device
72 * driver for it.
73 * The controllers that we can register through the regular device
74 * model are handled by the simple reset driver directly.
75 */
76static const struct of_device_id socfpga_early_reset_dt_ids[] __initconst = {
77 { .compatible = "altr,rst-mgr", },
78 { /* sentinel */ },
79};
80
81void __init socfpga_reset_init(void)
82{
83 struct device_node *np;
84
85 for_each_matching_node(np, socfpga_early_reset_dt_ids)
86 a10_reset_init(np);
87}
1/*
2 * Copyright 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de>
3 *
4 * based on
5 * Allwinner SoCs Reset Controller driver
6 *
7 * Copyright 2013 Maxime Ripard
8 *
9 * Maxime Ripard <maxime.ripard@free-electrons.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 */
16
17#include <linux/err.h>
18#include <linux/io.h>
19#include <linux/module.h>
20#include <linux/of.h>
21#include <linux/platform_device.h>
22#include <linux/reset-controller.h>
23#include <linux/spinlock.h>
24#include <linux/types.h>
25
26#define NR_BANKS 4
27
28struct socfpga_reset_data {
29 spinlock_t lock;
30 void __iomem *membase;
31 u32 modrst_offset;
32 struct reset_controller_dev rcdev;
33};
34
35static int socfpga_reset_assert(struct reset_controller_dev *rcdev,
36 unsigned long id)
37{
38 struct socfpga_reset_data *data = container_of(rcdev,
39 struct socfpga_reset_data,
40 rcdev);
41 int bank = id / BITS_PER_LONG;
42 int offset = id % BITS_PER_LONG;
43 unsigned long flags;
44 u32 reg;
45
46 spin_lock_irqsave(&data->lock, flags);
47
48 reg = readl(data->membase + data->modrst_offset + (bank * NR_BANKS));
49 writel(reg | BIT(offset), data->membase + data->modrst_offset +
50 (bank * NR_BANKS));
51 spin_unlock_irqrestore(&data->lock, flags);
52
53 return 0;
54}
55
56static int socfpga_reset_deassert(struct reset_controller_dev *rcdev,
57 unsigned long id)
58{
59 struct socfpga_reset_data *data = container_of(rcdev,
60 struct socfpga_reset_data,
61 rcdev);
62
63 int bank = id / BITS_PER_LONG;
64 int offset = id % BITS_PER_LONG;
65 unsigned long flags;
66 u32 reg;
67
68 spin_lock_irqsave(&data->lock, flags);
69
70 reg = readl(data->membase + data->modrst_offset + (bank * NR_BANKS));
71 writel(reg & ~BIT(offset), data->membase + data->modrst_offset +
72 (bank * NR_BANKS));
73
74 spin_unlock_irqrestore(&data->lock, flags);
75
76 return 0;
77}
78
79static int socfpga_reset_status(struct reset_controller_dev *rcdev,
80 unsigned long id)
81{
82 struct socfpga_reset_data *data = container_of(rcdev,
83 struct socfpga_reset_data, rcdev);
84 int bank = id / BITS_PER_LONG;
85 int offset = id % BITS_PER_LONG;
86 u32 reg;
87
88 reg = readl(data->membase + data->modrst_offset + (bank * NR_BANKS));
89
90 return !(reg & BIT(offset));
91}
92
93static const struct reset_control_ops socfpga_reset_ops = {
94 .assert = socfpga_reset_assert,
95 .deassert = socfpga_reset_deassert,
96 .status = socfpga_reset_status,
97};
98
99static int socfpga_reset_probe(struct platform_device *pdev)
100{
101 struct socfpga_reset_data *data;
102 struct resource *res;
103 struct device *dev = &pdev->dev;
104 struct device_node *np = dev->of_node;
105
106 /*
107 * The binding was mainlined without the required property.
108 * Do not continue, when we encounter an old DT.
109 */
110 if (!of_find_property(pdev->dev.of_node, "#reset-cells", NULL)) {
111 dev_err(&pdev->dev, "%s missing #reset-cells property\n",
112 pdev->dev.of_node->full_name);
113 return -EINVAL;
114 }
115
116 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
117 if (!data)
118 return -ENOMEM;
119
120 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
121 data->membase = devm_ioremap_resource(&pdev->dev, res);
122 if (IS_ERR(data->membase))
123 return PTR_ERR(data->membase);
124
125 if (of_property_read_u32(np, "altr,modrst-offset", &data->modrst_offset)) {
126 dev_warn(dev, "missing altr,modrst-offset property, assuming 0x10!\n");
127 data->modrst_offset = 0x10;
128 }
129
130 spin_lock_init(&data->lock);
131
132 data->rcdev.owner = THIS_MODULE;
133 data->rcdev.nr_resets = NR_BANKS * BITS_PER_LONG;
134 data->rcdev.ops = &socfpga_reset_ops;
135 data->rcdev.of_node = pdev->dev.of_node;
136
137 return reset_controller_register(&data->rcdev);
138}
139
140static int socfpga_reset_remove(struct platform_device *pdev)
141{
142 struct socfpga_reset_data *data = platform_get_drvdata(pdev);
143
144 reset_controller_unregister(&data->rcdev);
145
146 return 0;
147}
148
149static const struct of_device_id socfpga_reset_dt_ids[] = {
150 { .compatible = "altr,rst-mgr", },
151 { /* sentinel */ },
152};
153
154static struct platform_driver socfpga_reset_driver = {
155 .probe = socfpga_reset_probe,
156 .remove = socfpga_reset_remove,
157 .driver = {
158 .name = "socfpga-reset",
159 .of_match_table = socfpga_reset_dt_ids,
160 },
161};
162module_platform_driver(socfpga_reset_driver);
163
164MODULE_AUTHOR("Steffen Trumtrar <s.trumtrar@pengutronix.de");
165MODULE_DESCRIPTION("Socfpga Reset Controller Driver");
166MODULE_LICENSE("GPL");