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1/******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
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6 * GPL LICENSE SUMMARY
7 *
8 * Copyright(c) 2018, 2020 Intel Corporation
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11 * it under the terms of version 2 of the GNU General Public License as
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21 * Copyright(c) 2018, 2020 Intel Corporation
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50 *****************************************************************************/
51#ifndef __iwl_context_info_file_gen3_h__
52#define __iwl_context_info_file_gen3_h__
53
54#include "iwl-context-info.h"
55
56#define CSR_CTXT_INFO_BOOT_CTRL 0x0
57#define CSR_CTXT_INFO_ADDR 0x118
58#define CSR_IML_DATA_ADDR 0x120
59#define CSR_IML_SIZE_ADDR 0x128
60#define CSR_IML_RESP_ADDR 0x12c
61
62/* Set bit for enabling automatic function boot */
63#define CSR_AUTO_FUNC_BOOT_ENA BIT(1)
64/* Set bit for initiating function boot */
65#define CSR_AUTO_FUNC_INIT BIT(7)
66
67/**
68 * enum iwl_prph_scratch_mtr_format - tfd size configuration
69 * @IWL_PRPH_MTR_FORMAT_16B: 16 bit tfd
70 * @IWL_PRPH_MTR_FORMAT_32B: 32 bit tfd
71 * @IWL_PRPH_MTR_FORMAT_64B: 64 bit tfd
72 * @IWL_PRPH_MTR_FORMAT_256B: 256 bit tfd
73 */
74enum iwl_prph_scratch_mtr_format {
75 IWL_PRPH_MTR_FORMAT_16B = 0x0,
76 IWL_PRPH_MTR_FORMAT_32B = 0x40000,
77 IWL_PRPH_MTR_FORMAT_64B = 0x80000,
78 IWL_PRPH_MTR_FORMAT_256B = 0xC0000,
79};
80
81/**
82 * enum iwl_prph_scratch_flags - PRPH scratch control flags
83 * @IWL_PRPH_SCRATCH_EARLY_DEBUG_EN: enable early debug conf
84 * @IWL_PRPH_SCRATCH_EDBG_DEST_DRAM: use DRAM, with size allocated
85 * in hwm config.
86 * @IWL_PRPH_SCRATCH_EDBG_DEST_INTERNAL: use buffer on SRAM
87 * @IWL_PRPH_SCRATCH_EDBG_DEST_ST_ARBITER: use st arbiter, mainly for
88 * multicomm.
89 * @IWL_PRPH_SCRATCH_EDBG_DEST_TB22DTF: route debug data to SoC HW
90 * @IWL_PRPH_SCTATCH_RB_SIZE_4K: Use 4K RB size (the default is 2K)
91 * @IWL_PRPH_SCRATCH_MTR_MODE: format used for completion - 0: for
92 * completion descriptor, 1 for responses (legacy)
93 * @IWL_PRPH_SCRATCH_MTR_FORMAT: a mask for the size of the tfd.
94 * There are 4 optional values: 0: 16 bit, 1: 32 bit, 2: 64 bit,
95 * 3: 256 bit.
96 * @IWL_PRPH_SCRATCH_RB_SIZE_EXT_MASK: RB size full information, ignored
97 * by older firmware versions, so set IWL_PRPH_SCRATCH_RB_SIZE_4K
98 * appropriately; use the below values for this.
99 * @IWL_PRPH_SCRATCH_RB_SIZE_EXT_8K: 8kB RB size
100 * @IWL_PRPH_SCRATCH_RB_SIZE_EXT_12K: 12kB RB size
101 */
102enum iwl_prph_scratch_flags {
103 IWL_PRPH_SCRATCH_EARLY_DEBUG_EN = BIT(4),
104 IWL_PRPH_SCRATCH_EDBG_DEST_DRAM = BIT(8),
105 IWL_PRPH_SCRATCH_EDBG_DEST_INTERNAL = BIT(9),
106 IWL_PRPH_SCRATCH_EDBG_DEST_ST_ARBITER = BIT(10),
107 IWL_PRPH_SCRATCH_EDBG_DEST_TB22DTF = BIT(11),
108 IWL_PRPH_SCRATCH_RB_SIZE_4K = BIT(16),
109 IWL_PRPH_SCRATCH_MTR_MODE = BIT(17),
110 IWL_PRPH_SCRATCH_MTR_FORMAT = BIT(18) | BIT(19),
111 IWL_PRPH_SCRATCH_RB_SIZE_EXT_MASK = 0xf << 20,
112 IWL_PRPH_SCRATCH_RB_SIZE_EXT_8K = 8 << 20,
113 IWL_PRPH_SCRATCH_RB_SIZE_EXT_12K = 9 << 20,
114};
115
116/*
117 * struct iwl_prph_scratch_version - version structure
118 * @mac_id: SKU and revision id
119 * @version: prph scratch information version id
120 * @size: the size of the context information in DWs
121 * @reserved: reserved
122 */
123struct iwl_prph_scratch_version {
124 __le16 mac_id;
125 __le16 version;
126 __le16 size;
127 __le16 reserved;
128} __packed; /* PERIPH_SCRATCH_VERSION_S */
129
130/*
131 * struct iwl_prph_scratch_control - control structure
132 * @control_flags: context information flags see &enum iwl_prph_scratch_flags
133 * @reserved: reserved
134 */
135struct iwl_prph_scratch_control {
136 __le32 control_flags;
137 __le32 reserved;
138} __packed; /* PERIPH_SCRATCH_CONTROL_S */
139
140/*
141 * struct iwl_prph_scratch_ror_cfg - ror config
142 * @ror_base_addr: ror start address
143 * @ror_size: ror size in DWs
144 * @reserved: reserved
145 */
146struct iwl_prph_scratch_ror_cfg {
147 __le64 ror_base_addr;
148 __le32 ror_size;
149 __le32 reserved;
150} __packed; /* PERIPH_SCRATCH_ROR_CFG_S */
151
152/*
153 * struct iwl_prph_scratch_hwm_cfg - hwm config
154 * @hwm_base_addr: hwm start address
155 * @hwm_size: hwm size in DWs
156 * @reserved: reserved
157 */
158struct iwl_prph_scratch_hwm_cfg {
159 __le64 hwm_base_addr;
160 __le32 hwm_size;
161 __le32 reserved;
162} __packed; /* PERIPH_SCRATCH_HWM_CFG_S */
163
164/*
165 * struct iwl_prph_scratch_rbd_cfg - RBDs configuration
166 * @free_rbd_addr: default queue free RB CB base address
167 * @reserved: reserved
168 */
169struct iwl_prph_scratch_rbd_cfg {
170 __le64 free_rbd_addr;
171 __le32 reserved;
172} __packed; /* PERIPH_SCRATCH_RBD_CFG_S */
173
174/*
175 * struct iwl_prph_scratch_ctrl_cfg - prph scratch ctrl and config
176 * @version: version information of context info and HW
177 * @control: control flags of FH configurations
178 * @ror_cfg: ror configuration
179 * @hwm_cfg: hwm configuration
180 * @rbd_cfg: default RX queue configuration
181 */
182struct iwl_prph_scratch_ctrl_cfg {
183 struct iwl_prph_scratch_version version;
184 struct iwl_prph_scratch_control control;
185 struct iwl_prph_scratch_ror_cfg ror_cfg;
186 struct iwl_prph_scratch_hwm_cfg hwm_cfg;
187 struct iwl_prph_scratch_rbd_cfg rbd_cfg;
188} __packed; /* PERIPH_SCRATCH_CTRL_CFG_S */
189
190/*
191 * struct iwl_prph_scratch - peripheral scratch mapping
192 * @ctrl_cfg: control and configuration of prph scratch
193 * @dram: firmware images addresses in DRAM
194 * @reserved: reserved
195 */
196struct iwl_prph_scratch {
197 struct iwl_prph_scratch_ctrl_cfg ctrl_cfg;
198 __le32 reserved[16];
199 struct iwl_context_info_dram dram;
200} __packed; /* PERIPH_SCRATCH_S */
201
202/*
203 * struct iwl_prph_info - peripheral information
204 * @boot_stage_mirror: reflects the value in the Boot Stage CSR register
205 * @ipc_status_mirror: reflects the value in the IPC Status CSR register
206 * @sleep_notif: indicates the peripheral sleep status
207 * @reserved: reserved
208 */
209struct iwl_prph_info {
210 __le32 boot_stage_mirror;
211 __le32 ipc_status_mirror;
212 __le32 sleep_notif;
213 __le32 reserved;
214} __packed; /* PERIPH_INFO_S */
215
216/*
217 * struct iwl_context_info_gen3 - device INIT configuration
218 * @version: version of the context information
219 * @size: size of context information in DWs
220 * @config: context in which the peripheral would execute - a subset of
221 * capability csr register published by the peripheral
222 * @prph_info_base_addr: the peripheral information structure start address
223 * @cr_head_idx_arr_base_addr: the completion ring head index array
224 * start address
225 * @tr_tail_idx_arr_base_addr: the transfer ring tail index array
226 * start address
227 * @cr_tail_idx_arr_base_addr: the completion ring tail index array
228 * start address
229 * @tr_head_idx_arr_base_addr: the transfer ring head index array
230 * start address
231 * @cr_idx_arr_size: number of entries in the completion ring index array
232 * @tr_idx_arr_size: number of entries in the transfer ring index array
233 * @mtr_base_addr: the message transfer ring start address
234 * @mcr_base_addr: the message completion ring start address
235 * @mtr_size: number of entries which the message transfer ring can hold
236 * @mcr_size: number of entries which the message completion ring can hold
237 * @mtr_doorbell_vec: the doorbell vector associated with the message
238 * transfer ring
239 * @mcr_doorbell_vec: the doorbell vector associated with the message
240 * completion ring
241 * @mtr_msi_vec: the MSI which shall be generated by the peripheral after
242 * completing a transfer descriptor in the message transfer ring
243 * @mcr_msi_vec: the MSI which shall be generated by the peripheral after
244 * completing a completion descriptor in the message completion ring
245 * @mtr_opt_header_size: the size of the optional header in the transfer
246 * descriptor associated with the message transfer ring in DWs
247 * @mtr_opt_footer_size: the size of the optional footer in the transfer
248 * descriptor associated with the message transfer ring in DWs
249 * @mcr_opt_header_size: the size of the optional header in the completion
250 * descriptor associated with the message completion ring in DWs
251 * @mcr_opt_footer_size: the size of the optional footer in the completion
252 * descriptor associated with the message completion ring in DWs
253 * @msg_rings_ctrl_flags: message rings control flags
254 * @prph_info_msi_vec: the MSI which shall be generated by the peripheral
255 * after updating the Peripheral Information structure
256 * @prph_scratch_base_addr: the peripheral scratch structure start address
257 * @prph_scratch_size: the size of the peripheral scratch structure in DWs
258 * @reserved: reserved
259 */
260struct iwl_context_info_gen3 {
261 __le16 version;
262 __le16 size;
263 __le32 config;
264 __le64 prph_info_base_addr;
265 __le64 cr_head_idx_arr_base_addr;
266 __le64 tr_tail_idx_arr_base_addr;
267 __le64 cr_tail_idx_arr_base_addr;
268 __le64 tr_head_idx_arr_base_addr;
269 __le16 cr_idx_arr_size;
270 __le16 tr_idx_arr_size;
271 __le64 mtr_base_addr;
272 __le64 mcr_base_addr;
273 __le16 mtr_size;
274 __le16 mcr_size;
275 __le16 mtr_doorbell_vec;
276 __le16 mcr_doorbell_vec;
277 __le16 mtr_msi_vec;
278 __le16 mcr_msi_vec;
279 u8 mtr_opt_header_size;
280 u8 mtr_opt_footer_size;
281 u8 mcr_opt_header_size;
282 u8 mcr_opt_footer_size;
283 __le16 msg_rings_ctrl_flags;
284 __le16 prph_info_msi_vec;
285 __le64 prph_scratch_base_addr;
286 __le32 prph_scratch_size;
287 __le32 reserved;
288} __packed; /* IPC_CONTEXT_INFO_S */
289
290int iwl_pcie_ctxt_info_gen3_init(struct iwl_trans *trans,
291 const struct fw_img *fw);
292void iwl_pcie_ctxt_info_gen3_free(struct iwl_trans *trans);
293
294#endif /* __iwl_context_info_file_gen3_h__ */