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1// SPDX-License-Identifier: GPL-2.0
2//
3// flexcan.c - FLEXCAN CAN controller driver
4//
5// Copyright (c) 2005-2006 Varma Electronics Oy
6// Copyright (c) 2009 Sascha Hauer, Pengutronix
7// Copyright (c) 2010-2017 Pengutronix, Marc Kleine-Budde <kernel@pengutronix.de>
8// Copyright (c) 2014 David Jander, Protonic Holland
9//
10// Based on code originally by Andrey Volkov <avolkov@varma-el.com>
11
12#include <linux/netdevice.h>
13#include <linux/can.h>
14#include <linux/can/dev.h>
15#include <linux/can/error.h>
16#include <linux/can/led.h>
17#include <linux/can/rx-offload.h>
18#include <linux/clk.h>
19#include <linux/delay.h>
20#include <linux/interrupt.h>
21#include <linux/io.h>
22#include <linux/mfd/syscon.h>
23#include <linux/module.h>
24#include <linux/of.h>
25#include <linux/of_device.h>
26#include <linux/platform_device.h>
27#include <linux/pm_runtime.h>
28#include <linux/regulator/consumer.h>
29#include <linux/regmap.h>
30
31#define DRV_NAME "flexcan"
32
33/* 8 for RX fifo and 2 error handling */
34#define FLEXCAN_NAPI_WEIGHT (8 + 2)
35
36/* FLEXCAN module configuration register (CANMCR) bits */
37#define FLEXCAN_MCR_MDIS BIT(31)
38#define FLEXCAN_MCR_FRZ BIT(30)
39#define FLEXCAN_MCR_FEN BIT(29)
40#define FLEXCAN_MCR_HALT BIT(28)
41#define FLEXCAN_MCR_NOT_RDY BIT(27)
42#define FLEXCAN_MCR_WAK_MSK BIT(26)
43#define FLEXCAN_MCR_SOFTRST BIT(25)
44#define FLEXCAN_MCR_FRZ_ACK BIT(24)
45#define FLEXCAN_MCR_SUPV BIT(23)
46#define FLEXCAN_MCR_SLF_WAK BIT(22)
47#define FLEXCAN_MCR_WRN_EN BIT(21)
48#define FLEXCAN_MCR_LPM_ACK BIT(20)
49#define FLEXCAN_MCR_WAK_SRC BIT(19)
50#define FLEXCAN_MCR_DOZE BIT(18)
51#define FLEXCAN_MCR_SRX_DIS BIT(17)
52#define FLEXCAN_MCR_IRMQ BIT(16)
53#define FLEXCAN_MCR_LPRIO_EN BIT(13)
54#define FLEXCAN_MCR_AEN BIT(12)
55/* MCR_MAXMB: maximum used MBs is MAXMB + 1 */
56#define FLEXCAN_MCR_MAXMB(x) ((x) & 0x7f)
57#define FLEXCAN_MCR_IDAM_A (0x0 << 8)
58#define FLEXCAN_MCR_IDAM_B (0x1 << 8)
59#define FLEXCAN_MCR_IDAM_C (0x2 << 8)
60#define FLEXCAN_MCR_IDAM_D (0x3 << 8)
61
62/* FLEXCAN control register (CANCTRL) bits */
63#define FLEXCAN_CTRL_PRESDIV(x) (((x) & 0xff) << 24)
64#define FLEXCAN_CTRL_RJW(x) (((x) & 0x03) << 22)
65#define FLEXCAN_CTRL_PSEG1(x) (((x) & 0x07) << 19)
66#define FLEXCAN_CTRL_PSEG2(x) (((x) & 0x07) << 16)
67#define FLEXCAN_CTRL_BOFF_MSK BIT(15)
68#define FLEXCAN_CTRL_ERR_MSK BIT(14)
69#define FLEXCAN_CTRL_CLK_SRC BIT(13)
70#define FLEXCAN_CTRL_LPB BIT(12)
71#define FLEXCAN_CTRL_TWRN_MSK BIT(11)
72#define FLEXCAN_CTRL_RWRN_MSK BIT(10)
73#define FLEXCAN_CTRL_SMP BIT(7)
74#define FLEXCAN_CTRL_BOFF_REC BIT(6)
75#define FLEXCAN_CTRL_TSYN BIT(5)
76#define FLEXCAN_CTRL_LBUF BIT(4)
77#define FLEXCAN_CTRL_LOM BIT(3)
78#define FLEXCAN_CTRL_PROPSEG(x) ((x) & 0x07)
79#define FLEXCAN_CTRL_ERR_BUS (FLEXCAN_CTRL_ERR_MSK)
80#define FLEXCAN_CTRL_ERR_STATE \
81 (FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \
82 FLEXCAN_CTRL_BOFF_MSK)
83#define FLEXCAN_CTRL_ERR_ALL \
84 (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE)
85
86/* FLEXCAN control register 2 (CTRL2) bits */
87#define FLEXCAN_CTRL2_ECRWRE BIT(29)
88#define FLEXCAN_CTRL2_WRMFRZ BIT(28)
89#define FLEXCAN_CTRL2_RFFN(x) (((x) & 0x0f) << 24)
90#define FLEXCAN_CTRL2_TASD(x) (((x) & 0x1f) << 19)
91#define FLEXCAN_CTRL2_MRP BIT(18)
92#define FLEXCAN_CTRL2_RRS BIT(17)
93#define FLEXCAN_CTRL2_EACEN BIT(16)
94
95/* FLEXCAN memory error control register (MECR) bits */
96#define FLEXCAN_MECR_ECRWRDIS BIT(31)
97#define FLEXCAN_MECR_HANCEI_MSK BIT(19)
98#define FLEXCAN_MECR_FANCEI_MSK BIT(18)
99#define FLEXCAN_MECR_CEI_MSK BIT(16)
100#define FLEXCAN_MECR_HAERRIE BIT(15)
101#define FLEXCAN_MECR_FAERRIE BIT(14)
102#define FLEXCAN_MECR_EXTERRIE BIT(13)
103#define FLEXCAN_MECR_RERRDIS BIT(9)
104#define FLEXCAN_MECR_ECCDIS BIT(8)
105#define FLEXCAN_MECR_NCEFAFRZ BIT(7)
106
107/* FLEXCAN error and status register (ESR) bits */
108#define FLEXCAN_ESR_TWRN_INT BIT(17)
109#define FLEXCAN_ESR_RWRN_INT BIT(16)
110#define FLEXCAN_ESR_BIT1_ERR BIT(15)
111#define FLEXCAN_ESR_BIT0_ERR BIT(14)
112#define FLEXCAN_ESR_ACK_ERR BIT(13)
113#define FLEXCAN_ESR_CRC_ERR BIT(12)
114#define FLEXCAN_ESR_FRM_ERR BIT(11)
115#define FLEXCAN_ESR_STF_ERR BIT(10)
116#define FLEXCAN_ESR_TX_WRN BIT(9)
117#define FLEXCAN_ESR_RX_WRN BIT(8)
118#define FLEXCAN_ESR_IDLE BIT(7)
119#define FLEXCAN_ESR_TXRX BIT(6)
120#define FLEXCAN_EST_FLT_CONF_SHIFT (4)
121#define FLEXCAN_ESR_FLT_CONF_MASK (0x3 << FLEXCAN_EST_FLT_CONF_SHIFT)
122#define FLEXCAN_ESR_FLT_CONF_ACTIVE (0x0 << FLEXCAN_EST_FLT_CONF_SHIFT)
123#define FLEXCAN_ESR_FLT_CONF_PASSIVE (0x1 << FLEXCAN_EST_FLT_CONF_SHIFT)
124#define FLEXCAN_ESR_BOFF_INT BIT(2)
125#define FLEXCAN_ESR_ERR_INT BIT(1)
126#define FLEXCAN_ESR_WAK_INT BIT(0)
127#define FLEXCAN_ESR_ERR_BUS \
128 (FLEXCAN_ESR_BIT1_ERR | FLEXCAN_ESR_BIT0_ERR | \
129 FLEXCAN_ESR_ACK_ERR | FLEXCAN_ESR_CRC_ERR | \
130 FLEXCAN_ESR_FRM_ERR | FLEXCAN_ESR_STF_ERR)
131#define FLEXCAN_ESR_ERR_STATE \
132 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT)
133#define FLEXCAN_ESR_ERR_ALL \
134 (FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE)
135#define FLEXCAN_ESR_ALL_INT \
136 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | \
137 FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT | \
138 FLEXCAN_ESR_WAK_INT)
139
140/* FLEXCAN interrupt flag register (IFLAG) bits */
141/* Errata ERR005829 step7: Reserve first valid MB */
142#define FLEXCAN_TX_MB_RESERVED_OFF_FIFO 8
143#define FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP 0
144#define FLEXCAN_RX_MB_OFF_TIMESTAMP_FIRST (FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP + 1)
145#define FLEXCAN_IFLAG_MB(x) BIT_ULL(x)
146#define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7)
147#define FLEXCAN_IFLAG_RX_FIFO_WARN BIT(6)
148#define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5)
149
150/* FLEXCAN message buffers */
151#define FLEXCAN_MB_CODE_MASK (0xf << 24)
152#define FLEXCAN_MB_CODE_RX_BUSY_BIT (0x1 << 24)
153#define FLEXCAN_MB_CODE_RX_INACTIVE (0x0 << 24)
154#define FLEXCAN_MB_CODE_RX_EMPTY (0x4 << 24)
155#define FLEXCAN_MB_CODE_RX_FULL (0x2 << 24)
156#define FLEXCAN_MB_CODE_RX_OVERRUN (0x6 << 24)
157#define FLEXCAN_MB_CODE_RX_RANSWER (0xa << 24)
158
159#define FLEXCAN_MB_CODE_TX_INACTIVE (0x8 << 24)
160#define FLEXCAN_MB_CODE_TX_ABORT (0x9 << 24)
161#define FLEXCAN_MB_CODE_TX_DATA (0xc << 24)
162#define FLEXCAN_MB_CODE_TX_TANSWER (0xe << 24)
163
164#define FLEXCAN_MB_CNT_SRR BIT(22)
165#define FLEXCAN_MB_CNT_IDE BIT(21)
166#define FLEXCAN_MB_CNT_RTR BIT(20)
167#define FLEXCAN_MB_CNT_LENGTH(x) (((x) & 0xf) << 16)
168#define FLEXCAN_MB_CNT_TIMESTAMP(x) ((x) & 0xffff)
169
170#define FLEXCAN_TIMEOUT_US (250)
171
172/* FLEXCAN hardware feature flags
173 *
174 * Below is some version info we got:
175 * SOC Version IP-Version Glitch- [TR]WRN_INT IRQ Err Memory err RTR re-
176 * Filter? connected? Passive detection ception in MB
177 * MX25 FlexCAN2 03.00.00.00 no no no no no
178 * MX28 FlexCAN2 03.00.04.00 yes yes no no no
179 * MX35 FlexCAN2 03.00.00.00 no no no no no
180 * MX53 FlexCAN2 03.00.00.00 yes no no no no
181 * MX6s FlexCAN3 10.00.12.00 yes yes no no yes
182 * VF610 FlexCAN3 ? no yes no yes yes?
183 * LS1021A FlexCAN2 03.00.04.00 no yes no no yes
184 *
185 * Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected.
186 */
187#define FLEXCAN_QUIRK_BROKEN_WERR_STATE BIT(1) /* [TR]WRN_INT not connected */
188#define FLEXCAN_QUIRK_DISABLE_RXFG BIT(2) /* Disable RX FIFO Global mask */
189#define FLEXCAN_QUIRK_ENABLE_EACEN_RRS BIT(3) /* Enable EACEN and RRS bit in ctrl2 */
190#define FLEXCAN_QUIRK_DISABLE_MECR BIT(4) /* Disable Memory error detection */
191#define FLEXCAN_QUIRK_USE_OFF_TIMESTAMP BIT(5) /* Use timestamp based offloading */
192#define FLEXCAN_QUIRK_BROKEN_PERR_STATE BIT(6) /* No interrupt for error passive */
193#define FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN BIT(7) /* default to BE register access */
194#define FLEXCAN_QUIRK_SETUP_STOP_MODE BIT(8) /* Setup stop mode to support wakeup */
195
196/* Structure of the message buffer */
197struct flexcan_mb {
198 u32 can_ctrl;
199 u32 can_id;
200 u32 data[];
201};
202
203/* Structure of the hardware registers */
204struct flexcan_regs {
205 u32 mcr; /* 0x00 */
206 u32 ctrl; /* 0x04 */
207 u32 timer; /* 0x08 */
208 u32 _reserved1; /* 0x0c */
209 u32 rxgmask; /* 0x10 */
210 u32 rx14mask; /* 0x14 */
211 u32 rx15mask; /* 0x18 */
212 u32 ecr; /* 0x1c */
213 u32 esr; /* 0x20 */
214 u32 imask2; /* 0x24 */
215 u32 imask1; /* 0x28 */
216 u32 iflag2; /* 0x2c */
217 u32 iflag1; /* 0x30 */
218 union { /* 0x34 */
219 u32 gfwr_mx28; /* MX28, MX53 */
220 u32 ctrl2; /* MX6, VF610 */
221 };
222 u32 esr2; /* 0x38 */
223 u32 imeur; /* 0x3c */
224 u32 lrfr; /* 0x40 */
225 u32 crcr; /* 0x44 */
226 u32 rxfgmask; /* 0x48 */
227 u32 rxfir; /* 0x4c */
228 u32 _reserved3[12]; /* 0x50 */
229 u8 mb[2][512]; /* 0x80 */
230 /* FIFO-mode:
231 * MB
232 * 0x080...0x08f 0 RX message buffer
233 * 0x090...0x0df 1-5 reserverd
234 * 0x0e0...0x0ff 6-7 8 entry ID table
235 * (mx25, mx28, mx35, mx53)
236 * 0x0e0...0x2df 6-7..37 8..128 entry ID table
237 * size conf'ed via ctrl2::RFFN
238 * (mx6, vf610)
239 */
240 u32 _reserved4[256]; /* 0x480 */
241 u32 rximr[64]; /* 0x880 */
242 u32 _reserved5[24]; /* 0x980 */
243 u32 gfwr_mx6; /* 0x9e0 - MX6 */
244 u32 _reserved6[63]; /* 0x9e4 */
245 u32 mecr; /* 0xae0 */
246 u32 erriar; /* 0xae4 */
247 u32 erridpr; /* 0xae8 */
248 u32 errippr; /* 0xaec */
249 u32 rerrar; /* 0xaf0 */
250 u32 rerrdr; /* 0xaf4 */
251 u32 rerrsynr; /* 0xaf8 */
252 u32 errsr; /* 0xafc */
253};
254
255struct flexcan_devtype_data {
256 u32 quirks; /* quirks needed for different IP cores */
257};
258
259struct flexcan_stop_mode {
260 struct regmap *gpr;
261 u8 req_gpr;
262 u8 req_bit;
263 u8 ack_gpr;
264 u8 ack_bit;
265};
266
267struct flexcan_priv {
268 struct can_priv can;
269 struct can_rx_offload offload;
270 struct device *dev;
271
272 struct flexcan_regs __iomem *regs;
273 struct flexcan_mb __iomem *tx_mb;
274 struct flexcan_mb __iomem *tx_mb_reserved;
275 u8 tx_mb_idx;
276 u8 mb_count;
277 u8 mb_size;
278 u8 clk_src; /* clock source of CAN Protocol Engine */
279
280 u64 rx_mask;
281 u64 tx_mask;
282 u32 reg_ctrl_default;
283
284 struct clk *clk_ipg;
285 struct clk *clk_per;
286 const struct flexcan_devtype_data *devtype_data;
287 struct regulator *reg_xceiver;
288 struct flexcan_stop_mode stm;
289
290 /* Read and Write APIs */
291 u32 (*read)(void __iomem *addr);
292 void (*write)(u32 val, void __iomem *addr);
293};
294
295static const struct flexcan_devtype_data fsl_p1010_devtype_data = {
296 .quirks = FLEXCAN_QUIRK_BROKEN_WERR_STATE |
297 FLEXCAN_QUIRK_BROKEN_PERR_STATE |
298 FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN,
299};
300
301static const struct flexcan_devtype_data fsl_imx25_devtype_data = {
302 .quirks = FLEXCAN_QUIRK_BROKEN_WERR_STATE |
303 FLEXCAN_QUIRK_BROKEN_PERR_STATE,
304};
305
306static const struct flexcan_devtype_data fsl_imx28_devtype_data = {
307 .quirks = FLEXCAN_QUIRK_BROKEN_PERR_STATE,
308};
309
310static const struct flexcan_devtype_data fsl_imx6q_devtype_data = {
311 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
312 FLEXCAN_QUIRK_USE_OFF_TIMESTAMP | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
313 FLEXCAN_QUIRK_SETUP_STOP_MODE,
314};
315
316static const struct flexcan_devtype_data fsl_vf610_devtype_data = {
317 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
318 FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_USE_OFF_TIMESTAMP |
319 FLEXCAN_QUIRK_BROKEN_PERR_STATE,
320};
321
322static const struct flexcan_devtype_data fsl_ls1021a_r2_devtype_data = {
323 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
324 FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
325 FLEXCAN_QUIRK_USE_OFF_TIMESTAMP,
326};
327
328static const struct can_bittiming_const flexcan_bittiming_const = {
329 .name = DRV_NAME,
330 .tseg1_min = 4,
331 .tseg1_max = 16,
332 .tseg2_min = 2,
333 .tseg2_max = 8,
334 .sjw_max = 4,
335 .brp_min = 1,
336 .brp_max = 256,
337 .brp_inc = 1,
338};
339
340/* FlexCAN module is essentially modelled as a little-endian IP in most
341 * SoCs, i.e the registers as well as the message buffer areas are
342 * implemented in a little-endian fashion.
343 *
344 * However there are some SoCs (e.g. LS1021A) which implement the FlexCAN
345 * module in a big-endian fashion (i.e the registers as well as the
346 * message buffer areas are implemented in a big-endian way).
347 *
348 * In addition, the FlexCAN module can be found on SoCs having ARM or
349 * PPC cores. So, we need to abstract off the register read/write
350 * functions, ensuring that these cater to all the combinations of module
351 * endianness and underlying CPU endianness.
352 */
353static inline u32 flexcan_read_be(void __iomem *addr)
354{
355 return ioread32be(addr);
356}
357
358static inline void flexcan_write_be(u32 val, void __iomem *addr)
359{
360 iowrite32be(val, addr);
361}
362
363static inline u32 flexcan_read_le(void __iomem *addr)
364{
365 return ioread32(addr);
366}
367
368static inline void flexcan_write_le(u32 val, void __iomem *addr)
369{
370 iowrite32(val, addr);
371}
372
373static struct flexcan_mb __iomem *flexcan_get_mb(const struct flexcan_priv *priv,
374 u8 mb_index)
375{
376 u8 bank_size;
377 bool bank;
378
379 if (WARN_ON(mb_index >= priv->mb_count))
380 return NULL;
381
382 bank_size = sizeof(priv->regs->mb[0]) / priv->mb_size;
383
384 bank = mb_index >= bank_size;
385 if (bank)
386 mb_index -= bank_size;
387
388 return (struct flexcan_mb __iomem *)
389 (&priv->regs->mb[bank][priv->mb_size * mb_index]);
390}
391
392static int flexcan_low_power_enter_ack(struct flexcan_priv *priv)
393{
394 struct flexcan_regs __iomem *regs = priv->regs;
395 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
396
397 while (timeout-- && !(priv->read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
398 udelay(10);
399
400 if (!(priv->read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
401 return -ETIMEDOUT;
402
403 return 0;
404}
405
406static int flexcan_low_power_exit_ack(struct flexcan_priv *priv)
407{
408 struct flexcan_regs __iomem *regs = priv->regs;
409 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
410
411 while (timeout-- && (priv->read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
412 udelay(10);
413
414 if (priv->read(®s->mcr) & FLEXCAN_MCR_LPM_ACK)
415 return -ETIMEDOUT;
416
417 return 0;
418}
419
420static void flexcan_enable_wakeup_irq(struct flexcan_priv *priv, bool enable)
421{
422 struct flexcan_regs __iomem *regs = priv->regs;
423 u32 reg_mcr;
424
425 reg_mcr = priv->read(®s->mcr);
426
427 if (enable)
428 reg_mcr |= FLEXCAN_MCR_WAK_MSK;
429 else
430 reg_mcr &= ~FLEXCAN_MCR_WAK_MSK;
431
432 priv->write(reg_mcr, ®s->mcr);
433}
434
435static inline int flexcan_enter_stop_mode(struct flexcan_priv *priv)
436{
437 struct flexcan_regs __iomem *regs = priv->regs;
438 u32 reg_mcr;
439
440 reg_mcr = priv->read(®s->mcr);
441 reg_mcr |= FLEXCAN_MCR_SLF_WAK;
442 priv->write(reg_mcr, ®s->mcr);
443
444 /* enable stop request */
445 regmap_update_bits(priv->stm.gpr, priv->stm.req_gpr,
446 1 << priv->stm.req_bit, 1 << priv->stm.req_bit);
447
448 return flexcan_low_power_enter_ack(priv);
449}
450
451static inline int flexcan_exit_stop_mode(struct flexcan_priv *priv)
452{
453 struct flexcan_regs __iomem *regs = priv->regs;
454 u32 reg_mcr;
455
456 /* remove stop request */
457 regmap_update_bits(priv->stm.gpr, priv->stm.req_gpr,
458 1 << priv->stm.req_bit, 0);
459
460
461 reg_mcr = priv->read(®s->mcr);
462 reg_mcr &= ~FLEXCAN_MCR_SLF_WAK;
463 priv->write(reg_mcr, ®s->mcr);
464
465 return flexcan_low_power_exit_ack(priv);
466}
467
468static inline void flexcan_error_irq_enable(const struct flexcan_priv *priv)
469{
470 struct flexcan_regs __iomem *regs = priv->regs;
471 u32 reg_ctrl = (priv->reg_ctrl_default | FLEXCAN_CTRL_ERR_MSK);
472
473 priv->write(reg_ctrl, ®s->ctrl);
474}
475
476static inline void flexcan_error_irq_disable(const struct flexcan_priv *priv)
477{
478 struct flexcan_regs __iomem *regs = priv->regs;
479 u32 reg_ctrl = (priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_MSK);
480
481 priv->write(reg_ctrl, ®s->ctrl);
482}
483
484static int flexcan_clks_enable(const struct flexcan_priv *priv)
485{
486 int err;
487
488 err = clk_prepare_enable(priv->clk_ipg);
489 if (err)
490 return err;
491
492 err = clk_prepare_enable(priv->clk_per);
493 if (err)
494 clk_disable_unprepare(priv->clk_ipg);
495
496 return err;
497}
498
499static void flexcan_clks_disable(const struct flexcan_priv *priv)
500{
501 clk_disable_unprepare(priv->clk_per);
502 clk_disable_unprepare(priv->clk_ipg);
503}
504
505static inline int flexcan_transceiver_enable(const struct flexcan_priv *priv)
506{
507 if (!priv->reg_xceiver)
508 return 0;
509
510 return regulator_enable(priv->reg_xceiver);
511}
512
513static inline int flexcan_transceiver_disable(const struct flexcan_priv *priv)
514{
515 if (!priv->reg_xceiver)
516 return 0;
517
518 return regulator_disable(priv->reg_xceiver);
519}
520
521static int flexcan_chip_enable(struct flexcan_priv *priv)
522{
523 struct flexcan_regs __iomem *regs = priv->regs;
524 u32 reg;
525
526 reg = priv->read(®s->mcr);
527 reg &= ~FLEXCAN_MCR_MDIS;
528 priv->write(reg, ®s->mcr);
529
530 return flexcan_low_power_exit_ack(priv);
531}
532
533static int flexcan_chip_disable(struct flexcan_priv *priv)
534{
535 struct flexcan_regs __iomem *regs = priv->regs;
536 u32 reg;
537
538 reg = priv->read(®s->mcr);
539 reg |= FLEXCAN_MCR_MDIS;
540 priv->write(reg, ®s->mcr);
541
542 return flexcan_low_power_enter_ack(priv);
543}
544
545static int flexcan_chip_freeze(struct flexcan_priv *priv)
546{
547 struct flexcan_regs __iomem *regs = priv->regs;
548 unsigned int timeout = 1000 * 1000 * 10 / priv->can.bittiming.bitrate;
549 u32 reg;
550
551 reg = priv->read(®s->mcr);
552 reg |= FLEXCAN_MCR_HALT;
553 priv->write(reg, ®s->mcr);
554
555 while (timeout-- && !(priv->read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
556 udelay(100);
557
558 if (!(priv->read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
559 return -ETIMEDOUT;
560
561 return 0;
562}
563
564static int flexcan_chip_unfreeze(struct flexcan_priv *priv)
565{
566 struct flexcan_regs __iomem *regs = priv->regs;
567 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
568 u32 reg;
569
570 reg = priv->read(®s->mcr);
571 reg &= ~FLEXCAN_MCR_HALT;
572 priv->write(reg, ®s->mcr);
573
574 while (timeout-- && (priv->read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
575 udelay(10);
576
577 if (priv->read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK)
578 return -ETIMEDOUT;
579
580 return 0;
581}
582
583static int flexcan_chip_softreset(struct flexcan_priv *priv)
584{
585 struct flexcan_regs __iomem *regs = priv->regs;
586 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
587
588 priv->write(FLEXCAN_MCR_SOFTRST, ®s->mcr);
589 while (timeout-- && (priv->read(®s->mcr) & FLEXCAN_MCR_SOFTRST))
590 udelay(10);
591
592 if (priv->read(®s->mcr) & FLEXCAN_MCR_SOFTRST)
593 return -ETIMEDOUT;
594
595 return 0;
596}
597
598static int __flexcan_get_berr_counter(const struct net_device *dev,
599 struct can_berr_counter *bec)
600{
601 const struct flexcan_priv *priv = netdev_priv(dev);
602 struct flexcan_regs __iomem *regs = priv->regs;
603 u32 reg = priv->read(®s->ecr);
604
605 bec->txerr = (reg >> 0) & 0xff;
606 bec->rxerr = (reg >> 8) & 0xff;
607
608 return 0;
609}
610
611static int flexcan_get_berr_counter(const struct net_device *dev,
612 struct can_berr_counter *bec)
613{
614 const struct flexcan_priv *priv = netdev_priv(dev);
615 int err;
616
617 err = pm_runtime_get_sync(priv->dev);
618 if (err < 0)
619 return err;
620
621 err = __flexcan_get_berr_counter(dev, bec);
622
623 pm_runtime_put(priv->dev);
624
625 return err;
626}
627
628static netdev_tx_t flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
629{
630 const struct flexcan_priv *priv = netdev_priv(dev);
631 struct can_frame *cf = (struct can_frame *)skb->data;
632 u32 can_id;
633 u32 data;
634 u32 ctrl = FLEXCAN_MB_CODE_TX_DATA | (cf->can_dlc << 16);
635 int i;
636
637 if (can_dropped_invalid_skb(dev, skb))
638 return NETDEV_TX_OK;
639
640 netif_stop_queue(dev);
641
642 if (cf->can_id & CAN_EFF_FLAG) {
643 can_id = cf->can_id & CAN_EFF_MASK;
644 ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR;
645 } else {
646 can_id = (cf->can_id & CAN_SFF_MASK) << 18;
647 }
648
649 if (cf->can_id & CAN_RTR_FLAG)
650 ctrl |= FLEXCAN_MB_CNT_RTR;
651
652 for (i = 0; i < cf->can_dlc; i += sizeof(u32)) {
653 data = be32_to_cpup((__be32 *)&cf->data[i]);
654 priv->write(data, &priv->tx_mb->data[i / sizeof(u32)]);
655 }
656
657 can_put_echo_skb(skb, dev, 0);
658
659 priv->write(can_id, &priv->tx_mb->can_id);
660 priv->write(ctrl, &priv->tx_mb->can_ctrl);
661
662 /* Errata ERR005829 step8:
663 * Write twice INACTIVE(0x8) code to first MB.
664 */
665 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
666 &priv->tx_mb_reserved->can_ctrl);
667 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
668 &priv->tx_mb_reserved->can_ctrl);
669
670 return NETDEV_TX_OK;
671}
672
673static void flexcan_irq_bus_err(struct net_device *dev, u32 reg_esr)
674{
675 struct flexcan_priv *priv = netdev_priv(dev);
676 struct flexcan_regs __iomem *regs = priv->regs;
677 struct sk_buff *skb;
678 struct can_frame *cf;
679 bool rx_errors = false, tx_errors = false;
680 u32 timestamp;
681 int err;
682
683 timestamp = priv->read(®s->timer) << 16;
684
685 skb = alloc_can_err_skb(dev, &cf);
686 if (unlikely(!skb))
687 return;
688
689 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
690
691 if (reg_esr & FLEXCAN_ESR_BIT1_ERR) {
692 netdev_dbg(dev, "BIT1_ERR irq\n");
693 cf->data[2] |= CAN_ERR_PROT_BIT1;
694 tx_errors = true;
695 }
696 if (reg_esr & FLEXCAN_ESR_BIT0_ERR) {
697 netdev_dbg(dev, "BIT0_ERR irq\n");
698 cf->data[2] |= CAN_ERR_PROT_BIT0;
699 tx_errors = true;
700 }
701 if (reg_esr & FLEXCAN_ESR_ACK_ERR) {
702 netdev_dbg(dev, "ACK_ERR irq\n");
703 cf->can_id |= CAN_ERR_ACK;
704 cf->data[3] = CAN_ERR_PROT_LOC_ACK;
705 tx_errors = true;
706 }
707 if (reg_esr & FLEXCAN_ESR_CRC_ERR) {
708 netdev_dbg(dev, "CRC_ERR irq\n");
709 cf->data[2] |= CAN_ERR_PROT_BIT;
710 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ;
711 rx_errors = true;
712 }
713 if (reg_esr & FLEXCAN_ESR_FRM_ERR) {
714 netdev_dbg(dev, "FRM_ERR irq\n");
715 cf->data[2] |= CAN_ERR_PROT_FORM;
716 rx_errors = true;
717 }
718 if (reg_esr & FLEXCAN_ESR_STF_ERR) {
719 netdev_dbg(dev, "STF_ERR irq\n");
720 cf->data[2] |= CAN_ERR_PROT_STUFF;
721 rx_errors = true;
722 }
723
724 priv->can.can_stats.bus_error++;
725 if (rx_errors)
726 dev->stats.rx_errors++;
727 if (tx_errors)
728 dev->stats.tx_errors++;
729
730 err = can_rx_offload_queue_sorted(&priv->offload, skb, timestamp);
731 if (err)
732 dev->stats.rx_fifo_errors++;
733}
734
735static void flexcan_irq_state(struct net_device *dev, u32 reg_esr)
736{
737 struct flexcan_priv *priv = netdev_priv(dev);
738 struct flexcan_regs __iomem *regs = priv->regs;
739 struct sk_buff *skb;
740 struct can_frame *cf;
741 enum can_state new_state, rx_state, tx_state;
742 int flt;
743 struct can_berr_counter bec;
744 u32 timestamp;
745 int err;
746
747 flt = reg_esr & FLEXCAN_ESR_FLT_CONF_MASK;
748 if (likely(flt == FLEXCAN_ESR_FLT_CONF_ACTIVE)) {
749 tx_state = unlikely(reg_esr & FLEXCAN_ESR_TX_WRN) ?
750 CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
751 rx_state = unlikely(reg_esr & FLEXCAN_ESR_RX_WRN) ?
752 CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
753 new_state = max(tx_state, rx_state);
754 } else {
755 __flexcan_get_berr_counter(dev, &bec);
756 new_state = flt == FLEXCAN_ESR_FLT_CONF_PASSIVE ?
757 CAN_STATE_ERROR_PASSIVE : CAN_STATE_BUS_OFF;
758 rx_state = bec.rxerr >= bec.txerr ? new_state : 0;
759 tx_state = bec.rxerr <= bec.txerr ? new_state : 0;
760 }
761
762 /* state hasn't changed */
763 if (likely(new_state == priv->can.state))
764 return;
765
766 timestamp = priv->read(®s->timer) << 16;
767
768 skb = alloc_can_err_skb(dev, &cf);
769 if (unlikely(!skb))
770 return;
771
772 can_change_state(dev, cf, tx_state, rx_state);
773
774 if (unlikely(new_state == CAN_STATE_BUS_OFF))
775 can_bus_off(dev);
776
777 err = can_rx_offload_queue_sorted(&priv->offload, skb, timestamp);
778 if (err)
779 dev->stats.rx_fifo_errors++;
780}
781
782static inline u64 flexcan_read64_mask(struct flexcan_priv *priv, void __iomem *addr, u64 mask)
783{
784 u64 reg = 0;
785
786 if (upper_32_bits(mask))
787 reg = (u64)priv->read(addr - 4) << 32;
788 if (lower_32_bits(mask))
789 reg |= priv->read(addr);
790
791 return reg & mask;
792}
793
794static inline void flexcan_write64(struct flexcan_priv *priv, u64 val, void __iomem *addr)
795{
796 if (upper_32_bits(val))
797 priv->write(upper_32_bits(val), addr - 4);
798 if (lower_32_bits(val))
799 priv->write(lower_32_bits(val), addr);
800}
801
802static inline u64 flexcan_read_reg_iflag_rx(struct flexcan_priv *priv)
803{
804 return flexcan_read64_mask(priv, &priv->regs->iflag1, priv->rx_mask);
805}
806
807static inline u64 flexcan_read_reg_iflag_tx(struct flexcan_priv *priv)
808{
809 return flexcan_read64_mask(priv, &priv->regs->iflag1, priv->tx_mask);
810}
811
812static inline struct flexcan_priv *rx_offload_to_priv(struct can_rx_offload *offload)
813{
814 return container_of(offload, struct flexcan_priv, offload);
815}
816
817static struct sk_buff *flexcan_mailbox_read(struct can_rx_offload *offload,
818 unsigned int n, u32 *timestamp,
819 bool drop)
820{
821 struct flexcan_priv *priv = rx_offload_to_priv(offload);
822 struct flexcan_regs __iomem *regs = priv->regs;
823 struct flexcan_mb __iomem *mb;
824 struct sk_buff *skb;
825 struct can_frame *cf;
826 u32 reg_ctrl, reg_id, reg_iflag1;
827 int i;
828
829 if (unlikely(drop)) {
830 skb = ERR_PTR(-ENOBUFS);
831 goto mark_as_read;
832 }
833
834 mb = flexcan_get_mb(priv, n);
835
836 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
837 u32 code;
838
839 do {
840 reg_ctrl = priv->read(&mb->can_ctrl);
841 } while (reg_ctrl & FLEXCAN_MB_CODE_RX_BUSY_BIT);
842
843 /* is this MB empty? */
844 code = reg_ctrl & FLEXCAN_MB_CODE_MASK;
845 if ((code != FLEXCAN_MB_CODE_RX_FULL) &&
846 (code != FLEXCAN_MB_CODE_RX_OVERRUN))
847 return NULL;
848
849 if (code == FLEXCAN_MB_CODE_RX_OVERRUN) {
850 /* This MB was overrun, we lost data */
851 offload->dev->stats.rx_over_errors++;
852 offload->dev->stats.rx_errors++;
853 }
854 } else {
855 reg_iflag1 = priv->read(®s->iflag1);
856 if (!(reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE))
857 return NULL;
858
859 reg_ctrl = priv->read(&mb->can_ctrl);
860 }
861
862 skb = alloc_can_skb(offload->dev, &cf);
863 if (!skb) {
864 skb = ERR_PTR(-ENOMEM);
865 goto mark_as_read;
866 }
867
868 /* increase timstamp to full 32 bit */
869 *timestamp = reg_ctrl << 16;
870
871 reg_id = priv->read(&mb->can_id);
872 if (reg_ctrl & FLEXCAN_MB_CNT_IDE)
873 cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
874 else
875 cf->can_id = (reg_id >> 18) & CAN_SFF_MASK;
876
877 if (reg_ctrl & FLEXCAN_MB_CNT_RTR)
878 cf->can_id |= CAN_RTR_FLAG;
879 cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf);
880
881 for (i = 0; i < cf->can_dlc; i += sizeof(u32)) {
882 __be32 data = cpu_to_be32(priv->read(&mb->data[i / sizeof(u32)]));
883 *(__be32 *)(cf->data + i) = data;
884 }
885
886 mark_as_read:
887 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP)
888 flexcan_write64(priv, FLEXCAN_IFLAG_MB(n), ®s->iflag1);
889 else
890 priv->write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->iflag1);
891
892 /* Read the Free Running Timer. It is optional but recommended
893 * to unlock Mailbox as soon as possible and make it available
894 * for reception.
895 */
896 priv->read(®s->timer);
897
898 return skb;
899}
900
901static irqreturn_t flexcan_irq(int irq, void *dev_id)
902{
903 struct net_device *dev = dev_id;
904 struct net_device_stats *stats = &dev->stats;
905 struct flexcan_priv *priv = netdev_priv(dev);
906 struct flexcan_regs __iomem *regs = priv->regs;
907 irqreturn_t handled = IRQ_NONE;
908 u64 reg_iflag_tx;
909 u32 reg_esr;
910 enum can_state last_state = priv->can.state;
911
912 /* reception interrupt */
913 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
914 u64 reg_iflag_rx;
915 int ret;
916
917 while ((reg_iflag_rx = flexcan_read_reg_iflag_rx(priv))) {
918 handled = IRQ_HANDLED;
919 ret = can_rx_offload_irq_offload_timestamp(&priv->offload,
920 reg_iflag_rx);
921 if (!ret)
922 break;
923 }
924 } else {
925 u32 reg_iflag1;
926
927 reg_iflag1 = priv->read(®s->iflag1);
928 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) {
929 handled = IRQ_HANDLED;
930 can_rx_offload_irq_offload_fifo(&priv->offload);
931 }
932
933 /* FIFO overflow interrupt */
934 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) {
935 handled = IRQ_HANDLED;
936 priv->write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW,
937 ®s->iflag1);
938 dev->stats.rx_over_errors++;
939 dev->stats.rx_errors++;
940 }
941 }
942
943 reg_iflag_tx = flexcan_read_reg_iflag_tx(priv);
944
945 /* transmission complete interrupt */
946 if (reg_iflag_tx & priv->tx_mask) {
947 u32 reg_ctrl = priv->read(&priv->tx_mb->can_ctrl);
948
949 handled = IRQ_HANDLED;
950 stats->tx_bytes += can_rx_offload_get_echo_skb(&priv->offload,
951 0, reg_ctrl << 16);
952 stats->tx_packets++;
953 can_led_event(dev, CAN_LED_EVENT_TX);
954
955 /* after sending a RTR frame MB is in RX mode */
956 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
957 &priv->tx_mb->can_ctrl);
958 flexcan_write64(priv, priv->tx_mask, ®s->iflag1);
959 netif_wake_queue(dev);
960 }
961
962 reg_esr = priv->read(®s->esr);
963
964 /* ACK all bus error and state change IRQ sources */
965 if (reg_esr & FLEXCAN_ESR_ALL_INT) {
966 handled = IRQ_HANDLED;
967 priv->write(reg_esr & FLEXCAN_ESR_ALL_INT, ®s->esr);
968 }
969
970 /* state change interrupt or broken error state quirk fix is enabled */
971 if ((reg_esr & FLEXCAN_ESR_ERR_STATE) ||
972 (priv->devtype_data->quirks & (FLEXCAN_QUIRK_BROKEN_WERR_STATE |
973 FLEXCAN_QUIRK_BROKEN_PERR_STATE)))
974 flexcan_irq_state(dev, reg_esr);
975
976 /* bus error IRQ - handle if bus error reporting is activated */
977 if ((reg_esr & FLEXCAN_ESR_ERR_BUS) &&
978 (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING))
979 flexcan_irq_bus_err(dev, reg_esr);
980
981 /* availability of error interrupt among state transitions in case
982 * bus error reporting is de-activated and
983 * FLEXCAN_QUIRK_BROKEN_PERR_STATE is enabled:
984 * +--------------------------------------------------------------+
985 * | +----------------------------------------------+ [stopped / |
986 * | | | sleeping] -+
987 * +-+-> active <-> warning <-> passive -> bus off -+
988 * ___________^^^^^^^^^^^^_______________________________
989 * disabled(1) enabled disabled
990 *
991 * (1): enabled if FLEXCAN_QUIRK_BROKEN_WERR_STATE is enabled
992 */
993 if ((last_state != priv->can.state) &&
994 (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_PERR_STATE) &&
995 !(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) {
996 switch (priv->can.state) {
997 case CAN_STATE_ERROR_ACTIVE:
998 if (priv->devtype_data->quirks &
999 FLEXCAN_QUIRK_BROKEN_WERR_STATE)
1000 flexcan_error_irq_enable(priv);
1001 else
1002 flexcan_error_irq_disable(priv);
1003 break;
1004
1005 case CAN_STATE_ERROR_WARNING:
1006 flexcan_error_irq_enable(priv);
1007 break;
1008
1009 case CAN_STATE_ERROR_PASSIVE:
1010 case CAN_STATE_BUS_OFF:
1011 flexcan_error_irq_disable(priv);
1012 break;
1013
1014 default:
1015 break;
1016 }
1017 }
1018
1019 return handled;
1020}
1021
1022static void flexcan_set_bittiming(struct net_device *dev)
1023{
1024 const struct flexcan_priv *priv = netdev_priv(dev);
1025 const struct can_bittiming *bt = &priv->can.bittiming;
1026 struct flexcan_regs __iomem *regs = priv->regs;
1027 u32 reg;
1028
1029 reg = priv->read(®s->ctrl);
1030 reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) |
1031 FLEXCAN_CTRL_RJW(0x3) |
1032 FLEXCAN_CTRL_PSEG1(0x7) |
1033 FLEXCAN_CTRL_PSEG2(0x7) |
1034 FLEXCAN_CTRL_PROPSEG(0x7) |
1035 FLEXCAN_CTRL_LPB |
1036 FLEXCAN_CTRL_SMP |
1037 FLEXCAN_CTRL_LOM);
1038
1039 reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) |
1040 FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) |
1041 FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) |
1042 FLEXCAN_CTRL_RJW(bt->sjw - 1) |
1043 FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1);
1044
1045 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
1046 reg |= FLEXCAN_CTRL_LPB;
1047 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
1048 reg |= FLEXCAN_CTRL_LOM;
1049 if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
1050 reg |= FLEXCAN_CTRL_SMP;
1051
1052 netdev_dbg(dev, "writing ctrl=0x%08x\n", reg);
1053 priv->write(reg, ®s->ctrl);
1054
1055 /* print chip status */
1056 netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__,
1057 priv->read(®s->mcr), priv->read(®s->ctrl));
1058}
1059
1060/* flexcan_chip_start
1061 *
1062 * this functions is entered with clocks enabled
1063 *
1064 */
1065static int flexcan_chip_start(struct net_device *dev)
1066{
1067 struct flexcan_priv *priv = netdev_priv(dev);
1068 struct flexcan_regs __iomem *regs = priv->regs;
1069 u32 reg_mcr, reg_ctrl, reg_ctrl2, reg_mecr;
1070 u64 reg_imask;
1071 int err, i;
1072 struct flexcan_mb __iomem *mb;
1073
1074 /* enable module */
1075 err = flexcan_chip_enable(priv);
1076 if (err)
1077 return err;
1078
1079 /* soft reset */
1080 err = flexcan_chip_softreset(priv);
1081 if (err)
1082 goto out_chip_disable;
1083
1084 flexcan_set_bittiming(dev);
1085
1086 /* MCR
1087 *
1088 * enable freeze
1089 * halt now
1090 * only supervisor access
1091 * enable warning int
1092 * enable individual RX masking
1093 * choose format C
1094 * set max mailbox number
1095 */
1096 reg_mcr = priv->read(®s->mcr);
1097 reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff);
1098 reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT | FLEXCAN_MCR_SUPV |
1099 FLEXCAN_MCR_WRN_EN | FLEXCAN_MCR_IRMQ | FLEXCAN_MCR_IDAM_C |
1100 FLEXCAN_MCR_MAXMB(priv->tx_mb_idx);
1101
1102 /* MCR
1103 *
1104 * FIFO:
1105 * - disable for timestamp mode
1106 * - enable for FIFO mode
1107 */
1108 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP)
1109 reg_mcr &= ~FLEXCAN_MCR_FEN;
1110 else
1111 reg_mcr |= FLEXCAN_MCR_FEN;
1112
1113 /* MCR
1114 *
1115 * NOTE: In loopback mode, the CAN_MCR[SRXDIS] cannot be
1116 * asserted because this will impede the self reception
1117 * of a transmitted message. This is not documented in
1118 * earlier versions of flexcan block guide.
1119 *
1120 * Self Reception:
1121 * - enable Self Reception for loopback mode
1122 * (by clearing "Self Reception Disable" bit)
1123 * - disable for normal operation
1124 */
1125 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
1126 reg_mcr &= ~FLEXCAN_MCR_SRX_DIS;
1127 else
1128 reg_mcr |= FLEXCAN_MCR_SRX_DIS;
1129
1130 netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr);
1131 priv->write(reg_mcr, ®s->mcr);
1132
1133 /* CTRL
1134 *
1135 * disable timer sync feature
1136 *
1137 * disable auto busoff recovery
1138 * transmit lowest buffer first
1139 *
1140 * enable tx and rx warning interrupt
1141 * enable bus off interrupt
1142 * (== FLEXCAN_CTRL_ERR_STATE)
1143 */
1144 reg_ctrl = priv->read(®s->ctrl);
1145 reg_ctrl &= ~FLEXCAN_CTRL_TSYN;
1146 reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF |
1147 FLEXCAN_CTRL_ERR_STATE;
1148
1149 /* enable the "error interrupt" (FLEXCAN_CTRL_ERR_MSK),
1150 * on most Flexcan cores, too. Otherwise we don't get
1151 * any error warning or passive interrupts.
1152 */
1153 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_WERR_STATE ||
1154 priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
1155 reg_ctrl |= FLEXCAN_CTRL_ERR_MSK;
1156 else
1157 reg_ctrl &= ~FLEXCAN_CTRL_ERR_MSK;
1158
1159 /* save for later use */
1160 priv->reg_ctrl_default = reg_ctrl;
1161 /* leave interrupts disabled for now */
1162 reg_ctrl &= ~FLEXCAN_CTRL_ERR_ALL;
1163 netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl);
1164 priv->write(reg_ctrl, ®s->ctrl);
1165
1166 if ((priv->devtype_data->quirks & FLEXCAN_QUIRK_ENABLE_EACEN_RRS)) {
1167 reg_ctrl2 = priv->read(®s->ctrl2);
1168 reg_ctrl2 |= FLEXCAN_CTRL2_EACEN | FLEXCAN_CTRL2_RRS;
1169 priv->write(reg_ctrl2, ®s->ctrl2);
1170 }
1171
1172 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
1173 for (i = priv->offload.mb_first; i <= priv->offload.mb_last; i++) {
1174 mb = flexcan_get_mb(priv, i);
1175 priv->write(FLEXCAN_MB_CODE_RX_EMPTY,
1176 &mb->can_ctrl);
1177 }
1178 } else {
1179 /* clear and invalidate unused mailboxes first */
1180 for (i = FLEXCAN_TX_MB_RESERVED_OFF_FIFO; i < priv->mb_count; i++) {
1181 mb = flexcan_get_mb(priv, i);
1182 priv->write(FLEXCAN_MB_CODE_RX_INACTIVE,
1183 &mb->can_ctrl);
1184 }
1185 }
1186
1187 /* Errata ERR005829: mark first TX mailbox as INACTIVE */
1188 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
1189 &priv->tx_mb_reserved->can_ctrl);
1190
1191 /* mark TX mailbox as INACTIVE */
1192 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
1193 &priv->tx_mb->can_ctrl);
1194
1195 /* acceptance mask/acceptance code (accept everything) */
1196 priv->write(0x0, ®s->rxgmask);
1197 priv->write(0x0, ®s->rx14mask);
1198 priv->write(0x0, ®s->rx15mask);
1199
1200 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_RXFG)
1201 priv->write(0x0, ®s->rxfgmask);
1202
1203 /* clear acceptance filters */
1204 for (i = 0; i < priv->mb_count; i++)
1205 priv->write(0, ®s->rximr[i]);
1206
1207 /* On Vybrid, disable memory error detection interrupts
1208 * and freeze mode.
1209 * This also works around errata e5295 which generates
1210 * false positive memory errors and put the device in
1211 * freeze mode.
1212 */
1213 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_MECR) {
1214 /* Follow the protocol as described in "Detection
1215 * and Correction of Memory Errors" to write to
1216 * MECR register
1217 */
1218 reg_ctrl2 = priv->read(®s->ctrl2);
1219 reg_ctrl2 |= FLEXCAN_CTRL2_ECRWRE;
1220 priv->write(reg_ctrl2, ®s->ctrl2);
1221
1222 reg_mecr = priv->read(®s->mecr);
1223 reg_mecr &= ~FLEXCAN_MECR_ECRWRDIS;
1224 priv->write(reg_mecr, ®s->mecr);
1225 reg_mecr |= FLEXCAN_MECR_ECCDIS;
1226 reg_mecr &= ~(FLEXCAN_MECR_NCEFAFRZ | FLEXCAN_MECR_HANCEI_MSK |
1227 FLEXCAN_MECR_FANCEI_MSK);
1228 priv->write(reg_mecr, ®s->mecr);
1229 }
1230
1231 err = flexcan_transceiver_enable(priv);
1232 if (err)
1233 goto out_chip_disable;
1234
1235 /* synchronize with the can bus */
1236 err = flexcan_chip_unfreeze(priv);
1237 if (err)
1238 goto out_transceiver_disable;
1239
1240 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1241
1242 /* enable interrupts atomically */
1243 disable_irq(dev->irq);
1244 priv->write(priv->reg_ctrl_default, ®s->ctrl);
1245 reg_imask = priv->rx_mask | priv->tx_mask;
1246 priv->write(upper_32_bits(reg_imask), ®s->imask2);
1247 priv->write(lower_32_bits(reg_imask), ®s->imask1);
1248 enable_irq(dev->irq);
1249
1250 /* print chip status */
1251 netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__,
1252 priv->read(®s->mcr), priv->read(®s->ctrl));
1253
1254 return 0;
1255
1256 out_transceiver_disable:
1257 flexcan_transceiver_disable(priv);
1258 out_chip_disable:
1259 flexcan_chip_disable(priv);
1260 return err;
1261}
1262
1263/* flexcan_chip_stop
1264 *
1265 * this functions is entered with clocks enabled
1266 */
1267static void flexcan_chip_stop(struct net_device *dev)
1268{
1269 struct flexcan_priv *priv = netdev_priv(dev);
1270 struct flexcan_regs __iomem *regs = priv->regs;
1271
1272 /* freeze + disable module */
1273 flexcan_chip_freeze(priv);
1274 flexcan_chip_disable(priv);
1275
1276 /* Disable all interrupts */
1277 priv->write(0, ®s->imask2);
1278 priv->write(0, ®s->imask1);
1279 priv->write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
1280 ®s->ctrl);
1281
1282 flexcan_transceiver_disable(priv);
1283 priv->can.state = CAN_STATE_STOPPED;
1284}
1285
1286static int flexcan_open(struct net_device *dev)
1287{
1288 struct flexcan_priv *priv = netdev_priv(dev);
1289 int err;
1290
1291 err = pm_runtime_get_sync(priv->dev);
1292 if (err < 0)
1293 return err;
1294
1295 err = open_candev(dev);
1296 if (err)
1297 goto out_runtime_put;
1298
1299 err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev);
1300 if (err)
1301 goto out_close;
1302
1303 priv->mb_size = sizeof(struct flexcan_mb) + CAN_MAX_DLEN;
1304 priv->mb_count = (sizeof(priv->regs->mb[0]) / priv->mb_size) +
1305 (sizeof(priv->regs->mb[1]) / priv->mb_size);
1306
1307 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP)
1308 priv->tx_mb_reserved =
1309 flexcan_get_mb(priv, FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP);
1310 else
1311 priv->tx_mb_reserved =
1312 flexcan_get_mb(priv, FLEXCAN_TX_MB_RESERVED_OFF_FIFO);
1313 priv->tx_mb_idx = priv->mb_count - 1;
1314 priv->tx_mb = flexcan_get_mb(priv, priv->tx_mb_idx);
1315 priv->tx_mask = FLEXCAN_IFLAG_MB(priv->tx_mb_idx);
1316
1317 priv->offload.mailbox_read = flexcan_mailbox_read;
1318
1319 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
1320 priv->offload.mb_first = FLEXCAN_RX_MB_OFF_TIMESTAMP_FIRST;
1321 priv->offload.mb_last = priv->mb_count - 2;
1322
1323 priv->rx_mask = GENMASK_ULL(priv->offload.mb_last,
1324 priv->offload.mb_first);
1325 err = can_rx_offload_add_timestamp(dev, &priv->offload);
1326 } else {
1327 priv->rx_mask = FLEXCAN_IFLAG_RX_FIFO_OVERFLOW |
1328 FLEXCAN_IFLAG_RX_FIFO_AVAILABLE;
1329 err = can_rx_offload_add_fifo(dev, &priv->offload,
1330 FLEXCAN_NAPI_WEIGHT);
1331 }
1332 if (err)
1333 goto out_free_irq;
1334
1335 /* start chip and queuing */
1336 err = flexcan_chip_start(dev);
1337 if (err)
1338 goto out_offload_del;
1339
1340 can_led_event(dev, CAN_LED_EVENT_OPEN);
1341
1342 can_rx_offload_enable(&priv->offload);
1343 netif_start_queue(dev);
1344
1345 return 0;
1346
1347 out_offload_del:
1348 can_rx_offload_del(&priv->offload);
1349 out_free_irq:
1350 free_irq(dev->irq, dev);
1351 out_close:
1352 close_candev(dev);
1353 out_runtime_put:
1354 pm_runtime_put(priv->dev);
1355
1356 return err;
1357}
1358
1359static int flexcan_close(struct net_device *dev)
1360{
1361 struct flexcan_priv *priv = netdev_priv(dev);
1362
1363 netif_stop_queue(dev);
1364 can_rx_offload_disable(&priv->offload);
1365 flexcan_chip_stop(dev);
1366
1367 can_rx_offload_del(&priv->offload);
1368 free_irq(dev->irq, dev);
1369
1370 close_candev(dev);
1371 pm_runtime_put(priv->dev);
1372
1373 can_led_event(dev, CAN_LED_EVENT_STOP);
1374
1375 return 0;
1376}
1377
1378static int flexcan_set_mode(struct net_device *dev, enum can_mode mode)
1379{
1380 int err;
1381
1382 switch (mode) {
1383 case CAN_MODE_START:
1384 err = flexcan_chip_start(dev);
1385 if (err)
1386 return err;
1387
1388 netif_wake_queue(dev);
1389 break;
1390
1391 default:
1392 return -EOPNOTSUPP;
1393 }
1394
1395 return 0;
1396}
1397
1398static const struct net_device_ops flexcan_netdev_ops = {
1399 .ndo_open = flexcan_open,
1400 .ndo_stop = flexcan_close,
1401 .ndo_start_xmit = flexcan_start_xmit,
1402 .ndo_change_mtu = can_change_mtu,
1403};
1404
1405static int register_flexcandev(struct net_device *dev)
1406{
1407 struct flexcan_priv *priv = netdev_priv(dev);
1408 struct flexcan_regs __iomem *regs = priv->regs;
1409 u32 reg, err;
1410
1411 err = flexcan_clks_enable(priv);
1412 if (err)
1413 return err;
1414
1415 /* select "bus clock", chip must be disabled */
1416 err = flexcan_chip_disable(priv);
1417 if (err)
1418 goto out_clks_disable;
1419
1420 reg = priv->read(®s->ctrl);
1421 if (priv->clk_src)
1422 reg |= FLEXCAN_CTRL_CLK_SRC;
1423 else
1424 reg &= ~FLEXCAN_CTRL_CLK_SRC;
1425 priv->write(reg, ®s->ctrl);
1426
1427 err = flexcan_chip_enable(priv);
1428 if (err)
1429 goto out_chip_disable;
1430
1431 /* set freeze, halt and activate FIFO, restrict register access */
1432 reg = priv->read(®s->mcr);
1433 reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT |
1434 FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV;
1435 priv->write(reg, ®s->mcr);
1436
1437 /* Currently we only support newer versions of this core
1438 * featuring a RX hardware FIFO (although this driver doesn't
1439 * make use of it on some cores). Older cores, found on some
1440 * Coldfire derivates are not tested.
1441 */
1442 reg = priv->read(®s->mcr);
1443 if (!(reg & FLEXCAN_MCR_FEN)) {
1444 netdev_err(dev, "Could not enable RX FIFO, unsupported core\n");
1445 err = -ENODEV;
1446 goto out_chip_disable;
1447 }
1448
1449 err = register_candev(dev);
1450 if (err)
1451 goto out_chip_disable;
1452
1453 /* Disable core and let pm_runtime_put() disable the clocks.
1454 * If CONFIG_PM is not enabled, the clocks will stay powered.
1455 */
1456 flexcan_chip_disable(priv);
1457 pm_runtime_put(priv->dev);
1458
1459 return 0;
1460
1461 out_chip_disable:
1462 flexcan_chip_disable(priv);
1463 out_clks_disable:
1464 flexcan_clks_disable(priv);
1465 return err;
1466}
1467
1468static void unregister_flexcandev(struct net_device *dev)
1469{
1470 unregister_candev(dev);
1471}
1472
1473static int flexcan_setup_stop_mode(struct platform_device *pdev)
1474{
1475 struct net_device *dev = platform_get_drvdata(pdev);
1476 struct device_node *np = pdev->dev.of_node;
1477 struct device_node *gpr_np;
1478 struct flexcan_priv *priv;
1479 phandle phandle;
1480 u32 out_val[5];
1481 int ret;
1482
1483 if (!np)
1484 return -EINVAL;
1485
1486 /* stop mode property format is:
1487 * <&gpr req_gpr req_bit ack_gpr ack_bit>.
1488 */
1489 ret = of_property_read_u32_array(np, "fsl,stop-mode", out_val,
1490 ARRAY_SIZE(out_val));
1491 if (ret) {
1492 dev_dbg(&pdev->dev, "no stop-mode property\n");
1493 return ret;
1494 }
1495 phandle = *out_val;
1496
1497 gpr_np = of_find_node_by_phandle(phandle);
1498 if (!gpr_np) {
1499 dev_dbg(&pdev->dev, "could not find gpr node by phandle\n");
1500 return -ENODEV;
1501 }
1502
1503 priv = netdev_priv(dev);
1504 priv->stm.gpr = syscon_node_to_regmap(gpr_np);
1505 if (IS_ERR(priv->stm.gpr)) {
1506 dev_dbg(&pdev->dev, "could not find gpr regmap\n");
1507 ret = PTR_ERR(priv->stm.gpr);
1508 goto out_put_node;
1509 }
1510
1511 priv->stm.req_gpr = out_val[1];
1512 priv->stm.req_bit = out_val[2];
1513 priv->stm.ack_gpr = out_val[3];
1514 priv->stm.ack_bit = out_val[4];
1515
1516 dev_dbg(&pdev->dev,
1517 "gpr %s req_gpr=0x02%x req_bit=%u ack_gpr=0x02%x ack_bit=%u\n",
1518 gpr_np->full_name, priv->stm.req_gpr, priv->stm.req_bit,
1519 priv->stm.ack_gpr, priv->stm.ack_bit);
1520
1521 device_set_wakeup_capable(&pdev->dev, true);
1522
1523 if (of_property_read_bool(np, "wakeup-source"))
1524 device_set_wakeup_enable(&pdev->dev, true);
1525
1526 return 0;
1527
1528out_put_node:
1529 of_node_put(gpr_np);
1530 return ret;
1531}
1532
1533static const struct of_device_id flexcan_of_match[] = {
1534 { .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, },
1535 { .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, },
1536 { .compatible = "fsl,imx53-flexcan", .data = &fsl_imx25_devtype_data, },
1537 { .compatible = "fsl,imx35-flexcan", .data = &fsl_imx25_devtype_data, },
1538 { .compatible = "fsl,imx25-flexcan", .data = &fsl_imx25_devtype_data, },
1539 { .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, },
1540 { .compatible = "fsl,vf610-flexcan", .data = &fsl_vf610_devtype_data, },
1541 { .compatible = "fsl,ls1021ar2-flexcan", .data = &fsl_ls1021a_r2_devtype_data, },
1542 { /* sentinel */ },
1543};
1544MODULE_DEVICE_TABLE(of, flexcan_of_match);
1545
1546static const struct platform_device_id flexcan_id_table[] = {
1547 { .name = "flexcan", .driver_data = (kernel_ulong_t)&fsl_p1010_devtype_data, },
1548 { /* sentinel */ },
1549};
1550MODULE_DEVICE_TABLE(platform, flexcan_id_table);
1551
1552static int flexcan_probe(struct platform_device *pdev)
1553{
1554 const struct of_device_id *of_id;
1555 const struct flexcan_devtype_data *devtype_data;
1556 struct net_device *dev;
1557 struct flexcan_priv *priv;
1558 struct regulator *reg_xceiver;
1559 struct clk *clk_ipg = NULL, *clk_per = NULL;
1560 struct flexcan_regs __iomem *regs;
1561 int err, irq;
1562 u8 clk_src = 1;
1563 u32 clock_freq = 0;
1564
1565 reg_xceiver = devm_regulator_get(&pdev->dev, "xceiver");
1566 if (PTR_ERR(reg_xceiver) == -EPROBE_DEFER)
1567 return -EPROBE_DEFER;
1568 else if (IS_ERR(reg_xceiver))
1569 reg_xceiver = NULL;
1570
1571 if (pdev->dev.of_node) {
1572 of_property_read_u32(pdev->dev.of_node,
1573 "clock-frequency", &clock_freq);
1574 of_property_read_u8(pdev->dev.of_node,
1575 "fsl,clk-source", &clk_src);
1576 }
1577
1578 if (!clock_freq) {
1579 clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1580 if (IS_ERR(clk_ipg)) {
1581 dev_err(&pdev->dev, "no ipg clock defined\n");
1582 return PTR_ERR(clk_ipg);
1583 }
1584
1585 clk_per = devm_clk_get(&pdev->dev, "per");
1586 if (IS_ERR(clk_per)) {
1587 dev_err(&pdev->dev, "no per clock defined\n");
1588 return PTR_ERR(clk_per);
1589 }
1590 clock_freq = clk_get_rate(clk_per);
1591 }
1592
1593 irq = platform_get_irq(pdev, 0);
1594 if (irq <= 0)
1595 return -ENODEV;
1596
1597 regs = devm_platform_ioremap_resource(pdev, 0);
1598 if (IS_ERR(regs))
1599 return PTR_ERR(regs);
1600
1601 of_id = of_match_device(flexcan_of_match, &pdev->dev);
1602 if (of_id) {
1603 devtype_data = of_id->data;
1604 } else if (platform_get_device_id(pdev)->driver_data) {
1605 devtype_data = (struct flexcan_devtype_data *)
1606 platform_get_device_id(pdev)->driver_data;
1607 } else {
1608 return -ENODEV;
1609 }
1610
1611 dev = alloc_candev(sizeof(struct flexcan_priv), 1);
1612 if (!dev)
1613 return -ENOMEM;
1614
1615 platform_set_drvdata(pdev, dev);
1616 SET_NETDEV_DEV(dev, &pdev->dev);
1617
1618 dev->netdev_ops = &flexcan_netdev_ops;
1619 dev->irq = irq;
1620 dev->flags |= IFF_ECHO;
1621
1622 priv = netdev_priv(dev);
1623
1624 if (of_property_read_bool(pdev->dev.of_node, "big-endian") ||
1625 devtype_data->quirks & FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN) {
1626 priv->read = flexcan_read_be;
1627 priv->write = flexcan_write_be;
1628 } else {
1629 priv->read = flexcan_read_le;
1630 priv->write = flexcan_write_le;
1631 }
1632
1633 priv->dev = &pdev->dev;
1634 priv->can.clock.freq = clock_freq;
1635 priv->can.bittiming_const = &flexcan_bittiming_const;
1636 priv->can.do_set_mode = flexcan_set_mode;
1637 priv->can.do_get_berr_counter = flexcan_get_berr_counter;
1638 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
1639 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_3_SAMPLES |
1640 CAN_CTRLMODE_BERR_REPORTING;
1641 priv->regs = regs;
1642 priv->clk_ipg = clk_ipg;
1643 priv->clk_per = clk_per;
1644 priv->clk_src = clk_src;
1645 priv->devtype_data = devtype_data;
1646 priv->reg_xceiver = reg_xceiver;
1647
1648 pm_runtime_get_noresume(&pdev->dev);
1649 pm_runtime_set_active(&pdev->dev);
1650 pm_runtime_enable(&pdev->dev);
1651
1652 err = register_flexcandev(dev);
1653 if (err) {
1654 dev_err(&pdev->dev, "registering netdev failed\n");
1655 goto failed_register;
1656 }
1657
1658 devm_can_led_init(dev);
1659
1660 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE) {
1661 err = flexcan_setup_stop_mode(pdev);
1662 if (err)
1663 dev_dbg(&pdev->dev, "failed to setup stop-mode\n");
1664 }
1665
1666 return 0;
1667
1668 failed_register:
1669 free_candev(dev);
1670 return err;
1671}
1672
1673static int flexcan_remove(struct platform_device *pdev)
1674{
1675 struct net_device *dev = platform_get_drvdata(pdev);
1676
1677 unregister_flexcandev(dev);
1678 pm_runtime_disable(&pdev->dev);
1679 free_candev(dev);
1680
1681 return 0;
1682}
1683
1684static int __maybe_unused flexcan_suspend(struct device *device)
1685{
1686 struct net_device *dev = dev_get_drvdata(device);
1687 struct flexcan_priv *priv = netdev_priv(dev);
1688 int err = 0;
1689
1690 if (netif_running(dev)) {
1691 /* if wakeup is enabled, enter stop mode
1692 * else enter disabled mode.
1693 */
1694 if (device_may_wakeup(device)) {
1695 enable_irq_wake(dev->irq);
1696 err = flexcan_enter_stop_mode(priv);
1697 if (err)
1698 return err;
1699 } else {
1700 err = flexcan_chip_disable(priv);
1701 if (err)
1702 return err;
1703
1704 err = pm_runtime_force_suspend(device);
1705 }
1706 netif_stop_queue(dev);
1707 netif_device_detach(dev);
1708 }
1709 priv->can.state = CAN_STATE_SLEEPING;
1710
1711 return err;
1712}
1713
1714static int __maybe_unused flexcan_resume(struct device *device)
1715{
1716 struct net_device *dev = dev_get_drvdata(device);
1717 struct flexcan_priv *priv = netdev_priv(dev);
1718 int err = 0;
1719
1720 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1721 if (netif_running(dev)) {
1722 netif_device_attach(dev);
1723 netif_start_queue(dev);
1724 if (device_may_wakeup(device)) {
1725 disable_irq_wake(dev->irq);
1726 err = flexcan_exit_stop_mode(priv);
1727 if (err)
1728 return err;
1729 } else {
1730 err = pm_runtime_force_resume(device);
1731 if (err)
1732 return err;
1733
1734 err = flexcan_chip_enable(priv);
1735 }
1736 }
1737
1738 return err;
1739}
1740
1741static int __maybe_unused flexcan_runtime_suspend(struct device *device)
1742{
1743 struct net_device *dev = dev_get_drvdata(device);
1744 struct flexcan_priv *priv = netdev_priv(dev);
1745
1746 flexcan_clks_disable(priv);
1747
1748 return 0;
1749}
1750
1751static int __maybe_unused flexcan_runtime_resume(struct device *device)
1752{
1753 struct net_device *dev = dev_get_drvdata(device);
1754 struct flexcan_priv *priv = netdev_priv(dev);
1755
1756 return flexcan_clks_enable(priv);
1757}
1758
1759static int __maybe_unused flexcan_noirq_suspend(struct device *device)
1760{
1761 struct net_device *dev = dev_get_drvdata(device);
1762 struct flexcan_priv *priv = netdev_priv(dev);
1763
1764 if (netif_running(dev) && device_may_wakeup(device))
1765 flexcan_enable_wakeup_irq(priv, true);
1766
1767 return 0;
1768}
1769
1770static int __maybe_unused flexcan_noirq_resume(struct device *device)
1771{
1772 struct net_device *dev = dev_get_drvdata(device);
1773 struct flexcan_priv *priv = netdev_priv(dev);
1774
1775 if (netif_running(dev) && device_may_wakeup(device))
1776 flexcan_enable_wakeup_irq(priv, false);
1777
1778 return 0;
1779}
1780
1781static const struct dev_pm_ops flexcan_pm_ops = {
1782 SET_SYSTEM_SLEEP_PM_OPS(flexcan_suspend, flexcan_resume)
1783 SET_RUNTIME_PM_OPS(flexcan_runtime_suspend, flexcan_runtime_resume, NULL)
1784 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(flexcan_noirq_suspend, flexcan_noirq_resume)
1785};
1786
1787static struct platform_driver flexcan_driver = {
1788 .driver = {
1789 .name = DRV_NAME,
1790 .pm = &flexcan_pm_ops,
1791 .of_match_table = flexcan_of_match,
1792 },
1793 .probe = flexcan_probe,
1794 .remove = flexcan_remove,
1795 .id_table = flexcan_id_table,
1796};
1797
1798module_platform_driver(flexcan_driver);
1799
1800MODULE_AUTHOR("Sascha Hauer <kernel@pengutronix.de>, "
1801 "Marc Kleine-Budde <kernel@pengutronix.de>");
1802MODULE_LICENSE("GPL v2");
1803MODULE_DESCRIPTION("CAN port driver for flexcan based chip");
1/*
2 * flexcan.c - FLEXCAN CAN controller driver
3 *
4 * Copyright (c) 2005-2006 Varma Electronics Oy
5 * Copyright (c) 2009 Sascha Hauer, Pengutronix
6 * Copyright (c) 2010 Marc Kleine-Budde, Pengutronix
7 *
8 * Based on code originally by Andrey Volkov <avolkov@varma-el.com>
9 *
10 * LICENCE:
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation version 2.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 */
21
22#include <linux/netdevice.h>
23#include <linux/can.h>
24#include <linux/can/dev.h>
25#include <linux/can/error.h>
26#include <linux/can/led.h>
27#include <linux/clk.h>
28#include <linux/delay.h>
29#include <linux/interrupt.h>
30#include <linux/io.h>
31#include <linux/module.h>
32#include <linux/of.h>
33#include <linux/of_device.h>
34#include <linux/platform_device.h>
35#include <linux/regulator/consumer.h>
36
37#define DRV_NAME "flexcan"
38
39/* 8 for RX fifo and 2 error handling */
40#define FLEXCAN_NAPI_WEIGHT (8 + 2)
41
42/* FLEXCAN module configuration register (CANMCR) bits */
43#define FLEXCAN_MCR_MDIS BIT(31)
44#define FLEXCAN_MCR_FRZ BIT(30)
45#define FLEXCAN_MCR_FEN BIT(29)
46#define FLEXCAN_MCR_HALT BIT(28)
47#define FLEXCAN_MCR_NOT_RDY BIT(27)
48#define FLEXCAN_MCR_WAK_MSK BIT(26)
49#define FLEXCAN_MCR_SOFTRST BIT(25)
50#define FLEXCAN_MCR_FRZ_ACK BIT(24)
51#define FLEXCAN_MCR_SUPV BIT(23)
52#define FLEXCAN_MCR_SLF_WAK BIT(22)
53#define FLEXCAN_MCR_WRN_EN BIT(21)
54#define FLEXCAN_MCR_LPM_ACK BIT(20)
55#define FLEXCAN_MCR_WAK_SRC BIT(19)
56#define FLEXCAN_MCR_DOZE BIT(18)
57#define FLEXCAN_MCR_SRX_DIS BIT(17)
58#define FLEXCAN_MCR_BCC BIT(16)
59#define FLEXCAN_MCR_LPRIO_EN BIT(13)
60#define FLEXCAN_MCR_AEN BIT(12)
61#define FLEXCAN_MCR_MAXMB(x) ((x) & 0x7f)
62#define FLEXCAN_MCR_IDAM_A (0x0 << 8)
63#define FLEXCAN_MCR_IDAM_B (0x1 << 8)
64#define FLEXCAN_MCR_IDAM_C (0x2 << 8)
65#define FLEXCAN_MCR_IDAM_D (0x3 << 8)
66
67/* FLEXCAN control register (CANCTRL) bits */
68#define FLEXCAN_CTRL_PRESDIV(x) (((x) & 0xff) << 24)
69#define FLEXCAN_CTRL_RJW(x) (((x) & 0x03) << 22)
70#define FLEXCAN_CTRL_PSEG1(x) (((x) & 0x07) << 19)
71#define FLEXCAN_CTRL_PSEG2(x) (((x) & 0x07) << 16)
72#define FLEXCAN_CTRL_BOFF_MSK BIT(15)
73#define FLEXCAN_CTRL_ERR_MSK BIT(14)
74#define FLEXCAN_CTRL_CLK_SRC BIT(13)
75#define FLEXCAN_CTRL_LPB BIT(12)
76#define FLEXCAN_CTRL_TWRN_MSK BIT(11)
77#define FLEXCAN_CTRL_RWRN_MSK BIT(10)
78#define FLEXCAN_CTRL_SMP BIT(7)
79#define FLEXCAN_CTRL_BOFF_REC BIT(6)
80#define FLEXCAN_CTRL_TSYN BIT(5)
81#define FLEXCAN_CTRL_LBUF BIT(4)
82#define FLEXCAN_CTRL_LOM BIT(3)
83#define FLEXCAN_CTRL_PROPSEG(x) ((x) & 0x07)
84#define FLEXCAN_CTRL_ERR_BUS (FLEXCAN_CTRL_ERR_MSK)
85#define FLEXCAN_CTRL_ERR_STATE \
86 (FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \
87 FLEXCAN_CTRL_BOFF_MSK)
88#define FLEXCAN_CTRL_ERR_ALL \
89 (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE)
90
91/* FLEXCAN control register 2 (CTRL2) bits */
92#define FLEXCAN_CTRL2_ECRWRE BIT(29)
93#define FLEXCAN_CTRL2_WRMFRZ BIT(28)
94#define FLEXCAN_CTRL2_RFFN(x) (((x) & 0x0f) << 24)
95#define FLEXCAN_CTRL2_TASD(x) (((x) & 0x1f) << 19)
96#define FLEXCAN_CTRL2_MRP BIT(18)
97#define FLEXCAN_CTRL2_RRS BIT(17)
98#define FLEXCAN_CTRL2_EACEN BIT(16)
99
100/* FLEXCAN memory error control register (MECR) bits */
101#define FLEXCAN_MECR_ECRWRDIS BIT(31)
102#define FLEXCAN_MECR_HANCEI_MSK BIT(19)
103#define FLEXCAN_MECR_FANCEI_MSK BIT(18)
104#define FLEXCAN_MECR_CEI_MSK BIT(16)
105#define FLEXCAN_MECR_HAERRIE BIT(15)
106#define FLEXCAN_MECR_FAERRIE BIT(14)
107#define FLEXCAN_MECR_EXTERRIE BIT(13)
108#define FLEXCAN_MECR_RERRDIS BIT(9)
109#define FLEXCAN_MECR_ECCDIS BIT(8)
110#define FLEXCAN_MECR_NCEFAFRZ BIT(7)
111
112/* FLEXCAN error and status register (ESR) bits */
113#define FLEXCAN_ESR_TWRN_INT BIT(17)
114#define FLEXCAN_ESR_RWRN_INT BIT(16)
115#define FLEXCAN_ESR_BIT1_ERR BIT(15)
116#define FLEXCAN_ESR_BIT0_ERR BIT(14)
117#define FLEXCAN_ESR_ACK_ERR BIT(13)
118#define FLEXCAN_ESR_CRC_ERR BIT(12)
119#define FLEXCAN_ESR_FRM_ERR BIT(11)
120#define FLEXCAN_ESR_STF_ERR BIT(10)
121#define FLEXCAN_ESR_TX_WRN BIT(9)
122#define FLEXCAN_ESR_RX_WRN BIT(8)
123#define FLEXCAN_ESR_IDLE BIT(7)
124#define FLEXCAN_ESR_TXRX BIT(6)
125#define FLEXCAN_EST_FLT_CONF_SHIFT (4)
126#define FLEXCAN_ESR_FLT_CONF_MASK (0x3 << FLEXCAN_EST_FLT_CONF_SHIFT)
127#define FLEXCAN_ESR_FLT_CONF_ACTIVE (0x0 << FLEXCAN_EST_FLT_CONF_SHIFT)
128#define FLEXCAN_ESR_FLT_CONF_PASSIVE (0x1 << FLEXCAN_EST_FLT_CONF_SHIFT)
129#define FLEXCAN_ESR_BOFF_INT BIT(2)
130#define FLEXCAN_ESR_ERR_INT BIT(1)
131#define FLEXCAN_ESR_WAK_INT BIT(0)
132#define FLEXCAN_ESR_ERR_BUS \
133 (FLEXCAN_ESR_BIT1_ERR | FLEXCAN_ESR_BIT0_ERR | \
134 FLEXCAN_ESR_ACK_ERR | FLEXCAN_ESR_CRC_ERR | \
135 FLEXCAN_ESR_FRM_ERR | FLEXCAN_ESR_STF_ERR)
136#define FLEXCAN_ESR_ERR_STATE \
137 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT)
138#define FLEXCAN_ESR_ERR_ALL \
139 (FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE)
140#define FLEXCAN_ESR_ALL_INT \
141 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | \
142 FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT)
143
144/* FLEXCAN interrupt flag register (IFLAG) bits */
145/* Errata ERR005829 step7: Reserve first valid MB */
146#define FLEXCAN_TX_BUF_RESERVED 8
147#define FLEXCAN_TX_BUF_ID 9
148#define FLEXCAN_IFLAG_BUF(x) BIT(x)
149#define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7)
150#define FLEXCAN_IFLAG_RX_FIFO_WARN BIT(6)
151#define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5)
152#define FLEXCAN_IFLAG_DEFAULT \
153 (FLEXCAN_IFLAG_RX_FIFO_OVERFLOW | FLEXCAN_IFLAG_RX_FIFO_AVAILABLE | \
154 FLEXCAN_IFLAG_BUF(FLEXCAN_TX_BUF_ID))
155
156/* FLEXCAN message buffers */
157#define FLEXCAN_MB_CODE_RX_INACTIVE (0x0 << 24)
158#define FLEXCAN_MB_CODE_RX_EMPTY (0x4 << 24)
159#define FLEXCAN_MB_CODE_RX_FULL (0x2 << 24)
160#define FLEXCAN_MB_CODE_RX_OVERRUN (0x6 << 24)
161#define FLEXCAN_MB_CODE_RX_RANSWER (0xa << 24)
162
163#define FLEXCAN_MB_CODE_TX_INACTIVE (0x8 << 24)
164#define FLEXCAN_MB_CODE_TX_ABORT (0x9 << 24)
165#define FLEXCAN_MB_CODE_TX_DATA (0xc << 24)
166#define FLEXCAN_MB_CODE_TX_TANSWER (0xe << 24)
167
168#define FLEXCAN_MB_CNT_SRR BIT(22)
169#define FLEXCAN_MB_CNT_IDE BIT(21)
170#define FLEXCAN_MB_CNT_RTR BIT(20)
171#define FLEXCAN_MB_CNT_LENGTH(x) (((x) & 0xf) << 16)
172#define FLEXCAN_MB_CNT_TIMESTAMP(x) ((x) & 0xffff)
173
174#define FLEXCAN_TIMEOUT_US (50)
175
176/* FLEXCAN hardware feature flags
177 *
178 * Below is some version info we got:
179 * SOC Version IP-Version Glitch- [TR]WRN_INT Memory err RTR re-
180 * Filter? connected? detection ception in MB
181 * MX25 FlexCAN2 03.00.00.00 no no no no
182 * MX28 FlexCAN2 03.00.04.00 yes yes no no
183 * MX35 FlexCAN2 03.00.00.00 no no no no
184 * MX53 FlexCAN2 03.00.00.00 yes no no no
185 * MX6s FlexCAN3 10.00.12.00 yes yes no yes
186 * VF610 FlexCAN3 ? no yes yes yes?
187 *
188 * Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected.
189 */
190#define FLEXCAN_QUIRK_BROKEN_ERR_STATE BIT(1) /* [TR]WRN_INT not connected */
191#define FLEXCAN_QUIRK_DISABLE_RXFG BIT(2) /* Disable RX FIFO Global mask */
192#define FLEXCAN_QUIRK_DISABLE_MECR BIT(3) /* Disble Memory error detection */
193
194/* Structure of the message buffer */
195struct flexcan_mb {
196 u32 can_ctrl;
197 u32 can_id;
198 u32 data[2];
199};
200
201/* Structure of the hardware registers */
202struct flexcan_regs {
203 u32 mcr; /* 0x00 */
204 u32 ctrl; /* 0x04 */
205 u32 timer; /* 0x08 */
206 u32 _reserved1; /* 0x0c */
207 u32 rxgmask; /* 0x10 */
208 u32 rx14mask; /* 0x14 */
209 u32 rx15mask; /* 0x18 */
210 u32 ecr; /* 0x1c */
211 u32 esr; /* 0x20 */
212 u32 imask2; /* 0x24 */
213 u32 imask1; /* 0x28 */
214 u32 iflag2; /* 0x2c */
215 u32 iflag1; /* 0x30 */
216 u32 ctrl2; /* 0x34 */
217 u32 esr2; /* 0x38 */
218 u32 imeur; /* 0x3c */
219 u32 lrfr; /* 0x40 */
220 u32 crcr; /* 0x44 */
221 u32 rxfgmask; /* 0x48 */
222 u32 rxfir; /* 0x4c */
223 u32 _reserved3[12]; /* 0x50 */
224 struct flexcan_mb mb[64]; /* 0x80 */
225 /* FIFO-mode:
226 * MB
227 * 0x080...0x08f 0 RX message buffer
228 * 0x090...0x0df 1-5 reserverd
229 * 0x0e0...0x0ff 6-7 8 entry ID table
230 * (mx25, mx28, mx35, mx53)
231 * 0x0e0...0x2df 6-7..37 8..128 entry ID table
232 * size conf'ed via ctrl2::RFFN
233 * (mx6, vf610)
234 */
235 u32 _reserved4[408];
236 u32 mecr; /* 0xae0 */
237 u32 erriar; /* 0xae4 */
238 u32 erridpr; /* 0xae8 */
239 u32 errippr; /* 0xaec */
240 u32 rerrar; /* 0xaf0 */
241 u32 rerrdr; /* 0xaf4 */
242 u32 rerrsynr; /* 0xaf8 */
243 u32 errsr; /* 0xafc */
244};
245
246struct flexcan_devtype_data {
247 u32 quirks; /* quirks needed for different IP cores */
248};
249
250struct flexcan_priv {
251 struct can_priv can;
252 struct napi_struct napi;
253
254 struct flexcan_regs __iomem *regs;
255 u32 reg_esr;
256 u32 reg_ctrl_default;
257
258 struct clk *clk_ipg;
259 struct clk *clk_per;
260 struct flexcan_platform_data *pdata;
261 const struct flexcan_devtype_data *devtype_data;
262 struct regulator *reg_xceiver;
263};
264
265static struct flexcan_devtype_data fsl_p1010_devtype_data = {
266 .quirks = FLEXCAN_QUIRK_BROKEN_ERR_STATE,
267};
268
269static struct flexcan_devtype_data fsl_imx28_devtype_data;
270
271static struct flexcan_devtype_data fsl_imx6q_devtype_data = {
272 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG,
273};
274
275static struct flexcan_devtype_data fsl_vf610_devtype_data = {
276 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_DISABLE_MECR,
277};
278
279static const struct can_bittiming_const flexcan_bittiming_const = {
280 .name = DRV_NAME,
281 .tseg1_min = 4,
282 .tseg1_max = 16,
283 .tseg2_min = 2,
284 .tseg2_max = 8,
285 .sjw_max = 4,
286 .brp_min = 1,
287 .brp_max = 256,
288 .brp_inc = 1,
289};
290
291/* Abstract off the read/write for arm versus ppc. This
292 * assumes that PPC uses big-endian registers and everything
293 * else uses little-endian registers, independent of CPU
294 * endianness.
295 */
296#if defined(CONFIG_PPC)
297static inline u32 flexcan_read(void __iomem *addr)
298{
299 return in_be32(addr);
300}
301
302static inline void flexcan_write(u32 val, void __iomem *addr)
303{
304 out_be32(addr, val);
305}
306#else
307static inline u32 flexcan_read(void __iomem *addr)
308{
309 return readl(addr);
310}
311
312static inline void flexcan_write(u32 val, void __iomem *addr)
313{
314 writel(val, addr);
315}
316#endif
317
318static inline int flexcan_transceiver_enable(const struct flexcan_priv *priv)
319{
320 if (!priv->reg_xceiver)
321 return 0;
322
323 return regulator_enable(priv->reg_xceiver);
324}
325
326static inline int flexcan_transceiver_disable(const struct flexcan_priv *priv)
327{
328 if (!priv->reg_xceiver)
329 return 0;
330
331 return regulator_disable(priv->reg_xceiver);
332}
333
334static inline int flexcan_has_and_handle_berr(const struct flexcan_priv *priv,
335 u32 reg_esr)
336{
337 return (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) &&
338 (reg_esr & FLEXCAN_ESR_ERR_BUS);
339}
340
341static int flexcan_chip_enable(struct flexcan_priv *priv)
342{
343 struct flexcan_regs __iomem *regs = priv->regs;
344 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
345 u32 reg;
346
347 reg = flexcan_read(®s->mcr);
348 reg &= ~FLEXCAN_MCR_MDIS;
349 flexcan_write(reg, ®s->mcr);
350
351 while (timeout-- && (flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
352 udelay(10);
353
354 if (flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK)
355 return -ETIMEDOUT;
356
357 return 0;
358}
359
360static int flexcan_chip_disable(struct flexcan_priv *priv)
361{
362 struct flexcan_regs __iomem *regs = priv->regs;
363 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
364 u32 reg;
365
366 reg = flexcan_read(®s->mcr);
367 reg |= FLEXCAN_MCR_MDIS;
368 flexcan_write(reg, ®s->mcr);
369
370 while (timeout-- && !(flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
371 udelay(10);
372
373 if (!(flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
374 return -ETIMEDOUT;
375
376 return 0;
377}
378
379static int flexcan_chip_freeze(struct flexcan_priv *priv)
380{
381 struct flexcan_regs __iomem *regs = priv->regs;
382 unsigned int timeout = 1000 * 1000 * 10 / priv->can.bittiming.bitrate;
383 u32 reg;
384
385 reg = flexcan_read(®s->mcr);
386 reg |= FLEXCAN_MCR_HALT;
387 flexcan_write(reg, ®s->mcr);
388
389 while (timeout-- && !(flexcan_read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
390 udelay(100);
391
392 if (!(flexcan_read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
393 return -ETIMEDOUT;
394
395 return 0;
396}
397
398static int flexcan_chip_unfreeze(struct flexcan_priv *priv)
399{
400 struct flexcan_regs __iomem *regs = priv->regs;
401 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
402 u32 reg;
403
404 reg = flexcan_read(®s->mcr);
405 reg &= ~FLEXCAN_MCR_HALT;
406 flexcan_write(reg, ®s->mcr);
407
408 while (timeout-- && (flexcan_read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
409 udelay(10);
410
411 if (flexcan_read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK)
412 return -ETIMEDOUT;
413
414 return 0;
415}
416
417static int flexcan_chip_softreset(struct flexcan_priv *priv)
418{
419 struct flexcan_regs __iomem *regs = priv->regs;
420 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
421
422 flexcan_write(FLEXCAN_MCR_SOFTRST, ®s->mcr);
423 while (timeout-- && (flexcan_read(®s->mcr) & FLEXCAN_MCR_SOFTRST))
424 udelay(10);
425
426 if (flexcan_read(®s->mcr) & FLEXCAN_MCR_SOFTRST)
427 return -ETIMEDOUT;
428
429 return 0;
430}
431
432static int __flexcan_get_berr_counter(const struct net_device *dev,
433 struct can_berr_counter *bec)
434{
435 const struct flexcan_priv *priv = netdev_priv(dev);
436 struct flexcan_regs __iomem *regs = priv->regs;
437 u32 reg = flexcan_read(®s->ecr);
438
439 bec->txerr = (reg >> 0) & 0xff;
440 bec->rxerr = (reg >> 8) & 0xff;
441
442 return 0;
443}
444
445static int flexcan_get_berr_counter(const struct net_device *dev,
446 struct can_berr_counter *bec)
447{
448 const struct flexcan_priv *priv = netdev_priv(dev);
449 int err;
450
451 err = clk_prepare_enable(priv->clk_ipg);
452 if (err)
453 return err;
454
455 err = clk_prepare_enable(priv->clk_per);
456 if (err)
457 goto out_disable_ipg;
458
459 err = __flexcan_get_berr_counter(dev, bec);
460
461 clk_disable_unprepare(priv->clk_per);
462 out_disable_ipg:
463 clk_disable_unprepare(priv->clk_ipg);
464
465 return err;
466}
467
468static int flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
469{
470 const struct flexcan_priv *priv = netdev_priv(dev);
471 struct flexcan_regs __iomem *regs = priv->regs;
472 struct can_frame *cf = (struct can_frame *)skb->data;
473 u32 can_id;
474 u32 data;
475 u32 ctrl = FLEXCAN_MB_CODE_TX_DATA | (cf->can_dlc << 16);
476
477 if (can_dropped_invalid_skb(dev, skb))
478 return NETDEV_TX_OK;
479
480 netif_stop_queue(dev);
481
482 if (cf->can_id & CAN_EFF_FLAG) {
483 can_id = cf->can_id & CAN_EFF_MASK;
484 ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR;
485 } else {
486 can_id = (cf->can_id & CAN_SFF_MASK) << 18;
487 }
488
489 if (cf->can_id & CAN_RTR_FLAG)
490 ctrl |= FLEXCAN_MB_CNT_RTR;
491
492 if (cf->can_dlc > 0) {
493 data = be32_to_cpup((__be32 *)&cf->data[0]);
494 flexcan_write(data, ®s->mb[FLEXCAN_TX_BUF_ID].data[0]);
495 }
496 if (cf->can_dlc > 3) {
497 data = be32_to_cpup((__be32 *)&cf->data[4]);
498 flexcan_write(data, ®s->mb[FLEXCAN_TX_BUF_ID].data[1]);
499 }
500
501 can_put_echo_skb(skb, dev, 0);
502
503 flexcan_write(can_id, ®s->mb[FLEXCAN_TX_BUF_ID].can_id);
504 flexcan_write(ctrl, ®s->mb[FLEXCAN_TX_BUF_ID].can_ctrl);
505
506 /* Errata ERR005829 step8:
507 * Write twice INACTIVE(0x8) code to first MB.
508 */
509 flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
510 ®s->mb[FLEXCAN_TX_BUF_RESERVED].can_ctrl);
511 flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
512 ®s->mb[FLEXCAN_TX_BUF_RESERVED].can_ctrl);
513
514 return NETDEV_TX_OK;
515}
516
517static void do_bus_err(struct net_device *dev,
518 struct can_frame *cf, u32 reg_esr)
519{
520 struct flexcan_priv *priv = netdev_priv(dev);
521 int rx_errors = 0, tx_errors = 0;
522
523 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
524
525 if (reg_esr & FLEXCAN_ESR_BIT1_ERR) {
526 netdev_dbg(dev, "BIT1_ERR irq\n");
527 cf->data[2] |= CAN_ERR_PROT_BIT1;
528 tx_errors = 1;
529 }
530 if (reg_esr & FLEXCAN_ESR_BIT0_ERR) {
531 netdev_dbg(dev, "BIT0_ERR irq\n");
532 cf->data[2] |= CAN_ERR_PROT_BIT0;
533 tx_errors = 1;
534 }
535 if (reg_esr & FLEXCAN_ESR_ACK_ERR) {
536 netdev_dbg(dev, "ACK_ERR irq\n");
537 cf->can_id |= CAN_ERR_ACK;
538 cf->data[3] = CAN_ERR_PROT_LOC_ACK;
539 tx_errors = 1;
540 }
541 if (reg_esr & FLEXCAN_ESR_CRC_ERR) {
542 netdev_dbg(dev, "CRC_ERR irq\n");
543 cf->data[2] |= CAN_ERR_PROT_BIT;
544 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ;
545 rx_errors = 1;
546 }
547 if (reg_esr & FLEXCAN_ESR_FRM_ERR) {
548 netdev_dbg(dev, "FRM_ERR irq\n");
549 cf->data[2] |= CAN_ERR_PROT_FORM;
550 rx_errors = 1;
551 }
552 if (reg_esr & FLEXCAN_ESR_STF_ERR) {
553 netdev_dbg(dev, "STF_ERR irq\n");
554 cf->data[2] |= CAN_ERR_PROT_STUFF;
555 rx_errors = 1;
556 }
557
558 priv->can.can_stats.bus_error++;
559 if (rx_errors)
560 dev->stats.rx_errors++;
561 if (tx_errors)
562 dev->stats.tx_errors++;
563}
564
565static int flexcan_poll_bus_err(struct net_device *dev, u32 reg_esr)
566{
567 struct sk_buff *skb;
568 struct can_frame *cf;
569
570 skb = alloc_can_err_skb(dev, &cf);
571 if (unlikely(!skb))
572 return 0;
573
574 do_bus_err(dev, cf, reg_esr);
575
576 dev->stats.rx_packets++;
577 dev->stats.rx_bytes += cf->can_dlc;
578 netif_receive_skb(skb);
579
580 return 1;
581}
582
583static int flexcan_poll_state(struct net_device *dev, u32 reg_esr)
584{
585 struct flexcan_priv *priv = netdev_priv(dev);
586 struct sk_buff *skb;
587 struct can_frame *cf;
588 enum can_state new_state = 0, rx_state = 0, tx_state = 0;
589 int flt;
590 struct can_berr_counter bec;
591
592 flt = reg_esr & FLEXCAN_ESR_FLT_CONF_MASK;
593 if (likely(flt == FLEXCAN_ESR_FLT_CONF_ACTIVE)) {
594 tx_state = unlikely(reg_esr & FLEXCAN_ESR_TX_WRN) ?
595 CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
596 rx_state = unlikely(reg_esr & FLEXCAN_ESR_RX_WRN) ?
597 CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
598 new_state = max(tx_state, rx_state);
599 } else {
600 __flexcan_get_berr_counter(dev, &bec);
601 new_state = flt == FLEXCAN_ESR_FLT_CONF_PASSIVE ?
602 CAN_STATE_ERROR_PASSIVE : CAN_STATE_BUS_OFF;
603 rx_state = bec.rxerr >= bec.txerr ? new_state : 0;
604 tx_state = bec.rxerr <= bec.txerr ? new_state : 0;
605 }
606
607 /* state hasn't changed */
608 if (likely(new_state == priv->can.state))
609 return 0;
610
611 skb = alloc_can_err_skb(dev, &cf);
612 if (unlikely(!skb))
613 return 0;
614
615 can_change_state(dev, cf, tx_state, rx_state);
616
617 if (unlikely(new_state == CAN_STATE_BUS_OFF))
618 can_bus_off(dev);
619
620 dev->stats.rx_packets++;
621 dev->stats.rx_bytes += cf->can_dlc;
622 netif_receive_skb(skb);
623
624 return 1;
625}
626
627static void flexcan_read_fifo(const struct net_device *dev,
628 struct can_frame *cf)
629{
630 const struct flexcan_priv *priv = netdev_priv(dev);
631 struct flexcan_regs __iomem *regs = priv->regs;
632 struct flexcan_mb __iomem *mb = ®s->mb[0];
633 u32 reg_ctrl, reg_id;
634
635 reg_ctrl = flexcan_read(&mb->can_ctrl);
636 reg_id = flexcan_read(&mb->can_id);
637 if (reg_ctrl & FLEXCAN_MB_CNT_IDE)
638 cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
639 else
640 cf->can_id = (reg_id >> 18) & CAN_SFF_MASK;
641
642 if (reg_ctrl & FLEXCAN_MB_CNT_RTR)
643 cf->can_id |= CAN_RTR_FLAG;
644 cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf);
645
646 *(__be32 *)(cf->data + 0) = cpu_to_be32(flexcan_read(&mb->data[0]));
647 *(__be32 *)(cf->data + 4) = cpu_to_be32(flexcan_read(&mb->data[1]));
648
649 /* mark as read */
650 flexcan_write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->iflag1);
651 flexcan_read(®s->timer);
652}
653
654static int flexcan_read_frame(struct net_device *dev)
655{
656 struct net_device_stats *stats = &dev->stats;
657 struct can_frame *cf;
658 struct sk_buff *skb;
659
660 skb = alloc_can_skb(dev, &cf);
661 if (unlikely(!skb)) {
662 stats->rx_dropped++;
663 return 0;
664 }
665
666 flexcan_read_fifo(dev, cf);
667
668 stats->rx_packets++;
669 stats->rx_bytes += cf->can_dlc;
670 netif_receive_skb(skb);
671
672 can_led_event(dev, CAN_LED_EVENT_RX);
673
674 return 1;
675}
676
677static int flexcan_poll(struct napi_struct *napi, int quota)
678{
679 struct net_device *dev = napi->dev;
680 const struct flexcan_priv *priv = netdev_priv(dev);
681 struct flexcan_regs __iomem *regs = priv->regs;
682 u32 reg_iflag1, reg_esr;
683 int work_done = 0;
684
685 /* The error bits are cleared on read,
686 * use saved value from irq handler.
687 */
688 reg_esr = flexcan_read(®s->esr) | priv->reg_esr;
689
690 /* handle state changes */
691 work_done += flexcan_poll_state(dev, reg_esr);
692
693 /* handle RX-FIFO */
694 reg_iflag1 = flexcan_read(®s->iflag1);
695 while (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE &&
696 work_done < quota) {
697 work_done += flexcan_read_frame(dev);
698 reg_iflag1 = flexcan_read(®s->iflag1);
699 }
700
701 /* report bus errors */
702 if (flexcan_has_and_handle_berr(priv, reg_esr) && work_done < quota)
703 work_done += flexcan_poll_bus_err(dev, reg_esr);
704
705 if (work_done < quota) {
706 napi_complete(napi);
707 /* enable IRQs */
708 flexcan_write(FLEXCAN_IFLAG_DEFAULT, ®s->imask1);
709 flexcan_write(priv->reg_ctrl_default, ®s->ctrl);
710 }
711
712 return work_done;
713}
714
715static irqreturn_t flexcan_irq(int irq, void *dev_id)
716{
717 struct net_device *dev = dev_id;
718 struct net_device_stats *stats = &dev->stats;
719 struct flexcan_priv *priv = netdev_priv(dev);
720 struct flexcan_regs __iomem *regs = priv->regs;
721 u32 reg_iflag1, reg_esr;
722
723 reg_iflag1 = flexcan_read(®s->iflag1);
724 reg_esr = flexcan_read(®s->esr);
725
726 /* ACK all bus error and state change IRQ sources */
727 if (reg_esr & FLEXCAN_ESR_ALL_INT)
728 flexcan_write(reg_esr & FLEXCAN_ESR_ALL_INT, ®s->esr);
729
730 /* schedule NAPI in case of:
731 * - rx IRQ
732 * - state change IRQ
733 * - bus error IRQ and bus error reporting is activated
734 */
735 if ((reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) ||
736 (reg_esr & FLEXCAN_ESR_ERR_STATE) ||
737 flexcan_has_and_handle_berr(priv, reg_esr)) {
738 /* The error bits are cleared on read,
739 * save them for later use.
740 */
741 priv->reg_esr = reg_esr & FLEXCAN_ESR_ERR_BUS;
742 flexcan_write(FLEXCAN_IFLAG_DEFAULT &
743 ~FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->imask1);
744 flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
745 ®s->ctrl);
746 napi_schedule(&priv->napi);
747 }
748
749 /* FIFO overflow */
750 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) {
751 flexcan_write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW, ®s->iflag1);
752 dev->stats.rx_over_errors++;
753 dev->stats.rx_errors++;
754 }
755
756 /* transmission complete interrupt */
757 if (reg_iflag1 & (1 << FLEXCAN_TX_BUF_ID)) {
758 stats->tx_bytes += can_get_echo_skb(dev, 0);
759 stats->tx_packets++;
760 can_led_event(dev, CAN_LED_EVENT_TX);
761
762 /* after sending a RTR frame MB is in RX mode */
763 flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
764 ®s->mb[FLEXCAN_TX_BUF_ID].can_ctrl);
765 flexcan_write((1 << FLEXCAN_TX_BUF_ID), ®s->iflag1);
766 netif_wake_queue(dev);
767 }
768
769 return IRQ_HANDLED;
770}
771
772static void flexcan_set_bittiming(struct net_device *dev)
773{
774 const struct flexcan_priv *priv = netdev_priv(dev);
775 const struct can_bittiming *bt = &priv->can.bittiming;
776 struct flexcan_regs __iomem *regs = priv->regs;
777 u32 reg;
778
779 reg = flexcan_read(®s->ctrl);
780 reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) |
781 FLEXCAN_CTRL_RJW(0x3) |
782 FLEXCAN_CTRL_PSEG1(0x7) |
783 FLEXCAN_CTRL_PSEG2(0x7) |
784 FLEXCAN_CTRL_PROPSEG(0x7) |
785 FLEXCAN_CTRL_LPB |
786 FLEXCAN_CTRL_SMP |
787 FLEXCAN_CTRL_LOM);
788
789 reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) |
790 FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) |
791 FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) |
792 FLEXCAN_CTRL_RJW(bt->sjw - 1) |
793 FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1);
794
795 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
796 reg |= FLEXCAN_CTRL_LPB;
797 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
798 reg |= FLEXCAN_CTRL_LOM;
799 if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
800 reg |= FLEXCAN_CTRL_SMP;
801
802 netdev_dbg(dev, "writing ctrl=0x%08x\n", reg);
803 flexcan_write(reg, ®s->ctrl);
804
805 /* print chip status */
806 netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__,
807 flexcan_read(®s->mcr), flexcan_read(®s->ctrl));
808}
809
810/* flexcan_chip_start
811 *
812 * this functions is entered with clocks enabled
813 *
814 */
815static int flexcan_chip_start(struct net_device *dev)
816{
817 struct flexcan_priv *priv = netdev_priv(dev);
818 struct flexcan_regs __iomem *regs = priv->regs;
819 u32 reg_mcr, reg_ctrl, reg_ctrl2, reg_mecr;
820 int err, i;
821
822 /* enable module */
823 err = flexcan_chip_enable(priv);
824 if (err)
825 return err;
826
827 /* soft reset */
828 err = flexcan_chip_softreset(priv);
829 if (err)
830 goto out_chip_disable;
831
832 flexcan_set_bittiming(dev);
833
834 /* MCR
835 *
836 * enable freeze
837 * enable fifo
838 * halt now
839 * only supervisor access
840 * enable warning int
841 * disable local echo
842 * choose format C
843 * set max mailbox number
844 */
845 reg_mcr = flexcan_read(®s->mcr);
846 reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff);
847 reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_FEN | FLEXCAN_MCR_HALT |
848 FLEXCAN_MCR_SUPV | FLEXCAN_MCR_WRN_EN | FLEXCAN_MCR_SRX_DIS |
849 FLEXCAN_MCR_IDAM_C | FLEXCAN_MCR_MAXMB(FLEXCAN_TX_BUF_ID);
850 netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr);
851 flexcan_write(reg_mcr, ®s->mcr);
852
853 /* CTRL
854 *
855 * disable timer sync feature
856 *
857 * disable auto busoff recovery
858 * transmit lowest buffer first
859 *
860 * enable tx and rx warning interrupt
861 * enable bus off interrupt
862 * (== FLEXCAN_CTRL_ERR_STATE)
863 */
864 reg_ctrl = flexcan_read(®s->ctrl);
865 reg_ctrl &= ~FLEXCAN_CTRL_TSYN;
866 reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF |
867 FLEXCAN_CTRL_ERR_STATE;
868
869 /* enable the "error interrupt" (FLEXCAN_CTRL_ERR_MSK),
870 * on most Flexcan cores, too. Otherwise we don't get
871 * any error warning or passive interrupts.
872 */
873 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_ERR_STATE ||
874 priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
875 reg_ctrl |= FLEXCAN_CTRL_ERR_MSK;
876 else
877 reg_ctrl &= ~FLEXCAN_CTRL_ERR_MSK;
878
879 /* save for later use */
880 priv->reg_ctrl_default = reg_ctrl;
881 /* leave interrupts disabled for now */
882 reg_ctrl &= ~FLEXCAN_CTRL_ERR_ALL;
883 netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl);
884 flexcan_write(reg_ctrl, ®s->ctrl);
885
886 /* clear and invalidate all mailboxes first */
887 for (i = FLEXCAN_TX_BUF_ID; i < ARRAY_SIZE(regs->mb); i++) {
888 flexcan_write(FLEXCAN_MB_CODE_RX_INACTIVE,
889 ®s->mb[i].can_ctrl);
890 }
891
892 /* Errata ERR005829: mark first TX mailbox as INACTIVE */
893 flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
894 ®s->mb[FLEXCAN_TX_BUF_RESERVED].can_ctrl);
895
896 /* mark TX mailbox as INACTIVE */
897 flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
898 ®s->mb[FLEXCAN_TX_BUF_ID].can_ctrl);
899
900 /* acceptance mask/acceptance code (accept everything) */
901 flexcan_write(0x0, ®s->rxgmask);
902 flexcan_write(0x0, ®s->rx14mask);
903 flexcan_write(0x0, ®s->rx15mask);
904
905 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_RXFG)
906 flexcan_write(0x0, ®s->rxfgmask);
907
908 /* On Vybrid, disable memory error detection interrupts
909 * and freeze mode.
910 * This also works around errata e5295 which generates
911 * false positive memory errors and put the device in
912 * freeze mode.
913 */
914 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_MECR) {
915 /* Follow the protocol as described in "Detection
916 * and Correction of Memory Errors" to write to
917 * MECR register
918 */
919 reg_ctrl2 = flexcan_read(®s->ctrl2);
920 reg_ctrl2 |= FLEXCAN_CTRL2_ECRWRE;
921 flexcan_write(reg_ctrl2, ®s->ctrl2);
922
923 reg_mecr = flexcan_read(®s->mecr);
924 reg_mecr &= ~FLEXCAN_MECR_ECRWRDIS;
925 flexcan_write(reg_mecr, ®s->mecr);
926 reg_mecr &= ~(FLEXCAN_MECR_NCEFAFRZ | FLEXCAN_MECR_HANCEI_MSK |
927 FLEXCAN_MECR_FANCEI_MSK);
928 flexcan_write(reg_mecr, ®s->mecr);
929 }
930
931 err = flexcan_transceiver_enable(priv);
932 if (err)
933 goto out_chip_disable;
934
935 /* synchronize with the can bus */
936 err = flexcan_chip_unfreeze(priv);
937 if (err)
938 goto out_transceiver_disable;
939
940 priv->can.state = CAN_STATE_ERROR_ACTIVE;
941
942 /* enable interrupts atomically */
943 disable_irq(dev->irq);
944 flexcan_write(priv->reg_ctrl_default, ®s->ctrl);
945 flexcan_write(FLEXCAN_IFLAG_DEFAULT, ®s->imask1);
946 enable_irq(dev->irq);
947
948 /* print chip status */
949 netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__,
950 flexcan_read(®s->mcr), flexcan_read(®s->ctrl));
951
952 return 0;
953
954 out_transceiver_disable:
955 flexcan_transceiver_disable(priv);
956 out_chip_disable:
957 flexcan_chip_disable(priv);
958 return err;
959}
960
961/* flexcan_chip_stop
962 *
963 * this functions is entered with clocks enabled
964 */
965static void flexcan_chip_stop(struct net_device *dev)
966{
967 struct flexcan_priv *priv = netdev_priv(dev);
968 struct flexcan_regs __iomem *regs = priv->regs;
969
970 /* freeze + disable module */
971 flexcan_chip_freeze(priv);
972 flexcan_chip_disable(priv);
973
974 /* Disable all interrupts */
975 flexcan_write(0, ®s->imask1);
976 flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
977 ®s->ctrl);
978
979 flexcan_transceiver_disable(priv);
980 priv->can.state = CAN_STATE_STOPPED;
981}
982
983static int flexcan_open(struct net_device *dev)
984{
985 struct flexcan_priv *priv = netdev_priv(dev);
986 int err;
987
988 err = clk_prepare_enable(priv->clk_ipg);
989 if (err)
990 return err;
991
992 err = clk_prepare_enable(priv->clk_per);
993 if (err)
994 goto out_disable_ipg;
995
996 err = open_candev(dev);
997 if (err)
998 goto out_disable_per;
999
1000 err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev);
1001 if (err)
1002 goto out_close;
1003
1004 /* start chip and queuing */
1005 err = flexcan_chip_start(dev);
1006 if (err)
1007 goto out_free_irq;
1008
1009 can_led_event(dev, CAN_LED_EVENT_OPEN);
1010
1011 napi_enable(&priv->napi);
1012 netif_start_queue(dev);
1013
1014 return 0;
1015
1016 out_free_irq:
1017 free_irq(dev->irq, dev);
1018 out_close:
1019 close_candev(dev);
1020 out_disable_per:
1021 clk_disable_unprepare(priv->clk_per);
1022 out_disable_ipg:
1023 clk_disable_unprepare(priv->clk_ipg);
1024
1025 return err;
1026}
1027
1028static int flexcan_close(struct net_device *dev)
1029{
1030 struct flexcan_priv *priv = netdev_priv(dev);
1031
1032 netif_stop_queue(dev);
1033 napi_disable(&priv->napi);
1034 flexcan_chip_stop(dev);
1035
1036 free_irq(dev->irq, dev);
1037 clk_disable_unprepare(priv->clk_per);
1038 clk_disable_unprepare(priv->clk_ipg);
1039
1040 close_candev(dev);
1041
1042 can_led_event(dev, CAN_LED_EVENT_STOP);
1043
1044 return 0;
1045}
1046
1047static int flexcan_set_mode(struct net_device *dev, enum can_mode mode)
1048{
1049 int err;
1050
1051 switch (mode) {
1052 case CAN_MODE_START:
1053 err = flexcan_chip_start(dev);
1054 if (err)
1055 return err;
1056
1057 netif_wake_queue(dev);
1058 break;
1059
1060 default:
1061 return -EOPNOTSUPP;
1062 }
1063
1064 return 0;
1065}
1066
1067static const struct net_device_ops flexcan_netdev_ops = {
1068 .ndo_open = flexcan_open,
1069 .ndo_stop = flexcan_close,
1070 .ndo_start_xmit = flexcan_start_xmit,
1071 .ndo_change_mtu = can_change_mtu,
1072};
1073
1074static int register_flexcandev(struct net_device *dev)
1075{
1076 struct flexcan_priv *priv = netdev_priv(dev);
1077 struct flexcan_regs __iomem *regs = priv->regs;
1078 u32 reg, err;
1079
1080 err = clk_prepare_enable(priv->clk_ipg);
1081 if (err)
1082 return err;
1083
1084 err = clk_prepare_enable(priv->clk_per);
1085 if (err)
1086 goto out_disable_ipg;
1087
1088 /* select "bus clock", chip must be disabled */
1089 err = flexcan_chip_disable(priv);
1090 if (err)
1091 goto out_disable_per;
1092 reg = flexcan_read(®s->ctrl);
1093 reg |= FLEXCAN_CTRL_CLK_SRC;
1094 flexcan_write(reg, ®s->ctrl);
1095
1096 err = flexcan_chip_enable(priv);
1097 if (err)
1098 goto out_chip_disable;
1099
1100 /* set freeze, halt and activate FIFO, restrict register access */
1101 reg = flexcan_read(®s->mcr);
1102 reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT |
1103 FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV;
1104 flexcan_write(reg, ®s->mcr);
1105
1106 /* Currently we only support newer versions of this core
1107 * featuring a RX FIFO. Older cores found on some Coldfire
1108 * derivates are not yet supported.
1109 */
1110 reg = flexcan_read(®s->mcr);
1111 if (!(reg & FLEXCAN_MCR_FEN)) {
1112 netdev_err(dev, "Could not enable RX FIFO, unsupported core\n");
1113 err = -ENODEV;
1114 goto out_chip_disable;
1115 }
1116
1117 err = register_candev(dev);
1118
1119 /* disable core and turn off clocks */
1120 out_chip_disable:
1121 flexcan_chip_disable(priv);
1122 out_disable_per:
1123 clk_disable_unprepare(priv->clk_per);
1124 out_disable_ipg:
1125 clk_disable_unprepare(priv->clk_ipg);
1126
1127 return err;
1128}
1129
1130static void unregister_flexcandev(struct net_device *dev)
1131{
1132 unregister_candev(dev);
1133}
1134
1135static const struct of_device_id flexcan_of_match[] = {
1136 { .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, },
1137 { .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, },
1138 { .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, },
1139 { .compatible = "fsl,vf610-flexcan", .data = &fsl_vf610_devtype_data, },
1140 { /* sentinel */ },
1141};
1142MODULE_DEVICE_TABLE(of, flexcan_of_match);
1143
1144static const struct platform_device_id flexcan_id_table[] = {
1145 { .name = "flexcan", .driver_data = (kernel_ulong_t)&fsl_p1010_devtype_data, },
1146 { /* sentinel */ },
1147};
1148MODULE_DEVICE_TABLE(platform, flexcan_id_table);
1149
1150static int flexcan_probe(struct platform_device *pdev)
1151{
1152 const struct of_device_id *of_id;
1153 const struct flexcan_devtype_data *devtype_data;
1154 struct net_device *dev;
1155 struct flexcan_priv *priv;
1156 struct regulator *reg_xceiver;
1157 struct resource *mem;
1158 struct clk *clk_ipg = NULL, *clk_per = NULL;
1159 struct flexcan_regs __iomem *regs;
1160 int err, irq;
1161 u32 clock_freq = 0;
1162
1163 reg_xceiver = devm_regulator_get(&pdev->dev, "xceiver");
1164 if (PTR_ERR(reg_xceiver) == -EPROBE_DEFER)
1165 return -EPROBE_DEFER;
1166 else if (IS_ERR(reg_xceiver))
1167 reg_xceiver = NULL;
1168
1169 if (pdev->dev.of_node)
1170 of_property_read_u32(pdev->dev.of_node,
1171 "clock-frequency", &clock_freq);
1172
1173 if (!clock_freq) {
1174 clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1175 if (IS_ERR(clk_ipg)) {
1176 dev_err(&pdev->dev, "no ipg clock defined\n");
1177 return PTR_ERR(clk_ipg);
1178 }
1179
1180 clk_per = devm_clk_get(&pdev->dev, "per");
1181 if (IS_ERR(clk_per)) {
1182 dev_err(&pdev->dev, "no per clock defined\n");
1183 return PTR_ERR(clk_per);
1184 }
1185 clock_freq = clk_get_rate(clk_per);
1186 }
1187
1188 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1189 irq = platform_get_irq(pdev, 0);
1190 if (irq <= 0)
1191 return -ENODEV;
1192
1193 regs = devm_ioremap_resource(&pdev->dev, mem);
1194 if (IS_ERR(regs))
1195 return PTR_ERR(regs);
1196
1197 of_id = of_match_device(flexcan_of_match, &pdev->dev);
1198 if (of_id) {
1199 devtype_data = of_id->data;
1200 } else if (platform_get_device_id(pdev)->driver_data) {
1201 devtype_data = (struct flexcan_devtype_data *)
1202 platform_get_device_id(pdev)->driver_data;
1203 } else {
1204 return -ENODEV;
1205 }
1206
1207 dev = alloc_candev(sizeof(struct flexcan_priv), 1);
1208 if (!dev)
1209 return -ENOMEM;
1210
1211 dev->netdev_ops = &flexcan_netdev_ops;
1212 dev->irq = irq;
1213 dev->flags |= IFF_ECHO;
1214
1215 priv = netdev_priv(dev);
1216 priv->can.clock.freq = clock_freq;
1217 priv->can.bittiming_const = &flexcan_bittiming_const;
1218 priv->can.do_set_mode = flexcan_set_mode;
1219 priv->can.do_get_berr_counter = flexcan_get_berr_counter;
1220 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
1221 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_3_SAMPLES |
1222 CAN_CTRLMODE_BERR_REPORTING;
1223 priv->regs = regs;
1224 priv->clk_ipg = clk_ipg;
1225 priv->clk_per = clk_per;
1226 priv->pdata = dev_get_platdata(&pdev->dev);
1227 priv->devtype_data = devtype_data;
1228 priv->reg_xceiver = reg_xceiver;
1229
1230 netif_napi_add(dev, &priv->napi, flexcan_poll, FLEXCAN_NAPI_WEIGHT);
1231
1232 platform_set_drvdata(pdev, dev);
1233 SET_NETDEV_DEV(dev, &pdev->dev);
1234
1235 err = register_flexcandev(dev);
1236 if (err) {
1237 dev_err(&pdev->dev, "registering netdev failed\n");
1238 goto failed_register;
1239 }
1240
1241 devm_can_led_init(dev);
1242
1243 dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n",
1244 priv->regs, dev->irq);
1245
1246 return 0;
1247
1248 failed_register:
1249 free_candev(dev);
1250 return err;
1251}
1252
1253static int flexcan_remove(struct platform_device *pdev)
1254{
1255 struct net_device *dev = platform_get_drvdata(pdev);
1256 struct flexcan_priv *priv = netdev_priv(dev);
1257
1258 unregister_flexcandev(dev);
1259 netif_napi_del(&priv->napi);
1260 free_candev(dev);
1261
1262 return 0;
1263}
1264
1265static int __maybe_unused flexcan_suspend(struct device *device)
1266{
1267 struct net_device *dev = dev_get_drvdata(device);
1268 struct flexcan_priv *priv = netdev_priv(dev);
1269 int err;
1270
1271 err = flexcan_chip_disable(priv);
1272 if (err)
1273 return err;
1274
1275 if (netif_running(dev)) {
1276 netif_stop_queue(dev);
1277 netif_device_detach(dev);
1278 }
1279 priv->can.state = CAN_STATE_SLEEPING;
1280
1281 return 0;
1282}
1283
1284static int __maybe_unused flexcan_resume(struct device *device)
1285{
1286 struct net_device *dev = dev_get_drvdata(device);
1287 struct flexcan_priv *priv = netdev_priv(dev);
1288
1289 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1290 if (netif_running(dev)) {
1291 netif_device_attach(dev);
1292 netif_start_queue(dev);
1293 }
1294 return flexcan_chip_enable(priv);
1295}
1296
1297static SIMPLE_DEV_PM_OPS(flexcan_pm_ops, flexcan_suspend, flexcan_resume);
1298
1299static struct platform_driver flexcan_driver = {
1300 .driver = {
1301 .name = DRV_NAME,
1302 .pm = &flexcan_pm_ops,
1303 .of_match_table = flexcan_of_match,
1304 },
1305 .probe = flexcan_probe,
1306 .remove = flexcan_remove,
1307 .id_table = flexcan_id_table,
1308};
1309
1310module_platform_driver(flexcan_driver);
1311
1312MODULE_AUTHOR("Sascha Hauer <kernel@pengutronix.de>, "
1313 "Marc Kleine-Budde <kernel@pengutronix.de>");
1314MODULE_LICENSE("GPL v2");
1315MODULE_DESCRIPTION("CAN port driver for flexcan based chip");