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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * GPIO driver for the WinSystems WS16C48
4 * Copyright (C) 2016 William Breathitt Gray
5 */
6#include <linux/bitmap.h>
7#include <linux/bitops.h>
8#include <linux/device.h>
9#include <linux/errno.h>
10#include <linux/gpio/driver.h>
11#include <linux/io.h>
12#include <linux/ioport.h>
13#include <linux/interrupt.h>
14#include <linux/irqdesc.h>
15#include <linux/isa.h>
16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/moduleparam.h>
19#include <linux/spinlock.h>
20
21#define WS16C48_EXTENT 16
22#define MAX_NUM_WS16C48 max_num_isa_dev(WS16C48_EXTENT)
23
24static unsigned int base[MAX_NUM_WS16C48];
25static unsigned int num_ws16c48;
26module_param_hw_array(base, uint, ioport, &num_ws16c48, 0);
27MODULE_PARM_DESC(base, "WinSystems WS16C48 base addresses");
28
29static unsigned int irq[MAX_NUM_WS16C48];
30module_param_hw_array(irq, uint, irq, NULL, 0);
31MODULE_PARM_DESC(irq, "WinSystems WS16C48 interrupt line numbers");
32
33/**
34 * struct ws16c48_gpio - GPIO device private data structure
35 * @chip: instance of the gpio_chip
36 * @io_state: bit I/O state (whether bit is set to input or output)
37 * @out_state: output bits state
38 * @lock: synchronization lock to prevent I/O race conditions
39 * @irq_mask: I/O bits affected by interrupts
40 * @flow_mask: IRQ flow type mask for the respective I/O bits
41 * @base: base port address of the GPIO device
42 */
43struct ws16c48_gpio {
44 struct gpio_chip chip;
45 unsigned char io_state[6];
46 unsigned char out_state[6];
47 raw_spinlock_t lock;
48 unsigned long irq_mask;
49 unsigned long flow_mask;
50 unsigned base;
51};
52
53static int ws16c48_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
54{
55 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
56 const unsigned port = offset / 8;
57 const unsigned mask = BIT(offset % 8);
58
59 if (ws16c48gpio->io_state[port] & mask)
60 return GPIO_LINE_DIRECTION_IN;
61
62 return GPIO_LINE_DIRECTION_OUT;
63}
64
65static int ws16c48_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
66{
67 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
68 const unsigned port = offset / 8;
69 const unsigned mask = BIT(offset % 8);
70 unsigned long flags;
71
72 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
73
74 ws16c48gpio->io_state[port] |= mask;
75 ws16c48gpio->out_state[port] &= ~mask;
76 outb(ws16c48gpio->out_state[port], ws16c48gpio->base + port);
77
78 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
79
80 return 0;
81}
82
83static int ws16c48_gpio_direction_output(struct gpio_chip *chip,
84 unsigned offset, int value)
85{
86 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
87 const unsigned port = offset / 8;
88 const unsigned mask = BIT(offset % 8);
89 unsigned long flags;
90
91 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
92
93 ws16c48gpio->io_state[port] &= ~mask;
94 if (value)
95 ws16c48gpio->out_state[port] |= mask;
96 else
97 ws16c48gpio->out_state[port] &= ~mask;
98 outb(ws16c48gpio->out_state[port], ws16c48gpio->base + port);
99
100 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
101
102 return 0;
103}
104
105static int ws16c48_gpio_get(struct gpio_chip *chip, unsigned offset)
106{
107 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
108 const unsigned port = offset / 8;
109 const unsigned mask = BIT(offset % 8);
110 unsigned long flags;
111 unsigned port_state;
112
113 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
114
115 /* ensure that GPIO is set for input */
116 if (!(ws16c48gpio->io_state[port] & mask)) {
117 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
118 return -EINVAL;
119 }
120
121 port_state = inb(ws16c48gpio->base + port);
122
123 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
124
125 return !!(port_state & mask);
126}
127
128static int ws16c48_gpio_get_multiple(struct gpio_chip *chip,
129 unsigned long *mask, unsigned long *bits)
130{
131 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
132 unsigned long offset;
133 unsigned long gpio_mask;
134 unsigned int port_addr;
135 unsigned long port_state;
136
137 /* clear bits array to a clean slate */
138 bitmap_zero(bits, chip->ngpio);
139
140 for_each_set_clump8(offset, gpio_mask, mask, chip->ngpio) {
141 port_addr = ws16c48gpio->base + offset / 8;
142 port_state = inb(port_addr) & gpio_mask;
143
144 bitmap_set_value8(bits, port_state, offset);
145 }
146
147 return 0;
148}
149
150static void ws16c48_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
151{
152 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
153 const unsigned port = offset / 8;
154 const unsigned mask = BIT(offset % 8);
155 unsigned long flags;
156
157 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
158
159 /* ensure that GPIO is set for output */
160 if (ws16c48gpio->io_state[port] & mask) {
161 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
162 return;
163 }
164
165 if (value)
166 ws16c48gpio->out_state[port] |= mask;
167 else
168 ws16c48gpio->out_state[port] &= ~mask;
169 outb(ws16c48gpio->out_state[port], ws16c48gpio->base + port);
170
171 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
172}
173
174static void ws16c48_gpio_set_multiple(struct gpio_chip *chip,
175 unsigned long *mask, unsigned long *bits)
176{
177 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
178 unsigned long offset;
179 unsigned long gpio_mask;
180 size_t index;
181 unsigned int port_addr;
182 unsigned long bitmask;
183 unsigned long flags;
184
185 for_each_set_clump8(offset, gpio_mask, mask, chip->ngpio) {
186 index = offset / 8;
187 port_addr = ws16c48gpio->base + index;
188
189 /* mask out GPIO configured for input */
190 gpio_mask &= ~ws16c48gpio->io_state[index];
191 bitmask = bitmap_get_value8(bits, offset) & gpio_mask;
192
193 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
194
195 /* update output state data and set device gpio register */
196 ws16c48gpio->out_state[index] &= ~gpio_mask;
197 ws16c48gpio->out_state[index] |= bitmask;
198 outb(ws16c48gpio->out_state[index], port_addr);
199
200 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
201 }
202}
203
204static void ws16c48_irq_ack(struct irq_data *data)
205{
206 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
207 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
208 const unsigned long offset = irqd_to_hwirq(data);
209 const unsigned port = offset / 8;
210 const unsigned mask = BIT(offset % 8);
211 unsigned long flags;
212 unsigned port_state;
213
214 /* only the first 3 ports support interrupts */
215 if (port > 2)
216 return;
217
218 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
219
220 port_state = ws16c48gpio->irq_mask >> (8*port);
221
222 outb(0x80, ws16c48gpio->base + 7);
223 outb(port_state & ~mask, ws16c48gpio->base + 8 + port);
224 outb(port_state | mask, ws16c48gpio->base + 8 + port);
225 outb(0xC0, ws16c48gpio->base + 7);
226
227 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
228}
229
230static void ws16c48_irq_mask(struct irq_data *data)
231{
232 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
233 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
234 const unsigned long offset = irqd_to_hwirq(data);
235 const unsigned long mask = BIT(offset);
236 const unsigned port = offset / 8;
237 unsigned long flags;
238
239 /* only the first 3 ports support interrupts */
240 if (port > 2)
241 return;
242
243 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
244
245 ws16c48gpio->irq_mask &= ~mask;
246
247 outb(0x80, ws16c48gpio->base + 7);
248 outb(ws16c48gpio->irq_mask >> (8*port), ws16c48gpio->base + 8 + port);
249 outb(0xC0, ws16c48gpio->base + 7);
250
251 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
252}
253
254static void ws16c48_irq_unmask(struct irq_data *data)
255{
256 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
257 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
258 const unsigned long offset = irqd_to_hwirq(data);
259 const unsigned long mask = BIT(offset);
260 const unsigned port = offset / 8;
261 unsigned long flags;
262
263 /* only the first 3 ports support interrupts */
264 if (port > 2)
265 return;
266
267 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
268
269 ws16c48gpio->irq_mask |= mask;
270
271 outb(0x80, ws16c48gpio->base + 7);
272 outb(ws16c48gpio->irq_mask >> (8*port), ws16c48gpio->base + 8 + port);
273 outb(0xC0, ws16c48gpio->base + 7);
274
275 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
276}
277
278static int ws16c48_irq_set_type(struct irq_data *data, unsigned flow_type)
279{
280 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
281 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
282 const unsigned long offset = irqd_to_hwirq(data);
283 const unsigned long mask = BIT(offset);
284 const unsigned port = offset / 8;
285 unsigned long flags;
286
287 /* only the first 3 ports support interrupts */
288 if (port > 2)
289 return -EINVAL;
290
291 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
292
293 switch (flow_type) {
294 case IRQ_TYPE_NONE:
295 break;
296 case IRQ_TYPE_EDGE_RISING:
297 ws16c48gpio->flow_mask |= mask;
298 break;
299 case IRQ_TYPE_EDGE_FALLING:
300 ws16c48gpio->flow_mask &= ~mask;
301 break;
302 default:
303 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
304 return -EINVAL;
305 }
306
307 outb(0x40, ws16c48gpio->base + 7);
308 outb(ws16c48gpio->flow_mask >> (8*port), ws16c48gpio->base + 8 + port);
309 outb(0xC0, ws16c48gpio->base + 7);
310
311 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
312
313 return 0;
314}
315
316static struct irq_chip ws16c48_irqchip = {
317 .name = "ws16c48",
318 .irq_ack = ws16c48_irq_ack,
319 .irq_mask = ws16c48_irq_mask,
320 .irq_unmask = ws16c48_irq_unmask,
321 .irq_set_type = ws16c48_irq_set_type
322};
323
324static irqreturn_t ws16c48_irq_handler(int irq, void *dev_id)
325{
326 struct ws16c48_gpio *const ws16c48gpio = dev_id;
327 struct gpio_chip *const chip = &ws16c48gpio->chip;
328 unsigned long int_pending;
329 unsigned long port;
330 unsigned long int_id;
331 unsigned long gpio;
332
333 int_pending = inb(ws16c48gpio->base + 6) & 0x7;
334 if (!int_pending)
335 return IRQ_NONE;
336
337 /* loop until all pending interrupts are handled */
338 do {
339 for_each_set_bit(port, &int_pending, 3) {
340 int_id = inb(ws16c48gpio->base + 8 + port);
341 for_each_set_bit(gpio, &int_id, 8)
342 generic_handle_irq(irq_find_mapping(
343 chip->irq.domain, gpio + 8*port));
344 }
345
346 int_pending = inb(ws16c48gpio->base + 6) & 0x7;
347 } while (int_pending);
348
349 return IRQ_HANDLED;
350}
351
352#define WS16C48_NGPIO 48
353static const char *ws16c48_names[WS16C48_NGPIO] = {
354 "Port 0 Bit 0", "Port 0 Bit 1", "Port 0 Bit 2", "Port 0 Bit 3",
355 "Port 0 Bit 4", "Port 0 Bit 5", "Port 0 Bit 6", "Port 0 Bit 7",
356 "Port 1 Bit 0", "Port 1 Bit 1", "Port 1 Bit 2", "Port 1 Bit 3",
357 "Port 1 Bit 4", "Port 1 Bit 5", "Port 1 Bit 6", "Port 1 Bit 7",
358 "Port 2 Bit 0", "Port 2 Bit 1", "Port 2 Bit 2", "Port 2 Bit 3",
359 "Port 2 Bit 4", "Port 2 Bit 5", "Port 2 Bit 6", "Port 2 Bit 7",
360 "Port 3 Bit 0", "Port 3 Bit 1", "Port 3 Bit 2", "Port 3 Bit 3",
361 "Port 3 Bit 4", "Port 3 Bit 5", "Port 3 Bit 6", "Port 3 Bit 7",
362 "Port 4 Bit 0", "Port 4 Bit 1", "Port 4 Bit 2", "Port 4 Bit 3",
363 "Port 4 Bit 4", "Port 4 Bit 5", "Port 4 Bit 6", "Port 4 Bit 7",
364 "Port 5 Bit 0", "Port 5 Bit 1", "Port 5 Bit 2", "Port 5 Bit 3",
365 "Port 5 Bit 4", "Port 5 Bit 5", "Port 5 Bit 6", "Port 5 Bit 7"
366};
367
368static int ws16c48_irq_init_hw(struct gpio_chip *gc)
369{
370 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(gc);
371
372 /* Disable IRQ by default */
373 outb(0x80, ws16c48gpio->base + 7);
374 outb(0, ws16c48gpio->base + 8);
375 outb(0, ws16c48gpio->base + 9);
376 outb(0, ws16c48gpio->base + 10);
377 outb(0xC0, ws16c48gpio->base + 7);
378
379 return 0;
380}
381
382static int ws16c48_probe(struct device *dev, unsigned int id)
383{
384 struct ws16c48_gpio *ws16c48gpio;
385 const char *const name = dev_name(dev);
386 struct gpio_irq_chip *girq;
387 int err;
388
389 ws16c48gpio = devm_kzalloc(dev, sizeof(*ws16c48gpio), GFP_KERNEL);
390 if (!ws16c48gpio)
391 return -ENOMEM;
392
393 if (!devm_request_region(dev, base[id], WS16C48_EXTENT, name)) {
394 dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n",
395 base[id], base[id] + WS16C48_EXTENT);
396 return -EBUSY;
397 }
398
399 ws16c48gpio->chip.label = name;
400 ws16c48gpio->chip.parent = dev;
401 ws16c48gpio->chip.owner = THIS_MODULE;
402 ws16c48gpio->chip.base = -1;
403 ws16c48gpio->chip.ngpio = WS16C48_NGPIO;
404 ws16c48gpio->chip.names = ws16c48_names;
405 ws16c48gpio->chip.get_direction = ws16c48_gpio_get_direction;
406 ws16c48gpio->chip.direction_input = ws16c48_gpio_direction_input;
407 ws16c48gpio->chip.direction_output = ws16c48_gpio_direction_output;
408 ws16c48gpio->chip.get = ws16c48_gpio_get;
409 ws16c48gpio->chip.get_multiple = ws16c48_gpio_get_multiple;
410 ws16c48gpio->chip.set = ws16c48_gpio_set;
411 ws16c48gpio->chip.set_multiple = ws16c48_gpio_set_multiple;
412 ws16c48gpio->base = base[id];
413
414 girq = &ws16c48gpio->chip.irq;
415 girq->chip = &ws16c48_irqchip;
416 /* This will let us handle the parent IRQ in the driver */
417 girq->parent_handler = NULL;
418 girq->num_parents = 0;
419 girq->parents = NULL;
420 girq->default_type = IRQ_TYPE_NONE;
421 girq->handler = handle_edge_irq;
422 girq->init_hw = ws16c48_irq_init_hw;
423
424 raw_spin_lock_init(&ws16c48gpio->lock);
425
426 err = devm_gpiochip_add_data(dev, &ws16c48gpio->chip, ws16c48gpio);
427 if (err) {
428 dev_err(dev, "GPIO registering failed (%d)\n", err);
429 return err;
430 }
431
432 err = devm_request_irq(dev, irq[id], ws16c48_irq_handler, IRQF_SHARED,
433 name, ws16c48gpio);
434 if (err) {
435 dev_err(dev, "IRQ handler registering failed (%d)\n", err);
436 return err;
437 }
438
439 return 0;
440}
441
442static struct isa_driver ws16c48_driver = {
443 .probe = ws16c48_probe,
444 .driver = {
445 .name = "ws16c48"
446 },
447};
448
449module_isa_driver(ws16c48_driver, num_ws16c48);
450
451MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>");
452MODULE_DESCRIPTION("WinSystems WS16C48 GPIO driver");
453MODULE_LICENSE("GPL v2");
1/*
2 * GPIO driver for the WinSystems WS16C48
3 * Copyright (C) 2016 William Breathitt Gray
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License, version 2, as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
13 */
14#include <linux/bitops.h>
15#include <linux/device.h>
16#include <linux/errno.h>
17#include <linux/gpio/driver.h>
18#include <linux/io.h>
19#include <linux/ioport.h>
20#include <linux/interrupt.h>
21#include <linux/irqdesc.h>
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/moduleparam.h>
25#include <linux/platform_device.h>
26#include <linux/spinlock.h>
27
28static unsigned ws16c48_base;
29module_param(ws16c48_base, uint, 0);
30MODULE_PARM_DESC(ws16c48_base, "WinSystems WS16C48 base address");
31static unsigned ws16c48_irq;
32module_param(ws16c48_irq, uint, 0);
33MODULE_PARM_DESC(ws16c48_irq, "WinSystems WS16C48 interrupt line number");
34
35/**
36 * struct ws16c48_gpio - GPIO device private data structure
37 * @chip: instance of the gpio_chip
38 * @io_state: bit I/O state (whether bit is set to input or output)
39 * @out_state: output bits state
40 * @lock: synchronization lock to prevent I/O race conditions
41 * @irq_mask: I/O bits affected by interrupts
42 * @flow_mask: IRQ flow type mask for the respective I/O bits
43 * @base: base port address of the GPIO device
44 * @irq: Interrupt line number
45 */
46struct ws16c48_gpio {
47 struct gpio_chip chip;
48 unsigned char io_state[6];
49 unsigned char out_state[6];
50 spinlock_t lock;
51 unsigned long irq_mask;
52 unsigned long flow_mask;
53 unsigned base;
54 unsigned irq;
55};
56
57static int ws16c48_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
58{
59 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
60 const unsigned port = offset / 8;
61 const unsigned mask = BIT(offset % 8);
62
63 return !!(ws16c48gpio->io_state[port] & mask);
64}
65
66static int ws16c48_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
67{
68 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
69 const unsigned port = offset / 8;
70 const unsigned mask = BIT(offset % 8);
71 unsigned long flags;
72
73 spin_lock_irqsave(&ws16c48gpio->lock, flags);
74
75 ws16c48gpio->io_state[port] |= mask;
76 ws16c48gpio->out_state[port] &= ~mask;
77 outb(ws16c48gpio->out_state[port], ws16c48gpio->base + port);
78
79 spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
80
81 return 0;
82}
83
84static int ws16c48_gpio_direction_output(struct gpio_chip *chip,
85 unsigned offset, int value)
86{
87 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
88 const unsigned port = offset / 8;
89 const unsigned mask = BIT(offset % 8);
90 unsigned long flags;
91
92 spin_lock_irqsave(&ws16c48gpio->lock, flags);
93
94 ws16c48gpio->io_state[port] &= ~mask;
95 if (value)
96 ws16c48gpio->out_state[port] |= mask;
97 else
98 ws16c48gpio->out_state[port] &= ~mask;
99 outb(ws16c48gpio->out_state[port], ws16c48gpio->base + port);
100
101 spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
102
103 return 0;
104}
105
106static int ws16c48_gpio_get(struct gpio_chip *chip, unsigned offset)
107{
108 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
109 const unsigned port = offset / 8;
110 const unsigned mask = BIT(offset % 8);
111 unsigned long flags;
112 unsigned port_state;
113
114 spin_lock_irqsave(&ws16c48gpio->lock, flags);
115
116 /* ensure that GPIO is set for input */
117 if (!(ws16c48gpio->io_state[port] & mask)) {
118 spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
119 return -EINVAL;
120 }
121
122 port_state = inb(ws16c48gpio->base + port);
123
124 spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
125
126 return !!(port_state & mask);
127}
128
129static void ws16c48_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
130{
131 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
132 const unsigned port = offset / 8;
133 const unsigned mask = BIT(offset % 8);
134 unsigned long flags;
135
136 spin_lock_irqsave(&ws16c48gpio->lock, flags);
137
138 /* ensure that GPIO is set for output */
139 if (ws16c48gpio->io_state[port] & mask) {
140 spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
141 return;
142 }
143
144 if (value)
145 ws16c48gpio->out_state[port] |= mask;
146 else
147 ws16c48gpio->out_state[port] &= ~mask;
148 outb(ws16c48gpio->out_state[port], ws16c48gpio->base + port);
149
150 spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
151}
152
153static void ws16c48_irq_ack(struct irq_data *data)
154{
155 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
156 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
157 const unsigned long offset = irqd_to_hwirq(data);
158 const unsigned port = offset / 8;
159 const unsigned mask = BIT(offset % 8);
160 unsigned long flags;
161 unsigned port_state;
162
163 /* only the first 3 ports support interrupts */
164 if (port > 2)
165 return;
166
167 spin_lock_irqsave(&ws16c48gpio->lock, flags);
168
169 port_state = ws16c48gpio->irq_mask >> (8*port);
170
171 outb(0x80, ws16c48gpio->base + 7);
172 outb(port_state & ~mask, ws16c48gpio->base + 8 + port);
173 outb(port_state | mask, ws16c48gpio->base + 8 + port);
174 outb(0xC0, ws16c48gpio->base + 7);
175
176 spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
177}
178
179static void ws16c48_irq_mask(struct irq_data *data)
180{
181 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
182 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
183 const unsigned long offset = irqd_to_hwirq(data);
184 const unsigned long mask = BIT(offset);
185 const unsigned port = offset / 8;
186 unsigned long flags;
187
188 /* only the first 3 ports support interrupts */
189 if (port > 2)
190 return;
191
192 spin_lock_irqsave(&ws16c48gpio->lock, flags);
193
194 ws16c48gpio->irq_mask &= ~mask;
195
196 outb(0x80, ws16c48gpio->base + 7);
197 outb(ws16c48gpio->irq_mask >> (8*port), ws16c48gpio->base + 8 + port);
198 outb(0xC0, ws16c48gpio->base + 7);
199
200 spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
201}
202
203static void ws16c48_irq_unmask(struct irq_data *data)
204{
205 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
206 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
207 const unsigned long offset = irqd_to_hwirq(data);
208 const unsigned long mask = BIT(offset);
209 const unsigned port = offset / 8;
210 unsigned long flags;
211
212 /* only the first 3 ports support interrupts */
213 if (port > 2)
214 return;
215
216 spin_lock_irqsave(&ws16c48gpio->lock, flags);
217
218 ws16c48gpio->irq_mask |= mask;
219
220 outb(0x80, ws16c48gpio->base + 7);
221 outb(ws16c48gpio->irq_mask >> (8*port), ws16c48gpio->base + 8 + port);
222 outb(0xC0, ws16c48gpio->base + 7);
223
224 spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
225}
226
227static int ws16c48_irq_set_type(struct irq_data *data, unsigned flow_type)
228{
229 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
230 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
231 const unsigned long offset = irqd_to_hwirq(data);
232 const unsigned long mask = BIT(offset);
233 const unsigned port = offset / 8;
234 unsigned long flags;
235
236 /* only the first 3 ports support interrupts */
237 if (port > 2)
238 return -EINVAL;
239
240 spin_lock_irqsave(&ws16c48gpio->lock, flags);
241
242 switch (flow_type) {
243 case IRQ_TYPE_NONE:
244 break;
245 case IRQ_TYPE_EDGE_RISING:
246 ws16c48gpio->flow_mask |= mask;
247 break;
248 case IRQ_TYPE_EDGE_FALLING:
249 ws16c48gpio->flow_mask &= ~mask;
250 break;
251 default:
252 spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
253 return -EINVAL;
254 }
255
256 outb(0x40, ws16c48gpio->base + 7);
257 outb(ws16c48gpio->flow_mask >> (8*port), ws16c48gpio->base + 8 + port);
258 outb(0xC0, ws16c48gpio->base + 7);
259
260 spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
261
262 return 0;
263}
264
265static struct irq_chip ws16c48_irqchip = {
266 .name = "ws16c48",
267 .irq_ack = ws16c48_irq_ack,
268 .irq_mask = ws16c48_irq_mask,
269 .irq_unmask = ws16c48_irq_unmask,
270 .irq_set_type = ws16c48_irq_set_type
271};
272
273static irqreturn_t ws16c48_irq_handler(int irq, void *dev_id)
274{
275 struct ws16c48_gpio *const ws16c48gpio = dev_id;
276 struct gpio_chip *const chip = &ws16c48gpio->chip;
277 unsigned long int_pending;
278 unsigned long port;
279 unsigned long int_id;
280 unsigned long gpio;
281
282 int_pending = inb(ws16c48gpio->base + 6) & 0x7;
283 if (!int_pending)
284 return IRQ_NONE;
285
286 /* loop until all pending interrupts are handled */
287 do {
288 for_each_set_bit(port, &int_pending, 3) {
289 int_id = inb(ws16c48gpio->base + 8 + port);
290 for_each_set_bit(gpio, &int_id, 8)
291 generic_handle_irq(irq_find_mapping(
292 chip->irqdomain, gpio + 8*port));
293 }
294
295 int_pending = inb(ws16c48gpio->base + 6) & 0x7;
296 } while (int_pending);
297
298 return IRQ_HANDLED;
299}
300
301static int __init ws16c48_probe(struct platform_device *pdev)
302{
303 struct device *dev = &pdev->dev;
304 struct ws16c48_gpio *ws16c48gpio;
305 const unsigned base = ws16c48_base;
306 const unsigned extent = 16;
307 const char *const name = dev_name(dev);
308 int err;
309 const unsigned irq = ws16c48_irq;
310
311 ws16c48gpio = devm_kzalloc(dev, sizeof(*ws16c48gpio), GFP_KERNEL);
312 if (!ws16c48gpio)
313 return -ENOMEM;
314
315 if (!devm_request_region(dev, base, extent, name)) {
316 dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n",
317 base, base + extent);
318 return -EBUSY;
319 }
320
321 ws16c48gpio->chip.label = name;
322 ws16c48gpio->chip.parent = dev;
323 ws16c48gpio->chip.owner = THIS_MODULE;
324 ws16c48gpio->chip.base = -1;
325 ws16c48gpio->chip.ngpio = 48;
326 ws16c48gpio->chip.get_direction = ws16c48_gpio_get_direction;
327 ws16c48gpio->chip.direction_input = ws16c48_gpio_direction_input;
328 ws16c48gpio->chip.direction_output = ws16c48_gpio_direction_output;
329 ws16c48gpio->chip.get = ws16c48_gpio_get;
330 ws16c48gpio->chip.set = ws16c48_gpio_set;
331 ws16c48gpio->base = base;
332 ws16c48gpio->irq = irq;
333
334 spin_lock_init(&ws16c48gpio->lock);
335
336 dev_set_drvdata(dev, ws16c48gpio);
337
338 err = gpiochip_add_data(&ws16c48gpio->chip, ws16c48gpio);
339 if (err) {
340 dev_err(dev, "GPIO registering failed (%d)\n", err);
341 return err;
342 }
343
344 /* Disable IRQ by default */
345 outb(0x80, base + 7);
346 outb(0, base + 8);
347 outb(0, base + 9);
348 outb(0, base + 10);
349 outb(0xC0, base + 7);
350
351 err = gpiochip_irqchip_add(&ws16c48gpio->chip, &ws16c48_irqchip, 0,
352 handle_edge_irq, IRQ_TYPE_NONE);
353 if (err) {
354 dev_err(dev, "Could not add irqchip (%d)\n", err);
355 goto err_gpiochip_remove;
356 }
357
358 err = request_irq(irq, ws16c48_irq_handler, IRQF_SHARED, name,
359 ws16c48gpio);
360 if (err) {
361 dev_err(dev, "IRQ handler registering failed (%d)\n", err);
362 goto err_gpiochip_remove;
363 }
364
365 return 0;
366
367err_gpiochip_remove:
368 gpiochip_remove(&ws16c48gpio->chip);
369 return err;
370}
371
372static int ws16c48_remove(struct platform_device *pdev)
373{
374 struct ws16c48_gpio *const ws16c48gpio = platform_get_drvdata(pdev);
375
376 free_irq(ws16c48gpio->irq, ws16c48gpio);
377 gpiochip_remove(&ws16c48gpio->chip);
378
379 return 0;
380}
381
382static struct platform_device *ws16c48_device;
383
384static struct platform_driver ws16c48_driver = {
385 .driver = {
386 .name = "ws16c48"
387 },
388 .remove = ws16c48_remove
389};
390
391static void __exit ws16c48_exit(void)
392{
393 platform_device_unregister(ws16c48_device);
394 platform_driver_unregister(&ws16c48_driver);
395}
396
397static int __init ws16c48_init(void)
398{
399 int err;
400
401 ws16c48_device = platform_device_alloc(ws16c48_driver.driver.name, -1);
402 if (!ws16c48_device)
403 return -ENOMEM;
404
405 err = platform_device_add(ws16c48_device);
406 if (err)
407 goto err_platform_device;
408
409 err = platform_driver_probe(&ws16c48_driver, ws16c48_probe);
410 if (err)
411 goto err_platform_driver;
412
413 return 0;
414
415err_platform_driver:
416 platform_device_del(ws16c48_device);
417err_platform_device:
418 platform_device_put(ws16c48_device);
419 return err;
420}
421
422module_init(ws16c48_init);
423module_exit(ws16c48_exit);
424
425MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>");
426MODULE_DESCRIPTION("WinSystems WS16C48 GPIO driver");
427MODULE_LICENSE("GPL v2");