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1/*
2 * Copyright (C) 2015-2017 Broadcom
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation version 2.
7 *
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/bitops.h>
15#include <linux/gpio/driver.h>
16#include <linux/of_device.h>
17#include <linux/of_irq.h>
18#include <linux/module.h>
19#include <linux/irqdomain.h>
20#include <linux/irqchip/chained_irq.h>
21#include <linux/interrupt.h>
22
23enum gio_reg_index {
24 GIO_REG_ODEN = 0,
25 GIO_REG_DATA,
26 GIO_REG_IODIR,
27 GIO_REG_EC,
28 GIO_REG_EI,
29 GIO_REG_MASK,
30 GIO_REG_LEVEL,
31 GIO_REG_STAT,
32 NUMBER_OF_GIO_REGISTERS
33};
34
35#define GIO_BANK_SIZE (NUMBER_OF_GIO_REGISTERS * sizeof(u32))
36#define GIO_BANK_OFF(bank, off) (((bank) * GIO_BANK_SIZE) + (off * sizeof(u32)))
37#define GIO_ODEN(bank) GIO_BANK_OFF(bank, GIO_REG_ODEN)
38#define GIO_DATA(bank) GIO_BANK_OFF(bank, GIO_REG_DATA)
39#define GIO_IODIR(bank) GIO_BANK_OFF(bank, GIO_REG_IODIR)
40#define GIO_EC(bank) GIO_BANK_OFF(bank, GIO_REG_EC)
41#define GIO_EI(bank) GIO_BANK_OFF(bank, GIO_REG_EI)
42#define GIO_MASK(bank) GIO_BANK_OFF(bank, GIO_REG_MASK)
43#define GIO_LEVEL(bank) GIO_BANK_OFF(bank, GIO_REG_LEVEL)
44#define GIO_STAT(bank) GIO_BANK_OFF(bank, GIO_REG_STAT)
45
46struct brcmstb_gpio_bank {
47 struct list_head node;
48 int id;
49 struct gpio_chip gc;
50 struct brcmstb_gpio_priv *parent_priv;
51 u32 width;
52 u32 wake_active;
53 u32 saved_regs[GIO_REG_STAT]; /* Don't save and restore GIO_REG_STAT */
54};
55
56struct brcmstb_gpio_priv {
57 struct list_head bank_list;
58 void __iomem *reg_base;
59 struct platform_device *pdev;
60 struct irq_domain *irq_domain;
61 struct irq_chip irq_chip;
62 int parent_irq;
63 int gpio_base;
64 int num_gpios;
65 int parent_wake_irq;
66};
67
68#define MAX_GPIO_PER_BANK 32
69#define GPIO_BANK(gpio) ((gpio) >> 5)
70/* assumes MAX_GPIO_PER_BANK is a multiple of 2 */
71#define GPIO_BIT(gpio) ((gpio) & (MAX_GPIO_PER_BANK - 1))
72
73static inline struct brcmstb_gpio_priv *
74brcmstb_gpio_gc_to_priv(struct gpio_chip *gc)
75{
76 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
77 return bank->parent_priv;
78}
79
80static unsigned long
81__brcmstb_gpio_get_active_irqs(struct brcmstb_gpio_bank *bank)
82{
83 void __iomem *reg_base = bank->parent_priv->reg_base;
84
85 return bank->gc.read_reg(reg_base + GIO_STAT(bank->id)) &
86 bank->gc.read_reg(reg_base + GIO_MASK(bank->id));
87}
88
89static unsigned long
90brcmstb_gpio_get_active_irqs(struct brcmstb_gpio_bank *bank)
91{
92 unsigned long status;
93 unsigned long flags;
94
95 spin_lock_irqsave(&bank->gc.bgpio_lock, flags);
96 status = __brcmstb_gpio_get_active_irqs(bank);
97 spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags);
98
99 return status;
100}
101
102static int brcmstb_gpio_hwirq_to_offset(irq_hw_number_t hwirq,
103 struct brcmstb_gpio_bank *bank)
104{
105 return hwirq - (bank->gc.base - bank->parent_priv->gpio_base);
106}
107
108static void brcmstb_gpio_set_imask(struct brcmstb_gpio_bank *bank,
109 unsigned int hwirq, bool enable)
110{
111 struct gpio_chip *gc = &bank->gc;
112 struct brcmstb_gpio_priv *priv = bank->parent_priv;
113 u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(hwirq, bank));
114 u32 imask;
115 unsigned long flags;
116
117 spin_lock_irqsave(&gc->bgpio_lock, flags);
118 imask = gc->read_reg(priv->reg_base + GIO_MASK(bank->id));
119 if (enable)
120 imask |= mask;
121 else
122 imask &= ~mask;
123 gc->write_reg(priv->reg_base + GIO_MASK(bank->id), imask);
124 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
125}
126
127static int brcmstb_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
128{
129 struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc);
130 /* gc_offset is relative to this gpio_chip; want real offset */
131 int hwirq = offset + (gc->base - priv->gpio_base);
132
133 if (hwirq >= priv->num_gpios)
134 return -ENXIO;
135 return irq_create_mapping(priv->irq_domain, hwirq);
136}
137
138/* -------------------- IRQ chip functions -------------------- */
139
140static void brcmstb_gpio_irq_mask(struct irq_data *d)
141{
142 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
143 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
144
145 brcmstb_gpio_set_imask(bank, d->hwirq, false);
146}
147
148static void brcmstb_gpio_irq_unmask(struct irq_data *d)
149{
150 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
151 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
152
153 brcmstb_gpio_set_imask(bank, d->hwirq, true);
154}
155
156static void brcmstb_gpio_irq_ack(struct irq_data *d)
157{
158 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
159 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
160 struct brcmstb_gpio_priv *priv = bank->parent_priv;
161 u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank));
162
163 gc->write_reg(priv->reg_base + GIO_STAT(bank->id), mask);
164}
165
166static int brcmstb_gpio_irq_set_type(struct irq_data *d, unsigned int type)
167{
168 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
169 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
170 struct brcmstb_gpio_priv *priv = bank->parent_priv;
171 u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank));
172 u32 edge_insensitive, iedge_insensitive;
173 u32 edge_config, iedge_config;
174 u32 level, ilevel;
175 unsigned long flags;
176
177 switch (type) {
178 case IRQ_TYPE_LEVEL_LOW:
179 level = mask;
180 edge_config = 0;
181 edge_insensitive = 0;
182 break;
183 case IRQ_TYPE_LEVEL_HIGH:
184 level = mask;
185 edge_config = mask;
186 edge_insensitive = 0;
187 break;
188 case IRQ_TYPE_EDGE_FALLING:
189 level = 0;
190 edge_config = 0;
191 edge_insensitive = 0;
192 break;
193 case IRQ_TYPE_EDGE_RISING:
194 level = 0;
195 edge_config = mask;
196 edge_insensitive = 0;
197 break;
198 case IRQ_TYPE_EDGE_BOTH:
199 level = 0;
200 edge_config = 0; /* don't care, but want known value */
201 edge_insensitive = mask;
202 break;
203 default:
204 return -EINVAL;
205 }
206
207 spin_lock_irqsave(&bank->gc.bgpio_lock, flags);
208
209 iedge_config = bank->gc.read_reg(priv->reg_base +
210 GIO_EC(bank->id)) & ~mask;
211 iedge_insensitive = bank->gc.read_reg(priv->reg_base +
212 GIO_EI(bank->id)) & ~mask;
213 ilevel = bank->gc.read_reg(priv->reg_base +
214 GIO_LEVEL(bank->id)) & ~mask;
215
216 bank->gc.write_reg(priv->reg_base + GIO_EC(bank->id),
217 iedge_config | edge_config);
218 bank->gc.write_reg(priv->reg_base + GIO_EI(bank->id),
219 iedge_insensitive | edge_insensitive);
220 bank->gc.write_reg(priv->reg_base + GIO_LEVEL(bank->id),
221 ilevel | level);
222
223 spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags);
224 return 0;
225}
226
227static int brcmstb_gpio_priv_set_wake(struct brcmstb_gpio_priv *priv,
228 unsigned int enable)
229{
230 int ret = 0;
231
232 if (enable)
233 ret = enable_irq_wake(priv->parent_wake_irq);
234 else
235 ret = disable_irq_wake(priv->parent_wake_irq);
236 if (ret)
237 dev_err(&priv->pdev->dev, "failed to %s wake-up interrupt\n",
238 enable ? "enable" : "disable");
239 return ret;
240}
241
242static int brcmstb_gpio_irq_set_wake(struct irq_data *d, unsigned int enable)
243{
244 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
245 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
246 struct brcmstb_gpio_priv *priv = bank->parent_priv;
247 u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank));
248
249 /*
250 * Do not do anything specific for now, suspend/resume callbacks will
251 * configure the interrupt mask appropriately
252 */
253 if (enable)
254 bank->wake_active |= mask;
255 else
256 bank->wake_active &= ~mask;
257
258 return brcmstb_gpio_priv_set_wake(priv, enable);
259}
260
261static irqreturn_t brcmstb_gpio_wake_irq_handler(int irq, void *data)
262{
263 struct brcmstb_gpio_priv *priv = data;
264
265 if (!priv || irq != priv->parent_wake_irq)
266 return IRQ_NONE;
267
268 /* Nothing to do */
269 return IRQ_HANDLED;
270}
271
272static void brcmstb_gpio_irq_bank_handler(struct brcmstb_gpio_bank *bank)
273{
274 struct brcmstb_gpio_priv *priv = bank->parent_priv;
275 struct irq_domain *domain = priv->irq_domain;
276 int hwbase = bank->gc.base - priv->gpio_base;
277 unsigned long status;
278
279 while ((status = brcmstb_gpio_get_active_irqs(bank))) {
280 unsigned int irq, offset;
281
282 for_each_set_bit(offset, &status, 32) {
283 if (offset >= bank->width)
284 dev_warn(&priv->pdev->dev,
285 "IRQ for invalid GPIO (bank=%d, offset=%d)\n",
286 bank->id, offset);
287 irq = irq_linear_revmap(domain, hwbase + offset);
288 generic_handle_irq(irq);
289 }
290 }
291}
292
293/* Each UPG GIO block has one IRQ for all banks */
294static void brcmstb_gpio_irq_handler(struct irq_desc *desc)
295{
296 struct brcmstb_gpio_priv *priv = irq_desc_get_handler_data(desc);
297 struct irq_chip *chip = irq_desc_get_chip(desc);
298 struct brcmstb_gpio_bank *bank;
299
300 /* Interrupts weren't properly cleared during probe */
301 BUG_ON(!priv || !chip);
302
303 chained_irq_enter(chip, desc);
304 list_for_each_entry(bank, &priv->bank_list, node)
305 brcmstb_gpio_irq_bank_handler(bank);
306 chained_irq_exit(chip, desc);
307}
308
309static struct brcmstb_gpio_bank *brcmstb_gpio_hwirq_to_bank(
310 struct brcmstb_gpio_priv *priv, irq_hw_number_t hwirq)
311{
312 struct brcmstb_gpio_bank *bank;
313 int i = 0;
314
315 /* banks are in descending order */
316 list_for_each_entry_reverse(bank, &priv->bank_list, node) {
317 i += bank->gc.ngpio;
318 if (hwirq < i)
319 return bank;
320 }
321 return NULL;
322}
323
324/*
325 * This lock class tells lockdep that GPIO irqs are in a different
326 * category than their parents, so it won't report false recursion.
327 */
328static struct lock_class_key brcmstb_gpio_irq_lock_class;
329static struct lock_class_key brcmstb_gpio_irq_request_class;
330
331
332static int brcmstb_gpio_irq_map(struct irq_domain *d, unsigned int irq,
333 irq_hw_number_t hwirq)
334{
335 struct brcmstb_gpio_priv *priv = d->host_data;
336 struct brcmstb_gpio_bank *bank =
337 brcmstb_gpio_hwirq_to_bank(priv, hwirq);
338 struct platform_device *pdev = priv->pdev;
339 int ret;
340
341 if (!bank)
342 return -EINVAL;
343
344 dev_dbg(&pdev->dev, "Mapping irq %d for gpio line %d (bank %d)\n",
345 irq, (int)hwirq, bank->id);
346 ret = irq_set_chip_data(irq, &bank->gc);
347 if (ret < 0)
348 return ret;
349 irq_set_lockdep_class(irq, &brcmstb_gpio_irq_lock_class,
350 &brcmstb_gpio_irq_request_class);
351 irq_set_chip_and_handler(irq, &priv->irq_chip, handle_level_irq);
352 irq_set_noprobe(irq);
353 return 0;
354}
355
356static void brcmstb_gpio_irq_unmap(struct irq_domain *d, unsigned int irq)
357{
358 irq_set_chip_and_handler(irq, NULL, NULL);
359 irq_set_chip_data(irq, NULL);
360}
361
362static const struct irq_domain_ops brcmstb_gpio_irq_domain_ops = {
363 .map = brcmstb_gpio_irq_map,
364 .unmap = brcmstb_gpio_irq_unmap,
365 .xlate = irq_domain_xlate_twocell,
366};
367
368/* Make sure that the number of banks matches up between properties */
369static int brcmstb_gpio_sanity_check_banks(struct device *dev,
370 struct device_node *np, struct resource *res)
371{
372 int res_num_banks = resource_size(res) / GIO_BANK_SIZE;
373 int num_banks =
374 of_property_count_u32_elems(np, "brcm,gpio-bank-widths");
375
376 if (res_num_banks != num_banks) {
377 dev_err(dev, "Mismatch in banks: res had %d, bank-widths had %d\n",
378 res_num_banks, num_banks);
379 return -EINVAL;
380 } else {
381 return 0;
382 }
383}
384
385static int brcmstb_gpio_remove(struct platform_device *pdev)
386{
387 struct brcmstb_gpio_priv *priv = platform_get_drvdata(pdev);
388 struct brcmstb_gpio_bank *bank;
389 int offset, ret = 0, virq;
390
391 if (!priv) {
392 dev_err(&pdev->dev, "called %s without drvdata!\n", __func__);
393 return -EFAULT;
394 }
395
396 if (priv->parent_irq > 0)
397 irq_set_chained_handler_and_data(priv->parent_irq, NULL, NULL);
398
399 /* Remove all IRQ mappings and delete the domain */
400 if (priv->irq_domain) {
401 for (offset = 0; offset < priv->num_gpios; offset++) {
402 virq = irq_find_mapping(priv->irq_domain, offset);
403 irq_dispose_mapping(virq);
404 }
405 irq_domain_remove(priv->irq_domain);
406 }
407
408 /*
409 * You can lose return values below, but we report all errors, and it's
410 * more important to actually perform all of the steps.
411 */
412 list_for_each_entry(bank, &priv->bank_list, node)
413 gpiochip_remove(&bank->gc);
414
415 return ret;
416}
417
418static int brcmstb_gpio_of_xlate(struct gpio_chip *gc,
419 const struct of_phandle_args *gpiospec, u32 *flags)
420{
421 struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc);
422 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
423 int offset;
424
425 if (gc->of_gpio_n_cells != 2) {
426 WARN_ON(1);
427 return -EINVAL;
428 }
429
430 if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells))
431 return -EINVAL;
432
433 offset = gpiospec->args[0] - (gc->base - priv->gpio_base);
434 if (offset >= gc->ngpio || offset < 0)
435 return -EINVAL;
436
437 if (unlikely(offset >= bank->width)) {
438 dev_warn_ratelimited(&priv->pdev->dev,
439 "Received request for invalid GPIO offset %d\n",
440 gpiospec->args[0]);
441 }
442
443 if (flags)
444 *flags = gpiospec->args[1];
445
446 return offset;
447}
448
449/* priv->parent_irq and priv->num_gpios must be set before calling */
450static int brcmstb_gpio_irq_setup(struct platform_device *pdev,
451 struct brcmstb_gpio_priv *priv)
452{
453 struct device *dev = &pdev->dev;
454 struct device_node *np = dev->of_node;
455 int err;
456
457 priv->irq_domain =
458 irq_domain_add_linear(np, priv->num_gpios,
459 &brcmstb_gpio_irq_domain_ops,
460 priv);
461 if (!priv->irq_domain) {
462 dev_err(dev, "Couldn't allocate IRQ domain\n");
463 return -ENXIO;
464 }
465
466 if (of_property_read_bool(np, "wakeup-source")) {
467 priv->parent_wake_irq = platform_get_irq(pdev, 1);
468 if (priv->parent_wake_irq < 0) {
469 priv->parent_wake_irq = 0;
470 dev_warn(dev,
471 "Couldn't get wake IRQ - GPIOs will not be able to wake from sleep");
472 } else {
473 /*
474 * Set wakeup capability so we can process boot-time
475 * "wakeups" (e.g., from S5 cold boot)
476 */
477 device_set_wakeup_capable(dev, true);
478 device_wakeup_enable(dev);
479 err = devm_request_irq(dev, priv->parent_wake_irq,
480 brcmstb_gpio_wake_irq_handler,
481 IRQF_SHARED,
482 "brcmstb-gpio-wake", priv);
483
484 if (err < 0) {
485 dev_err(dev, "Couldn't request wake IRQ");
486 goto out_free_domain;
487 }
488 }
489 }
490
491 priv->irq_chip.name = dev_name(dev);
492 priv->irq_chip.irq_disable = brcmstb_gpio_irq_mask;
493 priv->irq_chip.irq_mask = brcmstb_gpio_irq_mask;
494 priv->irq_chip.irq_unmask = brcmstb_gpio_irq_unmask;
495 priv->irq_chip.irq_ack = brcmstb_gpio_irq_ack;
496 priv->irq_chip.irq_set_type = brcmstb_gpio_irq_set_type;
497
498 if (priv->parent_wake_irq)
499 priv->irq_chip.irq_set_wake = brcmstb_gpio_irq_set_wake;
500
501 irq_set_chained_handler_and_data(priv->parent_irq,
502 brcmstb_gpio_irq_handler, priv);
503 irq_set_status_flags(priv->parent_irq, IRQ_DISABLE_UNLAZY);
504
505 return 0;
506
507out_free_domain:
508 irq_domain_remove(priv->irq_domain);
509
510 return err;
511}
512
513static void brcmstb_gpio_bank_save(struct brcmstb_gpio_priv *priv,
514 struct brcmstb_gpio_bank *bank)
515{
516 struct gpio_chip *gc = &bank->gc;
517 unsigned int i;
518
519 for (i = 0; i < GIO_REG_STAT; i++)
520 bank->saved_regs[i] = gc->read_reg(priv->reg_base +
521 GIO_BANK_OFF(bank->id, i));
522}
523
524static void brcmstb_gpio_quiesce(struct device *dev, bool save)
525{
526 struct brcmstb_gpio_priv *priv = dev_get_drvdata(dev);
527 struct brcmstb_gpio_bank *bank;
528 struct gpio_chip *gc;
529 u32 imask;
530
531 /* disable non-wake interrupt */
532 if (priv->parent_irq >= 0)
533 disable_irq(priv->parent_irq);
534
535 list_for_each_entry(bank, &priv->bank_list, node) {
536 gc = &bank->gc;
537
538 if (save)
539 brcmstb_gpio_bank_save(priv, bank);
540
541 /* Unmask GPIOs which have been flagged as wake-up sources */
542 if (priv->parent_wake_irq)
543 imask = bank->wake_active;
544 else
545 imask = 0;
546 gc->write_reg(priv->reg_base + GIO_MASK(bank->id),
547 imask);
548 }
549}
550
551static void brcmstb_gpio_shutdown(struct platform_device *pdev)
552{
553 /* Enable GPIO for S5 cold boot */
554 brcmstb_gpio_quiesce(&pdev->dev, false);
555}
556
557#ifdef CONFIG_PM_SLEEP
558static void brcmstb_gpio_bank_restore(struct brcmstb_gpio_priv *priv,
559 struct brcmstb_gpio_bank *bank)
560{
561 struct gpio_chip *gc = &bank->gc;
562 unsigned int i;
563
564 for (i = 0; i < GIO_REG_STAT; i++)
565 gc->write_reg(priv->reg_base + GIO_BANK_OFF(bank->id, i),
566 bank->saved_regs[i]);
567}
568
569static int brcmstb_gpio_suspend(struct device *dev)
570{
571 brcmstb_gpio_quiesce(dev, true);
572 return 0;
573}
574
575static int brcmstb_gpio_resume(struct device *dev)
576{
577 struct brcmstb_gpio_priv *priv = dev_get_drvdata(dev);
578 struct brcmstb_gpio_bank *bank;
579 bool need_wakeup_event = false;
580
581 list_for_each_entry(bank, &priv->bank_list, node) {
582 need_wakeup_event |= !!__brcmstb_gpio_get_active_irqs(bank);
583 brcmstb_gpio_bank_restore(priv, bank);
584 }
585
586 if (priv->parent_wake_irq && need_wakeup_event)
587 pm_wakeup_event(dev, 0);
588
589 /* enable non-wake interrupt */
590 if (priv->parent_irq >= 0)
591 enable_irq(priv->parent_irq);
592
593 return 0;
594}
595
596#else
597#define brcmstb_gpio_suspend NULL
598#define brcmstb_gpio_resume NULL
599#endif /* CONFIG_PM_SLEEP */
600
601static const struct dev_pm_ops brcmstb_gpio_pm_ops = {
602 .suspend_noirq = brcmstb_gpio_suspend,
603 .resume_noirq = brcmstb_gpio_resume,
604};
605
606static void brcmstb_gpio_set_names(struct device *dev,
607 struct brcmstb_gpio_bank *bank)
608{
609 struct device_node *np = dev->of_node;
610 const char **names;
611 int nstrings, base;
612 unsigned int i;
613
614 base = bank->id * MAX_GPIO_PER_BANK;
615
616 nstrings = of_property_count_strings(np, "gpio-line-names");
617 if (nstrings <= base)
618 /* Line names not present */
619 return;
620
621 names = devm_kcalloc(dev, MAX_GPIO_PER_BANK, sizeof(*names),
622 GFP_KERNEL);
623 if (!names)
624 return;
625
626 /*
627 * Make sure to not index beyond the end of the number of descriptors
628 * of the GPIO device.
629 */
630 for (i = 0; i < bank->width; i++) {
631 const char *name;
632 int ret;
633
634 ret = of_property_read_string_index(np, "gpio-line-names",
635 base + i, &name);
636 if (ret) {
637 if (ret != -ENODATA)
638 dev_err(dev, "unable to name line %d: %d\n",
639 base + i, ret);
640 break;
641 }
642 if (*name)
643 names[i] = name;
644 }
645
646 bank->gc.names = names;
647}
648
649static int brcmstb_gpio_probe(struct platform_device *pdev)
650{
651 struct device *dev = &pdev->dev;
652 struct device_node *np = dev->of_node;
653 void __iomem *reg_base;
654 struct brcmstb_gpio_priv *priv;
655 struct resource *res;
656 struct property *prop;
657 const __be32 *p;
658 u32 bank_width;
659 int num_banks = 0;
660 int err;
661 static int gpio_base;
662 unsigned long flags = 0;
663 bool need_wakeup_event = false;
664
665 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
666 if (!priv)
667 return -ENOMEM;
668 platform_set_drvdata(pdev, priv);
669 INIT_LIST_HEAD(&priv->bank_list);
670
671 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
672 reg_base = devm_ioremap_resource(dev, res);
673 if (IS_ERR(reg_base))
674 return PTR_ERR(reg_base);
675
676 priv->gpio_base = gpio_base;
677 priv->reg_base = reg_base;
678 priv->pdev = pdev;
679
680 if (of_property_read_bool(np, "interrupt-controller")) {
681 priv->parent_irq = platform_get_irq(pdev, 0);
682 if (priv->parent_irq <= 0)
683 return -ENOENT;
684 } else {
685 priv->parent_irq = -ENOENT;
686 }
687
688 if (brcmstb_gpio_sanity_check_banks(dev, np, res))
689 return -EINVAL;
690
691 /*
692 * MIPS endianness is configured by boot strap, which also reverses all
693 * bus endianness (i.e., big-endian CPU + big endian bus ==> native
694 * endian I/O).
695 *
696 * Other architectures (e.g., ARM) either do not support big endian, or
697 * else leave I/O in little endian mode.
698 */
699#if defined(CONFIG_MIPS) && defined(__BIG_ENDIAN)
700 flags = BGPIOF_BIG_ENDIAN_BYTE_ORDER;
701#endif
702
703 of_property_for_each_u32(np, "brcm,gpio-bank-widths", prop, p,
704 bank_width) {
705 struct brcmstb_gpio_bank *bank;
706 struct gpio_chip *gc;
707
708 /*
709 * If bank_width is 0, then there is an empty bank in the
710 * register block. Special handling for this case.
711 */
712 if (bank_width == 0) {
713 dev_dbg(dev, "Width 0 found: Empty bank @ %d\n",
714 num_banks);
715 num_banks++;
716 gpio_base += MAX_GPIO_PER_BANK;
717 continue;
718 }
719
720 bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL);
721 if (!bank) {
722 err = -ENOMEM;
723 goto fail;
724 }
725
726 bank->parent_priv = priv;
727 bank->id = num_banks;
728 if (bank_width <= 0 || bank_width > MAX_GPIO_PER_BANK) {
729 dev_err(dev, "Invalid bank width %d\n", bank_width);
730 err = -EINVAL;
731 goto fail;
732 } else {
733 bank->width = bank_width;
734 }
735
736 /*
737 * Regs are 4 bytes wide, have data reg, no set/clear regs,
738 * and direction bits have 0 = output and 1 = input
739 */
740 gc = &bank->gc;
741 err = bgpio_init(gc, dev, 4,
742 reg_base + GIO_DATA(bank->id),
743 NULL, NULL, NULL,
744 reg_base + GIO_IODIR(bank->id), flags);
745 if (err) {
746 dev_err(dev, "bgpio_init() failed\n");
747 goto fail;
748 }
749
750 gc->of_node = np;
751 gc->owner = THIS_MODULE;
752 gc->label = devm_kasprintf(dev, GFP_KERNEL, "%pOF", dev->of_node);
753 if (!gc->label) {
754 err = -ENOMEM;
755 goto fail;
756 }
757 gc->base = gpio_base;
758 gc->of_gpio_n_cells = 2;
759 gc->of_xlate = brcmstb_gpio_of_xlate;
760 /* not all ngpio lines are valid, will use bank width later */
761 gc->ngpio = MAX_GPIO_PER_BANK;
762 if (priv->parent_irq > 0)
763 gc->to_irq = brcmstb_gpio_to_irq;
764
765 /*
766 * Mask all interrupts by default, since wakeup interrupts may
767 * be retained from S5 cold boot
768 */
769 need_wakeup_event |= !!__brcmstb_gpio_get_active_irqs(bank);
770 gc->write_reg(reg_base + GIO_MASK(bank->id), 0);
771
772 brcmstb_gpio_set_names(dev, bank);
773 err = gpiochip_add_data(gc, bank);
774 if (err) {
775 dev_err(dev, "Could not add gpiochip for bank %d\n",
776 bank->id);
777 goto fail;
778 }
779 gpio_base += gc->ngpio;
780
781 dev_dbg(dev, "bank=%d, base=%d, ngpio=%d, width=%d\n", bank->id,
782 gc->base, gc->ngpio, bank->width);
783
784 /* Everything looks good, so add bank to list */
785 list_add(&bank->node, &priv->bank_list);
786
787 num_banks++;
788 }
789
790 priv->num_gpios = gpio_base - priv->gpio_base;
791 if (priv->parent_irq > 0) {
792 err = brcmstb_gpio_irq_setup(pdev, priv);
793 if (err)
794 goto fail;
795 }
796
797 if (priv->parent_wake_irq && need_wakeup_event)
798 pm_wakeup_event(dev, 0);
799
800 return 0;
801
802fail:
803 (void) brcmstb_gpio_remove(pdev);
804 return err;
805}
806
807static const struct of_device_id brcmstb_gpio_of_match[] = {
808 { .compatible = "brcm,brcmstb-gpio" },
809 {},
810};
811
812MODULE_DEVICE_TABLE(of, brcmstb_gpio_of_match);
813
814static struct platform_driver brcmstb_gpio_driver = {
815 .driver = {
816 .name = "brcmstb-gpio",
817 .of_match_table = brcmstb_gpio_of_match,
818 .pm = &brcmstb_gpio_pm_ops,
819 },
820 .probe = brcmstb_gpio_probe,
821 .remove = brcmstb_gpio_remove,
822 .shutdown = brcmstb_gpio_shutdown,
823};
824module_platform_driver(brcmstb_gpio_driver);
825
826MODULE_AUTHOR("Gregory Fong");
827MODULE_DESCRIPTION("Driver for Broadcom BRCMSTB SoC UPG GPIO");
828MODULE_LICENSE("GPL v2");
1/*
2 * Copyright (C) 2015 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation version 2.
7 *
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/bitops.h>
15#include <linux/gpio/driver.h>
16#include <linux/of_device.h>
17#include <linux/of_irq.h>
18#include <linux/module.h>
19#include <linux/irqdomain.h>
20#include <linux/irqchip/chained_irq.h>
21#include <linux/interrupt.h>
22#include <linux/reboot.h>
23
24#define GIO_BANK_SIZE 0x20
25#define GIO_ODEN(bank) (((bank) * GIO_BANK_SIZE) + 0x00)
26#define GIO_DATA(bank) (((bank) * GIO_BANK_SIZE) + 0x04)
27#define GIO_IODIR(bank) (((bank) * GIO_BANK_SIZE) + 0x08)
28#define GIO_EC(bank) (((bank) * GIO_BANK_SIZE) + 0x0c)
29#define GIO_EI(bank) (((bank) * GIO_BANK_SIZE) + 0x10)
30#define GIO_MASK(bank) (((bank) * GIO_BANK_SIZE) + 0x14)
31#define GIO_LEVEL(bank) (((bank) * GIO_BANK_SIZE) + 0x18)
32#define GIO_STAT(bank) (((bank) * GIO_BANK_SIZE) + 0x1c)
33
34struct brcmstb_gpio_bank {
35 struct list_head node;
36 int id;
37 struct gpio_chip gc;
38 struct brcmstb_gpio_priv *parent_priv;
39 u32 width;
40 struct irq_chip irq_chip;
41};
42
43struct brcmstb_gpio_priv {
44 struct list_head bank_list;
45 void __iomem *reg_base;
46 struct platform_device *pdev;
47 int parent_irq;
48 int gpio_base;
49 bool can_wake;
50 int parent_wake_irq;
51 struct notifier_block reboot_notifier;
52};
53
54#define MAX_GPIO_PER_BANK 32
55#define GPIO_BANK(gpio) ((gpio) >> 5)
56/* assumes MAX_GPIO_PER_BANK is a multiple of 2 */
57#define GPIO_BIT(gpio) ((gpio) & (MAX_GPIO_PER_BANK - 1))
58
59static inline struct brcmstb_gpio_priv *
60brcmstb_gpio_gc_to_priv(struct gpio_chip *gc)
61{
62 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
63 return bank->parent_priv;
64}
65
66static void brcmstb_gpio_set_imask(struct brcmstb_gpio_bank *bank,
67 unsigned int offset, bool enable)
68{
69 struct gpio_chip *gc = &bank->gc;
70 struct brcmstb_gpio_priv *priv = bank->parent_priv;
71 u32 mask = gc->pin2mask(gc, offset);
72 u32 imask;
73 unsigned long flags;
74
75 spin_lock_irqsave(&gc->bgpio_lock, flags);
76 imask = gc->read_reg(priv->reg_base + GIO_MASK(bank->id));
77 if (enable)
78 imask |= mask;
79 else
80 imask &= ~mask;
81 gc->write_reg(priv->reg_base + GIO_MASK(bank->id), imask);
82 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
83}
84
85/* -------------------- IRQ chip functions -------------------- */
86
87static void brcmstb_gpio_irq_mask(struct irq_data *d)
88{
89 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
90 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
91
92 brcmstb_gpio_set_imask(bank, d->hwirq, false);
93}
94
95static void brcmstb_gpio_irq_unmask(struct irq_data *d)
96{
97 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
98 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
99
100 brcmstb_gpio_set_imask(bank, d->hwirq, true);
101}
102
103static int brcmstb_gpio_irq_set_type(struct irq_data *d, unsigned int type)
104{
105 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
106 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
107 struct brcmstb_gpio_priv *priv = bank->parent_priv;
108 u32 mask = BIT(d->hwirq);
109 u32 edge_insensitive, iedge_insensitive;
110 u32 edge_config, iedge_config;
111 u32 level, ilevel;
112 unsigned long flags;
113
114 switch (type) {
115 case IRQ_TYPE_LEVEL_LOW:
116 level = 0;
117 edge_config = 0;
118 edge_insensitive = 0;
119 break;
120 case IRQ_TYPE_LEVEL_HIGH:
121 level = mask;
122 edge_config = 0;
123 edge_insensitive = 0;
124 break;
125 case IRQ_TYPE_EDGE_FALLING:
126 level = 0;
127 edge_config = 0;
128 edge_insensitive = 0;
129 break;
130 case IRQ_TYPE_EDGE_RISING:
131 level = 0;
132 edge_config = mask;
133 edge_insensitive = 0;
134 break;
135 case IRQ_TYPE_EDGE_BOTH:
136 level = 0;
137 edge_config = 0; /* don't care, but want known value */
138 edge_insensitive = mask;
139 break;
140 default:
141 return -EINVAL;
142 }
143
144 spin_lock_irqsave(&bank->gc.bgpio_lock, flags);
145
146 iedge_config = bank->gc.read_reg(priv->reg_base +
147 GIO_EC(bank->id)) & ~mask;
148 iedge_insensitive = bank->gc.read_reg(priv->reg_base +
149 GIO_EI(bank->id)) & ~mask;
150 ilevel = bank->gc.read_reg(priv->reg_base +
151 GIO_LEVEL(bank->id)) & ~mask;
152
153 bank->gc.write_reg(priv->reg_base + GIO_EC(bank->id),
154 iedge_config | edge_config);
155 bank->gc.write_reg(priv->reg_base + GIO_EI(bank->id),
156 iedge_insensitive | edge_insensitive);
157 bank->gc.write_reg(priv->reg_base + GIO_LEVEL(bank->id),
158 ilevel | level);
159
160 spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags);
161 return 0;
162}
163
164static int brcmstb_gpio_priv_set_wake(struct brcmstb_gpio_priv *priv,
165 unsigned int enable)
166{
167 int ret = 0;
168
169 /*
170 * Only enable wake IRQ once for however many hwirqs can wake
171 * since they all use the same wake IRQ. Mask will be set
172 * up appropriately thanks to IRQCHIP_MASK_ON_SUSPEND flag.
173 */
174 if (enable)
175 ret = enable_irq_wake(priv->parent_wake_irq);
176 else
177 ret = disable_irq_wake(priv->parent_wake_irq);
178 if (ret)
179 dev_err(&priv->pdev->dev, "failed to %s wake-up interrupt\n",
180 enable ? "enable" : "disable");
181 return ret;
182}
183
184static int brcmstb_gpio_irq_set_wake(struct irq_data *d, unsigned int enable)
185{
186 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
187 struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc);
188
189 return brcmstb_gpio_priv_set_wake(priv, enable);
190}
191
192static irqreturn_t brcmstb_gpio_wake_irq_handler(int irq, void *data)
193{
194 struct brcmstb_gpio_priv *priv = data;
195
196 if (!priv || irq != priv->parent_wake_irq)
197 return IRQ_NONE;
198 pm_wakeup_event(&priv->pdev->dev, 0);
199 return IRQ_HANDLED;
200}
201
202static void brcmstb_gpio_irq_bank_handler(struct brcmstb_gpio_bank *bank)
203{
204 struct brcmstb_gpio_priv *priv = bank->parent_priv;
205 struct irq_domain *irq_domain = bank->gc.irqdomain;
206 void __iomem *reg_base = priv->reg_base;
207 unsigned long status;
208 unsigned long flags;
209
210 spin_lock_irqsave(&bank->gc.bgpio_lock, flags);
211 while ((status = bank->gc.read_reg(reg_base + GIO_STAT(bank->id)) &
212 bank->gc.read_reg(reg_base + GIO_MASK(bank->id)))) {
213 int bit;
214
215 for_each_set_bit(bit, &status, 32) {
216 u32 stat = bank->gc.read_reg(reg_base +
217 GIO_STAT(bank->id));
218 if (bit >= bank->width)
219 dev_warn(&priv->pdev->dev,
220 "IRQ for invalid GPIO (bank=%d, offset=%d)\n",
221 bank->id, bit);
222 bank->gc.write_reg(reg_base + GIO_STAT(bank->id),
223 stat | BIT(bit));
224 generic_handle_irq(irq_find_mapping(irq_domain, bit));
225 }
226 }
227 spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags);
228}
229
230/* Each UPG GIO block has one IRQ for all banks */
231static void brcmstb_gpio_irq_handler(struct irq_desc *desc)
232{
233 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
234 struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc);
235 struct irq_chip *chip = irq_desc_get_chip(desc);
236 struct brcmstb_gpio_bank *bank;
237
238 /* Interrupts weren't properly cleared during probe */
239 BUG_ON(!priv || !chip);
240
241 chained_irq_enter(chip, desc);
242 list_for_each_entry(bank, &priv->bank_list, node)
243 brcmstb_gpio_irq_bank_handler(bank);
244 chained_irq_exit(chip, desc);
245}
246
247static int brcmstb_gpio_reboot(struct notifier_block *nb,
248 unsigned long action, void *data)
249{
250 struct brcmstb_gpio_priv *priv =
251 container_of(nb, struct brcmstb_gpio_priv, reboot_notifier);
252
253 /* Enable GPIO for S5 cold boot */
254 if (action == SYS_POWER_OFF)
255 brcmstb_gpio_priv_set_wake(priv, 1);
256
257 return NOTIFY_DONE;
258}
259
260/* Make sure that the number of banks matches up between properties */
261static int brcmstb_gpio_sanity_check_banks(struct device *dev,
262 struct device_node *np, struct resource *res)
263{
264 int res_num_banks = resource_size(res) / GIO_BANK_SIZE;
265 int num_banks =
266 of_property_count_u32_elems(np, "brcm,gpio-bank-widths");
267
268 if (res_num_banks != num_banks) {
269 dev_err(dev, "Mismatch in banks: res had %d, bank-widths had %d\n",
270 res_num_banks, num_banks);
271 return -EINVAL;
272 } else {
273 return 0;
274 }
275}
276
277static int brcmstb_gpio_remove(struct platform_device *pdev)
278{
279 struct brcmstb_gpio_priv *priv = platform_get_drvdata(pdev);
280 struct brcmstb_gpio_bank *bank;
281 int ret = 0;
282
283 if (!priv) {
284 dev_err(&pdev->dev, "called %s without drvdata!\n", __func__);
285 return -EFAULT;
286 }
287
288 /*
289 * You can lose return values below, but we report all errors, and it's
290 * more important to actually perform all of the steps.
291 */
292 list_for_each_entry(bank, &priv->bank_list, node)
293 gpiochip_remove(&bank->gc);
294
295 if (priv->reboot_notifier.notifier_call) {
296 ret = unregister_reboot_notifier(&priv->reboot_notifier);
297 if (ret)
298 dev_err(&pdev->dev,
299 "failed to unregister reboot notifier\n");
300 }
301 return ret;
302}
303
304static int brcmstb_gpio_of_xlate(struct gpio_chip *gc,
305 const struct of_phandle_args *gpiospec, u32 *flags)
306{
307 struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc);
308 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
309 int offset;
310
311 if (gc->of_gpio_n_cells != 2) {
312 WARN_ON(1);
313 return -EINVAL;
314 }
315
316 if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells))
317 return -EINVAL;
318
319 offset = gpiospec->args[0] - (gc->base - priv->gpio_base);
320 if (offset >= gc->ngpio || offset < 0)
321 return -EINVAL;
322
323 if (unlikely(offset >= bank->width)) {
324 dev_warn_ratelimited(&priv->pdev->dev,
325 "Received request for invalid GPIO offset %d\n",
326 gpiospec->args[0]);
327 }
328
329 if (flags)
330 *flags = gpiospec->args[1];
331
332 return offset;
333}
334
335/* Before calling, must have bank->parent_irq set and gpiochip registered */
336static int brcmstb_gpio_irq_setup(struct platform_device *pdev,
337 struct brcmstb_gpio_bank *bank)
338{
339 struct brcmstb_gpio_priv *priv = bank->parent_priv;
340 struct device *dev = &pdev->dev;
341 struct device_node *np = dev->of_node;
342
343 bank->irq_chip.name = dev_name(dev);
344 bank->irq_chip.irq_mask = brcmstb_gpio_irq_mask;
345 bank->irq_chip.irq_unmask = brcmstb_gpio_irq_unmask;
346 bank->irq_chip.irq_set_type = brcmstb_gpio_irq_set_type;
347
348 /* Ensures that all non-wakeup IRQs are disabled at suspend */
349 bank->irq_chip.flags = IRQCHIP_MASK_ON_SUSPEND;
350
351 if (IS_ENABLED(CONFIG_PM_SLEEP) && !priv->can_wake &&
352 of_property_read_bool(np, "wakeup-source")) {
353 priv->parent_wake_irq = platform_get_irq(pdev, 1);
354 if (priv->parent_wake_irq < 0) {
355 dev_warn(dev,
356 "Couldn't get wake IRQ - GPIOs will not be able to wake from sleep");
357 } else {
358 int err;
359
360 /*
361 * Set wakeup capability before requesting wakeup
362 * interrupt, so we can process boot-time "wakeups"
363 * (e.g., from S5 cold boot)
364 */
365 device_set_wakeup_capable(dev, true);
366 device_wakeup_enable(dev);
367 err = devm_request_irq(dev, priv->parent_wake_irq,
368 brcmstb_gpio_wake_irq_handler, 0,
369 "brcmstb-gpio-wake", priv);
370
371 if (err < 0) {
372 dev_err(dev, "Couldn't request wake IRQ");
373 return err;
374 }
375
376 priv->reboot_notifier.notifier_call =
377 brcmstb_gpio_reboot;
378 register_reboot_notifier(&priv->reboot_notifier);
379 priv->can_wake = true;
380 }
381 }
382
383 if (priv->can_wake)
384 bank->irq_chip.irq_set_wake = brcmstb_gpio_irq_set_wake;
385
386 gpiochip_irqchip_add(&bank->gc, &bank->irq_chip, 0,
387 handle_simple_irq, IRQ_TYPE_NONE);
388 gpiochip_set_chained_irqchip(&bank->gc, &bank->irq_chip,
389 priv->parent_irq, brcmstb_gpio_irq_handler);
390
391 return 0;
392}
393
394static int brcmstb_gpio_probe(struct platform_device *pdev)
395{
396 struct device *dev = &pdev->dev;
397 struct device_node *np = dev->of_node;
398 void __iomem *reg_base;
399 struct brcmstb_gpio_priv *priv;
400 struct resource *res;
401 struct property *prop;
402 const __be32 *p;
403 u32 bank_width;
404 int num_banks = 0;
405 int err;
406 static int gpio_base;
407 unsigned long flags = 0;
408
409 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
410 if (!priv)
411 return -ENOMEM;
412 platform_set_drvdata(pdev, priv);
413 INIT_LIST_HEAD(&priv->bank_list);
414
415 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
416 reg_base = devm_ioremap_resource(dev, res);
417 if (IS_ERR(reg_base))
418 return PTR_ERR(reg_base);
419
420 priv->gpio_base = gpio_base;
421 priv->reg_base = reg_base;
422 priv->pdev = pdev;
423
424 if (of_property_read_bool(np, "interrupt-controller")) {
425 priv->parent_irq = platform_get_irq(pdev, 0);
426 if (priv->parent_irq <= 0) {
427 dev_err(dev, "Couldn't get IRQ");
428 return -ENOENT;
429 }
430 } else {
431 priv->parent_irq = -ENOENT;
432 }
433
434 if (brcmstb_gpio_sanity_check_banks(dev, np, res))
435 return -EINVAL;
436
437 /*
438 * MIPS endianness is configured by boot strap, which also reverses all
439 * bus endianness (i.e., big-endian CPU + big endian bus ==> native
440 * endian I/O).
441 *
442 * Other architectures (e.g., ARM) either do not support big endian, or
443 * else leave I/O in little endian mode.
444 */
445#if defined(CONFIG_MIPS) && defined(__BIG_ENDIAN)
446 flags = BGPIOF_BIG_ENDIAN_BYTE_ORDER;
447#endif
448
449 of_property_for_each_u32(np, "brcm,gpio-bank-widths", prop, p,
450 bank_width) {
451 struct brcmstb_gpio_bank *bank;
452 struct gpio_chip *gc;
453
454 bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL);
455 if (!bank) {
456 err = -ENOMEM;
457 goto fail;
458 }
459
460 bank->parent_priv = priv;
461 bank->id = num_banks;
462 if (bank_width <= 0 || bank_width > MAX_GPIO_PER_BANK) {
463 dev_err(dev, "Invalid bank width %d\n", bank_width);
464 goto fail;
465 } else {
466 bank->width = bank_width;
467 }
468
469 /*
470 * Regs are 4 bytes wide, have data reg, no set/clear regs,
471 * and direction bits have 0 = output and 1 = input
472 */
473 gc = &bank->gc;
474 err = bgpio_init(gc, dev, 4,
475 reg_base + GIO_DATA(bank->id),
476 NULL, NULL, NULL,
477 reg_base + GIO_IODIR(bank->id), flags);
478 if (err) {
479 dev_err(dev, "bgpio_init() failed\n");
480 goto fail;
481 }
482
483 gc->of_node = np;
484 gc->owner = THIS_MODULE;
485 gc->label = np->full_name;
486 gc->base = gpio_base;
487 gc->of_gpio_n_cells = 2;
488 gc->of_xlate = brcmstb_gpio_of_xlate;
489 /* not all ngpio lines are valid, will use bank width later */
490 gc->ngpio = MAX_GPIO_PER_BANK;
491
492 /*
493 * Mask all interrupts by default, since wakeup interrupts may
494 * be retained from S5 cold boot
495 */
496 gc->write_reg(reg_base + GIO_MASK(bank->id), 0);
497
498 err = gpiochip_add_data(gc, bank);
499 if (err) {
500 dev_err(dev, "Could not add gpiochip for bank %d\n",
501 bank->id);
502 goto fail;
503 }
504 gpio_base += gc->ngpio;
505
506 if (priv->parent_irq > 0) {
507 err = brcmstb_gpio_irq_setup(pdev, bank);
508 if (err)
509 goto fail;
510 }
511
512 dev_dbg(dev, "bank=%d, base=%d, ngpio=%d, width=%d\n", bank->id,
513 gc->base, gc->ngpio, bank->width);
514
515 /* Everything looks good, so add bank to list */
516 list_add(&bank->node, &priv->bank_list);
517
518 num_banks++;
519 }
520
521 dev_info(dev, "Registered %d banks (GPIO(s): %d-%d)\n",
522 num_banks, priv->gpio_base, gpio_base - 1);
523
524 return 0;
525
526fail:
527 (void) brcmstb_gpio_remove(pdev);
528 return err;
529}
530
531static const struct of_device_id brcmstb_gpio_of_match[] = {
532 { .compatible = "brcm,brcmstb-gpio" },
533 {},
534};
535
536MODULE_DEVICE_TABLE(of, brcmstb_gpio_of_match);
537
538static struct platform_driver brcmstb_gpio_driver = {
539 .driver = {
540 .name = "brcmstb-gpio",
541 .of_match_table = brcmstb_gpio_of_match,
542 },
543 .probe = brcmstb_gpio_probe,
544 .remove = brcmstb_gpio_remove,
545};
546module_platform_driver(brcmstb_gpio_driver);
547
548MODULE_AUTHOR("Gregory Fong");
549MODULE_DESCRIPTION("Driver for Broadcom BRCMSTB SoC UPG GPIO");
550MODULE_LICENSE("GPL v2");