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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * The file intends to implement PE based on the information from
4 * platforms. Basically, there have 3 types of PEs: PHB/Bus/Device.
5 * All the PEs should be organized as hierarchy tree. The first level
6 * of the tree will be associated to existing PHBs since the particular
7 * PE is only meaningful in one PHB domain.
8 *
9 * Copyright Benjamin Herrenschmidt & Gavin Shan, IBM Corporation 2012.
10 */
11
12#include <linux/delay.h>
13#include <linux/export.h>
14#include <linux/gfp.h>
15#include <linux/kernel.h>
16#include <linux/pci.h>
17#include <linux/string.h>
18
19#include <asm/pci-bridge.h>
20#include <asm/ppc-pci.h>
21
22static int eeh_pe_aux_size = 0;
23static LIST_HEAD(eeh_phb_pe);
24
25/**
26 * eeh_set_pe_aux_size - Set PE auxillary data size
27 * @size: PE auxillary data size
28 *
29 * Set PE auxillary data size
30 */
31void eeh_set_pe_aux_size(int size)
32{
33 if (size < 0)
34 return;
35
36 eeh_pe_aux_size = size;
37}
38
39/**
40 * eeh_pe_alloc - Allocate PE
41 * @phb: PCI controller
42 * @type: PE type
43 *
44 * Allocate PE instance dynamically.
45 */
46static struct eeh_pe *eeh_pe_alloc(struct pci_controller *phb, int type)
47{
48 struct eeh_pe *pe;
49 size_t alloc_size;
50
51 alloc_size = sizeof(struct eeh_pe);
52 if (eeh_pe_aux_size) {
53 alloc_size = ALIGN(alloc_size, cache_line_size());
54 alloc_size += eeh_pe_aux_size;
55 }
56
57 /* Allocate PHB PE */
58 pe = kzalloc(alloc_size, GFP_KERNEL);
59 if (!pe) return NULL;
60
61 /* Initialize PHB PE */
62 pe->type = type;
63 pe->phb = phb;
64 INIT_LIST_HEAD(&pe->child_list);
65 INIT_LIST_HEAD(&pe->edevs);
66
67 pe->data = (void *)pe + ALIGN(sizeof(struct eeh_pe),
68 cache_line_size());
69 return pe;
70}
71
72/**
73 * eeh_phb_pe_create - Create PHB PE
74 * @phb: PCI controller
75 *
76 * The function should be called while the PHB is detected during
77 * system boot or PCI hotplug in order to create PHB PE.
78 */
79int eeh_phb_pe_create(struct pci_controller *phb)
80{
81 struct eeh_pe *pe;
82
83 /* Allocate PHB PE */
84 pe = eeh_pe_alloc(phb, EEH_PE_PHB);
85 if (!pe) {
86 pr_err("%s: out of memory!\n", __func__);
87 return -ENOMEM;
88 }
89
90 /* Put it into the list */
91 list_add_tail(&pe->child, &eeh_phb_pe);
92
93 pr_debug("EEH: Add PE for PHB#%x\n", phb->global_number);
94
95 return 0;
96}
97
98/**
99 * eeh_wait_state - Wait for PE state
100 * @pe: EEH PE
101 * @max_wait: maximal period in millisecond
102 *
103 * Wait for the state of associated PE. It might take some time
104 * to retrieve the PE's state.
105 */
106int eeh_wait_state(struct eeh_pe *pe, int max_wait)
107{
108 int ret;
109 int mwait;
110
111 /*
112 * According to PAPR, the state of PE might be temporarily
113 * unavailable. Under the circumstance, we have to wait
114 * for indicated time determined by firmware. The maximal
115 * wait time is 5 minutes, which is acquired from the original
116 * EEH implementation. Also, the original implementation
117 * also defined the minimal wait time as 1 second.
118 */
119#define EEH_STATE_MIN_WAIT_TIME (1000)
120#define EEH_STATE_MAX_WAIT_TIME (300 * 1000)
121
122 while (1) {
123 ret = eeh_ops->get_state(pe, &mwait);
124
125 if (ret != EEH_STATE_UNAVAILABLE)
126 return ret;
127
128 if (max_wait <= 0) {
129 pr_warn("%s: Timeout when getting PE's state (%d)\n",
130 __func__, max_wait);
131 return EEH_STATE_NOT_SUPPORT;
132 }
133
134 if (mwait < EEH_STATE_MIN_WAIT_TIME) {
135 pr_warn("%s: Firmware returned bad wait value %d\n",
136 __func__, mwait);
137 mwait = EEH_STATE_MIN_WAIT_TIME;
138 } else if (mwait > EEH_STATE_MAX_WAIT_TIME) {
139 pr_warn("%s: Firmware returned too long wait value %d\n",
140 __func__, mwait);
141 mwait = EEH_STATE_MAX_WAIT_TIME;
142 }
143
144 msleep(min(mwait, max_wait));
145 max_wait -= mwait;
146 }
147}
148
149/**
150 * eeh_phb_pe_get - Retrieve PHB PE based on the given PHB
151 * @phb: PCI controller
152 *
153 * The overall PEs form hierarchy tree. The first layer of the
154 * hierarchy tree is composed of PHB PEs. The function is used
155 * to retrieve the corresponding PHB PE according to the given PHB.
156 */
157struct eeh_pe *eeh_phb_pe_get(struct pci_controller *phb)
158{
159 struct eeh_pe *pe;
160
161 list_for_each_entry(pe, &eeh_phb_pe, child) {
162 /*
163 * Actually, we needn't check the type since
164 * the PE for PHB has been determined when that
165 * was created.
166 */
167 if ((pe->type & EEH_PE_PHB) && pe->phb == phb)
168 return pe;
169 }
170
171 return NULL;
172}
173
174/**
175 * eeh_pe_next - Retrieve the next PE in the tree
176 * @pe: current PE
177 * @root: root PE
178 *
179 * The function is used to retrieve the next PE in the
180 * hierarchy PE tree.
181 */
182struct eeh_pe *eeh_pe_next(struct eeh_pe *pe, struct eeh_pe *root)
183{
184 struct list_head *next = pe->child_list.next;
185
186 if (next == &pe->child_list) {
187 while (1) {
188 if (pe == root)
189 return NULL;
190 next = pe->child.next;
191 if (next != &pe->parent->child_list)
192 break;
193 pe = pe->parent;
194 }
195 }
196
197 return list_entry(next, struct eeh_pe, child);
198}
199
200/**
201 * eeh_pe_traverse - Traverse PEs in the specified PHB
202 * @root: root PE
203 * @fn: callback
204 * @flag: extra parameter to callback
205 *
206 * The function is used to traverse the specified PE and its
207 * child PEs. The traversing is to be terminated once the
208 * callback returns something other than NULL, or no more PEs
209 * to be traversed.
210 */
211void *eeh_pe_traverse(struct eeh_pe *root,
212 eeh_pe_traverse_func fn, void *flag)
213{
214 struct eeh_pe *pe;
215 void *ret;
216
217 eeh_for_each_pe(root, pe) {
218 ret = fn(pe, flag);
219 if (ret) return ret;
220 }
221
222 return NULL;
223}
224
225/**
226 * eeh_pe_dev_traverse - Traverse the devices from the PE
227 * @root: EEH PE
228 * @fn: function callback
229 * @flag: extra parameter to callback
230 *
231 * The function is used to traverse the devices of the specified
232 * PE and its child PEs.
233 */
234void eeh_pe_dev_traverse(struct eeh_pe *root,
235 eeh_edev_traverse_func fn, void *flag)
236{
237 struct eeh_pe *pe;
238 struct eeh_dev *edev, *tmp;
239
240 if (!root) {
241 pr_warn("%s: Invalid PE %p\n",
242 __func__, root);
243 return;
244 }
245
246 /* Traverse root PE */
247 eeh_for_each_pe(root, pe)
248 eeh_pe_for_each_dev(pe, edev, tmp)
249 fn(edev, flag);
250}
251
252/**
253 * __eeh_pe_get - Check the PE address
254 * @data: EEH PE
255 * @flag: EEH device
256 *
257 * For one particular PE, it can be identified by PE address
258 * or tranditional BDF address. BDF address is composed of
259 * Bus/Device/Function number. The extra data referred by flag
260 * indicates which type of address should be used.
261 */
262struct eeh_pe_get_flag {
263 int pe_no;
264 int config_addr;
265};
266
267static void *__eeh_pe_get(struct eeh_pe *pe, void *flag)
268{
269 struct eeh_pe_get_flag *tmp = (struct eeh_pe_get_flag *) flag;
270
271 /* Unexpected PHB PE */
272 if (pe->type & EEH_PE_PHB)
273 return NULL;
274
275 /*
276 * We prefer PE address. For most cases, we should
277 * have non-zero PE address
278 */
279 if (eeh_has_flag(EEH_VALID_PE_ZERO)) {
280 if (tmp->pe_no == pe->addr)
281 return pe;
282 } else {
283 if (tmp->pe_no &&
284 (tmp->pe_no == pe->addr))
285 return pe;
286 }
287
288 /* Try BDF address */
289 if (tmp->config_addr &&
290 (tmp->config_addr == pe->config_addr))
291 return pe;
292
293 return NULL;
294}
295
296/**
297 * eeh_pe_get - Search PE based on the given address
298 * @phb: PCI controller
299 * @pe_no: PE number
300 * @config_addr: Config address
301 *
302 * Search the corresponding PE based on the specified address which
303 * is included in the eeh device. The function is used to check if
304 * the associated PE has been created against the PE address. It's
305 * notable that the PE address has 2 format: traditional PE address
306 * which is composed of PCI bus/device/function number, or unified
307 * PE address.
308 */
309struct eeh_pe *eeh_pe_get(struct pci_controller *phb,
310 int pe_no, int config_addr)
311{
312 struct eeh_pe *root = eeh_phb_pe_get(phb);
313 struct eeh_pe_get_flag tmp = { pe_no, config_addr };
314 struct eeh_pe *pe;
315
316 pe = eeh_pe_traverse(root, __eeh_pe_get, &tmp);
317
318 return pe;
319}
320
321/**
322 * eeh_pe_tree_insert - Add EEH device to parent PE
323 * @edev: EEH device
324 * @new_pe_parent: PE to create additional PEs under
325 *
326 * Add EEH device to the PE in edev->pe_config_addr. If a PE already
327 * exists with that address then @edev is added to that PE. Otherwise
328 * a new PE is created and inserted into the PE tree as a child of
329 * @new_pe_parent.
330 *
331 * If @new_pe_parent is NULL then the new PE will be inserted under
332 * directly under the the PHB.
333 */
334int eeh_pe_tree_insert(struct eeh_dev *edev, struct eeh_pe *new_pe_parent)
335{
336 struct pci_controller *hose = edev->controller;
337 struct eeh_pe *pe, *parent;
338
339 /* Check if the PE number is valid */
340 if (!eeh_has_flag(EEH_VALID_PE_ZERO) && !edev->pe_config_addr) {
341 eeh_edev_err(edev, "PE#0 is invalid for this PHB!\n");
342 return -EINVAL;
343 }
344
345 /*
346 * Search the PE has been existing or not according
347 * to the PE address. If that has been existing, the
348 * PE should be composed of PCI bus and its subordinate
349 * components.
350 */
351 pe = eeh_pe_get(hose, edev->pe_config_addr, edev->bdfn);
352 if (pe) {
353 if (pe->type & EEH_PE_INVALID) {
354 list_add_tail(&edev->entry, &pe->edevs);
355 edev->pe = pe;
356 /*
357 * We're running to here because of PCI hotplug caused by
358 * EEH recovery. We need clear EEH_PE_INVALID until the top.
359 */
360 parent = pe;
361 while (parent) {
362 if (!(parent->type & EEH_PE_INVALID))
363 break;
364 parent->type &= ~EEH_PE_INVALID;
365 parent = parent->parent;
366 }
367
368 eeh_edev_dbg(edev, "Added to existing PE (parent: PE#%x)\n",
369 pe->parent->addr);
370 } else {
371 /* Mark the PE as type of PCI bus */
372 pe->type = EEH_PE_BUS;
373 edev->pe = pe;
374
375 /* Put the edev to PE */
376 list_add_tail(&edev->entry, &pe->edevs);
377 eeh_edev_dbg(edev, "Added to bus PE\n");
378 }
379 return 0;
380 }
381
382 /* Create a new EEH PE */
383 if (edev->physfn)
384 pe = eeh_pe_alloc(hose, EEH_PE_VF);
385 else
386 pe = eeh_pe_alloc(hose, EEH_PE_DEVICE);
387 if (!pe) {
388 pr_err("%s: out of memory!\n", __func__);
389 return -ENOMEM;
390 }
391 pe->addr = edev->pe_config_addr;
392 pe->config_addr = edev->bdfn;
393
394 /*
395 * Put the new EEH PE into hierarchy tree. If the parent
396 * can't be found, the newly created PE will be attached
397 * to PHB directly. Otherwise, we have to associate the
398 * PE with its parent.
399 */
400 if (!new_pe_parent) {
401 new_pe_parent = eeh_phb_pe_get(hose);
402 if (!new_pe_parent) {
403 pr_err("%s: No PHB PE is found (PHB Domain=%d)\n",
404 __func__, hose->global_number);
405 edev->pe = NULL;
406 kfree(pe);
407 return -EEXIST;
408 }
409 }
410
411 /* link new PE into the tree */
412 pe->parent = new_pe_parent;
413 list_add_tail(&pe->child, &new_pe_parent->child_list);
414
415 /*
416 * Put the newly created PE into the child list and
417 * link the EEH device accordingly.
418 */
419 list_add_tail(&edev->entry, &pe->edevs);
420 edev->pe = pe;
421 eeh_edev_dbg(edev, "Added to new (parent: PE#%x)\n",
422 new_pe_parent->addr);
423
424 return 0;
425}
426
427/**
428 * eeh_pe_tree_remove - Remove one EEH device from the associated PE
429 * @edev: EEH device
430 *
431 * The PE hierarchy tree might be changed when doing PCI hotplug.
432 * Also, the PCI devices or buses could be removed from the system
433 * during EEH recovery. So we have to call the function remove the
434 * corresponding PE accordingly if necessary.
435 */
436int eeh_pe_tree_remove(struct eeh_dev *edev)
437{
438 struct eeh_pe *pe, *parent, *child;
439 bool keep, recover;
440 int cnt;
441
442 pe = eeh_dev_to_pe(edev);
443 if (!pe) {
444 eeh_edev_dbg(edev, "No PE found for device.\n");
445 return -EEXIST;
446 }
447
448 /* Remove the EEH device */
449 edev->pe = NULL;
450 list_del(&edev->entry);
451
452 /*
453 * Check if the parent PE includes any EEH devices.
454 * If not, we should delete that. Also, we should
455 * delete the parent PE if it doesn't have associated
456 * child PEs and EEH devices.
457 */
458 while (1) {
459 parent = pe->parent;
460
461 /* PHB PEs should never be removed */
462 if (pe->type & EEH_PE_PHB)
463 break;
464
465 /*
466 * XXX: KEEP is set while resetting a PE. I don't think it's
467 * ever set without RECOVERING also being set. I could
468 * be wrong though so catch that with a WARN.
469 */
470 keep = !!(pe->state & EEH_PE_KEEP);
471 recover = !!(pe->state & EEH_PE_RECOVERING);
472 WARN_ON(keep && !recover);
473
474 if (!keep && !recover) {
475 if (list_empty(&pe->edevs) &&
476 list_empty(&pe->child_list)) {
477 list_del(&pe->child);
478 kfree(pe);
479 } else {
480 break;
481 }
482 } else {
483 /*
484 * Mark the PE as invalid. At the end of the recovery
485 * process any invalid PEs will be garbage collected.
486 *
487 * We need to delay the free()ing of them since we can
488 * remove edev's while traversing the PE tree which
489 * might trigger the removal of a PE and we can't
490 * deal with that (yet).
491 */
492 if (list_empty(&pe->edevs)) {
493 cnt = 0;
494 list_for_each_entry(child, &pe->child_list, child) {
495 if (!(child->type & EEH_PE_INVALID)) {
496 cnt++;
497 break;
498 }
499 }
500
501 if (!cnt)
502 pe->type |= EEH_PE_INVALID;
503 else
504 break;
505 }
506 }
507
508 pe = parent;
509 }
510
511 return 0;
512}
513
514/**
515 * eeh_pe_update_time_stamp - Update PE's frozen time stamp
516 * @pe: EEH PE
517 *
518 * We have time stamp for each PE to trace its time of getting
519 * frozen in last hour. The function should be called to update
520 * the time stamp on first error of the specific PE. On the other
521 * handle, we needn't account for errors happened in last hour.
522 */
523void eeh_pe_update_time_stamp(struct eeh_pe *pe)
524{
525 time64_t tstamp;
526
527 if (!pe) return;
528
529 if (pe->freeze_count <= 0) {
530 pe->freeze_count = 0;
531 pe->tstamp = ktime_get_seconds();
532 } else {
533 tstamp = ktime_get_seconds();
534 if (tstamp - pe->tstamp > 3600) {
535 pe->tstamp = tstamp;
536 pe->freeze_count = 0;
537 }
538 }
539}
540
541/**
542 * eeh_pe_state_mark - Mark specified state for PE and its associated device
543 * @pe: EEH PE
544 *
545 * EEH error affects the current PE and its child PEs. The function
546 * is used to mark appropriate state for the affected PEs and the
547 * associated devices.
548 */
549void eeh_pe_state_mark(struct eeh_pe *root, int state)
550{
551 struct eeh_pe *pe;
552
553 eeh_for_each_pe(root, pe)
554 if (!(pe->state & EEH_PE_REMOVED))
555 pe->state |= state;
556}
557EXPORT_SYMBOL_GPL(eeh_pe_state_mark);
558
559/**
560 * eeh_pe_mark_isolated
561 * @pe: EEH PE
562 *
563 * Record that a PE has been isolated by marking the PE and it's children as
564 * EEH_PE_ISOLATED (and EEH_PE_CFG_BLOCKED, if required) and their PCI devices
565 * as pci_channel_io_frozen.
566 */
567void eeh_pe_mark_isolated(struct eeh_pe *root)
568{
569 struct eeh_pe *pe;
570 struct eeh_dev *edev;
571 struct pci_dev *pdev;
572
573 eeh_pe_state_mark(root, EEH_PE_ISOLATED);
574 eeh_for_each_pe(root, pe) {
575 list_for_each_entry(edev, &pe->edevs, entry) {
576 pdev = eeh_dev_to_pci_dev(edev);
577 if (pdev)
578 pdev->error_state = pci_channel_io_frozen;
579 }
580 /* Block PCI config access if required */
581 if (pe->state & EEH_PE_CFG_RESTRICTED)
582 pe->state |= EEH_PE_CFG_BLOCKED;
583 }
584}
585EXPORT_SYMBOL_GPL(eeh_pe_mark_isolated);
586
587static void __eeh_pe_dev_mode_mark(struct eeh_dev *edev, void *flag)
588{
589 int mode = *((int *)flag);
590
591 edev->mode |= mode;
592}
593
594/**
595 * eeh_pe_dev_state_mark - Mark state for all device under the PE
596 * @pe: EEH PE
597 *
598 * Mark specific state for all child devices of the PE.
599 */
600void eeh_pe_dev_mode_mark(struct eeh_pe *pe, int mode)
601{
602 eeh_pe_dev_traverse(pe, __eeh_pe_dev_mode_mark, &mode);
603}
604
605/**
606 * eeh_pe_state_clear - Clear state for the PE
607 * @data: EEH PE
608 * @state: state
609 * @include_passed: include passed-through devices?
610 *
611 * The function is used to clear the indicated state from the
612 * given PE. Besides, we also clear the check count of the PE
613 * as well.
614 */
615void eeh_pe_state_clear(struct eeh_pe *root, int state, bool include_passed)
616{
617 struct eeh_pe *pe;
618 struct eeh_dev *edev, *tmp;
619 struct pci_dev *pdev;
620
621 eeh_for_each_pe(root, pe) {
622 /* Keep the state of permanently removed PE intact */
623 if (pe->state & EEH_PE_REMOVED)
624 continue;
625
626 if (!include_passed && eeh_pe_passed(pe))
627 continue;
628
629 pe->state &= ~state;
630
631 /*
632 * Special treatment on clearing isolated state. Clear
633 * check count since last isolation and put all affected
634 * devices to normal state.
635 */
636 if (!(state & EEH_PE_ISOLATED))
637 continue;
638
639 pe->check_count = 0;
640 eeh_pe_for_each_dev(pe, edev, tmp) {
641 pdev = eeh_dev_to_pci_dev(edev);
642 if (!pdev)
643 continue;
644
645 pdev->error_state = pci_channel_io_normal;
646 }
647
648 /* Unblock PCI config access if required */
649 if (pe->state & EEH_PE_CFG_RESTRICTED)
650 pe->state &= ~EEH_PE_CFG_BLOCKED;
651 }
652}
653
654/*
655 * Some PCI bridges (e.g. PLX bridges) have primary/secondary
656 * buses assigned explicitly by firmware, and we probably have
657 * lost that after reset. So we have to delay the check until
658 * the PCI-CFG registers have been restored for the parent
659 * bridge.
660 *
661 * Don't use normal PCI-CFG accessors, which probably has been
662 * blocked on normal path during the stage. So we need utilize
663 * eeh operations, which is always permitted.
664 */
665static void eeh_bridge_check_link(struct eeh_dev *edev)
666{
667 int cap;
668 uint32_t val;
669 int timeout = 0;
670
671 /*
672 * We only check root port and downstream ports of
673 * PCIe switches
674 */
675 if (!(edev->mode & (EEH_DEV_ROOT_PORT | EEH_DEV_DS_PORT)))
676 return;
677
678 eeh_edev_dbg(edev, "Checking PCIe link...\n");
679
680 /* Check slot status */
681 cap = edev->pcie_cap;
682 eeh_ops->read_config(edev, cap + PCI_EXP_SLTSTA, 2, &val);
683 if (!(val & PCI_EXP_SLTSTA_PDS)) {
684 eeh_edev_dbg(edev, "No card in the slot (0x%04x) !\n", val);
685 return;
686 }
687
688 /* Check power status if we have the capability */
689 eeh_ops->read_config(edev, cap + PCI_EXP_SLTCAP, 2, &val);
690 if (val & PCI_EXP_SLTCAP_PCP) {
691 eeh_ops->read_config(edev, cap + PCI_EXP_SLTCTL, 2, &val);
692 if (val & PCI_EXP_SLTCTL_PCC) {
693 eeh_edev_dbg(edev, "In power-off state, power it on ...\n");
694 val &= ~(PCI_EXP_SLTCTL_PCC | PCI_EXP_SLTCTL_PIC);
695 val |= (0x0100 & PCI_EXP_SLTCTL_PIC);
696 eeh_ops->write_config(edev, cap + PCI_EXP_SLTCTL, 2, val);
697 msleep(2 * 1000);
698 }
699 }
700
701 /* Enable link */
702 eeh_ops->read_config(edev, cap + PCI_EXP_LNKCTL, 2, &val);
703 val &= ~PCI_EXP_LNKCTL_LD;
704 eeh_ops->write_config(edev, cap + PCI_EXP_LNKCTL, 2, val);
705
706 /* Check link */
707 eeh_ops->read_config(edev, cap + PCI_EXP_LNKCAP, 4, &val);
708 if (!(val & PCI_EXP_LNKCAP_DLLLARC)) {
709 eeh_edev_dbg(edev, "No link reporting capability (0x%08x) \n", val);
710 msleep(1000);
711 return;
712 }
713
714 /* Wait the link is up until timeout (5s) */
715 timeout = 0;
716 while (timeout < 5000) {
717 msleep(20);
718 timeout += 20;
719
720 eeh_ops->read_config(edev, cap + PCI_EXP_LNKSTA, 2, &val);
721 if (val & PCI_EXP_LNKSTA_DLLLA)
722 break;
723 }
724
725 if (val & PCI_EXP_LNKSTA_DLLLA)
726 eeh_edev_dbg(edev, "Link up (%s)\n",
727 (val & PCI_EXP_LNKSTA_CLS_2_5GB) ? "2.5GB" : "5GB");
728 else
729 eeh_edev_dbg(edev, "Link not ready (0x%04x)\n", val);
730}
731
732#define BYTE_SWAP(OFF) (8*((OFF)/4)+3-(OFF))
733#define SAVED_BYTE(OFF) (((u8 *)(edev->config_space))[BYTE_SWAP(OFF)])
734
735static void eeh_restore_bridge_bars(struct eeh_dev *edev)
736{
737 int i;
738
739 /*
740 * Device BARs: 0x10 - 0x18
741 * Bus numbers and windows: 0x18 - 0x30
742 */
743 for (i = 4; i < 13; i++)
744 eeh_ops->write_config(edev, i*4, 4, edev->config_space[i]);
745 /* Rom: 0x38 */
746 eeh_ops->write_config(edev, 14*4, 4, edev->config_space[14]);
747
748 /* Cache line & Latency timer: 0xC 0xD */
749 eeh_ops->write_config(edev, PCI_CACHE_LINE_SIZE, 1,
750 SAVED_BYTE(PCI_CACHE_LINE_SIZE));
751 eeh_ops->write_config(edev, PCI_LATENCY_TIMER, 1,
752 SAVED_BYTE(PCI_LATENCY_TIMER));
753 /* Max latency, min grant, interrupt ping and line: 0x3C */
754 eeh_ops->write_config(edev, 15*4, 4, edev->config_space[15]);
755
756 /* PCI Command: 0x4 */
757 eeh_ops->write_config(edev, PCI_COMMAND, 4, edev->config_space[1] |
758 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
759
760 /* Check the PCIe link is ready */
761 eeh_bridge_check_link(edev);
762}
763
764static void eeh_restore_device_bars(struct eeh_dev *edev)
765{
766 int i;
767 u32 cmd;
768
769 for (i = 4; i < 10; i++)
770 eeh_ops->write_config(edev, i*4, 4, edev->config_space[i]);
771 /* 12 == Expansion ROM Address */
772 eeh_ops->write_config(edev, 12*4, 4, edev->config_space[12]);
773
774 eeh_ops->write_config(edev, PCI_CACHE_LINE_SIZE, 1,
775 SAVED_BYTE(PCI_CACHE_LINE_SIZE));
776 eeh_ops->write_config(edev, PCI_LATENCY_TIMER, 1,
777 SAVED_BYTE(PCI_LATENCY_TIMER));
778
779 /* max latency, min grant, interrupt pin and line */
780 eeh_ops->write_config(edev, 15*4, 4, edev->config_space[15]);
781
782 /*
783 * Restore PERR & SERR bits, some devices require it,
784 * don't touch the other command bits
785 */
786 eeh_ops->read_config(edev, PCI_COMMAND, 4, &cmd);
787 if (edev->config_space[1] & PCI_COMMAND_PARITY)
788 cmd |= PCI_COMMAND_PARITY;
789 else
790 cmd &= ~PCI_COMMAND_PARITY;
791 if (edev->config_space[1] & PCI_COMMAND_SERR)
792 cmd |= PCI_COMMAND_SERR;
793 else
794 cmd &= ~PCI_COMMAND_SERR;
795 eeh_ops->write_config(edev, PCI_COMMAND, 4, cmd);
796}
797
798/**
799 * eeh_restore_one_device_bars - Restore the Base Address Registers for one device
800 * @data: EEH device
801 * @flag: Unused
802 *
803 * Loads the PCI configuration space base address registers,
804 * the expansion ROM base address, the latency timer, and etc.
805 * from the saved values in the device node.
806 */
807static void eeh_restore_one_device_bars(struct eeh_dev *edev, void *flag)
808{
809 /* Do special restore for bridges */
810 if (edev->mode & EEH_DEV_BRIDGE)
811 eeh_restore_bridge_bars(edev);
812 else
813 eeh_restore_device_bars(edev);
814
815 if (eeh_ops->restore_config)
816 eeh_ops->restore_config(edev);
817}
818
819/**
820 * eeh_pe_restore_bars - Restore the PCI config space info
821 * @pe: EEH PE
822 *
823 * This routine performs a recursive walk to the children
824 * of this device as well.
825 */
826void eeh_pe_restore_bars(struct eeh_pe *pe)
827{
828 /*
829 * We needn't take the EEH lock since eeh_pe_dev_traverse()
830 * will take that.
831 */
832 eeh_pe_dev_traverse(pe, eeh_restore_one_device_bars, NULL);
833}
834
835/**
836 * eeh_pe_loc_get - Retrieve location code binding to the given PE
837 * @pe: EEH PE
838 *
839 * Retrieve the location code of the given PE. If the primary PE bus
840 * is root bus, we will grab location code from PHB device tree node
841 * or root port. Otherwise, the upstream bridge's device tree node
842 * of the primary PE bus will be checked for the location code.
843 */
844const char *eeh_pe_loc_get(struct eeh_pe *pe)
845{
846 struct pci_bus *bus = eeh_pe_bus_get(pe);
847 struct device_node *dn;
848 const char *loc = NULL;
849
850 while (bus) {
851 dn = pci_bus_to_OF_node(bus);
852 if (!dn) {
853 bus = bus->parent;
854 continue;
855 }
856
857 if (pci_is_root_bus(bus))
858 loc = of_get_property(dn, "ibm,io-base-loc-code", NULL);
859 else
860 loc = of_get_property(dn, "ibm,slot-location-code",
861 NULL);
862
863 if (loc)
864 return loc;
865
866 bus = bus->parent;
867 }
868
869 return "N/A";
870}
871
872/**
873 * eeh_pe_bus_get - Retrieve PCI bus according to the given PE
874 * @pe: EEH PE
875 *
876 * Retrieve the PCI bus according to the given PE. Basically,
877 * there're 3 types of PEs: PHB/Bus/Device. For PHB PE, the
878 * primary PCI bus will be retrieved. The parent bus will be
879 * returned for BUS PE. However, we don't have associated PCI
880 * bus for DEVICE PE.
881 */
882struct pci_bus *eeh_pe_bus_get(struct eeh_pe *pe)
883{
884 struct eeh_dev *edev;
885 struct pci_dev *pdev;
886
887 if (pe->type & EEH_PE_PHB)
888 return pe->phb->bus;
889
890 /* The primary bus might be cached during probe time */
891 if (pe->state & EEH_PE_PRI_BUS)
892 return pe->bus;
893
894 /* Retrieve the parent PCI bus of first (top) PCI device */
895 edev = list_first_entry_or_null(&pe->edevs, struct eeh_dev, entry);
896 pdev = eeh_dev_to_pci_dev(edev);
897 if (pdev)
898 return pdev->bus;
899
900 return NULL;
901}
1/*
2 * The file intends to implement PE based on the information from
3 * platforms. Basically, there have 3 types of PEs: PHB/Bus/Device.
4 * All the PEs should be organized as hierarchy tree. The first level
5 * of the tree will be associated to existing PHBs since the particular
6 * PE is only meaningful in one PHB domain.
7 *
8 * Copyright Benjamin Herrenschmidt & Gavin Shan, IBM Corporation 2012.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 */
24
25#include <linux/delay.h>
26#include <linux/export.h>
27#include <linux/gfp.h>
28#include <linux/kernel.h>
29#include <linux/pci.h>
30#include <linux/string.h>
31
32#include <asm/pci-bridge.h>
33#include <asm/ppc-pci.h>
34
35static int eeh_pe_aux_size = 0;
36static LIST_HEAD(eeh_phb_pe);
37
38/**
39 * eeh_set_pe_aux_size - Set PE auxillary data size
40 * @size: PE auxillary data size
41 *
42 * Set PE auxillary data size
43 */
44void eeh_set_pe_aux_size(int size)
45{
46 if (size < 0)
47 return;
48
49 eeh_pe_aux_size = size;
50}
51
52/**
53 * eeh_pe_alloc - Allocate PE
54 * @phb: PCI controller
55 * @type: PE type
56 *
57 * Allocate PE instance dynamically.
58 */
59static struct eeh_pe *eeh_pe_alloc(struct pci_controller *phb, int type)
60{
61 struct eeh_pe *pe;
62 size_t alloc_size;
63
64 alloc_size = sizeof(struct eeh_pe);
65 if (eeh_pe_aux_size) {
66 alloc_size = ALIGN(alloc_size, cache_line_size());
67 alloc_size += eeh_pe_aux_size;
68 }
69
70 /* Allocate PHB PE */
71 pe = kzalloc(alloc_size, GFP_KERNEL);
72 if (!pe) return NULL;
73
74 /* Initialize PHB PE */
75 pe->type = type;
76 pe->phb = phb;
77 INIT_LIST_HEAD(&pe->child_list);
78 INIT_LIST_HEAD(&pe->child);
79 INIT_LIST_HEAD(&pe->edevs);
80
81 pe->data = (void *)pe + ALIGN(sizeof(struct eeh_pe),
82 cache_line_size());
83 return pe;
84}
85
86/**
87 * eeh_phb_pe_create - Create PHB PE
88 * @phb: PCI controller
89 *
90 * The function should be called while the PHB is detected during
91 * system boot or PCI hotplug in order to create PHB PE.
92 */
93int eeh_phb_pe_create(struct pci_controller *phb)
94{
95 struct eeh_pe *pe;
96
97 /* Allocate PHB PE */
98 pe = eeh_pe_alloc(phb, EEH_PE_PHB);
99 if (!pe) {
100 pr_err("%s: out of memory!\n", __func__);
101 return -ENOMEM;
102 }
103
104 /* Put it into the list */
105 list_add_tail(&pe->child, &eeh_phb_pe);
106
107 pr_debug("EEH: Add PE for PHB#%d\n", phb->global_number);
108
109 return 0;
110}
111
112/**
113 * eeh_phb_pe_get - Retrieve PHB PE based on the given PHB
114 * @phb: PCI controller
115 *
116 * The overall PEs form hierarchy tree. The first layer of the
117 * hierarchy tree is composed of PHB PEs. The function is used
118 * to retrieve the corresponding PHB PE according to the given PHB.
119 */
120struct eeh_pe *eeh_phb_pe_get(struct pci_controller *phb)
121{
122 struct eeh_pe *pe;
123
124 list_for_each_entry(pe, &eeh_phb_pe, child) {
125 /*
126 * Actually, we needn't check the type since
127 * the PE for PHB has been determined when that
128 * was created.
129 */
130 if ((pe->type & EEH_PE_PHB) && pe->phb == phb)
131 return pe;
132 }
133
134 return NULL;
135}
136
137/**
138 * eeh_pe_next - Retrieve the next PE in the tree
139 * @pe: current PE
140 * @root: root PE
141 *
142 * The function is used to retrieve the next PE in the
143 * hierarchy PE tree.
144 */
145static struct eeh_pe *eeh_pe_next(struct eeh_pe *pe,
146 struct eeh_pe *root)
147{
148 struct list_head *next = pe->child_list.next;
149
150 if (next == &pe->child_list) {
151 while (1) {
152 if (pe == root)
153 return NULL;
154 next = pe->child.next;
155 if (next != &pe->parent->child_list)
156 break;
157 pe = pe->parent;
158 }
159 }
160
161 return list_entry(next, struct eeh_pe, child);
162}
163
164/**
165 * eeh_pe_traverse - Traverse PEs in the specified PHB
166 * @root: root PE
167 * @fn: callback
168 * @flag: extra parameter to callback
169 *
170 * The function is used to traverse the specified PE and its
171 * child PEs. The traversing is to be terminated once the
172 * callback returns something other than NULL, or no more PEs
173 * to be traversed.
174 */
175void *eeh_pe_traverse(struct eeh_pe *root,
176 eeh_traverse_func fn, void *flag)
177{
178 struct eeh_pe *pe;
179 void *ret;
180
181 for (pe = root; pe; pe = eeh_pe_next(pe, root)) {
182 ret = fn(pe, flag);
183 if (ret) return ret;
184 }
185
186 return NULL;
187}
188
189/**
190 * eeh_pe_dev_traverse - Traverse the devices from the PE
191 * @root: EEH PE
192 * @fn: function callback
193 * @flag: extra parameter to callback
194 *
195 * The function is used to traverse the devices of the specified
196 * PE and its child PEs.
197 */
198void *eeh_pe_dev_traverse(struct eeh_pe *root,
199 eeh_traverse_func fn, void *flag)
200{
201 struct eeh_pe *pe;
202 struct eeh_dev *edev, *tmp;
203 void *ret;
204
205 if (!root) {
206 pr_warn("%s: Invalid PE %p\n",
207 __func__, root);
208 return NULL;
209 }
210
211 /* Traverse root PE */
212 for (pe = root; pe; pe = eeh_pe_next(pe, root)) {
213 eeh_pe_for_each_dev(pe, edev, tmp) {
214 ret = fn(edev, flag);
215 if (ret)
216 return ret;
217 }
218 }
219
220 return NULL;
221}
222
223/**
224 * __eeh_pe_get - Check the PE address
225 * @data: EEH PE
226 * @flag: EEH device
227 *
228 * For one particular PE, it can be identified by PE address
229 * or tranditional BDF address. BDF address is composed of
230 * Bus/Device/Function number. The extra data referred by flag
231 * indicates which type of address should be used.
232 */
233static void *__eeh_pe_get(void *data, void *flag)
234{
235 struct eeh_pe *pe = (struct eeh_pe *)data;
236 struct eeh_dev *edev = (struct eeh_dev *)flag;
237
238 /* Unexpected PHB PE */
239 if (pe->type & EEH_PE_PHB)
240 return NULL;
241
242 /*
243 * We prefer PE address. For most cases, we should
244 * have non-zero PE address
245 */
246 if (eeh_has_flag(EEH_VALID_PE_ZERO)) {
247 if (edev->pe_config_addr == pe->addr)
248 return pe;
249 } else {
250 if (edev->pe_config_addr &&
251 (edev->pe_config_addr == pe->addr))
252 return pe;
253 }
254
255 /* Try BDF address */
256 if (edev->config_addr &&
257 (edev->config_addr == pe->config_addr))
258 return pe;
259
260 return NULL;
261}
262
263/**
264 * eeh_pe_get - Search PE based on the given address
265 * @edev: EEH device
266 *
267 * Search the corresponding PE based on the specified address which
268 * is included in the eeh device. The function is used to check if
269 * the associated PE has been created against the PE address. It's
270 * notable that the PE address has 2 format: traditional PE address
271 * which is composed of PCI bus/device/function number, or unified
272 * PE address.
273 */
274struct eeh_pe *eeh_pe_get(struct eeh_dev *edev)
275{
276 struct eeh_pe *root = eeh_phb_pe_get(edev->phb);
277 struct eeh_pe *pe;
278
279 pe = eeh_pe_traverse(root, __eeh_pe_get, edev);
280
281 return pe;
282}
283
284/**
285 * eeh_pe_get_parent - Retrieve the parent PE
286 * @edev: EEH device
287 *
288 * The whole PEs existing in the system are organized as hierarchy
289 * tree. The function is used to retrieve the parent PE according
290 * to the parent EEH device.
291 */
292static struct eeh_pe *eeh_pe_get_parent(struct eeh_dev *edev)
293{
294 struct eeh_dev *parent;
295 struct pci_dn *pdn = eeh_dev_to_pdn(edev);
296
297 /*
298 * It might have the case for the indirect parent
299 * EEH device already having associated PE, but
300 * the direct parent EEH device doesn't have yet.
301 */
302 if (edev->physfn)
303 pdn = pci_get_pdn(edev->physfn);
304 else
305 pdn = pdn ? pdn->parent : NULL;
306 while (pdn) {
307 /* We're poking out of PCI territory */
308 parent = pdn_to_eeh_dev(pdn);
309 if (!parent)
310 return NULL;
311
312 if (parent->pe)
313 return parent->pe;
314
315 pdn = pdn->parent;
316 }
317
318 return NULL;
319}
320
321/**
322 * eeh_add_to_parent_pe - Add EEH device to parent PE
323 * @edev: EEH device
324 *
325 * Add EEH device to the parent PE. If the parent PE already
326 * exists, the PE type will be changed to EEH_PE_BUS. Otherwise,
327 * we have to create new PE to hold the EEH device and the new
328 * PE will be linked to its parent PE as well.
329 */
330int eeh_add_to_parent_pe(struct eeh_dev *edev)
331{
332 struct eeh_pe *pe, *parent;
333
334 /* Check if the PE number is valid */
335 if (!eeh_has_flag(EEH_VALID_PE_ZERO) && !edev->pe_config_addr) {
336 pr_err("%s: Invalid PE#0 for edev 0x%x on PHB#%d\n",
337 __func__, edev->config_addr, edev->phb->global_number);
338 return -EINVAL;
339 }
340
341 /*
342 * Search the PE has been existing or not according
343 * to the PE address. If that has been existing, the
344 * PE should be composed of PCI bus and its subordinate
345 * components.
346 */
347 pe = eeh_pe_get(edev);
348 if (pe && !(pe->type & EEH_PE_INVALID)) {
349 /* Mark the PE as type of PCI bus */
350 pe->type = EEH_PE_BUS;
351 edev->pe = pe;
352
353 /* Put the edev to PE */
354 list_add_tail(&edev->list, &pe->edevs);
355 pr_debug("EEH: Add %04x:%02x:%02x.%01x to Bus PE#%x\n",
356 edev->phb->global_number,
357 edev->config_addr >> 8,
358 PCI_SLOT(edev->config_addr & 0xFF),
359 PCI_FUNC(edev->config_addr & 0xFF),
360 pe->addr);
361 return 0;
362 } else if (pe && (pe->type & EEH_PE_INVALID)) {
363 list_add_tail(&edev->list, &pe->edevs);
364 edev->pe = pe;
365 /*
366 * We're running to here because of PCI hotplug caused by
367 * EEH recovery. We need clear EEH_PE_INVALID until the top.
368 */
369 parent = pe;
370 while (parent) {
371 if (!(parent->type & EEH_PE_INVALID))
372 break;
373 parent->type &= ~(EEH_PE_INVALID | EEH_PE_KEEP);
374 parent = parent->parent;
375 }
376
377 pr_debug("EEH: Add %04x:%02x:%02x.%01x to Device "
378 "PE#%x, Parent PE#%x\n",
379 edev->phb->global_number,
380 edev->config_addr >> 8,
381 PCI_SLOT(edev->config_addr & 0xFF),
382 PCI_FUNC(edev->config_addr & 0xFF),
383 pe->addr, pe->parent->addr);
384 return 0;
385 }
386
387 /* Create a new EEH PE */
388 if (edev->physfn)
389 pe = eeh_pe_alloc(edev->phb, EEH_PE_VF);
390 else
391 pe = eeh_pe_alloc(edev->phb, EEH_PE_DEVICE);
392 if (!pe) {
393 pr_err("%s: out of memory!\n", __func__);
394 return -ENOMEM;
395 }
396 pe->addr = edev->pe_config_addr;
397 pe->config_addr = edev->config_addr;
398
399 /*
400 * Put the new EEH PE into hierarchy tree. If the parent
401 * can't be found, the newly created PE will be attached
402 * to PHB directly. Otherwise, we have to associate the
403 * PE with its parent.
404 */
405 parent = eeh_pe_get_parent(edev);
406 if (!parent) {
407 parent = eeh_phb_pe_get(edev->phb);
408 if (!parent) {
409 pr_err("%s: No PHB PE is found (PHB Domain=%d)\n",
410 __func__, edev->phb->global_number);
411 edev->pe = NULL;
412 kfree(pe);
413 return -EEXIST;
414 }
415 }
416 pe->parent = parent;
417
418 /*
419 * Put the newly created PE into the child list and
420 * link the EEH device accordingly.
421 */
422 list_add_tail(&pe->child, &parent->child_list);
423 list_add_tail(&edev->list, &pe->edevs);
424 edev->pe = pe;
425 pr_debug("EEH: Add %04x:%02x:%02x.%01x to "
426 "Device PE#%x, Parent PE#%x\n",
427 edev->phb->global_number,
428 edev->config_addr >> 8,
429 PCI_SLOT(edev->config_addr & 0xFF),
430 PCI_FUNC(edev->config_addr & 0xFF),
431 pe->addr, pe->parent->addr);
432
433 return 0;
434}
435
436/**
437 * eeh_rmv_from_parent_pe - Remove one EEH device from the associated PE
438 * @edev: EEH device
439 *
440 * The PE hierarchy tree might be changed when doing PCI hotplug.
441 * Also, the PCI devices or buses could be removed from the system
442 * during EEH recovery. So we have to call the function remove the
443 * corresponding PE accordingly if necessary.
444 */
445int eeh_rmv_from_parent_pe(struct eeh_dev *edev)
446{
447 struct eeh_pe *pe, *parent, *child;
448 int cnt;
449
450 if (!edev->pe) {
451 pr_debug("%s: No PE found for device %04x:%02x:%02x.%01x\n",
452 __func__, edev->phb->global_number,
453 edev->config_addr >> 8,
454 PCI_SLOT(edev->config_addr & 0xFF),
455 PCI_FUNC(edev->config_addr & 0xFF));
456 return -EEXIST;
457 }
458
459 /* Remove the EEH device */
460 pe = eeh_dev_to_pe(edev);
461 edev->pe = NULL;
462 list_del(&edev->list);
463
464 /*
465 * Check if the parent PE includes any EEH devices.
466 * If not, we should delete that. Also, we should
467 * delete the parent PE if it doesn't have associated
468 * child PEs and EEH devices.
469 */
470 while (1) {
471 parent = pe->parent;
472 if (pe->type & EEH_PE_PHB)
473 break;
474
475 if (!(pe->state & EEH_PE_KEEP)) {
476 if (list_empty(&pe->edevs) &&
477 list_empty(&pe->child_list)) {
478 list_del(&pe->child);
479 kfree(pe);
480 } else {
481 break;
482 }
483 } else {
484 if (list_empty(&pe->edevs)) {
485 cnt = 0;
486 list_for_each_entry(child, &pe->child_list, child) {
487 if (!(child->type & EEH_PE_INVALID)) {
488 cnt++;
489 break;
490 }
491 }
492
493 if (!cnt)
494 pe->type |= EEH_PE_INVALID;
495 else
496 break;
497 }
498 }
499
500 pe = parent;
501 }
502
503 return 0;
504}
505
506/**
507 * eeh_pe_update_time_stamp - Update PE's frozen time stamp
508 * @pe: EEH PE
509 *
510 * We have time stamp for each PE to trace its time of getting
511 * frozen in last hour. The function should be called to update
512 * the time stamp on first error of the specific PE. On the other
513 * handle, we needn't account for errors happened in last hour.
514 */
515void eeh_pe_update_time_stamp(struct eeh_pe *pe)
516{
517 struct timeval tstamp;
518
519 if (!pe) return;
520
521 if (pe->freeze_count <= 0) {
522 pe->freeze_count = 0;
523 do_gettimeofday(&pe->tstamp);
524 } else {
525 do_gettimeofday(&tstamp);
526 if (tstamp.tv_sec - pe->tstamp.tv_sec > 3600) {
527 pe->tstamp = tstamp;
528 pe->freeze_count = 0;
529 }
530 }
531}
532
533/**
534 * __eeh_pe_state_mark - Mark the state for the PE
535 * @data: EEH PE
536 * @flag: state
537 *
538 * The function is used to mark the indicated state for the given
539 * PE. Also, the associated PCI devices will be put into IO frozen
540 * state as well.
541 */
542static void *__eeh_pe_state_mark(void *data, void *flag)
543{
544 struct eeh_pe *pe = (struct eeh_pe *)data;
545 int state = *((int *)flag);
546 struct eeh_dev *edev, *tmp;
547 struct pci_dev *pdev;
548
549 /* Keep the state of permanently removed PE intact */
550 if (pe->state & EEH_PE_REMOVED)
551 return NULL;
552
553 pe->state |= state;
554
555 /* Offline PCI devices if applicable */
556 if (!(state & EEH_PE_ISOLATED))
557 return NULL;
558
559 eeh_pe_for_each_dev(pe, edev, tmp) {
560 pdev = eeh_dev_to_pci_dev(edev);
561 if (pdev)
562 pdev->error_state = pci_channel_io_frozen;
563 }
564
565 /* Block PCI config access if required */
566 if (pe->state & EEH_PE_CFG_RESTRICTED)
567 pe->state |= EEH_PE_CFG_BLOCKED;
568
569 return NULL;
570}
571
572/**
573 * eeh_pe_state_mark - Mark specified state for PE and its associated device
574 * @pe: EEH PE
575 *
576 * EEH error affects the current PE and its child PEs. The function
577 * is used to mark appropriate state for the affected PEs and the
578 * associated devices.
579 */
580void eeh_pe_state_mark(struct eeh_pe *pe, int state)
581{
582 eeh_pe_traverse(pe, __eeh_pe_state_mark, &state);
583}
584
585static void *__eeh_pe_dev_mode_mark(void *data, void *flag)
586{
587 struct eeh_dev *edev = data;
588 int mode = *((int *)flag);
589
590 edev->mode |= mode;
591
592 return NULL;
593}
594
595/**
596 * eeh_pe_dev_state_mark - Mark state for all device under the PE
597 * @pe: EEH PE
598 *
599 * Mark specific state for all child devices of the PE.
600 */
601void eeh_pe_dev_mode_mark(struct eeh_pe *pe, int mode)
602{
603 eeh_pe_dev_traverse(pe, __eeh_pe_dev_mode_mark, &mode);
604}
605
606/**
607 * __eeh_pe_state_clear - Clear state for the PE
608 * @data: EEH PE
609 * @flag: state
610 *
611 * The function is used to clear the indicated state from the
612 * given PE. Besides, we also clear the check count of the PE
613 * as well.
614 */
615static void *__eeh_pe_state_clear(void *data, void *flag)
616{
617 struct eeh_pe *pe = (struct eeh_pe *)data;
618 int state = *((int *)flag);
619 struct eeh_dev *edev, *tmp;
620 struct pci_dev *pdev;
621
622 /* Keep the state of permanently removed PE intact */
623 if (pe->state & EEH_PE_REMOVED)
624 return NULL;
625
626 pe->state &= ~state;
627
628 /*
629 * Special treatment on clearing isolated state. Clear
630 * check count since last isolation and put all affected
631 * devices to normal state.
632 */
633 if (!(state & EEH_PE_ISOLATED))
634 return NULL;
635
636 pe->check_count = 0;
637 eeh_pe_for_each_dev(pe, edev, tmp) {
638 pdev = eeh_dev_to_pci_dev(edev);
639 if (!pdev)
640 continue;
641
642 pdev->error_state = pci_channel_io_normal;
643 }
644
645 /* Unblock PCI config access if required */
646 if (pe->state & EEH_PE_CFG_RESTRICTED)
647 pe->state &= ~EEH_PE_CFG_BLOCKED;
648
649 return NULL;
650}
651
652/**
653 * eeh_pe_state_clear - Clear state for the PE and its children
654 * @pe: PE
655 * @state: state to be cleared
656 *
657 * When the PE and its children has been recovered from error,
658 * we need clear the error state for that. The function is used
659 * for the purpose.
660 */
661void eeh_pe_state_clear(struct eeh_pe *pe, int state)
662{
663 eeh_pe_traverse(pe, __eeh_pe_state_clear, &state);
664}
665
666/**
667 * eeh_pe_state_mark_with_cfg - Mark PE state with unblocked config space
668 * @pe: PE
669 * @state: PE state to be set
670 *
671 * Set specified flag to PE and its child PEs. The PCI config space
672 * of some PEs is blocked automatically when EEH_PE_ISOLATED is set,
673 * which isn't needed in some situations. The function allows to set
674 * the specified flag to indicated PEs without blocking their PCI
675 * config space.
676 */
677void eeh_pe_state_mark_with_cfg(struct eeh_pe *pe, int state)
678{
679 eeh_pe_traverse(pe, __eeh_pe_state_mark, &state);
680 if (!(state & EEH_PE_ISOLATED))
681 return;
682
683 /* Clear EEH_PE_CFG_BLOCKED, which might be set just now */
684 state = EEH_PE_CFG_BLOCKED;
685 eeh_pe_traverse(pe, __eeh_pe_state_clear, &state);
686}
687
688/*
689 * Some PCI bridges (e.g. PLX bridges) have primary/secondary
690 * buses assigned explicitly by firmware, and we probably have
691 * lost that after reset. So we have to delay the check until
692 * the PCI-CFG registers have been restored for the parent
693 * bridge.
694 *
695 * Don't use normal PCI-CFG accessors, which probably has been
696 * blocked on normal path during the stage. So we need utilize
697 * eeh operations, which is always permitted.
698 */
699static void eeh_bridge_check_link(struct eeh_dev *edev)
700{
701 struct pci_dn *pdn = eeh_dev_to_pdn(edev);
702 int cap;
703 uint32_t val;
704 int timeout = 0;
705
706 /*
707 * We only check root port and downstream ports of
708 * PCIe switches
709 */
710 if (!(edev->mode & (EEH_DEV_ROOT_PORT | EEH_DEV_DS_PORT)))
711 return;
712
713 pr_debug("%s: Check PCIe link for %04x:%02x:%02x.%01x ...\n",
714 __func__, edev->phb->global_number,
715 edev->config_addr >> 8,
716 PCI_SLOT(edev->config_addr & 0xFF),
717 PCI_FUNC(edev->config_addr & 0xFF));
718
719 /* Check slot status */
720 cap = edev->pcie_cap;
721 eeh_ops->read_config(pdn, cap + PCI_EXP_SLTSTA, 2, &val);
722 if (!(val & PCI_EXP_SLTSTA_PDS)) {
723 pr_debug(" No card in the slot (0x%04x) !\n", val);
724 return;
725 }
726
727 /* Check power status if we have the capability */
728 eeh_ops->read_config(pdn, cap + PCI_EXP_SLTCAP, 2, &val);
729 if (val & PCI_EXP_SLTCAP_PCP) {
730 eeh_ops->read_config(pdn, cap + PCI_EXP_SLTCTL, 2, &val);
731 if (val & PCI_EXP_SLTCTL_PCC) {
732 pr_debug(" In power-off state, power it on ...\n");
733 val &= ~(PCI_EXP_SLTCTL_PCC | PCI_EXP_SLTCTL_PIC);
734 val |= (0x0100 & PCI_EXP_SLTCTL_PIC);
735 eeh_ops->write_config(pdn, cap + PCI_EXP_SLTCTL, 2, val);
736 msleep(2 * 1000);
737 }
738 }
739
740 /* Enable link */
741 eeh_ops->read_config(pdn, cap + PCI_EXP_LNKCTL, 2, &val);
742 val &= ~PCI_EXP_LNKCTL_LD;
743 eeh_ops->write_config(pdn, cap + PCI_EXP_LNKCTL, 2, val);
744
745 /* Check link */
746 eeh_ops->read_config(pdn, cap + PCI_EXP_LNKCAP, 4, &val);
747 if (!(val & PCI_EXP_LNKCAP_DLLLARC)) {
748 pr_debug(" No link reporting capability (0x%08x) \n", val);
749 msleep(1000);
750 return;
751 }
752
753 /* Wait the link is up until timeout (5s) */
754 timeout = 0;
755 while (timeout < 5000) {
756 msleep(20);
757 timeout += 20;
758
759 eeh_ops->read_config(pdn, cap + PCI_EXP_LNKSTA, 2, &val);
760 if (val & PCI_EXP_LNKSTA_DLLLA)
761 break;
762 }
763
764 if (val & PCI_EXP_LNKSTA_DLLLA)
765 pr_debug(" Link up (%s)\n",
766 (val & PCI_EXP_LNKSTA_CLS_2_5GB) ? "2.5GB" : "5GB");
767 else
768 pr_debug(" Link not ready (0x%04x)\n", val);
769}
770
771#define BYTE_SWAP(OFF) (8*((OFF)/4)+3-(OFF))
772#define SAVED_BYTE(OFF) (((u8 *)(edev->config_space))[BYTE_SWAP(OFF)])
773
774static void eeh_restore_bridge_bars(struct eeh_dev *edev)
775{
776 struct pci_dn *pdn = eeh_dev_to_pdn(edev);
777 int i;
778
779 /*
780 * Device BARs: 0x10 - 0x18
781 * Bus numbers and windows: 0x18 - 0x30
782 */
783 for (i = 4; i < 13; i++)
784 eeh_ops->write_config(pdn, i*4, 4, edev->config_space[i]);
785 /* Rom: 0x38 */
786 eeh_ops->write_config(pdn, 14*4, 4, edev->config_space[14]);
787
788 /* Cache line & Latency timer: 0xC 0xD */
789 eeh_ops->write_config(pdn, PCI_CACHE_LINE_SIZE, 1,
790 SAVED_BYTE(PCI_CACHE_LINE_SIZE));
791 eeh_ops->write_config(pdn, PCI_LATENCY_TIMER, 1,
792 SAVED_BYTE(PCI_LATENCY_TIMER));
793 /* Max latency, min grant, interrupt ping and line: 0x3C */
794 eeh_ops->write_config(pdn, 15*4, 4, edev->config_space[15]);
795
796 /* PCI Command: 0x4 */
797 eeh_ops->write_config(pdn, PCI_COMMAND, 4, edev->config_space[1]);
798
799 /* Check the PCIe link is ready */
800 eeh_bridge_check_link(edev);
801}
802
803static void eeh_restore_device_bars(struct eeh_dev *edev)
804{
805 struct pci_dn *pdn = eeh_dev_to_pdn(edev);
806 int i;
807 u32 cmd;
808
809 for (i = 4; i < 10; i++)
810 eeh_ops->write_config(pdn, i*4, 4, edev->config_space[i]);
811 /* 12 == Expansion ROM Address */
812 eeh_ops->write_config(pdn, 12*4, 4, edev->config_space[12]);
813
814 eeh_ops->write_config(pdn, PCI_CACHE_LINE_SIZE, 1,
815 SAVED_BYTE(PCI_CACHE_LINE_SIZE));
816 eeh_ops->write_config(pdn, PCI_LATENCY_TIMER, 1,
817 SAVED_BYTE(PCI_LATENCY_TIMER));
818
819 /* max latency, min grant, interrupt pin and line */
820 eeh_ops->write_config(pdn, 15*4, 4, edev->config_space[15]);
821
822 /*
823 * Restore PERR & SERR bits, some devices require it,
824 * don't touch the other command bits
825 */
826 eeh_ops->read_config(pdn, PCI_COMMAND, 4, &cmd);
827 if (edev->config_space[1] & PCI_COMMAND_PARITY)
828 cmd |= PCI_COMMAND_PARITY;
829 else
830 cmd &= ~PCI_COMMAND_PARITY;
831 if (edev->config_space[1] & PCI_COMMAND_SERR)
832 cmd |= PCI_COMMAND_SERR;
833 else
834 cmd &= ~PCI_COMMAND_SERR;
835 eeh_ops->write_config(pdn, PCI_COMMAND, 4, cmd);
836}
837
838/**
839 * eeh_restore_one_device_bars - Restore the Base Address Registers for one device
840 * @data: EEH device
841 * @flag: Unused
842 *
843 * Loads the PCI configuration space base address registers,
844 * the expansion ROM base address, the latency timer, and etc.
845 * from the saved values in the device node.
846 */
847static void *eeh_restore_one_device_bars(void *data, void *flag)
848{
849 struct eeh_dev *edev = (struct eeh_dev *)data;
850 struct pci_dn *pdn = eeh_dev_to_pdn(edev);
851
852 /* Do special restore for bridges */
853 if (edev->mode & EEH_DEV_BRIDGE)
854 eeh_restore_bridge_bars(edev);
855 else
856 eeh_restore_device_bars(edev);
857
858 if (eeh_ops->restore_config && pdn)
859 eeh_ops->restore_config(pdn);
860
861 return NULL;
862}
863
864/**
865 * eeh_pe_restore_bars - Restore the PCI config space info
866 * @pe: EEH PE
867 *
868 * This routine performs a recursive walk to the children
869 * of this device as well.
870 */
871void eeh_pe_restore_bars(struct eeh_pe *pe)
872{
873 /*
874 * We needn't take the EEH lock since eeh_pe_dev_traverse()
875 * will take that.
876 */
877 eeh_pe_dev_traverse(pe, eeh_restore_one_device_bars, NULL);
878}
879
880/**
881 * eeh_pe_loc_get - Retrieve location code binding to the given PE
882 * @pe: EEH PE
883 *
884 * Retrieve the location code of the given PE. If the primary PE bus
885 * is root bus, we will grab location code from PHB device tree node
886 * or root port. Otherwise, the upstream bridge's device tree node
887 * of the primary PE bus will be checked for the location code.
888 */
889const char *eeh_pe_loc_get(struct eeh_pe *pe)
890{
891 struct pci_bus *bus = eeh_pe_bus_get(pe);
892 struct device_node *dn;
893 const char *loc = NULL;
894
895 while (bus) {
896 dn = pci_bus_to_OF_node(bus);
897 if (!dn) {
898 bus = bus->parent;
899 continue;
900 }
901
902 if (pci_is_root_bus(bus))
903 loc = of_get_property(dn, "ibm,io-base-loc-code", NULL);
904 else
905 loc = of_get_property(dn, "ibm,slot-location-code",
906 NULL);
907
908 if (loc)
909 return loc;
910
911 bus = bus->parent;
912 }
913
914 return "N/A";
915}
916
917/**
918 * eeh_pe_bus_get - Retrieve PCI bus according to the given PE
919 * @pe: EEH PE
920 *
921 * Retrieve the PCI bus according to the given PE. Basically,
922 * there're 3 types of PEs: PHB/Bus/Device. For PHB PE, the
923 * primary PCI bus will be retrieved. The parent bus will be
924 * returned for BUS PE. However, we don't have associated PCI
925 * bus for DEVICE PE.
926 */
927struct pci_bus *eeh_pe_bus_get(struct eeh_pe *pe)
928{
929 struct eeh_dev *edev;
930 struct pci_dev *pdev;
931
932 if (pe->type & EEH_PE_PHB)
933 return pe->phb->bus;
934
935 /* The primary bus might be cached during probe time */
936 if (pe->state & EEH_PE_PRI_BUS)
937 return pe->bus;
938
939 /* Retrieve the parent PCI bus of first (top) PCI device */
940 edev = list_first_entry_or_null(&pe->edevs, struct eeh_dev, list);
941 pdev = eeh_dev_to_pci_dev(edev);
942 if (pdev)
943 return pdev->bus;
944
945 return NULL;
946}