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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright (c) 2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2410 Watchdog Timer Support
7 *
8 * Based on, softdog.c by Alan Cox,
9 * (c) Copyright 1996 Alan Cox <alan@lxorguk.ukuu.org.uk>
10 */
11
12#include <linux/module.h>
13#include <linux/moduleparam.h>
14#include <linux/types.h>
15#include <linux/timer.h>
16#include <linux/watchdog.h>
17#include <linux/platform_device.h>
18#include <linux/interrupt.h>
19#include <linux/clk.h>
20#include <linux/uaccess.h>
21#include <linux/io.h>
22#include <linux/cpufreq.h>
23#include <linux/slab.h>
24#include <linux/err.h>
25#include <linux/of.h>
26#include <linux/of_device.h>
27#include <linux/mfd/syscon.h>
28#include <linux/regmap.h>
29#include <linux/delay.h>
30
31#define S3C2410_WTCON 0x00
32#define S3C2410_WTDAT 0x04
33#define S3C2410_WTCNT 0x08
34#define S3C2410_WTCLRINT 0x0c
35
36#define S3C2410_WTCNT_MAXCNT 0xffff
37
38#define S3C2410_WTCON_RSTEN (1 << 0)
39#define S3C2410_WTCON_INTEN (1 << 2)
40#define S3C2410_WTCON_ENABLE (1 << 5)
41
42#define S3C2410_WTCON_DIV16 (0 << 3)
43#define S3C2410_WTCON_DIV32 (1 << 3)
44#define S3C2410_WTCON_DIV64 (2 << 3)
45#define S3C2410_WTCON_DIV128 (3 << 3)
46
47#define S3C2410_WTCON_MAXDIV 0x80
48
49#define S3C2410_WTCON_PRESCALE(x) ((x) << 8)
50#define S3C2410_WTCON_PRESCALE_MASK (0xff << 8)
51#define S3C2410_WTCON_PRESCALE_MAX 0xff
52
53#define S3C2410_WATCHDOG_ATBOOT (0)
54#define S3C2410_WATCHDOG_DEFAULT_TIME (15)
55
56#define EXYNOS5_RST_STAT_REG_OFFSET 0x0404
57#define EXYNOS5_WDT_DISABLE_REG_OFFSET 0x0408
58#define EXYNOS5_WDT_MASK_RESET_REG_OFFSET 0x040c
59#define QUIRK_HAS_PMU_CONFIG (1 << 0)
60#define QUIRK_HAS_RST_STAT (1 << 1)
61#define QUIRK_HAS_WTCLRINT_REG (1 << 2)
62
63/* These quirks require that we have a PMU register map */
64#define QUIRKS_HAVE_PMUREG (QUIRK_HAS_PMU_CONFIG | \
65 QUIRK_HAS_RST_STAT)
66
67static bool nowayout = WATCHDOG_NOWAYOUT;
68static int tmr_margin;
69static int tmr_atboot = S3C2410_WATCHDOG_ATBOOT;
70static int soft_noboot;
71
72module_param(tmr_margin, int, 0);
73module_param(tmr_atboot, int, 0);
74module_param(nowayout, bool, 0);
75module_param(soft_noboot, int, 0);
76
77MODULE_PARM_DESC(tmr_margin, "Watchdog tmr_margin in seconds. (default="
78 __MODULE_STRING(S3C2410_WATCHDOG_DEFAULT_TIME) ")");
79MODULE_PARM_DESC(tmr_atboot,
80 "Watchdog is started at boot time if set to 1, default="
81 __MODULE_STRING(S3C2410_WATCHDOG_ATBOOT));
82MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
83 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
84MODULE_PARM_DESC(soft_noboot, "Watchdog action, set to 1 to ignore reboots, 0 to reboot (default 0)");
85
86/**
87 * struct s3c2410_wdt_variant - Per-variant config data
88 *
89 * @disable_reg: Offset in pmureg for the register that disables the watchdog
90 * timer reset functionality.
91 * @mask_reset_reg: Offset in pmureg for the register that masks the watchdog
92 * timer reset functionality.
93 * @mask_bit: Bit number for the watchdog timer in the disable register and the
94 * mask reset register.
95 * @rst_stat_reg: Offset in pmureg for the register that has the reset status.
96 * @rst_stat_bit: Bit number in the rst_stat register indicating a watchdog
97 * reset.
98 * @quirks: A bitfield of quirks.
99 */
100
101struct s3c2410_wdt_variant {
102 int disable_reg;
103 int mask_reset_reg;
104 int mask_bit;
105 int rst_stat_reg;
106 int rst_stat_bit;
107 u32 quirks;
108};
109
110struct s3c2410_wdt {
111 struct device *dev;
112 struct clk *clock;
113 void __iomem *reg_base;
114 unsigned int count;
115 spinlock_t lock;
116 unsigned long wtcon_save;
117 unsigned long wtdat_save;
118 struct watchdog_device wdt_device;
119 struct notifier_block freq_transition;
120 const struct s3c2410_wdt_variant *drv_data;
121 struct regmap *pmureg;
122};
123
124static const struct s3c2410_wdt_variant drv_data_s3c2410 = {
125 .quirks = 0
126};
127
128#ifdef CONFIG_OF
129static const struct s3c2410_wdt_variant drv_data_s3c6410 = {
130 .quirks = QUIRK_HAS_WTCLRINT_REG,
131};
132
133static const struct s3c2410_wdt_variant drv_data_exynos5250 = {
134 .disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET,
135 .mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET,
136 .mask_bit = 20,
137 .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
138 .rst_stat_bit = 20,
139 .quirks = QUIRK_HAS_PMU_CONFIG | QUIRK_HAS_RST_STAT \
140 | QUIRK_HAS_WTCLRINT_REG,
141};
142
143static const struct s3c2410_wdt_variant drv_data_exynos5420 = {
144 .disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET,
145 .mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET,
146 .mask_bit = 0,
147 .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
148 .rst_stat_bit = 9,
149 .quirks = QUIRK_HAS_PMU_CONFIG | QUIRK_HAS_RST_STAT \
150 | QUIRK_HAS_WTCLRINT_REG,
151};
152
153static const struct s3c2410_wdt_variant drv_data_exynos7 = {
154 .disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET,
155 .mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET,
156 .mask_bit = 23,
157 .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
158 .rst_stat_bit = 23, /* A57 WDTRESET */
159 .quirks = QUIRK_HAS_PMU_CONFIG | QUIRK_HAS_RST_STAT \
160 | QUIRK_HAS_WTCLRINT_REG,
161};
162
163static const struct of_device_id s3c2410_wdt_match[] = {
164 { .compatible = "samsung,s3c2410-wdt",
165 .data = &drv_data_s3c2410 },
166 { .compatible = "samsung,s3c6410-wdt",
167 .data = &drv_data_s3c6410 },
168 { .compatible = "samsung,exynos5250-wdt",
169 .data = &drv_data_exynos5250 },
170 { .compatible = "samsung,exynos5420-wdt",
171 .data = &drv_data_exynos5420 },
172 { .compatible = "samsung,exynos7-wdt",
173 .data = &drv_data_exynos7 },
174 {},
175};
176MODULE_DEVICE_TABLE(of, s3c2410_wdt_match);
177#endif
178
179static const struct platform_device_id s3c2410_wdt_ids[] = {
180 {
181 .name = "s3c2410-wdt",
182 .driver_data = (unsigned long)&drv_data_s3c2410,
183 },
184 {}
185};
186MODULE_DEVICE_TABLE(platform, s3c2410_wdt_ids);
187
188/* functions */
189
190static inline unsigned int s3c2410wdt_max_timeout(struct clk *clock)
191{
192 unsigned long freq = clk_get_rate(clock);
193
194 return S3C2410_WTCNT_MAXCNT / (freq / (S3C2410_WTCON_PRESCALE_MAX + 1)
195 / S3C2410_WTCON_MAXDIV);
196}
197
198static inline struct s3c2410_wdt *freq_to_wdt(struct notifier_block *nb)
199{
200 return container_of(nb, struct s3c2410_wdt, freq_transition);
201}
202
203static int s3c2410wdt_mask_and_disable_reset(struct s3c2410_wdt *wdt, bool mask)
204{
205 int ret;
206 u32 mask_val = 1 << wdt->drv_data->mask_bit;
207 u32 val = 0;
208
209 /* No need to do anything if no PMU CONFIG needed */
210 if (!(wdt->drv_data->quirks & QUIRK_HAS_PMU_CONFIG))
211 return 0;
212
213 if (mask)
214 val = mask_val;
215
216 ret = regmap_update_bits(wdt->pmureg,
217 wdt->drv_data->disable_reg,
218 mask_val, val);
219 if (ret < 0)
220 goto error;
221
222 ret = regmap_update_bits(wdt->pmureg,
223 wdt->drv_data->mask_reset_reg,
224 mask_val, val);
225 error:
226 if (ret < 0)
227 dev_err(wdt->dev, "failed to update reg(%d)\n", ret);
228
229 return ret;
230}
231
232static int s3c2410wdt_keepalive(struct watchdog_device *wdd)
233{
234 struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
235
236 spin_lock(&wdt->lock);
237 writel(wdt->count, wdt->reg_base + S3C2410_WTCNT);
238 spin_unlock(&wdt->lock);
239
240 return 0;
241}
242
243static void __s3c2410wdt_stop(struct s3c2410_wdt *wdt)
244{
245 unsigned long wtcon;
246
247 wtcon = readl(wdt->reg_base + S3C2410_WTCON);
248 wtcon &= ~(S3C2410_WTCON_ENABLE | S3C2410_WTCON_RSTEN);
249 writel(wtcon, wdt->reg_base + S3C2410_WTCON);
250}
251
252static int s3c2410wdt_stop(struct watchdog_device *wdd)
253{
254 struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
255
256 spin_lock(&wdt->lock);
257 __s3c2410wdt_stop(wdt);
258 spin_unlock(&wdt->lock);
259
260 return 0;
261}
262
263static int s3c2410wdt_start(struct watchdog_device *wdd)
264{
265 unsigned long wtcon;
266 struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
267
268 spin_lock(&wdt->lock);
269
270 __s3c2410wdt_stop(wdt);
271
272 wtcon = readl(wdt->reg_base + S3C2410_WTCON);
273 wtcon |= S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128;
274
275 if (soft_noboot) {
276 wtcon |= S3C2410_WTCON_INTEN;
277 wtcon &= ~S3C2410_WTCON_RSTEN;
278 } else {
279 wtcon &= ~S3C2410_WTCON_INTEN;
280 wtcon |= S3C2410_WTCON_RSTEN;
281 }
282
283 dev_dbg(wdt->dev, "Starting watchdog: count=0x%08x, wtcon=%08lx\n",
284 wdt->count, wtcon);
285
286 writel(wdt->count, wdt->reg_base + S3C2410_WTDAT);
287 writel(wdt->count, wdt->reg_base + S3C2410_WTCNT);
288 writel(wtcon, wdt->reg_base + S3C2410_WTCON);
289 spin_unlock(&wdt->lock);
290
291 return 0;
292}
293
294static inline int s3c2410wdt_is_running(struct s3c2410_wdt *wdt)
295{
296 return readl(wdt->reg_base + S3C2410_WTCON) & S3C2410_WTCON_ENABLE;
297}
298
299static int s3c2410wdt_set_heartbeat(struct watchdog_device *wdd,
300 unsigned int timeout)
301{
302 struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
303 unsigned long freq = clk_get_rate(wdt->clock);
304 unsigned int count;
305 unsigned int divisor = 1;
306 unsigned long wtcon;
307
308 if (timeout < 1)
309 return -EINVAL;
310
311 freq = DIV_ROUND_UP(freq, 128);
312 count = timeout * freq;
313
314 dev_dbg(wdt->dev, "Heartbeat: count=%d, timeout=%d, freq=%lu\n",
315 count, timeout, freq);
316
317 /* if the count is bigger than the watchdog register,
318 then work out what we need to do (and if) we can
319 actually make this value
320 */
321
322 if (count >= 0x10000) {
323 divisor = DIV_ROUND_UP(count, 0xffff);
324
325 if (divisor > 0x100) {
326 dev_err(wdt->dev, "timeout %d too big\n", timeout);
327 return -EINVAL;
328 }
329 }
330
331 dev_dbg(wdt->dev, "Heartbeat: timeout=%d, divisor=%d, count=%d (%08x)\n",
332 timeout, divisor, count, DIV_ROUND_UP(count, divisor));
333
334 count = DIV_ROUND_UP(count, divisor);
335 wdt->count = count;
336
337 /* update the pre-scaler */
338 wtcon = readl(wdt->reg_base + S3C2410_WTCON);
339 wtcon &= ~S3C2410_WTCON_PRESCALE_MASK;
340 wtcon |= S3C2410_WTCON_PRESCALE(divisor-1);
341
342 writel(count, wdt->reg_base + S3C2410_WTDAT);
343 writel(wtcon, wdt->reg_base + S3C2410_WTCON);
344
345 wdd->timeout = (count * divisor) / freq;
346
347 return 0;
348}
349
350static int s3c2410wdt_restart(struct watchdog_device *wdd, unsigned long action,
351 void *data)
352{
353 struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
354 void __iomem *wdt_base = wdt->reg_base;
355
356 /* disable watchdog, to be safe */
357 writel(0, wdt_base + S3C2410_WTCON);
358
359 /* put initial values into count and data */
360 writel(0x80, wdt_base + S3C2410_WTCNT);
361 writel(0x80, wdt_base + S3C2410_WTDAT);
362
363 /* set the watchdog to go and reset... */
364 writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV16 |
365 S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x20),
366 wdt_base + S3C2410_WTCON);
367
368 /* wait for reset to assert... */
369 mdelay(500);
370
371 return 0;
372}
373
374#define OPTIONS (WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE)
375
376static const struct watchdog_info s3c2410_wdt_ident = {
377 .options = OPTIONS,
378 .firmware_version = 0,
379 .identity = "S3C2410 Watchdog",
380};
381
382static const struct watchdog_ops s3c2410wdt_ops = {
383 .owner = THIS_MODULE,
384 .start = s3c2410wdt_start,
385 .stop = s3c2410wdt_stop,
386 .ping = s3c2410wdt_keepalive,
387 .set_timeout = s3c2410wdt_set_heartbeat,
388 .restart = s3c2410wdt_restart,
389};
390
391static const struct watchdog_device s3c2410_wdd = {
392 .info = &s3c2410_wdt_ident,
393 .ops = &s3c2410wdt_ops,
394 .timeout = S3C2410_WATCHDOG_DEFAULT_TIME,
395};
396
397/* interrupt handler code */
398
399static irqreturn_t s3c2410wdt_irq(int irqno, void *param)
400{
401 struct s3c2410_wdt *wdt = platform_get_drvdata(param);
402
403 dev_info(wdt->dev, "watchdog timer expired (irq)\n");
404
405 s3c2410wdt_keepalive(&wdt->wdt_device);
406
407 if (wdt->drv_data->quirks & QUIRK_HAS_WTCLRINT_REG)
408 writel(0x1, wdt->reg_base + S3C2410_WTCLRINT);
409
410 return IRQ_HANDLED;
411}
412
413#ifdef CONFIG_ARM_S3C24XX_CPUFREQ
414
415static int s3c2410wdt_cpufreq_transition(struct notifier_block *nb,
416 unsigned long val, void *data)
417{
418 int ret;
419 struct s3c2410_wdt *wdt = freq_to_wdt(nb);
420
421 if (!s3c2410wdt_is_running(wdt))
422 goto done;
423
424 if (val == CPUFREQ_PRECHANGE) {
425 /* To ensure that over the change we don't cause the
426 * watchdog to trigger, we perform an keep-alive if
427 * the watchdog is running.
428 */
429
430 s3c2410wdt_keepalive(&wdt->wdt_device);
431 } else if (val == CPUFREQ_POSTCHANGE) {
432 s3c2410wdt_stop(&wdt->wdt_device);
433
434 ret = s3c2410wdt_set_heartbeat(&wdt->wdt_device,
435 wdt->wdt_device.timeout);
436
437 if (ret >= 0)
438 s3c2410wdt_start(&wdt->wdt_device);
439 else
440 goto err;
441 }
442
443done:
444 return 0;
445
446 err:
447 dev_err(wdt->dev, "cannot set new value for timeout %d\n",
448 wdt->wdt_device.timeout);
449 return ret;
450}
451
452static inline int s3c2410wdt_cpufreq_register(struct s3c2410_wdt *wdt)
453{
454 wdt->freq_transition.notifier_call = s3c2410wdt_cpufreq_transition;
455
456 return cpufreq_register_notifier(&wdt->freq_transition,
457 CPUFREQ_TRANSITION_NOTIFIER);
458}
459
460static inline void s3c2410wdt_cpufreq_deregister(struct s3c2410_wdt *wdt)
461{
462 wdt->freq_transition.notifier_call = s3c2410wdt_cpufreq_transition;
463
464 cpufreq_unregister_notifier(&wdt->freq_transition,
465 CPUFREQ_TRANSITION_NOTIFIER);
466}
467
468#else
469
470static inline int s3c2410wdt_cpufreq_register(struct s3c2410_wdt *wdt)
471{
472 return 0;
473}
474
475static inline void s3c2410wdt_cpufreq_deregister(struct s3c2410_wdt *wdt)
476{
477}
478#endif
479
480static inline unsigned int s3c2410wdt_get_bootstatus(struct s3c2410_wdt *wdt)
481{
482 unsigned int rst_stat;
483 int ret;
484
485 if (!(wdt->drv_data->quirks & QUIRK_HAS_RST_STAT))
486 return 0;
487
488 ret = regmap_read(wdt->pmureg, wdt->drv_data->rst_stat_reg, &rst_stat);
489 if (ret)
490 dev_warn(wdt->dev, "Couldn't get RST_STAT register\n");
491 else if (rst_stat & BIT(wdt->drv_data->rst_stat_bit))
492 return WDIOF_CARDRESET;
493
494 return 0;
495}
496
497static inline const struct s3c2410_wdt_variant *
498s3c2410_get_wdt_drv_data(struct platform_device *pdev)
499{
500 const struct s3c2410_wdt_variant *variant;
501
502 variant = of_device_get_match_data(&pdev->dev);
503 if (!variant) {
504 /* Device matched by platform_device_id */
505 variant = (struct s3c2410_wdt_variant *)
506 platform_get_device_id(pdev)->driver_data;
507 }
508
509 return variant;
510}
511
512static int s3c2410wdt_probe(struct platform_device *pdev)
513{
514 struct device *dev = &pdev->dev;
515 struct s3c2410_wdt *wdt;
516 struct resource *wdt_irq;
517 unsigned int wtcon;
518 int started = 0;
519 int ret;
520
521 wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
522 if (!wdt)
523 return -ENOMEM;
524
525 wdt->dev = dev;
526 spin_lock_init(&wdt->lock);
527 wdt->wdt_device = s3c2410_wdd;
528
529 wdt->drv_data = s3c2410_get_wdt_drv_data(pdev);
530 if (wdt->drv_data->quirks & QUIRKS_HAVE_PMUREG) {
531 wdt->pmureg = syscon_regmap_lookup_by_phandle(dev->of_node,
532 "samsung,syscon-phandle");
533 if (IS_ERR(wdt->pmureg)) {
534 dev_err(dev, "syscon regmap lookup failed.\n");
535 return PTR_ERR(wdt->pmureg);
536 }
537 }
538
539 wdt_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
540 if (wdt_irq == NULL) {
541 dev_err(dev, "no irq resource specified\n");
542 ret = -ENOENT;
543 goto err;
544 }
545
546 /* get the memory region for the watchdog timer */
547 wdt->reg_base = devm_platform_ioremap_resource(pdev, 0);
548 if (IS_ERR(wdt->reg_base)) {
549 ret = PTR_ERR(wdt->reg_base);
550 goto err;
551 }
552
553 wdt->clock = devm_clk_get(dev, "watchdog");
554 if (IS_ERR(wdt->clock)) {
555 dev_err(dev, "failed to find watchdog clock source\n");
556 ret = PTR_ERR(wdt->clock);
557 goto err;
558 }
559
560 ret = clk_prepare_enable(wdt->clock);
561 if (ret < 0) {
562 dev_err(dev, "failed to enable clock\n");
563 return ret;
564 }
565
566 wdt->wdt_device.min_timeout = 1;
567 wdt->wdt_device.max_timeout = s3c2410wdt_max_timeout(wdt->clock);
568
569 ret = s3c2410wdt_cpufreq_register(wdt);
570 if (ret < 0) {
571 dev_err(dev, "failed to register cpufreq\n");
572 goto err_clk;
573 }
574
575 watchdog_set_drvdata(&wdt->wdt_device, wdt);
576
577 /* see if we can actually set the requested timer margin, and if
578 * not, try the default value */
579
580 watchdog_init_timeout(&wdt->wdt_device, tmr_margin, dev);
581 ret = s3c2410wdt_set_heartbeat(&wdt->wdt_device,
582 wdt->wdt_device.timeout);
583 if (ret) {
584 started = s3c2410wdt_set_heartbeat(&wdt->wdt_device,
585 S3C2410_WATCHDOG_DEFAULT_TIME);
586
587 if (started == 0)
588 dev_info(dev,
589 "tmr_margin value out of range, default %d used\n",
590 S3C2410_WATCHDOG_DEFAULT_TIME);
591 else
592 dev_info(dev, "default timer value is out of range, cannot start\n");
593 }
594
595 ret = devm_request_irq(dev, wdt_irq->start, s3c2410wdt_irq, 0,
596 pdev->name, pdev);
597 if (ret != 0) {
598 dev_err(dev, "failed to install irq (%d)\n", ret);
599 goto err_cpufreq;
600 }
601
602 watchdog_set_nowayout(&wdt->wdt_device, nowayout);
603 watchdog_set_restart_priority(&wdt->wdt_device, 128);
604
605 wdt->wdt_device.bootstatus = s3c2410wdt_get_bootstatus(wdt);
606 wdt->wdt_device.parent = dev;
607
608 ret = watchdog_register_device(&wdt->wdt_device);
609 if (ret)
610 goto err_cpufreq;
611
612 ret = s3c2410wdt_mask_and_disable_reset(wdt, false);
613 if (ret < 0)
614 goto err_unregister;
615
616 if (tmr_atboot && started == 0) {
617 dev_info(dev, "starting watchdog timer\n");
618 s3c2410wdt_start(&wdt->wdt_device);
619 } else if (!tmr_atboot) {
620 /* if we're not enabling the watchdog, then ensure it is
621 * disabled if it has been left running from the bootloader
622 * or other source */
623
624 s3c2410wdt_stop(&wdt->wdt_device);
625 }
626
627 platform_set_drvdata(pdev, wdt);
628
629 /* print out a statement of readiness */
630
631 wtcon = readl(wdt->reg_base + S3C2410_WTCON);
632
633 dev_info(dev, "watchdog %sactive, reset %sabled, irq %sabled\n",
634 (wtcon & S3C2410_WTCON_ENABLE) ? "" : "in",
635 (wtcon & S3C2410_WTCON_RSTEN) ? "en" : "dis",
636 (wtcon & S3C2410_WTCON_INTEN) ? "en" : "dis");
637
638 return 0;
639
640 err_unregister:
641 watchdog_unregister_device(&wdt->wdt_device);
642
643 err_cpufreq:
644 s3c2410wdt_cpufreq_deregister(wdt);
645
646 err_clk:
647 clk_disable_unprepare(wdt->clock);
648
649 err:
650 return ret;
651}
652
653static int s3c2410wdt_remove(struct platform_device *dev)
654{
655 int ret;
656 struct s3c2410_wdt *wdt = platform_get_drvdata(dev);
657
658 ret = s3c2410wdt_mask_and_disable_reset(wdt, true);
659 if (ret < 0)
660 return ret;
661
662 watchdog_unregister_device(&wdt->wdt_device);
663
664 s3c2410wdt_cpufreq_deregister(wdt);
665
666 clk_disable_unprepare(wdt->clock);
667
668 return 0;
669}
670
671static void s3c2410wdt_shutdown(struct platform_device *dev)
672{
673 struct s3c2410_wdt *wdt = platform_get_drvdata(dev);
674
675 s3c2410wdt_mask_and_disable_reset(wdt, true);
676
677 s3c2410wdt_stop(&wdt->wdt_device);
678}
679
680#ifdef CONFIG_PM_SLEEP
681
682static int s3c2410wdt_suspend(struct device *dev)
683{
684 int ret;
685 struct s3c2410_wdt *wdt = dev_get_drvdata(dev);
686
687 /* Save watchdog state, and turn it off. */
688 wdt->wtcon_save = readl(wdt->reg_base + S3C2410_WTCON);
689 wdt->wtdat_save = readl(wdt->reg_base + S3C2410_WTDAT);
690
691 ret = s3c2410wdt_mask_and_disable_reset(wdt, true);
692 if (ret < 0)
693 return ret;
694
695 /* Note that WTCNT doesn't need to be saved. */
696 s3c2410wdt_stop(&wdt->wdt_device);
697
698 return 0;
699}
700
701static int s3c2410wdt_resume(struct device *dev)
702{
703 int ret;
704 struct s3c2410_wdt *wdt = dev_get_drvdata(dev);
705
706 /* Restore watchdog state. */
707 writel(wdt->wtdat_save, wdt->reg_base + S3C2410_WTDAT);
708 writel(wdt->wtdat_save, wdt->reg_base + S3C2410_WTCNT);/* Reset count */
709 writel(wdt->wtcon_save, wdt->reg_base + S3C2410_WTCON);
710
711 ret = s3c2410wdt_mask_and_disable_reset(wdt, false);
712 if (ret < 0)
713 return ret;
714
715 dev_info(dev, "watchdog %sabled\n",
716 (wdt->wtcon_save & S3C2410_WTCON_ENABLE) ? "en" : "dis");
717
718 return 0;
719}
720#endif
721
722static SIMPLE_DEV_PM_OPS(s3c2410wdt_pm_ops, s3c2410wdt_suspend,
723 s3c2410wdt_resume);
724
725static struct platform_driver s3c2410wdt_driver = {
726 .probe = s3c2410wdt_probe,
727 .remove = s3c2410wdt_remove,
728 .shutdown = s3c2410wdt_shutdown,
729 .id_table = s3c2410_wdt_ids,
730 .driver = {
731 .name = "s3c2410-wdt",
732 .pm = &s3c2410wdt_pm_ops,
733 .of_match_table = of_match_ptr(s3c2410_wdt_match),
734 },
735};
736
737module_platform_driver(s3c2410wdt_driver);
738
739MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, Dimitry Andric <dimitry.andric@tomtom.com>");
740MODULE_DESCRIPTION("S3C2410 Watchdog Device Driver");
741MODULE_LICENSE("GPL");
1/*
2 * Copyright (c) 2004 Simtec Electronics
3 * Ben Dooks <ben@simtec.co.uk>
4 *
5 * S3C2410 Watchdog Timer Support
6 *
7 * Based on, softdog.c by Alan Cox,
8 * (c) Copyright 1996 Alan Cox <alan@lxorguk.ukuu.org.uk>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 */
20
21#include <linux/module.h>
22#include <linux/moduleparam.h>
23#include <linux/types.h>
24#include <linux/timer.h>
25#include <linux/watchdog.h>
26#include <linux/platform_device.h>
27#include <linux/interrupt.h>
28#include <linux/clk.h>
29#include <linux/uaccess.h>
30#include <linux/io.h>
31#include <linux/cpufreq.h>
32#include <linux/slab.h>
33#include <linux/err.h>
34#include <linux/of.h>
35#include <linux/of_device.h>
36#include <linux/mfd/syscon.h>
37#include <linux/regmap.h>
38#include <linux/delay.h>
39
40#define S3C2410_WTCON 0x00
41#define S3C2410_WTDAT 0x04
42#define S3C2410_WTCNT 0x08
43#define S3C2410_WTCLRINT 0x0c
44
45#define S3C2410_WTCNT_MAXCNT 0xffff
46
47#define S3C2410_WTCON_RSTEN (1 << 0)
48#define S3C2410_WTCON_INTEN (1 << 2)
49#define S3C2410_WTCON_ENABLE (1 << 5)
50
51#define S3C2410_WTCON_DIV16 (0 << 3)
52#define S3C2410_WTCON_DIV32 (1 << 3)
53#define S3C2410_WTCON_DIV64 (2 << 3)
54#define S3C2410_WTCON_DIV128 (3 << 3)
55
56#define S3C2410_WTCON_MAXDIV 0x80
57
58#define S3C2410_WTCON_PRESCALE(x) ((x) << 8)
59#define S3C2410_WTCON_PRESCALE_MASK (0xff << 8)
60#define S3C2410_WTCON_PRESCALE_MAX 0xff
61
62#define S3C2410_WATCHDOG_ATBOOT (0)
63#define S3C2410_WATCHDOG_DEFAULT_TIME (15)
64
65#define EXYNOS5_RST_STAT_REG_OFFSET 0x0404
66#define EXYNOS5_WDT_DISABLE_REG_OFFSET 0x0408
67#define EXYNOS5_WDT_MASK_RESET_REG_OFFSET 0x040c
68#define QUIRK_HAS_PMU_CONFIG (1 << 0)
69#define QUIRK_HAS_RST_STAT (1 << 1)
70#define QUIRK_HAS_WTCLRINT_REG (1 << 2)
71
72/* These quirks require that we have a PMU register map */
73#define QUIRKS_HAVE_PMUREG (QUIRK_HAS_PMU_CONFIG | \
74 QUIRK_HAS_RST_STAT)
75
76static bool nowayout = WATCHDOG_NOWAYOUT;
77static int tmr_margin;
78static int tmr_atboot = S3C2410_WATCHDOG_ATBOOT;
79static int soft_noboot;
80
81module_param(tmr_margin, int, 0);
82module_param(tmr_atboot, int, 0);
83module_param(nowayout, bool, 0);
84module_param(soft_noboot, int, 0);
85
86MODULE_PARM_DESC(tmr_margin, "Watchdog tmr_margin in seconds. (default="
87 __MODULE_STRING(S3C2410_WATCHDOG_DEFAULT_TIME) ")");
88MODULE_PARM_DESC(tmr_atboot,
89 "Watchdog is started at boot time if set to 1, default="
90 __MODULE_STRING(S3C2410_WATCHDOG_ATBOOT));
91MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
92 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
93MODULE_PARM_DESC(soft_noboot, "Watchdog action, set to 1 to ignore reboots, 0 to reboot (default 0)");
94
95/**
96 * struct s3c2410_wdt_variant - Per-variant config data
97 *
98 * @disable_reg: Offset in pmureg for the register that disables the watchdog
99 * timer reset functionality.
100 * @mask_reset_reg: Offset in pmureg for the register that masks the watchdog
101 * timer reset functionality.
102 * @mask_bit: Bit number for the watchdog timer in the disable register and the
103 * mask reset register.
104 * @rst_stat_reg: Offset in pmureg for the register that has the reset status.
105 * @rst_stat_bit: Bit number in the rst_stat register indicating a watchdog
106 * reset.
107 * @quirks: A bitfield of quirks.
108 */
109
110struct s3c2410_wdt_variant {
111 int disable_reg;
112 int mask_reset_reg;
113 int mask_bit;
114 int rst_stat_reg;
115 int rst_stat_bit;
116 u32 quirks;
117};
118
119struct s3c2410_wdt {
120 struct device *dev;
121 struct clk *clock;
122 void __iomem *reg_base;
123 unsigned int count;
124 spinlock_t lock;
125 unsigned long wtcon_save;
126 unsigned long wtdat_save;
127 struct watchdog_device wdt_device;
128 struct notifier_block freq_transition;
129 const struct s3c2410_wdt_variant *drv_data;
130 struct regmap *pmureg;
131};
132
133static const struct s3c2410_wdt_variant drv_data_s3c2410 = {
134 .quirks = 0
135};
136
137#ifdef CONFIG_OF
138static const struct s3c2410_wdt_variant drv_data_s3c6410 = {
139 .quirks = QUIRK_HAS_WTCLRINT_REG,
140};
141
142static const struct s3c2410_wdt_variant drv_data_exynos5250 = {
143 .disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET,
144 .mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET,
145 .mask_bit = 20,
146 .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
147 .rst_stat_bit = 20,
148 .quirks = QUIRK_HAS_PMU_CONFIG | QUIRK_HAS_RST_STAT \
149 | QUIRK_HAS_WTCLRINT_REG,
150};
151
152static const struct s3c2410_wdt_variant drv_data_exynos5420 = {
153 .disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET,
154 .mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET,
155 .mask_bit = 0,
156 .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
157 .rst_stat_bit = 9,
158 .quirks = QUIRK_HAS_PMU_CONFIG | QUIRK_HAS_RST_STAT \
159 | QUIRK_HAS_WTCLRINT_REG,
160};
161
162static const struct s3c2410_wdt_variant drv_data_exynos7 = {
163 .disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET,
164 .mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET,
165 .mask_bit = 23,
166 .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
167 .rst_stat_bit = 23, /* A57 WDTRESET */
168 .quirks = QUIRK_HAS_PMU_CONFIG | QUIRK_HAS_RST_STAT \
169 | QUIRK_HAS_WTCLRINT_REG,
170};
171
172static const struct of_device_id s3c2410_wdt_match[] = {
173 { .compatible = "samsung,s3c2410-wdt",
174 .data = &drv_data_s3c2410 },
175 { .compatible = "samsung,s3c6410-wdt",
176 .data = &drv_data_s3c6410 },
177 { .compatible = "samsung,exynos5250-wdt",
178 .data = &drv_data_exynos5250 },
179 { .compatible = "samsung,exynos5420-wdt",
180 .data = &drv_data_exynos5420 },
181 { .compatible = "samsung,exynos7-wdt",
182 .data = &drv_data_exynos7 },
183 {},
184};
185MODULE_DEVICE_TABLE(of, s3c2410_wdt_match);
186#endif
187
188static const struct platform_device_id s3c2410_wdt_ids[] = {
189 {
190 .name = "s3c2410-wdt",
191 .driver_data = (unsigned long)&drv_data_s3c2410,
192 },
193 {}
194};
195MODULE_DEVICE_TABLE(platform, s3c2410_wdt_ids);
196
197/* functions */
198
199static inline unsigned int s3c2410wdt_max_timeout(struct clk *clock)
200{
201 unsigned long freq = clk_get_rate(clock);
202
203 return S3C2410_WTCNT_MAXCNT / (freq / (S3C2410_WTCON_PRESCALE_MAX + 1)
204 / S3C2410_WTCON_MAXDIV);
205}
206
207static inline struct s3c2410_wdt *freq_to_wdt(struct notifier_block *nb)
208{
209 return container_of(nb, struct s3c2410_wdt, freq_transition);
210}
211
212static int s3c2410wdt_mask_and_disable_reset(struct s3c2410_wdt *wdt, bool mask)
213{
214 int ret;
215 u32 mask_val = 1 << wdt->drv_data->mask_bit;
216 u32 val = 0;
217
218 /* No need to do anything if no PMU CONFIG needed */
219 if (!(wdt->drv_data->quirks & QUIRK_HAS_PMU_CONFIG))
220 return 0;
221
222 if (mask)
223 val = mask_val;
224
225 ret = regmap_update_bits(wdt->pmureg,
226 wdt->drv_data->disable_reg,
227 mask_val, val);
228 if (ret < 0)
229 goto error;
230
231 ret = regmap_update_bits(wdt->pmureg,
232 wdt->drv_data->mask_reset_reg,
233 mask_val, val);
234 error:
235 if (ret < 0)
236 dev_err(wdt->dev, "failed to update reg(%d)\n", ret);
237
238 return ret;
239}
240
241static int s3c2410wdt_keepalive(struct watchdog_device *wdd)
242{
243 struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
244
245 spin_lock(&wdt->lock);
246 writel(wdt->count, wdt->reg_base + S3C2410_WTCNT);
247 spin_unlock(&wdt->lock);
248
249 return 0;
250}
251
252static void __s3c2410wdt_stop(struct s3c2410_wdt *wdt)
253{
254 unsigned long wtcon;
255
256 wtcon = readl(wdt->reg_base + S3C2410_WTCON);
257 wtcon &= ~(S3C2410_WTCON_ENABLE | S3C2410_WTCON_RSTEN);
258 writel(wtcon, wdt->reg_base + S3C2410_WTCON);
259}
260
261static int s3c2410wdt_stop(struct watchdog_device *wdd)
262{
263 struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
264
265 spin_lock(&wdt->lock);
266 __s3c2410wdt_stop(wdt);
267 spin_unlock(&wdt->lock);
268
269 return 0;
270}
271
272static int s3c2410wdt_start(struct watchdog_device *wdd)
273{
274 unsigned long wtcon;
275 struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
276
277 spin_lock(&wdt->lock);
278
279 __s3c2410wdt_stop(wdt);
280
281 wtcon = readl(wdt->reg_base + S3C2410_WTCON);
282 wtcon |= S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128;
283
284 if (soft_noboot) {
285 wtcon |= S3C2410_WTCON_INTEN;
286 wtcon &= ~S3C2410_WTCON_RSTEN;
287 } else {
288 wtcon &= ~S3C2410_WTCON_INTEN;
289 wtcon |= S3C2410_WTCON_RSTEN;
290 }
291
292 dev_dbg(wdt->dev, "Starting watchdog: count=0x%08x, wtcon=%08lx\n",
293 wdt->count, wtcon);
294
295 writel(wdt->count, wdt->reg_base + S3C2410_WTDAT);
296 writel(wdt->count, wdt->reg_base + S3C2410_WTCNT);
297 writel(wtcon, wdt->reg_base + S3C2410_WTCON);
298 spin_unlock(&wdt->lock);
299
300 return 0;
301}
302
303static inline int s3c2410wdt_is_running(struct s3c2410_wdt *wdt)
304{
305 return readl(wdt->reg_base + S3C2410_WTCON) & S3C2410_WTCON_ENABLE;
306}
307
308static int s3c2410wdt_set_heartbeat(struct watchdog_device *wdd,
309 unsigned int timeout)
310{
311 struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
312 unsigned long freq = clk_get_rate(wdt->clock);
313 unsigned int count;
314 unsigned int divisor = 1;
315 unsigned long wtcon;
316
317 if (timeout < 1)
318 return -EINVAL;
319
320 freq = DIV_ROUND_UP(freq, 128);
321 count = timeout * freq;
322
323 dev_dbg(wdt->dev, "Heartbeat: count=%d, timeout=%d, freq=%lu\n",
324 count, timeout, freq);
325
326 /* if the count is bigger than the watchdog register,
327 then work out what we need to do (and if) we can
328 actually make this value
329 */
330
331 if (count >= 0x10000) {
332 divisor = DIV_ROUND_UP(count, 0xffff);
333
334 if (divisor > 0x100) {
335 dev_err(wdt->dev, "timeout %d too big\n", timeout);
336 return -EINVAL;
337 }
338 }
339
340 dev_dbg(wdt->dev, "Heartbeat: timeout=%d, divisor=%d, count=%d (%08x)\n",
341 timeout, divisor, count, DIV_ROUND_UP(count, divisor));
342
343 count = DIV_ROUND_UP(count, divisor);
344 wdt->count = count;
345
346 /* update the pre-scaler */
347 wtcon = readl(wdt->reg_base + S3C2410_WTCON);
348 wtcon &= ~S3C2410_WTCON_PRESCALE_MASK;
349 wtcon |= S3C2410_WTCON_PRESCALE(divisor-1);
350
351 writel(count, wdt->reg_base + S3C2410_WTDAT);
352 writel(wtcon, wdt->reg_base + S3C2410_WTCON);
353
354 wdd->timeout = (count * divisor) / freq;
355
356 return 0;
357}
358
359static int s3c2410wdt_restart(struct watchdog_device *wdd, unsigned long action,
360 void *data)
361{
362 struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
363 void __iomem *wdt_base = wdt->reg_base;
364
365 /* disable watchdog, to be safe */
366 writel(0, wdt_base + S3C2410_WTCON);
367
368 /* put initial values into count and data */
369 writel(0x80, wdt_base + S3C2410_WTCNT);
370 writel(0x80, wdt_base + S3C2410_WTDAT);
371
372 /* set the watchdog to go and reset... */
373 writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV16 |
374 S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x20),
375 wdt_base + S3C2410_WTCON);
376
377 /* wait for reset to assert... */
378 mdelay(500);
379
380 return 0;
381}
382
383#define OPTIONS (WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE)
384
385static const struct watchdog_info s3c2410_wdt_ident = {
386 .options = OPTIONS,
387 .firmware_version = 0,
388 .identity = "S3C2410 Watchdog",
389};
390
391static const struct watchdog_ops s3c2410wdt_ops = {
392 .owner = THIS_MODULE,
393 .start = s3c2410wdt_start,
394 .stop = s3c2410wdt_stop,
395 .ping = s3c2410wdt_keepalive,
396 .set_timeout = s3c2410wdt_set_heartbeat,
397 .restart = s3c2410wdt_restart,
398};
399
400static const struct watchdog_device s3c2410_wdd = {
401 .info = &s3c2410_wdt_ident,
402 .ops = &s3c2410wdt_ops,
403 .timeout = S3C2410_WATCHDOG_DEFAULT_TIME,
404};
405
406/* interrupt handler code */
407
408static irqreturn_t s3c2410wdt_irq(int irqno, void *param)
409{
410 struct s3c2410_wdt *wdt = platform_get_drvdata(param);
411
412 dev_info(wdt->dev, "watchdog timer expired (irq)\n");
413
414 s3c2410wdt_keepalive(&wdt->wdt_device);
415
416 if (wdt->drv_data->quirks & QUIRK_HAS_WTCLRINT_REG)
417 writel(0x1, wdt->reg_base + S3C2410_WTCLRINT);
418
419 return IRQ_HANDLED;
420}
421
422#ifdef CONFIG_ARM_S3C24XX_CPUFREQ
423
424static int s3c2410wdt_cpufreq_transition(struct notifier_block *nb,
425 unsigned long val, void *data)
426{
427 int ret;
428 struct s3c2410_wdt *wdt = freq_to_wdt(nb);
429
430 if (!s3c2410wdt_is_running(wdt))
431 goto done;
432
433 if (val == CPUFREQ_PRECHANGE) {
434 /* To ensure that over the change we don't cause the
435 * watchdog to trigger, we perform an keep-alive if
436 * the watchdog is running.
437 */
438
439 s3c2410wdt_keepalive(&wdt->wdt_device);
440 } else if (val == CPUFREQ_POSTCHANGE) {
441 s3c2410wdt_stop(&wdt->wdt_device);
442
443 ret = s3c2410wdt_set_heartbeat(&wdt->wdt_device,
444 wdt->wdt_device.timeout);
445
446 if (ret >= 0)
447 s3c2410wdt_start(&wdt->wdt_device);
448 else
449 goto err;
450 }
451
452done:
453 return 0;
454
455 err:
456 dev_err(wdt->dev, "cannot set new value for timeout %d\n",
457 wdt->wdt_device.timeout);
458 return ret;
459}
460
461static inline int s3c2410wdt_cpufreq_register(struct s3c2410_wdt *wdt)
462{
463 wdt->freq_transition.notifier_call = s3c2410wdt_cpufreq_transition;
464
465 return cpufreq_register_notifier(&wdt->freq_transition,
466 CPUFREQ_TRANSITION_NOTIFIER);
467}
468
469static inline void s3c2410wdt_cpufreq_deregister(struct s3c2410_wdt *wdt)
470{
471 wdt->freq_transition.notifier_call = s3c2410wdt_cpufreq_transition;
472
473 cpufreq_unregister_notifier(&wdt->freq_transition,
474 CPUFREQ_TRANSITION_NOTIFIER);
475}
476
477#else
478
479static inline int s3c2410wdt_cpufreq_register(struct s3c2410_wdt *wdt)
480{
481 return 0;
482}
483
484static inline void s3c2410wdt_cpufreq_deregister(struct s3c2410_wdt *wdt)
485{
486}
487#endif
488
489static inline unsigned int s3c2410wdt_get_bootstatus(struct s3c2410_wdt *wdt)
490{
491 unsigned int rst_stat;
492 int ret;
493
494 if (!(wdt->drv_data->quirks & QUIRK_HAS_RST_STAT))
495 return 0;
496
497 ret = regmap_read(wdt->pmureg, wdt->drv_data->rst_stat_reg, &rst_stat);
498 if (ret)
499 dev_warn(wdt->dev, "Couldn't get RST_STAT register\n");
500 else if (rst_stat & BIT(wdt->drv_data->rst_stat_bit))
501 return WDIOF_CARDRESET;
502
503 return 0;
504}
505
506static inline const struct s3c2410_wdt_variant *
507s3c2410_get_wdt_drv_data(struct platform_device *pdev)
508{
509 const struct s3c2410_wdt_variant *variant;
510
511 variant = of_device_get_match_data(&pdev->dev);
512 if (!variant) {
513 /* Device matched by platform_device_id */
514 variant = (struct s3c2410_wdt_variant *)
515 platform_get_device_id(pdev)->driver_data;
516 }
517
518 return variant;
519}
520
521static int s3c2410wdt_probe(struct platform_device *pdev)
522{
523 struct device *dev = &pdev->dev;
524 struct s3c2410_wdt *wdt;
525 struct resource *wdt_mem;
526 struct resource *wdt_irq;
527 unsigned int wtcon;
528 int started = 0;
529 int ret;
530
531 wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
532 if (!wdt)
533 return -ENOMEM;
534
535 wdt->dev = dev;
536 spin_lock_init(&wdt->lock);
537 wdt->wdt_device = s3c2410_wdd;
538
539 wdt->drv_data = s3c2410_get_wdt_drv_data(pdev);
540 if (wdt->drv_data->quirks & QUIRKS_HAVE_PMUREG) {
541 wdt->pmureg = syscon_regmap_lookup_by_phandle(dev->of_node,
542 "samsung,syscon-phandle");
543 if (IS_ERR(wdt->pmureg)) {
544 dev_err(dev, "syscon regmap lookup failed.\n");
545 return PTR_ERR(wdt->pmureg);
546 }
547 }
548
549 wdt_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
550 if (wdt_irq == NULL) {
551 dev_err(dev, "no irq resource specified\n");
552 ret = -ENOENT;
553 goto err;
554 }
555
556 /* get the memory region for the watchdog timer */
557 wdt_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
558 wdt->reg_base = devm_ioremap_resource(dev, wdt_mem);
559 if (IS_ERR(wdt->reg_base)) {
560 ret = PTR_ERR(wdt->reg_base);
561 goto err;
562 }
563
564 wdt->clock = devm_clk_get(dev, "watchdog");
565 if (IS_ERR(wdt->clock)) {
566 dev_err(dev, "failed to find watchdog clock source\n");
567 ret = PTR_ERR(wdt->clock);
568 goto err;
569 }
570
571 ret = clk_prepare_enable(wdt->clock);
572 if (ret < 0) {
573 dev_err(dev, "failed to enable clock\n");
574 return ret;
575 }
576
577 wdt->wdt_device.min_timeout = 1;
578 wdt->wdt_device.max_timeout = s3c2410wdt_max_timeout(wdt->clock);
579
580 ret = s3c2410wdt_cpufreq_register(wdt);
581 if (ret < 0) {
582 dev_err(dev, "failed to register cpufreq\n");
583 goto err_clk;
584 }
585
586 watchdog_set_drvdata(&wdt->wdt_device, wdt);
587
588 /* see if we can actually set the requested timer margin, and if
589 * not, try the default value */
590
591 watchdog_init_timeout(&wdt->wdt_device, tmr_margin, dev);
592 ret = s3c2410wdt_set_heartbeat(&wdt->wdt_device,
593 wdt->wdt_device.timeout);
594 if (ret) {
595 started = s3c2410wdt_set_heartbeat(&wdt->wdt_device,
596 S3C2410_WATCHDOG_DEFAULT_TIME);
597
598 if (started == 0)
599 dev_info(dev,
600 "tmr_margin value out of range, default %d used\n",
601 S3C2410_WATCHDOG_DEFAULT_TIME);
602 else
603 dev_info(dev, "default timer value is out of range, cannot start\n");
604 }
605
606 ret = devm_request_irq(dev, wdt_irq->start, s3c2410wdt_irq, 0,
607 pdev->name, pdev);
608 if (ret != 0) {
609 dev_err(dev, "failed to install irq (%d)\n", ret);
610 goto err_cpufreq;
611 }
612
613 watchdog_set_nowayout(&wdt->wdt_device, nowayout);
614 watchdog_set_restart_priority(&wdt->wdt_device, 128);
615
616 wdt->wdt_device.bootstatus = s3c2410wdt_get_bootstatus(wdt);
617 wdt->wdt_device.parent = dev;
618
619 ret = watchdog_register_device(&wdt->wdt_device);
620 if (ret) {
621 dev_err(dev, "cannot register watchdog (%d)\n", ret);
622 goto err_cpufreq;
623 }
624
625 ret = s3c2410wdt_mask_and_disable_reset(wdt, false);
626 if (ret < 0)
627 goto err_unregister;
628
629 if (tmr_atboot && started == 0) {
630 dev_info(dev, "starting watchdog timer\n");
631 s3c2410wdt_start(&wdt->wdt_device);
632 } else if (!tmr_atboot) {
633 /* if we're not enabling the watchdog, then ensure it is
634 * disabled if it has been left running from the bootloader
635 * or other source */
636
637 s3c2410wdt_stop(&wdt->wdt_device);
638 }
639
640 platform_set_drvdata(pdev, wdt);
641
642 /* print out a statement of readiness */
643
644 wtcon = readl(wdt->reg_base + S3C2410_WTCON);
645
646 dev_info(dev, "watchdog %sactive, reset %sabled, irq %sabled\n",
647 (wtcon & S3C2410_WTCON_ENABLE) ? "" : "in",
648 (wtcon & S3C2410_WTCON_RSTEN) ? "en" : "dis",
649 (wtcon & S3C2410_WTCON_INTEN) ? "en" : "dis");
650
651 return 0;
652
653 err_unregister:
654 watchdog_unregister_device(&wdt->wdt_device);
655
656 err_cpufreq:
657 s3c2410wdt_cpufreq_deregister(wdt);
658
659 err_clk:
660 clk_disable_unprepare(wdt->clock);
661
662 err:
663 return ret;
664}
665
666static int s3c2410wdt_remove(struct platform_device *dev)
667{
668 int ret;
669 struct s3c2410_wdt *wdt = platform_get_drvdata(dev);
670
671 ret = s3c2410wdt_mask_and_disable_reset(wdt, true);
672 if (ret < 0)
673 return ret;
674
675 watchdog_unregister_device(&wdt->wdt_device);
676
677 s3c2410wdt_cpufreq_deregister(wdt);
678
679 clk_disable_unprepare(wdt->clock);
680
681 return 0;
682}
683
684static void s3c2410wdt_shutdown(struct platform_device *dev)
685{
686 struct s3c2410_wdt *wdt = platform_get_drvdata(dev);
687
688 s3c2410wdt_mask_and_disable_reset(wdt, true);
689
690 s3c2410wdt_stop(&wdt->wdt_device);
691}
692
693#ifdef CONFIG_PM_SLEEP
694
695static int s3c2410wdt_suspend(struct device *dev)
696{
697 int ret;
698 struct s3c2410_wdt *wdt = dev_get_drvdata(dev);
699
700 /* Save watchdog state, and turn it off. */
701 wdt->wtcon_save = readl(wdt->reg_base + S3C2410_WTCON);
702 wdt->wtdat_save = readl(wdt->reg_base + S3C2410_WTDAT);
703
704 ret = s3c2410wdt_mask_and_disable_reset(wdt, true);
705 if (ret < 0)
706 return ret;
707
708 /* Note that WTCNT doesn't need to be saved. */
709 s3c2410wdt_stop(&wdt->wdt_device);
710
711 return 0;
712}
713
714static int s3c2410wdt_resume(struct device *dev)
715{
716 int ret;
717 struct s3c2410_wdt *wdt = dev_get_drvdata(dev);
718
719 /* Restore watchdog state. */
720 writel(wdt->wtdat_save, wdt->reg_base + S3C2410_WTDAT);
721 writel(wdt->wtdat_save, wdt->reg_base + S3C2410_WTCNT);/* Reset count */
722 writel(wdt->wtcon_save, wdt->reg_base + S3C2410_WTCON);
723
724 ret = s3c2410wdt_mask_and_disable_reset(wdt, false);
725 if (ret < 0)
726 return ret;
727
728 dev_info(dev, "watchdog %sabled\n",
729 (wdt->wtcon_save & S3C2410_WTCON_ENABLE) ? "en" : "dis");
730
731 return 0;
732}
733#endif
734
735static SIMPLE_DEV_PM_OPS(s3c2410wdt_pm_ops, s3c2410wdt_suspend,
736 s3c2410wdt_resume);
737
738static struct platform_driver s3c2410wdt_driver = {
739 .probe = s3c2410wdt_probe,
740 .remove = s3c2410wdt_remove,
741 .shutdown = s3c2410wdt_shutdown,
742 .id_table = s3c2410_wdt_ids,
743 .driver = {
744 .name = "s3c2410-wdt",
745 .pm = &s3c2410wdt_pm_ops,
746 .of_match_table = of_match_ptr(s3c2410_wdt_match),
747 },
748};
749
750module_platform_driver(s3c2410wdt_driver);
751
752MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, Dimitry Andric <dimitry.andric@tomtom.com>");
753MODULE_DESCRIPTION("S3C2410 Watchdog Device Driver");
754MODULE_LICENSE("GPL");