1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Driver core for Samsung SoC onboard UARTs.
   4 *
   5 * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
   6 *	http://armlinux.simtec.co.uk/
   7 */
   8
   9/* Note on 2410 error handling
  10 *
  11 * The s3c2410 manual has a love/hate affair with the contents of the
  12 * UERSTAT register in the UART blocks, and keeps marking some of the
  13 * error bits as reserved. Having checked with the s3c2410x01,
  14 * it copes with BREAKs properly, so I am happy to ignore the RESERVED
  15 * feature from the latter versions of the manual.
  16 *
  17 * If it becomes aparrent that latter versions of the 2410 remove these
  18 * bits, then action will have to be taken to differentiate the versions
  19 * and change the policy on BREAK
  20 *
  21 * BJD, 04-Nov-2004
  22 */
  23
  24#include <linux/dmaengine.h>
  25#include <linux/dma-mapping.h>
  26#include <linux/slab.h>
  27#include <linux/module.h>
  28#include <linux/ioport.h>
  29#include <linux/io.h>
  30#include <linux/platform_device.h>
  31#include <linux/init.h>
  32#include <linux/sysrq.h>
  33#include <linux/console.h>
  34#include <linux/tty.h>
  35#include <linux/tty_flip.h>
  36#include <linux/serial_core.h>
  37#include <linux/serial.h>
  38#include <linux/serial_s3c.h>
  39#include <linux/delay.h>
  40#include <linux/clk.h>
  41#include <linux/cpufreq.h>
  42#include <linux/of.h>
  43#include <asm/irq.h>
  44
  45/* UART name and device definitions */
  46
  47#define S3C24XX_SERIAL_NAME	"ttySAC"
  48#define S3C24XX_SERIAL_MAJOR	204
  49#define S3C24XX_SERIAL_MINOR	64
  50
  51#define S3C24XX_TX_PIO			1
  52#define S3C24XX_TX_DMA			2
  53#define S3C24XX_RX_PIO			1
  54#define S3C24XX_RX_DMA			2
  55
  56/* flag to ignore all characters coming in */
  57#define RXSTAT_DUMMY_READ (0x10000000)
  58
  59struct s3c24xx_uart_info {
  60	char			*name;
  61	unsigned int		type;
  62	unsigned int		fifosize;
  63	unsigned long		rx_fifomask;
  64	unsigned long		rx_fifoshift;
  65	unsigned long		rx_fifofull;
  66	unsigned long		tx_fifomask;
  67	unsigned long		tx_fifoshift;
  68	unsigned long		tx_fifofull;
  69	unsigned int		def_clk_sel;
  70	unsigned long		num_clks;
  71	unsigned long		clksel_mask;
  72	unsigned long		clksel_shift;
  73
  74	/* uart port features */
  75
  76	unsigned int		has_divslot:1;
  77};
  78
  79struct s3c24xx_serial_drv_data {
  80	struct s3c24xx_uart_info	*info;
  81	struct s3c2410_uartcfg		*def_cfg;
  82	unsigned int			fifosize[CONFIG_SERIAL_SAMSUNG_UARTS];
  83};
  84
  85struct s3c24xx_uart_dma {
  86	unsigned int			rx_chan_id;
  87	unsigned int			tx_chan_id;
  88
  89	struct dma_slave_config		rx_conf;
  90	struct dma_slave_config		tx_conf;
  91
  92	struct dma_chan			*rx_chan;
  93	struct dma_chan			*tx_chan;
  94
  95	dma_addr_t			rx_addr;
  96	dma_addr_t			tx_addr;
  97
  98	dma_cookie_t			rx_cookie;
  99	dma_cookie_t			tx_cookie;
 100
 101	char				*rx_buf;
 102
 103	dma_addr_t			tx_transfer_addr;
 104
 105	size_t				rx_size;
 106	size_t				tx_size;
 107
 108	struct dma_async_tx_descriptor	*tx_desc;
 109	struct dma_async_tx_descriptor	*rx_desc;
 110
 111	int				tx_bytes_requested;
 112	int				rx_bytes_requested;
 113};
 114
 115struct s3c24xx_uart_port {
 116	unsigned char			rx_claimed;
 117	unsigned char			tx_claimed;
 118	unsigned char			rx_enabled;
 119	unsigned char			tx_enabled;
 120	unsigned int			pm_level;
 121	unsigned long			baudclk_rate;
 122	unsigned int			min_dma_size;
 123
 124	unsigned int			rx_irq;
 125	unsigned int			tx_irq;
 126
 127	unsigned int			tx_in_progress;
 128	unsigned int			tx_mode;
 129	unsigned int			rx_mode;
 130
 131	struct s3c24xx_uart_info	*info;
 132	struct clk			*clk;
 133	struct clk			*baudclk;
 134	struct uart_port		port;
 135	struct s3c24xx_serial_drv_data	*drv_data;
 136
 137	/* reference to platform data */
 138	struct s3c2410_uartcfg		*cfg;
 139
 140	struct s3c24xx_uart_dma		*dma;
 141
 142#ifdef CONFIG_ARM_S3C24XX_CPUFREQ
 143	struct notifier_block		freq_transition;
 144#endif
 145};
 146
 147/* conversion functions */
 148
 149#define s3c24xx_dev_to_port(__dev) dev_get_drvdata(__dev)
 150
 151/* register access controls */
 152
 153#define portaddr(port, reg) ((port)->membase + (reg))
 154#define portaddrl(port, reg) \
 155	((unsigned long *)(unsigned long)((port)->membase + (reg)))
 156
 157static u32 rd_reg(struct uart_port *port, u32 reg)
 158{
 159	switch (port->iotype) {
 160	case UPIO_MEM:
 161		return readb_relaxed(portaddr(port, reg));
 162	case UPIO_MEM32:
 163		return readl_relaxed(portaddr(port, reg));
 164	default:
 165		return 0;
 166	}
 167	return 0;
 168}
 169
 170#define rd_regl(port, reg) (readl_relaxed(portaddr(port, reg)))
 171
 172static void wr_reg(struct uart_port *port, u32 reg, u32 val)
 173{
 174	switch (port->iotype) {
 175	case UPIO_MEM:
 176		writeb_relaxed(val, portaddr(port, reg));
 177		break;
 178	case UPIO_MEM32:
 179		writel_relaxed(val, portaddr(port, reg));
 180		break;
 181	}
 182}
 183
 184#define wr_regl(port, reg, val) writel_relaxed(val, portaddr(port, reg))
 185
 186/* Byte-order aware bit setting/clearing functions. */
 187
 188static inline void s3c24xx_set_bit(struct uart_port *port, int idx,
 189				   unsigned int reg)
 190{
 191	unsigned long flags;
 192	u32 val;
 193
 194	local_irq_save(flags);
 195	val = rd_regl(port, reg);
 196	val |= (1 << idx);
 197	wr_regl(port, reg, val);
 198	local_irq_restore(flags);
 199}
 200
 201static inline void s3c24xx_clear_bit(struct uart_port *port, int idx,
 202				     unsigned int reg)
 203{
 204	unsigned long flags;
 205	u32 val;
 206
 207	local_irq_save(flags);
 208	val = rd_regl(port, reg);
 209	val &= ~(1 << idx);
 210	wr_regl(port, reg, val);
 211	local_irq_restore(flags);
 212}
 213
 214static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
 215{
 216	return container_of(port, struct s3c24xx_uart_port, port);
 217}
 218
 219/* translate a port to the device name */
 220
 221static inline const char *s3c24xx_serial_portname(struct uart_port *port)
 222{
 223	return to_platform_device(port->dev)->name;
 224}
 225
 226static int s3c24xx_serial_txempty_nofifo(struct uart_port *port)
 227{
 228	return rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE;
 229}
 230
 231/*
 232 * s3c64xx and later SoC's include the interrupt mask and status registers in
 233 * the controller itself, unlike the s3c24xx SoC's which have these registers
 234 * in the interrupt controller. Check if the port type is s3c64xx or higher.
 235 */
 236static int s3c24xx_serial_has_interrupt_mask(struct uart_port *port)
 237{
 238	return to_ourport(port)->info->type == PORT_S3C6400;
 239}
 240
 241static void s3c24xx_serial_rx_enable(struct uart_port *port)
 242{
 243	struct s3c24xx_uart_port *ourport = to_ourport(port);
 244	unsigned long flags;
 245	unsigned int ucon, ufcon;
 246	int count = 10000;
 247
 248	spin_lock_irqsave(&port->lock, flags);
 249
 250	while (--count && !s3c24xx_serial_txempty_nofifo(port))
 251		udelay(100);
 252
 253	ufcon = rd_regl(port, S3C2410_UFCON);
 254	ufcon |= S3C2410_UFCON_RESETRX;
 255	wr_regl(port, S3C2410_UFCON, ufcon);
 256
 257	ucon = rd_regl(port, S3C2410_UCON);
 258	ucon |= S3C2410_UCON_RXIRQMODE;
 259	wr_regl(port, S3C2410_UCON, ucon);
 260
 261	ourport->rx_enabled = 1;
 262	spin_unlock_irqrestore(&port->lock, flags);
 263}
 264
 265static void s3c24xx_serial_rx_disable(struct uart_port *port)
 266{
 267	struct s3c24xx_uart_port *ourport = to_ourport(port);
 268	unsigned long flags;
 269	unsigned int ucon;
 270
 271	spin_lock_irqsave(&port->lock, flags);
 272
 273	ucon = rd_regl(port, S3C2410_UCON);
 274	ucon &= ~S3C2410_UCON_RXIRQMODE;
 275	wr_regl(port, S3C2410_UCON, ucon);
 276
 277	ourport->rx_enabled = 0;
 278	spin_unlock_irqrestore(&port->lock, flags);
 279}
 280
 281static void s3c24xx_serial_stop_tx(struct uart_port *port)
 282{
 283	struct s3c24xx_uart_port *ourport = to_ourport(port);
 284	struct s3c24xx_uart_dma *dma = ourport->dma;
 285	struct circ_buf *xmit = &port->state->xmit;
 286	struct dma_tx_state state;
 287	int count;
 288
 289	if (!ourport->tx_enabled)
 290		return;
 291
 292	if (s3c24xx_serial_has_interrupt_mask(port))
 293		s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM);
 294	else
 295		disable_irq_nosync(ourport->tx_irq);
 296
 297	if (dma && dma->tx_chan && ourport->tx_in_progress == S3C24XX_TX_DMA) {
 298		dmaengine_pause(dma->tx_chan);
 299		dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
 300		dmaengine_terminate_all(dma->tx_chan);
 301		dma_sync_single_for_cpu(ourport->port.dev,
 302			dma->tx_transfer_addr, dma->tx_size, DMA_TO_DEVICE);
 303		async_tx_ack(dma->tx_desc);
 304		count = dma->tx_bytes_requested - state.residue;
 305		xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
 306		port->icount.tx += count;
 307	}
 308
 309	ourport->tx_enabled = 0;
 310	ourport->tx_in_progress = 0;
 311
 312	if (port->flags & UPF_CONS_FLOW)
 313		s3c24xx_serial_rx_enable(port);
 314
 315	ourport->tx_mode = 0;
 316}
 317
 318static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport);
 319
 320static void s3c24xx_serial_tx_dma_complete(void *args)
 321{
 322	struct s3c24xx_uart_port *ourport = args;
 323	struct uart_port *port = &ourport->port;
 324	struct circ_buf *xmit = &port->state->xmit;
 325	struct s3c24xx_uart_dma *dma = ourport->dma;
 326	struct dma_tx_state state;
 327	unsigned long flags;
 328	int count;
 329
 330	dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
 331	count = dma->tx_bytes_requested - state.residue;
 332	async_tx_ack(dma->tx_desc);
 333
 334	dma_sync_single_for_cpu(ourport->port.dev, dma->tx_transfer_addr,
 335				dma->tx_size, DMA_TO_DEVICE);
 336
 337	spin_lock_irqsave(&port->lock, flags);
 338
 339	xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
 340	port->icount.tx += count;
 341	ourport->tx_in_progress = 0;
 342
 343	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 344		uart_write_wakeup(port);
 345
 346	s3c24xx_serial_start_next_tx(ourport);
 347	spin_unlock_irqrestore(&port->lock, flags);
 348}
 349
 350static void enable_tx_dma(struct s3c24xx_uart_port *ourport)
 351{
 352	struct uart_port *port = &ourport->port;
 353	u32 ucon;
 354
 355	/* Mask Tx interrupt */
 356	if (s3c24xx_serial_has_interrupt_mask(port))
 357		s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM);
 358	else
 359		disable_irq_nosync(ourport->tx_irq);
 360
 361	/* Enable tx dma mode */
 362	ucon = rd_regl(port, S3C2410_UCON);
 363	ucon &= ~(S3C64XX_UCON_TXBURST_MASK | S3C64XX_UCON_TXMODE_MASK);
 364	ucon |= (dma_get_cache_alignment() >= 16) ?
 365		S3C64XX_UCON_TXBURST_16 : S3C64XX_UCON_TXBURST_1;
 366	ucon |= S3C64XX_UCON_TXMODE_DMA;
 367	wr_regl(port,  S3C2410_UCON, ucon);
 368
 369	ourport->tx_mode = S3C24XX_TX_DMA;
 370}
 371
 372static void enable_tx_pio(struct s3c24xx_uart_port *ourport)
 373{
 374	struct uart_port *port = &ourport->port;
 375	u32 ucon, ufcon;
 376
 377	/* Set ufcon txtrig */
 378	ourport->tx_in_progress = S3C24XX_TX_PIO;
 379	ufcon = rd_regl(port, S3C2410_UFCON);
 380	wr_regl(port,  S3C2410_UFCON, ufcon);
 381
 382	/* Enable tx pio mode */
 383	ucon = rd_regl(port, S3C2410_UCON);
 384	ucon &= ~(S3C64XX_UCON_TXMODE_MASK);
 385	ucon |= S3C64XX_UCON_TXMODE_CPU;
 386	wr_regl(port,  S3C2410_UCON, ucon);
 387
 388	/* Unmask Tx interrupt */
 389	if (s3c24xx_serial_has_interrupt_mask(port))
 390		s3c24xx_clear_bit(port, S3C64XX_UINTM_TXD,
 391				  S3C64XX_UINTM);
 392	else
 393		enable_irq(ourport->tx_irq);
 394
 395	ourport->tx_mode = S3C24XX_TX_PIO;
 396}
 397
 398static void s3c24xx_serial_start_tx_pio(struct s3c24xx_uart_port *ourport)
 399{
 400	if (ourport->tx_mode != S3C24XX_TX_PIO)
 401		enable_tx_pio(ourport);
 402}
 403
 404static int s3c24xx_serial_start_tx_dma(struct s3c24xx_uart_port *ourport,
 405				      unsigned int count)
 406{
 407	struct uart_port *port = &ourport->port;
 408	struct circ_buf *xmit = &port->state->xmit;
 409	struct s3c24xx_uart_dma *dma = ourport->dma;
 410
 411	if (ourport->tx_mode != S3C24XX_TX_DMA)
 412		enable_tx_dma(ourport);
 413
 414	dma->tx_size = count & ~(dma_get_cache_alignment() - 1);
 415	dma->tx_transfer_addr = dma->tx_addr + xmit->tail;
 416
 417	dma_sync_single_for_device(ourport->port.dev, dma->tx_transfer_addr,
 418				dma->tx_size, DMA_TO_DEVICE);
 419
 420	dma->tx_desc = dmaengine_prep_slave_single(dma->tx_chan,
 421				dma->tx_transfer_addr, dma->tx_size,
 422				DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
 423	if (!dma->tx_desc) {
 424		dev_err(ourport->port.dev, "Unable to get desc for Tx\n");
 425		return -EIO;
 426	}
 427
 428	dma->tx_desc->callback = s3c24xx_serial_tx_dma_complete;
 429	dma->tx_desc->callback_param = ourport;
 430	dma->tx_bytes_requested = dma->tx_size;
 431
 432	ourport->tx_in_progress = S3C24XX_TX_DMA;
 433	dma->tx_cookie = dmaengine_submit(dma->tx_desc);
 434	dma_async_issue_pending(dma->tx_chan);
 435	return 0;
 436}
 437
 438static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport)
 439{
 440	struct uart_port *port = &ourport->port;
 441	struct circ_buf *xmit = &port->state->xmit;
 442	unsigned long count;
 443
 444	/* Get data size up to the end of buffer */
 445	count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 446
 447	if (!count) {
 448		s3c24xx_serial_stop_tx(port);
 449		return;
 450	}
 451
 452	if (!ourport->dma || !ourport->dma->tx_chan ||
 453	    count < ourport->min_dma_size ||
 454	    xmit->tail & (dma_get_cache_alignment() - 1))
 455		s3c24xx_serial_start_tx_pio(ourport);
 456	else
 457		s3c24xx_serial_start_tx_dma(ourport, count);
 458}
 459
 460static void s3c24xx_serial_start_tx(struct uart_port *port)
 461{
 462	struct s3c24xx_uart_port *ourport = to_ourport(port);
 463	struct circ_buf *xmit = &port->state->xmit;
 464
 465	if (!ourport->tx_enabled) {
 466		if (port->flags & UPF_CONS_FLOW)
 467			s3c24xx_serial_rx_disable(port);
 468
 469		ourport->tx_enabled = 1;
 470		if (!ourport->dma || !ourport->dma->tx_chan)
 471			s3c24xx_serial_start_tx_pio(ourport);
 472	}
 473
 474	if (ourport->dma && ourport->dma->tx_chan) {
 475		if (!uart_circ_empty(xmit) && !ourport->tx_in_progress)
 476			s3c24xx_serial_start_next_tx(ourport);
 477	}
 478}
 479
 480static void s3c24xx_uart_copy_rx_to_tty(struct s3c24xx_uart_port *ourport,
 481		struct tty_port *tty, int count)
 482{
 483	struct s3c24xx_uart_dma *dma = ourport->dma;
 484	int copied;
 485
 486	if (!count)
 487		return;
 488
 489	dma_sync_single_for_cpu(ourport->port.dev, dma->rx_addr,
 490				dma->rx_size, DMA_FROM_DEVICE);
 491
 492	ourport->port.icount.rx += count;
 493	if (!tty) {
 494		dev_err(ourport->port.dev, "No tty port\n");
 495		return;
 496	}
 497	copied = tty_insert_flip_string(tty,
 498			((unsigned char *)(ourport->dma->rx_buf)), count);
 499	if (copied != count) {
 500		WARN_ON(1);
 501		dev_err(ourport->port.dev, "RxData copy to tty layer failed\n");
 502	}
 503}
 504
 505static void s3c24xx_serial_stop_rx(struct uart_port *port)
 506{
 507	struct s3c24xx_uart_port *ourport = to_ourport(port);
 508	struct s3c24xx_uart_dma *dma = ourport->dma;
 509	struct tty_port *t = &port->state->port;
 510	struct dma_tx_state state;
 511	enum dma_status dma_status;
 512	unsigned int received;
 513
 514	if (ourport->rx_enabled) {
 515		dev_dbg(port->dev, "stopping rx\n");
 516		if (s3c24xx_serial_has_interrupt_mask(port))
 517			s3c24xx_set_bit(port, S3C64XX_UINTM_RXD,
 518					S3C64XX_UINTM);
 519		else
 520			disable_irq_nosync(ourport->rx_irq);
 521		ourport->rx_enabled = 0;
 522	}
 523	if (dma && dma->rx_chan) {
 524		dmaengine_pause(dma->tx_chan);
 525		dma_status = dmaengine_tx_status(dma->rx_chan,
 526				dma->rx_cookie, &state);
 527		if (dma_status == DMA_IN_PROGRESS ||
 528			dma_status == DMA_PAUSED) {
 529			received = dma->rx_bytes_requested - state.residue;
 530			dmaengine_terminate_all(dma->rx_chan);
 531			s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
 532		}
 533	}
 534}
 535
 536static inline struct s3c24xx_uart_info
 537	*s3c24xx_port_to_info(struct uart_port *port)
 538{
 539	return to_ourport(port)->info;
 540}
 541
 542static inline struct s3c2410_uartcfg
 543	*s3c24xx_port_to_cfg(struct uart_port *port)
 544{
 545	struct s3c24xx_uart_port *ourport;
 546
 547	if (port->dev == NULL)
 548		return NULL;
 549
 550	ourport = container_of(port, struct s3c24xx_uart_port, port);
 551	return ourport->cfg;
 552}
 553
 554static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
 555				     unsigned long ufstat)
 556{
 557	struct s3c24xx_uart_info *info = ourport->info;
 558
 559	if (ufstat & info->rx_fifofull)
 560		return ourport->port.fifosize;
 561
 562	return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
 563}
 564
 565static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport);
 566static void s3c24xx_serial_rx_dma_complete(void *args)
 567{
 568	struct s3c24xx_uart_port *ourport = args;
 569	struct uart_port *port = &ourport->port;
 570
 571	struct s3c24xx_uart_dma *dma = ourport->dma;
 572	struct tty_port *t = &port->state->port;
 573	struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
 574
 575	struct dma_tx_state state;
 576	unsigned long flags;
 577	int received;
 578
 579	dmaengine_tx_status(dma->rx_chan,  dma->rx_cookie, &state);
 580	received  = dma->rx_bytes_requested - state.residue;
 581	async_tx_ack(dma->rx_desc);
 582
 583	spin_lock_irqsave(&port->lock, flags);
 584
 585	if (received)
 586		s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
 587
 588	if (tty) {
 589		tty_flip_buffer_push(t);
 590		tty_kref_put(tty);
 591	}
 592
 593	s3c64xx_start_rx_dma(ourport);
 594
 595	spin_unlock_irqrestore(&port->lock, flags);
 596}
 597
 598static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport)
 599{
 600	struct s3c24xx_uart_dma *dma = ourport->dma;
 601
 602	dma_sync_single_for_device(ourport->port.dev, dma->rx_addr,
 603				dma->rx_size, DMA_FROM_DEVICE);
 604
 605	dma->rx_desc = dmaengine_prep_slave_single(dma->rx_chan,
 606				dma->rx_addr, dma->rx_size, DMA_DEV_TO_MEM,
 607				DMA_PREP_INTERRUPT);
 608	if (!dma->rx_desc) {
 609		dev_err(ourport->port.dev, "Unable to get desc for Rx\n");
 610		return;
 611	}
 612
 613	dma->rx_desc->callback = s3c24xx_serial_rx_dma_complete;
 614	dma->rx_desc->callback_param = ourport;
 615	dma->rx_bytes_requested = dma->rx_size;
 616
 617	dma->rx_cookie = dmaengine_submit(dma->rx_desc);
 618	dma_async_issue_pending(dma->rx_chan);
 619}
 620
 621/* ? - where has parity gone?? */
 622#define S3C2410_UERSTAT_PARITY (0x1000)
 623
 624static void enable_rx_dma(struct s3c24xx_uart_port *ourport)
 625{
 626	struct uart_port *port = &ourport->port;
 627	unsigned int ucon;
 628
 629	/* set Rx mode to DMA mode */
 630	ucon = rd_regl(port, S3C2410_UCON);
 631	ucon &= ~(S3C64XX_UCON_RXBURST_MASK |
 632			S3C64XX_UCON_TIMEOUT_MASK |
 633			S3C64XX_UCON_EMPTYINT_EN |
 634			S3C64XX_UCON_DMASUS_EN |
 635			S3C64XX_UCON_TIMEOUT_EN |
 636			S3C64XX_UCON_RXMODE_MASK);
 637	ucon |= S3C64XX_UCON_RXBURST_16 |
 638			0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
 639			S3C64XX_UCON_EMPTYINT_EN |
 640			S3C64XX_UCON_TIMEOUT_EN |
 641			S3C64XX_UCON_RXMODE_DMA;
 642	wr_regl(port, S3C2410_UCON, ucon);
 643
 644	ourport->rx_mode = S3C24XX_RX_DMA;
 645}
 646
 647static void enable_rx_pio(struct s3c24xx_uart_port *ourport)
 648{
 649	struct uart_port *port = &ourport->port;
 650	unsigned int ucon;
 651
 652	/* set Rx mode to DMA mode */
 653	ucon = rd_regl(port, S3C2410_UCON);
 654	ucon &= ~(S3C64XX_UCON_TIMEOUT_MASK |
 655			S3C64XX_UCON_EMPTYINT_EN |
 656			S3C64XX_UCON_DMASUS_EN |
 657			S3C64XX_UCON_TIMEOUT_EN |
 658			S3C64XX_UCON_RXMODE_MASK);
 659	ucon |= 0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
 660			S3C64XX_UCON_TIMEOUT_EN |
 661			S3C64XX_UCON_RXMODE_CPU;
 662	wr_regl(port, S3C2410_UCON, ucon);
 663
 664	ourport->rx_mode = S3C24XX_RX_PIO;
 665}
 666
 667static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport);
 668
 669static irqreturn_t s3c24xx_serial_rx_chars_dma(void *dev_id)
 670{
 671	unsigned int utrstat, received;
 672	struct s3c24xx_uart_port *ourport = dev_id;
 673	struct uart_port *port = &ourport->port;
 674	struct s3c24xx_uart_dma *dma = ourport->dma;
 675	struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
 676	struct tty_port *t = &port->state->port;
 677	unsigned long flags;
 678	struct dma_tx_state state;
 679
 680	utrstat = rd_regl(port, S3C2410_UTRSTAT);
 681	rd_regl(port, S3C2410_UFSTAT);
 682
 683	spin_lock_irqsave(&port->lock, flags);
 684
 685	if (!(utrstat & S3C2410_UTRSTAT_TIMEOUT)) {
 686		s3c64xx_start_rx_dma(ourport);
 687		if (ourport->rx_mode == S3C24XX_RX_PIO)
 688			enable_rx_dma(ourport);
 689		goto finish;
 690	}
 691
 692	if (ourport->rx_mode == S3C24XX_RX_DMA) {
 693		dmaengine_pause(dma->rx_chan);
 694		dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state);
 695		dmaengine_terminate_all(dma->rx_chan);
 696		received = dma->rx_bytes_requested - state.residue;
 697		s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
 698
 699		enable_rx_pio(ourport);
 700	}
 701
 702	s3c24xx_serial_rx_drain_fifo(ourport);
 703
 704	if (tty) {
 705		tty_flip_buffer_push(t);
 706		tty_kref_put(tty);
 707	}
 708
 709	wr_regl(port, S3C2410_UTRSTAT, S3C2410_UTRSTAT_TIMEOUT);
 710
 711finish:
 712	spin_unlock_irqrestore(&port->lock, flags);
 713
 714	return IRQ_HANDLED;
 715}
 716
 717static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport)
 718{
 719	struct uart_port *port = &ourport->port;
 720	unsigned int ufcon, ch, flag, ufstat, uerstat;
 721	unsigned int fifocnt = 0;
 722	int max_count = port->fifosize;
 723
 724	while (max_count-- > 0) {
 725		/*
 726		 * Receive all characters known to be in FIFO
 727		 * before reading FIFO level again
 728		 */
 729		if (fifocnt == 0) {
 730			ufstat = rd_regl(port, S3C2410_UFSTAT);
 731			fifocnt = s3c24xx_serial_rx_fifocnt(ourport, ufstat);
 732			if (fifocnt == 0)
 733				break;
 734		}
 735		fifocnt--;
 736
 737		uerstat = rd_regl(port, S3C2410_UERSTAT);
 738		ch = rd_reg(port, S3C2410_URXH);
 739
 740		if (port->flags & UPF_CONS_FLOW) {
 741			int txe = s3c24xx_serial_txempty_nofifo(port);
 742
 743			if (ourport->rx_enabled) {
 744				if (!txe) {
 745					ourport->rx_enabled = 0;
 746					continue;
 747				}
 748			} else {
 749				if (txe) {
 750					ufcon = rd_regl(port, S3C2410_UFCON);
 751					ufcon |= S3C2410_UFCON_RESETRX;
 752					wr_regl(port, S3C2410_UFCON, ufcon);
 753					ourport->rx_enabled = 1;
 754					return;
 755				}
 756				continue;
 757			}
 758		}
 759
 760		/* insert the character into the buffer */
 761
 762		flag = TTY_NORMAL;
 763		port->icount.rx++;
 764
 765		if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
 766			dev_dbg(port->dev,
 767				"rxerr: port ch=0x%02x, rxs=0x%08x\n",
 768				ch, uerstat);
 769
 770			/* check for break */
 771			if (uerstat & S3C2410_UERSTAT_BREAK) {
 772				dev_dbg(port->dev, "break!\n");
 773				port->icount.brk++;
 774				if (uart_handle_break(port))
 775					continue; /* Ignore character */
 776			}
 777
 778			if (uerstat & S3C2410_UERSTAT_FRAME)
 779				port->icount.frame++;
 780			if (uerstat & S3C2410_UERSTAT_OVERRUN)
 781				port->icount.overrun++;
 782
 783			uerstat &= port->read_status_mask;
 784
 785			if (uerstat & S3C2410_UERSTAT_BREAK)
 786				flag = TTY_BREAK;
 787			else if (uerstat & S3C2410_UERSTAT_PARITY)
 788				flag = TTY_PARITY;
 789			else if (uerstat & (S3C2410_UERSTAT_FRAME |
 790					    S3C2410_UERSTAT_OVERRUN))
 791				flag = TTY_FRAME;
 792		}
 793
 794		if (uart_handle_sysrq_char(port, ch))
 795			continue; /* Ignore character */
 796
 797		uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN,
 798				 ch, flag);
 799	}
 800
 801	tty_flip_buffer_push(&port->state->port);
 802}
 803
 804static irqreturn_t s3c24xx_serial_rx_chars_pio(void *dev_id)
 805{
 806	struct s3c24xx_uart_port *ourport = dev_id;
 807	struct uart_port *port = &ourport->port;
 808	unsigned long flags;
 809
 810	spin_lock_irqsave(&port->lock, flags);
 811	s3c24xx_serial_rx_drain_fifo(ourport);
 812	spin_unlock_irqrestore(&port->lock, flags);
 813
 814	return IRQ_HANDLED;
 815}
 816
 817static irqreturn_t s3c24xx_serial_rx_chars(int irq, void *dev_id)
 818{
 819	struct s3c24xx_uart_port *ourport = dev_id;
 820
 821	if (ourport->dma && ourport->dma->rx_chan)
 822		return s3c24xx_serial_rx_chars_dma(dev_id);
 823	return s3c24xx_serial_rx_chars_pio(dev_id);
 824}
 825
 826static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id)
 827{
 828	struct s3c24xx_uart_port *ourport = id;
 829	struct uart_port *port = &ourport->port;
 830	struct circ_buf *xmit = &port->state->xmit;
 831	unsigned long flags;
 832	int count, dma_count = 0;
 833
 834	spin_lock_irqsave(&port->lock, flags);
 835
 836	count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 837
 838	if (ourport->dma && ourport->dma->tx_chan &&
 839	    count >= ourport->min_dma_size) {
 840		int align = dma_get_cache_alignment() -
 841			(xmit->tail & (dma_get_cache_alignment() - 1));
 842		if (count - align >= ourport->min_dma_size) {
 843			dma_count = count - align;
 844			count = align;
 845		}
 846	}
 847
 848	if (port->x_char) {
 849		wr_reg(port, S3C2410_UTXH, port->x_char);
 850		port->icount.tx++;
 851		port->x_char = 0;
 852		goto out;
 853	}
 854
 855	/* if there isn't anything more to transmit, or the uart is now
 856	 * stopped, disable the uart and exit
 857	 */
 858
 859	if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
 860		s3c24xx_serial_stop_tx(port);
 861		goto out;
 862	}
 863
 864	/* try and drain the buffer... */
 865
 866	if (count > port->fifosize) {
 867		count = port->fifosize;
 868		dma_count = 0;
 869	}
 870
 871	while (!uart_circ_empty(xmit) && count > 0) {
 872		if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
 873			break;
 874
 875		wr_reg(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
 876		xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 877		port->icount.tx++;
 878		count--;
 879	}
 880
 881	if (!count && dma_count) {
 882		s3c24xx_serial_start_tx_dma(ourport, dma_count);
 883		goto out;
 884	}
 885
 886	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) {
 887		spin_unlock(&port->lock);
 888		uart_write_wakeup(port);
 889		spin_lock(&port->lock);
 890	}
 891
 892	if (uart_circ_empty(xmit))
 893		s3c24xx_serial_stop_tx(port);
 894
 895out:
 896	spin_unlock_irqrestore(&port->lock, flags);
 897	return IRQ_HANDLED;
 898}
 899
 900/* interrupt handler for s3c64xx and later SoC's.*/
 901static irqreturn_t s3c64xx_serial_handle_irq(int irq, void *id)
 902{
 903	struct s3c24xx_uart_port *ourport = id;
 904	struct uart_port *port = &ourport->port;
 905	unsigned int pend = rd_regl(port, S3C64XX_UINTP);
 906	irqreturn_t ret = IRQ_HANDLED;
 907
 908	if (pend & S3C64XX_UINTM_RXD_MSK) {
 909		ret = s3c24xx_serial_rx_chars(irq, id);
 910		wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_RXD_MSK);
 911	}
 912	if (pend & S3C64XX_UINTM_TXD_MSK) {
 913		ret = s3c24xx_serial_tx_chars(irq, id);
 914		wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_TXD_MSK);
 915	}
 916	return ret;
 917}
 918
 919static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
 920{
 921	struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
 922	unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT);
 923	unsigned long ufcon = rd_regl(port, S3C2410_UFCON);
 924
 925	if (ufcon & S3C2410_UFCON_FIFOMODE) {
 926		if ((ufstat & info->tx_fifomask) != 0 ||
 927		    (ufstat & info->tx_fifofull))
 928			return 0;
 929
 930		return 1;
 931	}
 932
 933	return s3c24xx_serial_txempty_nofifo(port);
 934}
 935
 936/* no modem control lines */
 937static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
 938{
 939	unsigned int umstat = rd_reg(port, S3C2410_UMSTAT);
 940
 941	if (umstat & S3C2410_UMSTAT_CTS)
 942		return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
 943	else
 944		return TIOCM_CAR | TIOCM_DSR;
 945}
 946
 947static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
 948{
 949	unsigned int umcon = rd_regl(port, S3C2410_UMCON);
 950
 951	if (mctrl & TIOCM_RTS)
 952		umcon |= S3C2410_UMCOM_RTS_LOW;
 953	else
 954		umcon &= ~S3C2410_UMCOM_RTS_LOW;
 955
 956	wr_regl(port, S3C2410_UMCON, umcon);
 957}
 958
 959static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
 960{
 961	unsigned long flags;
 962	unsigned int ucon;
 963
 964	spin_lock_irqsave(&port->lock, flags);
 965
 966	ucon = rd_regl(port, S3C2410_UCON);
 967
 968	if (break_state)
 969		ucon |= S3C2410_UCON_SBREAK;
 970	else
 971		ucon &= ~S3C2410_UCON_SBREAK;
 972
 973	wr_regl(port, S3C2410_UCON, ucon);
 974
 975	spin_unlock_irqrestore(&port->lock, flags);
 976}
 977
 978static int s3c24xx_serial_request_dma(struct s3c24xx_uart_port *p)
 979{
 980	struct s3c24xx_uart_dma	*dma = p->dma;
 981	struct dma_slave_caps dma_caps;
 982	const char *reason = NULL;
 983	int ret;
 984
 985	/* Default slave configuration parameters */
 986	dma->rx_conf.direction		= DMA_DEV_TO_MEM;
 987	dma->rx_conf.src_addr_width	= DMA_SLAVE_BUSWIDTH_1_BYTE;
 988	dma->rx_conf.src_addr		= p->port.mapbase + S3C2410_URXH;
 989	dma->rx_conf.src_maxburst	= 1;
 990
 991	dma->tx_conf.direction		= DMA_MEM_TO_DEV;
 992	dma->tx_conf.dst_addr_width	= DMA_SLAVE_BUSWIDTH_1_BYTE;
 993	dma->tx_conf.dst_addr		= p->port.mapbase + S3C2410_UTXH;
 994	dma->tx_conf.dst_maxburst	= 1;
 995
 996	dma->rx_chan = dma_request_chan(p->port.dev, "rx");
 997
 998	if (IS_ERR(dma->rx_chan)) {
 999		reason = "DMA RX channel request failed";
1000		ret = PTR_ERR(dma->rx_chan);
1001		goto err_warn;
1002	}
1003
1004	ret = dma_get_slave_caps(dma->rx_chan, &dma_caps);
1005	if (ret < 0 ||
1006	    dma_caps.residue_granularity < DMA_RESIDUE_GRANULARITY_BURST) {
1007		reason = "insufficient DMA RX engine capabilities";
1008		ret = -EOPNOTSUPP;
1009		goto err_release_rx;
1010	}
1011
1012	dmaengine_slave_config(dma->rx_chan, &dma->rx_conf);
1013
1014	dma->tx_chan = dma_request_chan(p->port.dev, "tx");
1015	if (IS_ERR(dma->tx_chan)) {
1016		reason = "DMA TX channel request failed";
1017		ret = PTR_ERR(dma->tx_chan);
1018		goto err_release_rx;
1019	}
1020
1021	ret = dma_get_slave_caps(dma->tx_chan, &dma_caps);
1022	if (ret < 0 ||
1023	    dma_caps.residue_granularity < DMA_RESIDUE_GRANULARITY_BURST) {
1024		reason = "insufficient DMA TX engine capabilities";
1025		ret = -EOPNOTSUPP;
1026		goto err_release_tx;
1027	}
1028
1029	dmaengine_slave_config(dma->tx_chan, &dma->tx_conf);
1030
1031	/* RX buffer */
1032	dma->rx_size = PAGE_SIZE;
1033
1034	dma->rx_buf = kmalloc(dma->rx_size, GFP_KERNEL);
1035	if (!dma->rx_buf) {
1036		ret = -ENOMEM;
1037		goto err_release_tx;
1038	}
1039
1040	dma->rx_addr = dma_map_single(p->port.dev, dma->rx_buf,
1041				dma->rx_size, DMA_FROM_DEVICE);
1042	if (dma_mapping_error(p->port.dev, dma->rx_addr)) {
1043		reason = "DMA mapping error for RX buffer";
1044		ret = -EIO;
1045		goto err_free_rx;
1046	}
1047
1048	/* TX buffer */
1049	dma->tx_addr = dma_map_single(p->port.dev, p->port.state->xmit.buf,
1050				UART_XMIT_SIZE, DMA_TO_DEVICE);
1051	if (dma_mapping_error(p->port.dev, dma->tx_addr)) {
1052		reason = "DMA mapping error for TX buffer";
1053		ret = -EIO;
1054		goto err_unmap_rx;
1055	}
1056
1057	return 0;
1058
1059err_unmap_rx:
1060	dma_unmap_single(p->port.dev, dma->rx_addr, dma->rx_size,
1061			 DMA_FROM_DEVICE);
1062err_free_rx:
1063	kfree(dma->rx_buf);
1064err_release_tx:
1065	dma_release_channel(dma->tx_chan);
1066err_release_rx:
1067	dma_release_channel(dma->rx_chan);
1068err_warn:
1069	if (reason)
1070		dev_warn(p->port.dev, "%s, DMA will not be used\n", reason);
1071	return ret;
1072}
1073
1074static void s3c24xx_serial_release_dma(struct s3c24xx_uart_port *p)
1075{
1076	struct s3c24xx_uart_dma	*dma = p->dma;
1077
1078	if (dma->rx_chan) {
1079		dmaengine_terminate_all(dma->rx_chan);
1080		dma_unmap_single(p->port.dev, dma->rx_addr,
1081				dma->rx_size, DMA_FROM_DEVICE);
1082		kfree(dma->rx_buf);
1083		dma_release_channel(dma->rx_chan);
1084		dma->rx_chan = NULL;
1085	}
1086
1087	if (dma->tx_chan) {
1088		dmaengine_terminate_all(dma->tx_chan);
1089		dma_unmap_single(p->port.dev, dma->tx_addr,
1090				UART_XMIT_SIZE, DMA_TO_DEVICE);
1091		dma_release_channel(dma->tx_chan);
1092		dma->tx_chan = NULL;
1093	}
1094}
1095
1096static void s3c24xx_serial_shutdown(struct uart_port *port)
1097{
1098	struct s3c24xx_uart_port *ourport = to_ourport(port);
1099
1100	if (ourport->tx_claimed) {
1101		if (!s3c24xx_serial_has_interrupt_mask(port))
1102			free_irq(ourport->tx_irq, ourport);
1103		ourport->tx_enabled = 0;
1104		ourport->tx_claimed = 0;
1105		ourport->tx_mode = 0;
1106	}
1107
1108	if (ourport->rx_claimed) {
1109		if (!s3c24xx_serial_has_interrupt_mask(port))
1110			free_irq(ourport->rx_irq, ourport);
1111		ourport->rx_claimed = 0;
1112		ourport->rx_enabled = 0;
1113	}
1114
1115	/* Clear pending interrupts and mask all interrupts */
1116	if (s3c24xx_serial_has_interrupt_mask(port)) {
1117		free_irq(port->irq, ourport);
1118
1119		wr_regl(port, S3C64XX_UINTP, 0xf);
1120		wr_regl(port, S3C64XX_UINTM, 0xf);
1121	}
1122
1123	if (ourport->dma)
1124		s3c24xx_serial_release_dma(ourport);
1125
1126	ourport->tx_in_progress = 0;
1127}
1128
1129static int s3c24xx_serial_startup(struct uart_port *port)
1130{
1131	struct s3c24xx_uart_port *ourport = to_ourport(port);
1132	int ret;
1133
1134	ourport->rx_enabled = 1;
1135
1136	ret = request_irq(ourport->rx_irq, s3c24xx_serial_rx_chars, 0,
1137			  s3c24xx_serial_portname(port), ourport);
1138
1139	if (ret != 0) {
1140		dev_err(port->dev, "cannot get irq %d\n", ourport->rx_irq);
1141		return ret;
1142	}
1143
1144	ourport->rx_claimed = 1;
1145
1146	dev_dbg(port->dev, "requesting tx irq...\n");
1147
1148	ourport->tx_enabled = 1;
1149
1150	ret = request_irq(ourport->tx_irq, s3c24xx_serial_tx_chars, 0,
1151			  s3c24xx_serial_portname(port), ourport);
1152
1153	if (ret) {
1154		dev_err(port->dev, "cannot get irq %d\n", ourport->tx_irq);
1155		goto err;
1156	}
1157
1158	ourport->tx_claimed = 1;
1159
1160	/* the port reset code should have done the correct
1161	 * register setup for the port controls
1162	 */
1163
1164	return ret;
1165
1166err:
1167	s3c24xx_serial_shutdown(port);
1168	return ret;
1169}
1170
1171static int s3c64xx_serial_startup(struct uart_port *port)
1172{
1173	struct s3c24xx_uart_port *ourport = to_ourport(port);
1174	unsigned long flags;
1175	unsigned int ufcon;
1176	int ret;
1177
1178	wr_regl(port, S3C64XX_UINTM, 0xf);
1179	if (ourport->dma) {
1180		ret = s3c24xx_serial_request_dma(ourport);
1181		if (ret < 0) {
1182			devm_kfree(port->dev, ourport->dma);
1183			ourport->dma = NULL;
1184		}
1185	}
1186
1187	ret = request_irq(port->irq, s3c64xx_serial_handle_irq, IRQF_SHARED,
1188			  s3c24xx_serial_portname(port), ourport);
1189	if (ret) {
1190		dev_err(port->dev, "cannot get irq %d\n", port->irq);
1191		return ret;
1192	}
1193
1194	/* For compatibility with s3c24xx Soc's */
1195	ourport->rx_enabled = 1;
1196	ourport->rx_claimed = 1;
1197	ourport->tx_enabled = 0;
1198	ourport->tx_claimed = 1;
1199
1200	spin_lock_irqsave(&port->lock, flags);
1201
1202	ufcon = rd_regl(port, S3C2410_UFCON);
1203	ufcon |= S3C2410_UFCON_RESETRX | S5PV210_UFCON_RXTRIG8;
1204	if (!uart_console(port))
1205		ufcon |= S3C2410_UFCON_RESETTX;
1206	wr_regl(port, S3C2410_UFCON, ufcon);
1207
1208	enable_rx_pio(ourport);
1209
1210	spin_unlock_irqrestore(&port->lock, flags);
1211
1212	/* Enable Rx Interrupt */
1213	s3c24xx_clear_bit(port, S3C64XX_UINTM_RXD, S3C64XX_UINTM);
1214
1215	return ret;
1216}
1217
1218/* power power management control */
1219
1220static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
1221			      unsigned int old)
1222{
1223	struct s3c24xx_uart_port *ourport = to_ourport(port);
1224	int timeout = 10000;
1225
1226	ourport->pm_level = level;
1227
1228	switch (level) {
1229	case 3:
1230		while (--timeout && !s3c24xx_serial_txempty_nofifo(port))
1231			udelay(100);
1232
1233		if (!IS_ERR(ourport->baudclk))
1234			clk_disable_unprepare(ourport->baudclk);
1235
1236		clk_disable_unprepare(ourport->clk);
1237		break;
1238
1239	case 0:
1240		clk_prepare_enable(ourport->clk);
1241
1242		if (!IS_ERR(ourport->baudclk))
1243			clk_prepare_enable(ourport->baudclk);
1244
1245		break;
1246	default:
1247		dev_err(port->dev, "s3c24xx_serial: unknown pm %d\n", level);
1248	}
1249}
1250
1251/* baud rate calculation
1252 *
1253 * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
1254 * of different sources, including the peripheral clock ("pclk") and an
1255 * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
1256 * with a programmable extra divisor.
1257 *
1258 * The following code goes through the clock sources, and calculates the
1259 * baud clocks (and the resultant actual baud rates) and then tries to
1260 * pick the closest one and select that.
1261 *
1262 */
1263
1264#define MAX_CLK_NAME_LENGTH 15
1265
1266static inline int s3c24xx_serial_getsource(struct uart_port *port)
1267{
1268	struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1269	unsigned int ucon;
1270
1271	if (info->num_clks == 1)
1272		return 0;
1273
1274	ucon = rd_regl(port, S3C2410_UCON);
1275	ucon &= info->clksel_mask;
1276	return ucon >> info->clksel_shift;
1277}
1278
1279static void s3c24xx_serial_setsource(struct uart_port *port,
1280			unsigned int clk_sel)
1281{
1282	struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1283	unsigned int ucon;
1284
1285	if (info->num_clks == 1)
1286		return;
1287
1288	ucon = rd_regl(port, S3C2410_UCON);
1289	if ((ucon & info->clksel_mask) >> info->clksel_shift == clk_sel)
1290		return;
1291
1292	ucon &= ~info->clksel_mask;
1293	ucon |= clk_sel << info->clksel_shift;
1294	wr_regl(port, S3C2410_UCON, ucon);
1295}
1296
1297static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port *ourport,
1298			unsigned int req_baud, struct clk **best_clk,
1299			unsigned int *clk_num)
1300{
1301	struct s3c24xx_uart_info *info = ourport->info;
1302	struct clk *clk;
1303	unsigned long rate;
1304	unsigned int cnt, baud, quot, best_quot = 0;
1305	char clkname[MAX_CLK_NAME_LENGTH];
1306	int calc_deviation, deviation = (1 << 30) - 1;
1307
1308	for (cnt = 0; cnt < info->num_clks; cnt++) {
1309		/* Keep selected clock if provided */
1310		if (ourport->cfg->clk_sel &&
1311			!(ourport->cfg->clk_sel & (1 << cnt)))
1312			continue;
1313
1314		sprintf(clkname, "clk_uart_baud%d", cnt);
1315		clk = clk_get(ourport->port.dev, clkname);
1316		if (IS_ERR(clk))
1317			continue;
1318
1319		rate = clk_get_rate(clk);
1320		if (!rate)
1321			continue;
1322
1323		if (ourport->info->has_divslot) {
1324			unsigned long div = rate / req_baud;
1325
1326			/* The UDIVSLOT register on the newer UARTs allows us to
1327			 * get a divisor adjustment of 1/16th on the baud clock.
1328			 *
1329			 * We don't keep the UDIVSLOT value (the 16ths we
1330			 * calculated by not multiplying the baud by 16) as it
1331			 * is easy enough to recalculate.
1332			 */
1333
1334			quot = div / 16;
1335			baud = rate / div;
1336		} else {
1337			quot = (rate + (8 * req_baud)) / (16 * req_baud);
1338			baud = rate / (quot * 16);
1339		}
1340		quot--;
1341
1342		calc_deviation = req_baud - baud;
1343		if (calc_deviation < 0)
1344			calc_deviation = -calc_deviation;
1345
1346		if (calc_deviation < deviation) {
1347			*best_clk = clk;
1348			best_quot = quot;
1349			*clk_num = cnt;
1350			deviation = calc_deviation;
1351		}
1352	}
1353
1354	return best_quot;
1355}
1356
1357/* udivslot_table[]
1358 *
1359 * This table takes the fractional value of the baud divisor and gives
1360 * the recommended setting for the UDIVSLOT register.
1361 */
1362static u16 udivslot_table[16] = {
1363	[0] = 0x0000,
1364	[1] = 0x0080,
1365	[2] = 0x0808,
1366	[3] = 0x0888,
1367	[4] = 0x2222,
1368	[5] = 0x4924,
1369	[6] = 0x4A52,
1370	[7] = 0x54AA,
1371	[8] = 0x5555,
1372	[9] = 0xD555,
1373	[10] = 0xD5D5,
1374	[11] = 0xDDD5,
1375	[12] = 0xDDDD,
1376	[13] = 0xDFDD,
1377	[14] = 0xDFDF,
1378	[15] = 0xFFDF,
1379};
1380
1381static void s3c24xx_serial_set_termios(struct uart_port *port,
1382				       struct ktermios *termios,
1383				       struct ktermios *old)
1384{
1385	struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
1386	struct s3c24xx_uart_port *ourport = to_ourport(port);
1387	struct clk *clk = ERR_PTR(-EINVAL);
1388	unsigned long flags;
1389	unsigned int baud, quot, clk_sel = 0;
1390	unsigned int ulcon;
1391	unsigned int umcon;
1392	unsigned int udivslot = 0;
1393
1394	/*
1395	 * We don't support modem control lines.
1396	 */
1397	termios->c_cflag &= ~(HUPCL | CMSPAR);
1398	termios->c_cflag |= CLOCAL;
1399
1400	/*
1401	 * Ask the core to calculate the divisor for us.
1402	 */
1403
1404	baud = uart_get_baud_rate(port, termios, old, 0, 3000000);
1405	quot = s3c24xx_serial_getclk(ourport, baud, &clk, &clk_sel);
1406	if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
1407		quot = port->custom_divisor;
1408	if (IS_ERR(clk))
1409		return;
1410
1411	/* check to see if we need  to change clock source */
1412
1413	if (ourport->baudclk != clk) {
1414		clk_prepare_enable(clk);
1415
1416		s3c24xx_serial_setsource(port, clk_sel);
1417
1418		if (!IS_ERR(ourport->baudclk)) {
1419			clk_disable_unprepare(ourport->baudclk);
1420			ourport->baudclk = ERR_PTR(-EINVAL);
1421		}
1422
1423		ourport->baudclk = clk;
1424		ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0;
1425	}
1426
1427	if (ourport->info->has_divslot) {
1428		unsigned int div = ourport->baudclk_rate / baud;
1429
1430		if (cfg->has_fracval) {
1431			udivslot = (div & 15);
1432			dev_dbg(port->dev, "fracval = %04x\n", udivslot);
1433		} else {
1434			udivslot = udivslot_table[div & 15];
1435			dev_dbg(port->dev, "udivslot = %04x (div %d)\n",
1436				udivslot, div & 15);
1437		}
1438	}
1439
1440	switch (termios->c_cflag & CSIZE) {
1441	case CS5:
1442		dev_dbg(port->dev, "config: 5bits/char\n");
1443		ulcon = S3C2410_LCON_CS5;
1444		break;
1445	case CS6:
1446		dev_dbg(port->dev, "config: 6bits/char\n");
1447		ulcon = S3C2410_LCON_CS6;
1448		break;
1449	case CS7:
1450		dev_dbg(port->dev, "config: 7bits/char\n");
1451		ulcon = S3C2410_LCON_CS7;
1452		break;
1453	case CS8:
1454	default:
1455		dev_dbg(port->dev, "config: 8bits/char\n");
1456		ulcon = S3C2410_LCON_CS8;
1457		break;
1458	}
1459
1460	/* preserve original lcon IR settings */
1461	ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
1462
1463	if (termios->c_cflag & CSTOPB)
1464		ulcon |= S3C2410_LCON_STOPB;
1465
1466	if (termios->c_cflag & PARENB) {
1467		if (termios->c_cflag & PARODD)
1468			ulcon |= S3C2410_LCON_PODD;
1469		else
1470			ulcon |= S3C2410_LCON_PEVEN;
1471	} else {
1472		ulcon |= S3C2410_LCON_PNONE;
1473	}
1474
1475	spin_lock_irqsave(&port->lock, flags);
1476
1477	dev_dbg(port->dev,
1478		"setting ulcon to %08x, brddiv to %d, udivslot %08x\n",
1479		ulcon, quot, udivslot);
1480
1481	wr_regl(port, S3C2410_ULCON, ulcon);
1482	wr_regl(port, S3C2410_UBRDIV, quot);
1483
1484	port->status &= ~UPSTAT_AUTOCTS;
1485
1486	umcon = rd_regl(port, S3C2410_UMCON);
1487	if (termios->c_cflag & CRTSCTS) {
1488		umcon |= S3C2410_UMCOM_AFC;
1489		/* Disable RTS when RX FIFO contains 63 bytes */
1490		umcon &= ~S3C2412_UMCON_AFC_8;
1491		port->status = UPSTAT_AUTOCTS;
1492	} else {
1493		umcon &= ~S3C2410_UMCOM_AFC;
1494	}
1495	wr_regl(port, S3C2410_UMCON, umcon);
1496
1497	if (ourport->info->has_divslot)
1498		wr_regl(port, S3C2443_DIVSLOT, udivslot);
1499
1500	dev_dbg(port->dev,
1501		"uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
1502		rd_regl(port, S3C2410_ULCON),
1503		rd_regl(port, S3C2410_UCON),
1504		rd_regl(port, S3C2410_UFCON));
1505
1506	/*
1507	 * Update the per-port timeout.
1508	 */
1509	uart_update_timeout(port, termios->c_cflag, baud);
1510
1511	/*
1512	 * Which character status flags are we interested in?
1513	 */
1514	port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
1515	if (termios->c_iflag & INPCK)
1516		port->read_status_mask |= S3C2410_UERSTAT_FRAME |
1517			S3C2410_UERSTAT_PARITY;
1518	/*
1519	 * Which character status flags should we ignore?
1520	 */
1521	port->ignore_status_mask = 0;
1522	if (termios->c_iflag & IGNPAR)
1523		port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
1524	if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
1525		port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
1526
1527	/*
1528	 * Ignore all characters if CREAD is not set.
1529	 */
1530	if ((termios->c_cflag & CREAD) == 0)
1531		port->ignore_status_mask |= RXSTAT_DUMMY_READ;
1532
1533	spin_unlock_irqrestore(&port->lock, flags);
1534}
1535
1536static const char *s3c24xx_serial_type(struct uart_port *port)
1537{
1538	switch (port->type) {
1539	case PORT_S3C2410:
1540		return "S3C2410";
1541	case PORT_S3C2440:
1542		return "S3C2440";
1543	case PORT_S3C2412:
1544		return "S3C2412";
1545	case PORT_S3C6400:
1546		return "S3C6400/10";
1547	default:
1548		return NULL;
1549	}
1550}
1551
1552#define MAP_SIZE (0x100)
1553
1554static void s3c24xx_serial_release_port(struct uart_port *port)
1555{
1556	release_mem_region(port->mapbase, MAP_SIZE);
1557}
1558
1559static int s3c24xx_serial_request_port(struct uart_port *port)
1560{
1561	const char *name = s3c24xx_serial_portname(port);
1562
1563	return request_mem_region(port->mapbase, MAP_SIZE, name) ? 0 : -EBUSY;
1564}
1565
1566static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
1567{
1568	struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1569
1570	if (flags & UART_CONFIG_TYPE &&
1571	    s3c24xx_serial_request_port(port) == 0)
1572		port->type = info->type;
1573}
1574
1575/*
1576 * verify the new serial_struct (for TIOCSSERIAL).
1577 */
1578static int
1579s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
1580{
1581	struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1582
1583	if (ser->type != PORT_UNKNOWN && ser->type != info->type)
1584		return -EINVAL;
1585
1586	return 0;
1587}
1588
1589#ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1590
1591static struct console s3c24xx_serial_console;
1592
1593static int __init s3c24xx_serial_console_init(void)
1594{
1595	register_console(&s3c24xx_serial_console);
1596	return 0;
1597}
1598console_initcall(s3c24xx_serial_console_init);
1599
1600#define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
1601#else
1602#define S3C24XX_SERIAL_CONSOLE NULL
1603#endif
1604
1605#if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1606static int s3c24xx_serial_get_poll_char(struct uart_port *port);
1607static void s3c24xx_serial_put_poll_char(struct uart_port *port,
1608			 unsigned char c);
1609#endif
1610
1611static struct uart_ops s3c24xx_serial_ops = {
1612	.pm		= s3c24xx_serial_pm,
1613	.tx_empty	= s3c24xx_serial_tx_empty,
1614	.get_mctrl	= s3c24xx_serial_get_mctrl,
1615	.set_mctrl	= s3c24xx_serial_set_mctrl,
1616	.stop_tx	= s3c24xx_serial_stop_tx,
1617	.start_tx	= s3c24xx_serial_start_tx,
1618	.stop_rx	= s3c24xx_serial_stop_rx,
1619	.break_ctl	= s3c24xx_serial_break_ctl,
1620	.startup	= s3c24xx_serial_startup,
1621	.shutdown	= s3c24xx_serial_shutdown,
1622	.set_termios	= s3c24xx_serial_set_termios,
1623	.type		= s3c24xx_serial_type,
1624	.release_port	= s3c24xx_serial_release_port,
1625	.request_port	= s3c24xx_serial_request_port,
1626	.config_port	= s3c24xx_serial_config_port,
1627	.verify_port	= s3c24xx_serial_verify_port,
1628#if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1629	.poll_get_char = s3c24xx_serial_get_poll_char,
1630	.poll_put_char = s3c24xx_serial_put_poll_char,
1631#endif
1632};
1633
1634static struct uart_driver s3c24xx_uart_drv = {
1635	.owner		= THIS_MODULE,
1636	.driver_name	= "s3c2410_serial",
1637	.nr		= CONFIG_SERIAL_SAMSUNG_UARTS,
1638	.cons		= S3C24XX_SERIAL_CONSOLE,
1639	.dev_name	= S3C24XX_SERIAL_NAME,
1640	.major		= S3C24XX_SERIAL_MAJOR,
1641	.minor		= S3C24XX_SERIAL_MINOR,
1642};
1643
1644#define __PORT_LOCK_UNLOCKED(i) \
1645	__SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[i].port.lock)
1646static struct s3c24xx_uart_port
1647s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS] = {
1648	[0] = {
1649		.port = {
1650			.lock		= __PORT_LOCK_UNLOCKED(0),
1651			.iotype		= UPIO_MEM,
1652			.uartclk	= 0,
1653			.fifosize	= 16,
1654			.ops		= &s3c24xx_serial_ops,
1655			.flags		= UPF_BOOT_AUTOCONF,
1656			.line		= 0,
1657		}
1658	},
1659	[1] = {
1660		.port = {
1661			.lock		= __PORT_LOCK_UNLOCKED(1),
1662			.iotype		= UPIO_MEM,
1663			.uartclk	= 0,
1664			.fifosize	= 16,
1665			.ops		= &s3c24xx_serial_ops,
1666			.flags		= UPF_BOOT_AUTOCONF,
1667			.line		= 1,
1668		}
1669	},
1670#if CONFIG_SERIAL_SAMSUNG_UARTS > 2
1671	[2] = {
1672		.port = {
1673			.lock		= __PORT_LOCK_UNLOCKED(2),
1674			.iotype		= UPIO_MEM,
1675			.uartclk	= 0,
1676			.fifosize	= 16,
1677			.ops		= &s3c24xx_serial_ops,
1678			.flags		= UPF_BOOT_AUTOCONF,
1679			.line		= 2,
1680		}
1681	},
1682#endif
1683#if CONFIG_SERIAL_SAMSUNG_UARTS > 3
1684	[3] = {
1685		.port = {
1686			.lock		= __PORT_LOCK_UNLOCKED(3),
1687			.iotype		= UPIO_MEM,
1688			.uartclk	= 0,
1689			.fifosize	= 16,
1690			.ops		= &s3c24xx_serial_ops,
1691			.flags		= UPF_BOOT_AUTOCONF,
1692			.line		= 3,
1693		}
1694	}
1695#endif
1696};
1697#undef __PORT_LOCK_UNLOCKED
1698
1699/* s3c24xx_serial_resetport
1700 *
1701 * reset the fifos and other the settings.
1702 */
1703
1704static void s3c24xx_serial_resetport(struct uart_port *port,
1705				   struct s3c2410_uartcfg *cfg)
1706{
1707	struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1708	unsigned long ucon = rd_regl(port, S3C2410_UCON);
1709	unsigned int ucon_mask;
1710
1711	ucon_mask = info->clksel_mask;
1712	if (info->type == PORT_S3C2440)
1713		ucon_mask |= S3C2440_UCON0_DIVMASK;
1714
1715	ucon &= ucon_mask;
1716	wr_regl(port, S3C2410_UCON,  ucon | cfg->ucon);
1717
1718	/* reset both fifos */
1719	wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1720	wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1721
1722	/* some delay is required after fifo reset */
1723	udelay(1);
1724}
1725
1726#ifdef CONFIG_ARM_S3C24XX_CPUFREQ
1727
1728static int s3c24xx_serial_cpufreq_transition(struct notifier_block *nb,
1729					     unsigned long val, void *data)
1730{
1731	struct s3c24xx_uart_port *port;
1732	struct uart_port *uport;
1733
1734	port = container_of(nb, struct s3c24xx_uart_port, freq_transition);
1735	uport = &port->port;
1736
1737	/* check to see if port is enabled */
1738
1739	if (port->pm_level != 0)
1740		return 0;
1741
1742	/* try and work out if the baudrate is changing, we can detect
1743	 * a change in rate, but we do not have support for detecting
1744	 * a disturbance in the clock-rate over the change.
1745	 */
1746
1747	if (IS_ERR(port->baudclk))
1748		goto exit;
1749
1750	if (port->baudclk_rate == clk_get_rate(port->baudclk))
1751		goto exit;
1752
1753	if (val == CPUFREQ_PRECHANGE) {
1754		/* we should really shut the port down whilst the
1755		 * frequency change is in progress.
1756		 */
1757
1758	} else if (val == CPUFREQ_POSTCHANGE) {
1759		struct ktermios *termios;
1760		struct tty_struct *tty;
1761
1762		if (uport->state == NULL)
1763			goto exit;
1764
1765		tty = uport->state->port.tty;
1766
1767		if (tty == NULL)
1768			goto exit;
1769
1770		termios = &tty->termios;
1771
1772		if (termios == NULL) {
1773			dev_warn(uport->dev, "%s: no termios?\n", __func__);
1774			goto exit;
1775		}
1776
1777		s3c24xx_serial_set_termios(uport, termios, NULL);
1778	}
1779
1780exit:
1781	return 0;
1782}
1783
1784static inline int
1785s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1786{
1787	port->freq_transition.notifier_call = s3c24xx_serial_cpufreq_transition;
1788
1789	return cpufreq_register_notifier(&port->freq_transition,
1790					 CPUFREQ_TRANSITION_NOTIFIER);
1791}
1792
1793static inline void
1794s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1795{
1796	cpufreq_unregister_notifier(&port->freq_transition,
1797				    CPUFREQ_TRANSITION_NOTIFIER);
1798}
1799
1800#else
1801static inline int
1802s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1803{
1804	return 0;
1805}
1806
1807static inline void
1808s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1809{
1810}
1811#endif
1812
1813static int s3c24xx_serial_enable_baudclk(struct s3c24xx_uart_port *ourport)
1814{
1815	struct device *dev = ourport->port.dev;
1816	struct s3c24xx_uart_info *info = ourport->info;
1817	char clk_name[MAX_CLK_NAME_LENGTH];
1818	unsigned int clk_sel;
1819	struct clk *clk;
1820	int clk_num;
1821	int ret;
1822
1823	clk_sel = ourport->cfg->clk_sel ? : info->def_clk_sel;
1824	for (clk_num = 0; clk_num < info->num_clks; clk_num++) {
1825		if (!(clk_sel & (1 << clk_num)))
1826			continue;
1827
1828		sprintf(clk_name, "clk_uart_baud%d", clk_num);
1829		clk = clk_get(dev, clk_name);
1830		if (IS_ERR(clk))
1831			continue;
1832
1833		ret = clk_prepare_enable(clk);
1834		if (ret) {
1835			clk_put(clk);
1836			continue;
1837		}
1838
1839		ourport->baudclk = clk;
1840		ourport->baudclk_rate = clk_get_rate(clk);
1841		s3c24xx_serial_setsource(&ourport->port, clk_num);
1842
1843		return 0;
1844	}
1845
1846	return -EINVAL;
1847}
1848
1849/* s3c24xx_serial_init_port
1850 *
1851 * initialise a single serial port from the platform device given
1852 */
1853
1854static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
1855				    struct platform_device *platdev)
1856{
1857	struct uart_port *port = &ourport->port;
1858	struct s3c2410_uartcfg *cfg = ourport->cfg;
1859	struct resource *res;
1860	int ret;
1861
1862	if (platdev == NULL)
1863		return -ENODEV;
1864
1865	if (port->mapbase != 0)
1866		return -EINVAL;
1867
1868	/* setup info for port */
1869	port->dev	= &platdev->dev;
1870
1871	/* Startup sequence is different for s3c64xx and higher SoC's */
1872	if (s3c24xx_serial_has_interrupt_mask(port))
1873		s3c24xx_serial_ops.startup = s3c64xx_serial_startup;
1874
1875	port->uartclk = 1;
1876
1877	if (cfg->uart_flags & UPF_CONS_FLOW) {
1878		dev_dbg(port->dev, "enabling flow control\n");
1879		port->flags |= UPF_CONS_FLOW;
1880	}
1881
1882	/* sort our the physical and virtual addresses for each UART */
1883
1884	res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
1885	if (res == NULL) {
1886		dev_err(port->dev, "failed to find memory resource for uart\n");
1887		return -EINVAL;
1888	}
1889
1890	dev_dbg(port->dev, "resource %pR)\n", res);
1891
1892	port->membase = devm_ioremap(port->dev, res->start, resource_size(res));
1893	if (!port->membase) {
1894		dev_err(port->dev, "failed to remap controller address\n");
1895		return -EBUSY;
1896	}
1897
1898	port->mapbase = res->start;
1899	ret = platform_get_irq(platdev, 0);
1900	if (ret < 0) {
1901		port->irq = 0;
1902	} else {
1903		port->irq = ret;
1904		ourport->rx_irq = ret;
1905		ourport->tx_irq = ret + 1;
1906	}
1907
1908	if (!s3c24xx_serial_has_interrupt_mask(port)) {
1909		ret = platform_get_irq(platdev, 1);
1910		if (ret > 0)
1911			ourport->tx_irq = ret;
1912	}
1913	/*
1914	 * DMA is currently supported only on DT platforms, if DMA properties
1915	 * are specified.
1916	 */
1917	if (platdev->dev.of_node && of_find_property(platdev->dev.of_node,
1918						     "dmas", NULL)) {
1919		ourport->dma = devm_kzalloc(port->dev,
1920					    sizeof(*ourport->dma),
1921					    GFP_KERNEL);
1922		if (!ourport->dma) {
1923			ret = -ENOMEM;
1924			goto err;
1925		}
1926	}
1927
1928	ourport->clk	= clk_get(&platdev->dev, "uart");
1929	if (IS_ERR(ourport->clk)) {
1930		pr_err("%s: Controller clock not found\n",
1931				dev_name(&platdev->dev));
1932		ret = PTR_ERR(ourport->clk);
1933		goto err;
1934	}
1935
1936	ret = clk_prepare_enable(ourport->clk);
1937	if (ret) {
1938		pr_err("uart: clock failed to prepare+enable: %d\n", ret);
1939		clk_put(ourport->clk);
1940		goto err;
1941	}
1942
1943	ret = s3c24xx_serial_enable_baudclk(ourport);
1944	if (ret)
1945		pr_warn("uart: failed to enable baudclk\n");
1946
1947	/* Keep all interrupts masked and cleared */
1948	if (s3c24xx_serial_has_interrupt_mask(port)) {
1949		wr_regl(port, S3C64XX_UINTM, 0xf);
1950		wr_regl(port, S3C64XX_UINTP, 0xf);
1951		wr_regl(port, S3C64XX_UINTSP, 0xf);
1952	}
1953
1954	dev_dbg(port->dev, "port: map=%pa, mem=%p, irq=%d (%d,%d), clock=%u\n",
1955		&port->mapbase, port->membase, port->irq,
1956		ourport->rx_irq, ourport->tx_irq, port->uartclk);
1957
1958	/* reset the fifos (and setup the uart) */
1959	s3c24xx_serial_resetport(port, cfg);
1960
1961	return 0;
1962
1963err:
1964	port->mapbase = 0;
1965	return ret;
1966}
1967
1968/* Device driver serial port probe */
1969
1970#ifdef CONFIG_OF
1971static const struct of_device_id s3c24xx_uart_dt_match[];
1972#endif
1973
1974static int probe_index;
1975
1976static inline struct s3c24xx_serial_drv_data *
1977s3c24xx_get_driver_data(struct platform_device *pdev)
1978{
1979#ifdef CONFIG_OF
1980	if (pdev->dev.of_node) {
1981		const struct of_device_id *match;
1982
1983		match = of_match_node(s3c24xx_uart_dt_match, pdev->dev.of_node);
1984		return (struct s3c24xx_serial_drv_data *)match->data;
1985	}
1986#endif
1987	return (struct s3c24xx_serial_drv_data *)
1988			platform_get_device_id(pdev)->driver_data;
1989}
1990
1991static int s3c24xx_serial_probe(struct platform_device *pdev)
1992{
1993	struct device_node *np = pdev->dev.of_node;
1994	struct s3c24xx_uart_port *ourport;
1995	int index = probe_index;
1996	int ret, prop = 0;
1997
1998	if (np) {
1999		ret = of_alias_get_id(np, "serial");
2000		if (ret >= 0)
2001			index = ret;
2002	}
2003
2004	if (index >= ARRAY_SIZE(s3c24xx_serial_ports)) {
2005		dev_err(&pdev->dev, "serial%d out of range\n", index);
2006		return -EINVAL;
2007	}
2008	ourport = &s3c24xx_serial_ports[index];
2009
2010	ourport->drv_data = s3c24xx_get_driver_data(pdev);
2011	if (!ourport->drv_data) {
2012		dev_err(&pdev->dev, "could not find driver data\n");
2013		return -ENODEV;
2014	}
2015
2016	ourport->baudclk = ERR_PTR(-EINVAL);
2017	ourport->info = ourport->drv_data->info;
2018	ourport->cfg = (dev_get_platdata(&pdev->dev)) ?
2019			dev_get_platdata(&pdev->dev) :
2020			ourport->drv_data->def_cfg;
2021
2022	if (np) {
2023		of_property_read_u32(np,
2024			"samsung,uart-fifosize", &ourport->port.fifosize);
2025
2026		if (of_property_read_u32(np, "reg-io-width", &prop) == 0) {
2027			switch (prop) {
2028			case 1:
2029				ourport->port.iotype = UPIO_MEM;
2030				break;
2031			case 4:
2032				ourport->port.iotype = UPIO_MEM32;
2033				break;
2034			default:
2035				dev_warn(&pdev->dev, "unsupported reg-io-width (%d)\n",
2036						prop);
2037				ret = -EINVAL;
2038				break;
2039			}
2040		}
2041	}
2042
2043	if (ourport->drv_data->fifosize[index])
2044		ourport->port.fifosize = ourport->drv_data->fifosize[index];
2045	else if (ourport->info->fifosize)
2046		ourport->port.fifosize = ourport->info->fifosize;
2047	ourport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_SAMSUNG_CONSOLE);
2048
2049	/*
2050	 * DMA transfers must be aligned at least to cache line size,
2051	 * so find minimal transfer size suitable for DMA mode
2052	 */
2053	ourport->min_dma_size = max_t(int, ourport->port.fifosize,
2054				    dma_get_cache_alignment());
2055
2056	dev_dbg(&pdev->dev, "%s: initialising port %p...\n", __func__, ourport);
2057
2058	ret = s3c24xx_serial_init_port(ourport, pdev);
2059	if (ret < 0)
2060		return ret;
2061
2062	if (!s3c24xx_uart_drv.state) {
2063		ret = uart_register_driver(&s3c24xx_uart_drv);
2064		if (ret < 0) {
2065			pr_err("Failed to register Samsung UART driver\n");
2066			return ret;
2067		}
2068	}
2069
2070	dev_dbg(&pdev->dev, "%s: adding port\n", __func__);
2071	uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
2072	platform_set_drvdata(pdev, &ourport->port);
2073
2074	/*
2075	 * Deactivate the clock enabled in s3c24xx_serial_init_port here,
2076	 * so that a potential re-enablement through the pm-callback overlaps
2077	 * and keeps the clock enabled in this case.
2078	 */
2079	clk_disable_unprepare(ourport->clk);
2080	if (!IS_ERR(ourport->baudclk))
2081		clk_disable_unprepare(ourport->baudclk);
2082
2083	ret = s3c24xx_serial_cpufreq_register(ourport);
2084	if (ret < 0)
2085		dev_err(&pdev->dev, "failed to add cpufreq notifier\n");
2086
2087	probe_index++;
2088
2089	return 0;
2090}
2091
2092static int s3c24xx_serial_remove(struct platform_device *dev)
2093{
2094	struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
2095
2096	if (port) {
2097		s3c24xx_serial_cpufreq_deregister(to_ourport(port));
2098		uart_remove_one_port(&s3c24xx_uart_drv, port);
2099	}
2100
2101	uart_unregister_driver(&s3c24xx_uart_drv);
2102
2103	return 0;
2104}
2105
2106/* UART power management code */
2107#ifdef CONFIG_PM_SLEEP
2108static int s3c24xx_serial_suspend(struct device *dev)
2109{
2110	struct uart_port *port = s3c24xx_dev_to_port(dev);
2111
2112	if (port)
2113		uart_suspend_port(&s3c24xx_uart_drv, port);
2114
2115	return 0;
2116}
2117
2118static int s3c24xx_serial_resume(struct device *dev)
2119{
2120	struct uart_port *port = s3c24xx_dev_to_port(dev);
2121	struct s3c24xx_uart_port *ourport = to_ourport(port);
2122
2123	if (port) {
2124		clk_prepare_enable(ourport->clk);
2125		if (!IS_ERR(ourport->baudclk))
2126			clk_prepare_enable(ourport->baudclk);
2127		s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
2128		if (!IS_ERR(ourport->baudclk))
2129			clk_disable_unprepare(ourport->baudclk);
2130		clk_disable_unprepare(ourport->clk);
2131
2132		uart_resume_port(&s3c24xx_uart_drv, port);
2133	}
2134
2135	return 0;
2136}
2137
2138static int s3c24xx_serial_resume_noirq(struct device *dev)
2139{
2140	struct uart_port *port = s3c24xx_dev_to_port(dev);
2141	struct s3c24xx_uart_port *ourport = to_ourport(port);
2142
2143	if (port) {
2144		/* restore IRQ mask */
2145		if (s3c24xx_serial_has_interrupt_mask(port)) {
2146			unsigned int uintm = 0xf;
2147
2148			if (ourport->tx_enabled)
2149				uintm &= ~S3C64XX_UINTM_TXD_MSK;
2150			if (ourport->rx_enabled)
2151				uintm &= ~S3C64XX_UINTM_RXD_MSK;
2152			clk_prepare_enable(ourport->clk);
2153			if (!IS_ERR(ourport->baudclk))
2154				clk_prepare_enable(ourport->baudclk);
2155			wr_regl(port, S3C64XX_UINTM, uintm);
2156			if (!IS_ERR(ourport->baudclk))
2157				clk_disable_unprepare(ourport->baudclk);
2158			clk_disable_unprepare(ourport->clk);
2159		}
2160	}
2161
2162	return 0;
2163}
2164
2165static const struct dev_pm_ops s3c24xx_serial_pm_ops = {
2166	.suspend = s3c24xx_serial_suspend,
2167	.resume = s3c24xx_serial_resume,
2168	.resume_noirq = s3c24xx_serial_resume_noirq,
2169};
2170#define SERIAL_SAMSUNG_PM_OPS	(&s3c24xx_serial_pm_ops)
2171
2172#else /* !CONFIG_PM_SLEEP */
2173
2174#define SERIAL_SAMSUNG_PM_OPS	NULL
2175#endif /* CONFIG_PM_SLEEP */
2176
2177/* Console code */
2178
2179#ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
2180
2181static struct uart_port *cons_uart;
2182
2183static int
2184s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
2185{
2186	struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
2187	unsigned long ufstat, utrstat;
2188
2189	if (ufcon & S3C2410_UFCON_FIFOMODE) {
2190		/* fifo mode - check amount of data in fifo registers... */
2191
2192		ufstat = rd_regl(port, S3C2410_UFSTAT);
2193		return (ufstat & info->tx_fifofull) ? 0 : 1;
2194	}
2195
2196	/* in non-fifo mode, we go and use the tx buffer empty */
2197
2198	utrstat = rd_regl(port, S3C2410_UTRSTAT);
2199	return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0;
2200}
2201
2202static bool
2203s3c24xx_port_configured(unsigned int ucon)
2204{
2205	/* consider the serial port configured if the tx/rx mode set */
2206	return (ucon & 0xf) != 0;
2207}
2208
2209#ifdef CONFIG_CONSOLE_POLL
2210/*
2211 * Console polling routines for writing and reading from the uart while
2212 * in an interrupt or debug context.
2213 */
2214
2215static int s3c24xx_serial_get_poll_char(struct uart_port *port)
2216{
2217	struct s3c24xx_uart_port *ourport = to_ourport(port);
2218	unsigned int ufstat;
2219
2220	ufstat = rd_regl(port, S3C2410_UFSTAT);
2221	if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
2222		return NO_POLL_CHAR;
2223
2224	return rd_reg(port, S3C2410_URXH);
2225}
2226
2227static void s3c24xx_serial_put_poll_char(struct uart_port *port,
2228		unsigned char c)
2229{
2230	unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
2231	unsigned int ucon = rd_regl(port, S3C2410_UCON);
2232
2233	/* not possible to xmit on unconfigured port */
2234	if (!s3c24xx_port_configured(ucon))
2235		return;
2236
2237	while (!s3c24xx_serial_console_txrdy(port, ufcon))
2238		cpu_relax();
2239	wr_reg(port, S3C2410_UTXH, c);
2240}
2241
2242#endif /* CONFIG_CONSOLE_POLL */
2243
2244static void
2245s3c24xx_serial_console_putchar(struct uart_port *port, int ch)
2246{
2247	unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
2248
2249	while (!s3c24xx_serial_console_txrdy(port, ufcon))
2250		cpu_relax();
2251	wr_reg(port, S3C2410_UTXH, ch);
2252}
2253
2254static void
2255s3c24xx_serial_console_write(struct console *co, const char *s,
2256			     unsigned int count)
2257{
2258	unsigned int ucon = rd_regl(cons_uart, S3C2410_UCON);
2259
2260	/* not possible to xmit on unconfigured port */
2261	if (!s3c24xx_port_configured(ucon))
2262		return;
2263
2264	uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar);
2265}
2266
2267static void __init
2268s3c24xx_serial_get_options(struct uart_port *port, int *baud,
2269			   int *parity, int *bits)
2270{
2271	struct clk *clk;
2272	unsigned int ulcon;
2273	unsigned int ucon;
2274	unsigned int ubrdiv;
2275	unsigned long rate;
2276	unsigned int clk_sel;
2277	char clk_name[MAX_CLK_NAME_LENGTH];
2278
2279	ulcon  = rd_regl(port, S3C2410_ULCON);
2280	ucon   = rd_regl(port, S3C2410_UCON);
2281	ubrdiv = rd_regl(port, S3C2410_UBRDIV);
2282
2283	if (s3c24xx_port_configured(ucon)) {
2284		switch (ulcon & S3C2410_LCON_CSMASK) {
2285		case S3C2410_LCON_CS5:
2286			*bits = 5;
2287			break;
2288		case S3C2410_LCON_CS6:
2289			*bits = 6;
2290			break;
2291		case S3C2410_LCON_CS7:
2292			*bits = 7;
2293			break;
2294		case S3C2410_LCON_CS8:
2295		default:
2296			*bits = 8;
2297			break;
2298		}
2299
2300		switch (ulcon & S3C2410_LCON_PMASK) {
2301		case S3C2410_LCON_PEVEN:
2302			*parity = 'e';
2303			break;
2304
2305		case S3C2410_LCON_PODD:
2306			*parity = 'o';
2307			break;
2308
2309		case S3C2410_LCON_PNONE:
2310		default:
2311			*parity = 'n';
2312		}
2313
2314		/* now calculate the baud rate */
2315
2316		clk_sel = s3c24xx_serial_getsource(port);
2317		sprintf(clk_name, "clk_uart_baud%d", clk_sel);
2318
2319		clk = clk_get(port->dev, clk_name);
2320		if (!IS_ERR(clk))
2321			rate = clk_get_rate(clk);
2322		else
2323			rate = 1;
2324
2325		*baud = rate / (16 * (ubrdiv + 1));
2326		dev_dbg(port->dev, "calculated baud %d\n", *baud);
2327	}
2328}
2329
2330static int __init
2331s3c24xx_serial_console_setup(struct console *co, char *options)
2332{
2333	struct uart_port *port;
2334	int baud = 9600;
2335	int bits = 8;
2336	int parity = 'n';
2337	int flow = 'n';
2338
2339	/* is this a valid port */
2340
2341	if (co->index == -1 || co->index >= CONFIG_SERIAL_SAMSUNG_UARTS)
2342		co->index = 0;
2343
2344	port = &s3c24xx_serial_ports[co->index].port;
2345
2346	/* is the port configured? */
2347
2348	if (port->mapbase == 0x0)
2349		return -ENODEV;
2350
2351	cons_uart = port;
2352
2353	/*
2354	 * Check whether an invalid uart number has been specified, and
2355	 * if so, search for the first available port that does have
2356	 * console support.
2357	 */
2358	if (options)
2359		uart_parse_options(options, &baud, &parity, &bits, &flow);
2360	else
2361		s3c24xx_serial_get_options(port, &baud, &parity, &bits);
2362
2363	dev_dbg(port->dev, "baud %d\n", baud);
2364
2365	return uart_set_options(port, co, baud, parity, bits, flow);
2366}
2367
2368static struct console s3c24xx_serial_console = {
2369	.name		= S3C24XX_SERIAL_NAME,
2370	.device		= uart_console_device,
2371	.flags		= CON_PRINTBUFFER,
2372	.index		= -1,
2373	.write		= s3c24xx_serial_console_write,
2374	.setup		= s3c24xx_serial_console_setup,
2375	.data		= &s3c24xx_uart_drv,
2376};
2377#endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */
2378
2379#ifdef CONFIG_CPU_S3C2410
2380static struct s3c24xx_serial_drv_data s3c2410_serial_drv_data = {
2381	.info = &(struct s3c24xx_uart_info) {
2382		.name		= "Samsung S3C2410 UART",
2383		.type		= PORT_S3C2410,
2384		.fifosize	= 16,
2385		.rx_fifomask	= S3C2410_UFSTAT_RXMASK,
2386		.rx_fifoshift	= S3C2410_UFSTAT_RXSHIFT,
2387		.rx_fifofull	= S3C2410_UFSTAT_RXFULL,
2388		.tx_fifofull	= S3C2410_UFSTAT_TXFULL,
2389		.tx_fifomask	= S3C2410_UFSTAT_TXMASK,
2390		.tx_fifoshift	= S3C2410_UFSTAT_TXSHIFT,
2391		.def_clk_sel	= S3C2410_UCON_CLKSEL0,
2392		.num_clks	= 2,
2393		.clksel_mask	= S3C2410_UCON_CLKMASK,
2394		.clksel_shift	= S3C2410_UCON_CLKSHIFT,
2395	},
2396	.def_cfg = &(struct s3c2410_uartcfg) {
2397		.ucon		= S3C2410_UCON_DEFAULT,
2398		.ufcon		= S3C2410_UFCON_DEFAULT,
2399	},
2400};
2401#define S3C2410_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2410_serial_drv_data)
2402#else
2403#define S3C2410_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2404#endif
2405
2406#ifdef CONFIG_CPU_S3C2412
2407static struct s3c24xx_serial_drv_data s3c2412_serial_drv_data = {
2408	.info = &(struct s3c24xx_uart_info) {
2409		.name		= "Samsung S3C2412 UART",
2410		.type		= PORT_S3C2412,
2411		.fifosize	= 64,
2412		.has_divslot	= 1,
2413		.rx_fifomask	= S3C2440_UFSTAT_RXMASK,
2414		.rx_fifoshift	= S3C2440_UFSTAT_RXSHIFT,
2415		.rx_fifofull	= S3C2440_UFSTAT_RXFULL,
2416		.tx_fifofull	= S3C2440_UFSTAT_TXFULL,
2417		.tx_fifomask	= S3C2440_UFSTAT_TXMASK,
2418		.tx_fifoshift	= S3C2440_UFSTAT_TXSHIFT,
2419		.def_clk_sel	= S3C2410_UCON_CLKSEL2,
2420		.num_clks	= 4,
2421		.clksel_mask	= S3C2412_UCON_CLKMASK,
2422		.clksel_shift	= S3C2412_UCON_CLKSHIFT,
2423	},
2424	.def_cfg = &(struct s3c2410_uartcfg) {
2425		.ucon		= S3C2410_UCON_DEFAULT,
2426		.ufcon		= S3C2410_UFCON_DEFAULT,
2427	},
2428};
2429#define S3C2412_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2412_serial_drv_data)
2430#else
2431#define S3C2412_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2432#endif
2433
2434#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2416) || \
2435	defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2442)
2436static struct s3c24xx_serial_drv_data s3c2440_serial_drv_data = {
2437	.info = &(struct s3c24xx_uart_info) {
2438		.name		= "Samsung S3C2440 UART",
2439		.type		= PORT_S3C2440,
2440		.fifosize	= 64,
2441		.has_divslot	= 1,
2442		.rx_fifomask	= S3C2440_UFSTAT_RXMASK,
2443		.rx_fifoshift	= S3C2440_UFSTAT_RXSHIFT,
2444		.rx_fifofull	= S3C2440_UFSTAT_RXFULL,
2445		.tx_fifofull	= S3C2440_UFSTAT_TXFULL,
2446		.tx_fifomask	= S3C2440_UFSTAT_TXMASK,
2447		.tx_fifoshift	= S3C2440_UFSTAT_TXSHIFT,
2448		.def_clk_sel	= S3C2410_UCON_CLKSEL2,
2449		.num_clks	= 4,
2450		.clksel_mask	= S3C2412_UCON_CLKMASK,
2451		.clksel_shift	= S3C2412_UCON_CLKSHIFT,
2452	},
2453	.def_cfg = &(struct s3c2410_uartcfg) {
2454		.ucon		= S3C2410_UCON_DEFAULT,
2455		.ufcon		= S3C2410_UFCON_DEFAULT,
2456	},
2457};
2458#define S3C2440_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2440_serial_drv_data)
2459#else
2460#define S3C2440_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2461#endif
2462
2463#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
2464static struct s3c24xx_serial_drv_data s3c6400_serial_drv_data = {
2465	.info = &(struct s3c24xx_uart_info) {
2466		.name		= "Samsung S3C6400 UART",
2467		.type		= PORT_S3C6400,
2468		.fifosize	= 64,
2469		.has_divslot	= 1,
2470		.rx_fifomask	= S3C2440_UFSTAT_RXMASK,
2471		.rx_fifoshift	= S3C2440_UFSTAT_RXSHIFT,
2472		.rx_fifofull	= S3C2440_UFSTAT_RXFULL,
2473		.tx_fifofull	= S3C2440_UFSTAT_TXFULL,
2474		.tx_fifomask	= S3C2440_UFSTAT_TXMASK,
2475		.tx_fifoshift	= S3C2440_UFSTAT_TXSHIFT,
2476		.def_clk_sel	= S3C2410_UCON_CLKSEL2,
2477		.num_clks	= 4,
2478		.clksel_mask	= S3C6400_UCON_CLKMASK,
2479		.clksel_shift	= S3C6400_UCON_CLKSHIFT,
2480	},
2481	.def_cfg = &(struct s3c2410_uartcfg) {
2482		.ucon		= S3C2410_UCON_DEFAULT,
2483		.ufcon		= S3C2410_UFCON_DEFAULT,
2484	},
2485};
2486#define S3C6400_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c6400_serial_drv_data)
2487#else
2488#define S3C6400_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2489#endif
2490
2491#ifdef CONFIG_CPU_S5PV210
2492static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
2493	.info = &(struct s3c24xx_uart_info) {
2494		.name		= "Samsung S5PV210 UART",
2495		.type		= PORT_S3C6400,
2496		.has_divslot	= 1,
2497		.rx_fifomask	= S5PV210_UFSTAT_RXMASK,
2498		.rx_fifoshift	= S5PV210_UFSTAT_RXSHIFT,
2499		.rx_fifofull	= S5PV210_UFSTAT_RXFULL,
2500		.tx_fifofull	= S5PV210_UFSTAT_TXFULL,
2501		.tx_fifomask	= S5PV210_UFSTAT_TXMASK,
2502		.tx_fifoshift	= S5PV210_UFSTAT_TXSHIFT,
2503		.def_clk_sel	= S3C2410_UCON_CLKSEL0,
2504		.num_clks	= 2,
2505		.clksel_mask	= S5PV210_UCON_CLKMASK,
2506		.clksel_shift	= S5PV210_UCON_CLKSHIFT,
2507	},
2508	.def_cfg = &(struct s3c2410_uartcfg) {
2509		.ucon		= S5PV210_UCON_DEFAULT,
2510		.ufcon		= S5PV210_UFCON_DEFAULT,
2511	},
2512	.fifosize = { 256, 64, 16, 16 },
2513};
2514#define S5PV210_SERIAL_DRV_DATA ((kernel_ulong_t)&s5pv210_serial_drv_data)
2515#else
2516#define S5PV210_SERIAL_DRV_DATA	(kernel_ulong_t)NULL
2517#endif
2518
2519#if defined(CONFIG_ARCH_EXYNOS)
2520#define EXYNOS_COMMON_SERIAL_DRV_DATA				\
2521	.info = &(struct s3c24xx_uart_info) {			\
2522		.name		= "Samsung Exynos UART",	\
2523		.type		= PORT_S3C6400,			\
2524		.has_divslot	= 1,				\
2525		.rx_fifomask	= S5PV210_UFSTAT_RXMASK,	\
2526		.rx_fifoshift	= S5PV210_UFSTAT_RXSHIFT,	\
2527		.rx_fifofull	= S5PV210_UFSTAT_RXFULL,	\
2528		.tx_fifofull	= S5PV210_UFSTAT_TXFULL,	\
2529		.tx_fifomask	= S5PV210_UFSTAT_TXMASK,	\
2530		.tx_fifoshift	= S5PV210_UFSTAT_TXSHIFT,	\
2531		.def_clk_sel	= S3C2410_UCON_CLKSEL0,		\
2532		.num_clks	= 1,				\
2533		.clksel_mask	= 0,				\
2534		.clksel_shift	= 0,				\
2535	},							\
2536	.def_cfg = &(struct s3c2410_uartcfg) {			\
2537		.ucon		= S5PV210_UCON_DEFAULT,		\
2538		.ufcon		= S5PV210_UFCON_DEFAULT,	\
2539		.has_fracval	= 1,				\
2540	}							\
2541
2542static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = {
2543	EXYNOS_COMMON_SERIAL_DRV_DATA,
2544	.fifosize = { 256, 64, 16, 16 },
2545};
2546
2547static struct s3c24xx_serial_drv_data exynos5433_serial_drv_data = {
2548	EXYNOS_COMMON_SERIAL_DRV_DATA,
2549	.fifosize = { 64, 256, 16, 256 },
2550};
2551
2552#define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos4210_serial_drv_data)
2553#define EXYNOS5433_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos5433_serial_drv_data)
2554#else
2555#define EXYNOS4210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2556#define EXYNOS5433_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2557#endif
2558
2559static const struct platform_device_id s3c24xx_serial_driver_ids[] = {
2560	{
2561		.name		= "s3c2410-uart",
2562		.driver_data	= S3C2410_SERIAL_DRV_DATA,
2563	}, {
2564		.name		= "s3c2412-uart",
2565		.driver_data	= S3C2412_SERIAL_DRV_DATA,
2566	}, {
2567		.name		= "s3c2440-uart",
2568		.driver_data	= S3C2440_SERIAL_DRV_DATA,
2569	}, {
2570		.name		= "s3c6400-uart",
2571		.driver_data	= S3C6400_SERIAL_DRV_DATA,
2572	}, {
2573		.name		= "s5pv210-uart",
2574		.driver_data	= S5PV210_SERIAL_DRV_DATA,
2575	}, {
2576		.name		= "exynos4210-uart",
2577		.driver_data	= EXYNOS4210_SERIAL_DRV_DATA,
2578	}, {
2579		.name		= "exynos5433-uart",
2580		.driver_data	= EXYNOS5433_SERIAL_DRV_DATA,
2581	},
2582	{ },
2583};
2584MODULE_DEVICE_TABLE(platform, s3c24xx_serial_driver_ids);
2585
2586#ifdef CONFIG_OF
2587static const struct of_device_id s3c24xx_uart_dt_match[] = {
2588	{ .compatible = "samsung,s3c2410-uart",
2589		.data = (void *)S3C2410_SERIAL_DRV_DATA },
2590	{ .compatible = "samsung,s3c2412-uart",
2591		.data = (void *)S3C2412_SERIAL_DRV_DATA },
2592	{ .compatible = "samsung,s3c2440-uart",
2593		.data = (void *)S3C2440_SERIAL_DRV_DATA },
2594	{ .compatible = "samsung,s3c6400-uart",
2595		.data = (void *)S3C6400_SERIAL_DRV_DATA },
2596	{ .compatible = "samsung,s5pv210-uart",
2597		.data = (void *)S5PV210_SERIAL_DRV_DATA },
2598	{ .compatible = "samsung,exynos4210-uart",
2599		.data = (void *)EXYNOS4210_SERIAL_DRV_DATA },
2600	{ .compatible = "samsung,exynos5433-uart",
2601		.data = (void *)EXYNOS5433_SERIAL_DRV_DATA },
2602	{},
2603};
2604MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match);
2605#endif
2606
2607static struct platform_driver samsung_serial_driver = {
2608	.probe		= s3c24xx_serial_probe,
2609	.remove		= s3c24xx_serial_remove,
2610	.id_table	= s3c24xx_serial_driver_ids,
2611	.driver		= {
2612		.name	= "samsung-uart",
2613		.pm	= SERIAL_SAMSUNG_PM_OPS,
2614		.of_match_table	= of_match_ptr(s3c24xx_uart_dt_match),
2615	},
2616};
2617
2618module_platform_driver(samsung_serial_driver);
2619
2620#ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
2621/*
2622 * Early console.
2623 */
2624
2625static void wr_reg_barrier(struct uart_port *port, u32 reg, u32 val)
2626{
2627	switch (port->iotype) {
2628	case UPIO_MEM:
2629		writeb(val, portaddr(port, reg));
2630		break;
2631	case UPIO_MEM32:
2632		writel(val, portaddr(port, reg));
2633		break;
2634	}
2635}
2636
2637struct samsung_early_console_data {
2638	u32 txfull_mask;
2639};
2640
2641static void samsung_early_busyuart(struct uart_port *port)
2642{
2643	while (!(readl(port->membase + S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXFE))
2644		;
2645}
2646
2647static void samsung_early_busyuart_fifo(struct uart_port *port)
2648{
2649	struct samsung_early_console_data *data = port->private_data;
2650
2651	while (readl(port->membase + S3C2410_UFSTAT) & data->txfull_mask)
2652		;
2653}
2654
2655static void samsung_early_putc(struct uart_port *port, int c)
2656{
2657	if (readl(port->membase + S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE)
2658		samsung_early_busyuart_fifo(port);
2659	else
2660		samsung_early_busyuart(port);
2661
2662	wr_reg_barrier(port, S3C2410_UTXH, c);
2663}
2664
2665static void samsung_early_write(struct console *con, const char *s,
2666				unsigned int n)
2667{
2668	struct earlycon_device *dev = con->data;
2669
2670	uart_console_write(&dev->port, s, n, samsung_early_putc);
2671}
2672
2673static int __init samsung_early_console_setup(struct earlycon_device *device,
2674					      const char *opt)
2675{
2676	if (!device->port.membase)
2677		return -ENODEV;
2678
2679	device->con->write = samsung_early_write;
2680	return 0;
2681}
2682
2683/* S3C2410 */
2684static struct samsung_early_console_data s3c2410_early_console_data = {
2685	.txfull_mask = S3C2410_UFSTAT_TXFULL,
2686};
2687
2688static int __init s3c2410_early_console_setup(struct earlycon_device *device,
2689					      const char *opt)
2690{
2691	device->port.private_data = &s3c2410_early_console_data;
2692	return samsung_early_console_setup(device, opt);
2693}
2694
2695OF_EARLYCON_DECLARE(s3c2410, "samsung,s3c2410-uart",
2696			s3c2410_early_console_setup);
2697
2698/* S3C2412, S3C2440, S3C64xx */
2699static struct samsung_early_console_data s3c2440_early_console_data = {
2700	.txfull_mask = S3C2440_UFSTAT_TXFULL,
2701};
2702
2703static int __init s3c2440_early_console_setup(struct earlycon_device *device,
2704					      const char *opt)
2705{
2706	device->port.private_data = &s3c2440_early_console_data;
2707	return samsung_early_console_setup(device, opt);
2708}
2709
2710OF_EARLYCON_DECLARE(s3c2412, "samsung,s3c2412-uart",
2711			s3c2440_early_console_setup);
2712OF_EARLYCON_DECLARE(s3c2440, "samsung,s3c2440-uart",
2713			s3c2440_early_console_setup);
2714OF_EARLYCON_DECLARE(s3c6400, "samsung,s3c6400-uart",
2715			s3c2440_early_console_setup);
2716
2717/* S5PV210, Exynos */
2718static struct samsung_early_console_data s5pv210_early_console_data = {
2719	.txfull_mask = S5PV210_UFSTAT_TXFULL,
2720};
2721
2722static int __init s5pv210_early_console_setup(struct earlycon_device *device,
2723					      const char *opt)
2724{
2725	device->port.private_data = &s5pv210_early_console_data;
2726	return samsung_early_console_setup(device, opt);
2727}
2728
2729OF_EARLYCON_DECLARE(s5pv210, "samsung,s5pv210-uart",
2730			s5pv210_early_console_setup);
2731OF_EARLYCON_DECLARE(exynos4210, "samsung,exynos4210-uart",
2732			s5pv210_early_console_setup);
2733#endif
2734
2735MODULE_ALIAS("platform:samsung-uart");
2736MODULE_DESCRIPTION("Samsung SoC Serial port driver");
2737MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
2738MODULE_LICENSE("GPL v2");