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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * phy-zynqmp.c - PHY driver for Xilinx ZynqMP GT.
4 *
5 * Copyright (C) 2018-2020 Xilinx Inc.
6 *
7 * Author: Anurag Kumar Vulisha <anuragku@xilinx.com>
8 * Author: Subbaraya Sundeep <sundeep.lkml@gmail.com>
9 * Author: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
10 *
11 * This driver is tested for USB, SATA and Display Port currently.
12 * Other controllers PCIe and SGMII should also work but that is
13 * experimental as of now.
14 */
15
16#include <linux/clk.h>
17#include <linux/delay.h>
18#include <linux/io.h>
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/of.h>
22#include <linux/phy/phy.h>
23#include <linux/platform_device.h>
24#include <linux/slab.h>
25
26#include <dt-bindings/phy/phy.h>
27
28/*
29 * Lane Registers
30 */
31
32/* TX De-emphasis parameters */
33#define L0_TX_ANA_TM_18 0x0048
34#define L0_TX_ANA_TM_118 0x01d8
35#define L0_TX_ANA_TM_118_FORCE_17_0 BIT(0)
36
37/* DN Resistor calibration code parameters */
38#define L0_TXPMA_ST_3 0x0b0c
39#define L0_DN_CALIB_CODE 0x3f
40
41/* PMA control parameters */
42#define L0_TXPMD_TM_45 0x0cb4
43#define L0_TXPMD_TM_48 0x0cc0
44#define L0_TXPMD_TM_45_OVER_DP_MAIN BIT(0)
45#define L0_TXPMD_TM_45_ENABLE_DP_MAIN BIT(1)
46#define L0_TXPMD_TM_45_OVER_DP_POST1 BIT(2)
47#define L0_TXPMD_TM_45_ENABLE_DP_POST1 BIT(3)
48#define L0_TXPMD_TM_45_OVER_DP_POST2 BIT(4)
49#define L0_TXPMD_TM_45_ENABLE_DP_POST2 BIT(5)
50
51/* PCS control parameters */
52#define L0_TM_DIG_6 0x106c
53#define L0_TM_DIS_DESCRAMBLE_DECODER 0x0f
54#define L0_TX_DIG_61 0x00f4
55#define L0_TM_DISABLE_SCRAMBLE_ENCODER 0x0f
56
57/* PLL Test Mode register parameters */
58#define L0_TM_PLL_DIG_37 0x2094
59#define L0_TM_COARSE_CODE_LIMIT 0x10
60
61/* PLL SSC step size offsets */
62#define L0_PLL_SS_STEPS_0_LSB 0x2368
63#define L0_PLL_SS_STEPS_1_MSB 0x236c
64#define L0_PLL_SS_STEP_SIZE_0_LSB 0x2370
65#define L0_PLL_SS_STEP_SIZE_1 0x2374
66#define L0_PLL_SS_STEP_SIZE_2 0x2378
67#define L0_PLL_SS_STEP_SIZE_3_MSB 0x237c
68#define L0_PLL_STATUS_READ_1 0x23e4
69
70/* SSC step size parameters */
71#define STEP_SIZE_0_MASK 0xff
72#define STEP_SIZE_1_MASK 0xff
73#define STEP_SIZE_2_MASK 0xff
74#define STEP_SIZE_3_MASK 0x3
75#define STEP_SIZE_SHIFT 8
76#define FORCE_STEP_SIZE 0x10
77#define FORCE_STEPS 0x20
78#define STEPS_0_MASK 0xff
79#define STEPS_1_MASK 0x07
80
81/* Reference clock selection parameters */
82#define L0_Ln_REF_CLK_SEL(n) (0x2860 + (n) * 4)
83#define L0_REF_CLK_SEL_MASK 0x8f
84
85/* Calibration digital logic parameters */
86#define L3_TM_CALIB_DIG19 0xec4c
87#define L3_CALIB_DONE_STATUS 0xef14
88#define L3_TM_CALIB_DIG18 0xec48
89#define L3_TM_CALIB_DIG19_NSW 0x07
90#define L3_TM_CALIB_DIG18_NSW 0xe0
91#define L3_TM_OVERRIDE_NSW_CODE 0x20
92#define L3_CALIB_DONE 0x02
93#define L3_NSW_SHIFT 5
94#define L3_NSW_PIPE_SHIFT 4
95#define L3_NSW_CALIB_SHIFT 3
96
97#define PHY_REG_OFFSET 0x4000
98
99/*
100 * Global Registers
101 */
102
103/* Refclk selection parameters */
104#define PLL_REF_SEL(n) (0x10000 + (n) * 4)
105#define PLL_FREQ_MASK 0x1f
106#define PLL_STATUS_LOCKED 0x10
107
108/* Inter Connect Matrix parameters */
109#define ICM_CFG0 0x10010
110#define ICM_CFG1 0x10014
111#define ICM_CFG0_L0_MASK 0x07
112#define ICM_CFG0_L1_MASK 0x70
113#define ICM_CFG1_L2_MASK 0x07
114#define ICM_CFG2_L3_MASK 0x70
115#define ICM_CFG_SHIFT 4
116
117/* Inter Connect Matrix allowed protocols */
118#define ICM_PROTOCOL_PD 0x0
119#define ICM_PROTOCOL_PCIE 0x1
120#define ICM_PROTOCOL_SATA 0x2
121#define ICM_PROTOCOL_USB 0x3
122#define ICM_PROTOCOL_DP 0x4
123#define ICM_PROTOCOL_SGMII 0x5
124
125/* Test Mode common reset control parameters */
126#define TM_CMN_RST 0x10018
127#define TM_CMN_RST_EN 0x1
128#define TM_CMN_RST_SET 0x2
129#define TM_CMN_RST_MASK 0x3
130
131/* Bus width parameters */
132#define TX_PROT_BUS_WIDTH 0x10040
133#define RX_PROT_BUS_WIDTH 0x10044
134#define PROT_BUS_WIDTH_10 0x0
135#define PROT_BUS_WIDTH_20 0x1
136#define PROT_BUS_WIDTH_40 0x2
137#define PROT_BUS_WIDTH_SHIFT 2
138
139/* Number of GT lanes */
140#define NUM_LANES 4
141
142/* SIOU SATA control register */
143#define SATA_CONTROL_OFFSET 0x0100
144
145/* Total number of controllers */
146#define CONTROLLERS_PER_LANE 5
147
148/* Protocol Type parameters */
149#define XPSGTR_TYPE_USB0 0 /* USB controller 0 */
150#define XPSGTR_TYPE_USB1 1 /* USB controller 1 */
151#define XPSGTR_TYPE_SATA_0 2 /* SATA controller lane 0 */
152#define XPSGTR_TYPE_SATA_1 3 /* SATA controller lane 1 */
153#define XPSGTR_TYPE_PCIE_0 4 /* PCIe controller lane 0 */
154#define XPSGTR_TYPE_PCIE_1 5 /* PCIe controller lane 1 */
155#define XPSGTR_TYPE_PCIE_2 6 /* PCIe controller lane 2 */
156#define XPSGTR_TYPE_PCIE_3 7 /* PCIe controller lane 3 */
157#define XPSGTR_TYPE_DP_0 8 /* Display Port controller lane 0 */
158#define XPSGTR_TYPE_DP_1 9 /* Display Port controller lane 1 */
159#define XPSGTR_TYPE_SGMII0 10 /* Ethernet SGMII controller 0 */
160#define XPSGTR_TYPE_SGMII1 11 /* Ethernet SGMII controller 1 */
161#define XPSGTR_TYPE_SGMII2 12 /* Ethernet SGMII controller 2 */
162#define XPSGTR_TYPE_SGMII3 13 /* Ethernet SGMII controller 3 */
163
164/* Timeout values */
165#define TIMEOUT_US 1000
166
167struct xpsgtr_dev;
168
169/**
170 * struct xpsgtr_ssc - structure to hold SSC settings for a lane
171 * @refclk_rate: PLL reference clock frequency
172 * @pll_ref_clk: value to be written to register for corresponding ref clk rate
173 * @steps: number of steps of SSC (Spread Spectrum Clock)
174 * @step_size: step size of each step
175 */
176struct xpsgtr_ssc {
177 u32 refclk_rate;
178 u8 pll_ref_clk;
179 u32 steps;
180 u32 step_size;
181};
182
183/**
184 * struct xpsgtr_phy - representation of a lane
185 * @phy: pointer to the kernel PHY device
186 * @type: controller which uses this lane
187 * @lane: lane number
188 * @protocol: protocol in which the lane operates
189 * @skip_phy_init: skip phy_init() if true
190 * @dev: pointer to the xpsgtr_dev instance
191 * @refclk: reference clock index
192 */
193struct xpsgtr_phy {
194 struct phy *phy;
195 u8 type;
196 u8 lane;
197 u8 protocol;
198 bool skip_phy_init;
199 struct xpsgtr_dev *dev;
200 unsigned int refclk;
201};
202
203/**
204 * struct xpsgtr_dev - representation of a ZynMP GT device
205 * @dev: pointer to device
206 * @serdes: serdes base address
207 * @siou: siou base address
208 * @gtr_mutex: mutex for locking
209 * @phys: PHY lanes
210 * @refclk_sscs: spread spectrum settings for the reference clocks
211 * @tx_term_fix: fix for GT issue
212 * @saved_icm_cfg0: stored value of ICM CFG0 register
213 * @saved_icm_cfg1: stored value of ICM CFG1 register
214 */
215struct xpsgtr_dev {
216 struct device *dev;
217 void __iomem *serdes;
218 void __iomem *siou;
219 struct mutex gtr_mutex; /* mutex for locking */
220 struct xpsgtr_phy phys[NUM_LANES];
221 const struct xpsgtr_ssc *refclk_sscs[NUM_LANES];
222 bool tx_term_fix;
223 unsigned int saved_icm_cfg0;
224 unsigned int saved_icm_cfg1;
225};
226
227/*
228 * Configuration Data
229 */
230
231/* lookup table to hold all settings needed for a ref clock frequency */
232static const struct xpsgtr_ssc ssc_lookup[] = {
233 { 19200000, 0x05, 608, 264020 },
234 { 20000000, 0x06, 634, 243454 },
235 { 24000000, 0x07, 760, 168973 },
236 { 26000000, 0x08, 824, 143860 },
237 { 27000000, 0x09, 856, 86551 },
238 { 38400000, 0x0a, 1218, 65896 },
239 { 40000000, 0x0b, 634, 243454 },
240 { 52000000, 0x0c, 824, 143860 },
241 { 100000000, 0x0d, 1058, 87533 },
242 { 108000000, 0x0e, 856, 86551 },
243 { 125000000, 0x0f, 992, 119497 },
244 { 135000000, 0x10, 1070, 55393 },
245 { 150000000, 0x11, 792, 187091 }
246};
247
248/*
249 * I/O Accessors
250 */
251
252static inline u32 xpsgtr_read(struct xpsgtr_dev *gtr_dev, u32 reg)
253{
254 return readl(gtr_dev->serdes + reg);
255}
256
257static inline void xpsgtr_write(struct xpsgtr_dev *gtr_dev, u32 reg, u32 value)
258{
259 writel(value, gtr_dev->serdes + reg);
260}
261
262static inline void xpsgtr_clr_set(struct xpsgtr_dev *gtr_dev, u32 reg,
263 u32 clr, u32 set)
264{
265 u32 value = xpsgtr_read(gtr_dev, reg);
266
267 value &= ~clr;
268 value |= set;
269 xpsgtr_write(gtr_dev, reg, value);
270}
271
272static inline u32 xpsgtr_read_phy(struct xpsgtr_phy *gtr_phy, u32 reg)
273{
274 void __iomem *addr = gtr_phy->dev->serdes
275 + gtr_phy->lane * PHY_REG_OFFSET + reg;
276
277 return readl(addr);
278}
279
280static inline void xpsgtr_write_phy(struct xpsgtr_phy *gtr_phy,
281 u32 reg, u32 value)
282{
283 void __iomem *addr = gtr_phy->dev->serdes
284 + gtr_phy->lane * PHY_REG_OFFSET + reg;
285
286 writel(value, addr);
287}
288
289static inline void xpsgtr_clr_set_phy(struct xpsgtr_phy *gtr_phy,
290 u32 reg, u32 clr, u32 set)
291{
292 void __iomem *addr = gtr_phy->dev->serdes
293 + gtr_phy->lane * PHY_REG_OFFSET + reg;
294
295 writel((readl(addr) & ~clr) | set, addr);
296}
297
298/*
299 * Hardware Configuration
300 */
301
302/* Wait for the PLL to lock (with a timeout). */
303static int xpsgtr_wait_pll_lock(struct phy *phy)
304{
305 struct xpsgtr_phy *gtr_phy = phy_get_drvdata(phy);
306 struct xpsgtr_dev *gtr_dev = gtr_phy->dev;
307 unsigned int timeout = TIMEOUT_US;
308 int ret;
309
310 dev_dbg(gtr_dev->dev, "Waiting for PLL lock\n");
311
312 while (1) {
313 u32 reg = xpsgtr_read_phy(gtr_phy, L0_PLL_STATUS_READ_1);
314
315 if ((reg & PLL_STATUS_LOCKED) == PLL_STATUS_LOCKED) {
316 ret = 0;
317 break;
318 }
319
320 if (--timeout == 0) {
321 ret = -ETIMEDOUT;
322 break;
323 }
324
325 udelay(1);
326 }
327
328 if (ret == -ETIMEDOUT)
329 dev_err(gtr_dev->dev,
330 "lane %u (type %u, protocol %u): PLL lock timeout\n",
331 gtr_phy->lane, gtr_phy->type, gtr_phy->protocol);
332
333 return ret;
334}
335
336/* Configure PLL and spread-sprectrum clock. */
337static void xpsgtr_configure_pll(struct xpsgtr_phy *gtr_phy)
338{
339 const struct xpsgtr_ssc *ssc;
340 u32 step_size;
341
342 ssc = gtr_phy->dev->refclk_sscs[gtr_phy->refclk];
343 step_size = ssc->step_size;
344
345 xpsgtr_clr_set(gtr_phy->dev, PLL_REF_SEL(gtr_phy->lane),
346 PLL_FREQ_MASK, ssc->pll_ref_clk);
347
348 /* Enable lane clock sharing, if required */
349 if (gtr_phy->refclk != gtr_phy->lane) {
350 /* Lane3 Ref Clock Selection Register */
351 xpsgtr_clr_set(gtr_phy->dev, L0_Ln_REF_CLK_SEL(gtr_phy->lane),
352 L0_REF_CLK_SEL_MASK, 1 << gtr_phy->refclk);
353 }
354
355 /* SSC step size [7:0] */
356 xpsgtr_clr_set_phy(gtr_phy, L0_PLL_SS_STEP_SIZE_0_LSB,
357 STEP_SIZE_0_MASK, step_size & STEP_SIZE_0_MASK);
358
359 /* SSC step size [15:8] */
360 step_size >>= STEP_SIZE_SHIFT;
361 xpsgtr_clr_set_phy(gtr_phy, L0_PLL_SS_STEP_SIZE_1,
362 STEP_SIZE_1_MASK, step_size & STEP_SIZE_1_MASK);
363
364 /* SSC step size [23:16] */
365 step_size >>= STEP_SIZE_SHIFT;
366 xpsgtr_clr_set_phy(gtr_phy, L0_PLL_SS_STEP_SIZE_2,
367 STEP_SIZE_2_MASK, step_size & STEP_SIZE_2_MASK);
368
369 /* SSC steps [7:0] */
370 xpsgtr_clr_set_phy(gtr_phy, L0_PLL_SS_STEPS_0_LSB,
371 STEPS_0_MASK, ssc->steps & STEPS_0_MASK);
372
373 /* SSC steps [10:8] */
374 xpsgtr_clr_set_phy(gtr_phy, L0_PLL_SS_STEPS_1_MSB,
375 STEPS_1_MASK,
376 (ssc->steps >> STEP_SIZE_SHIFT) & STEPS_1_MASK);
377
378 /* SSC step size [24:25] */
379 step_size >>= STEP_SIZE_SHIFT;
380 xpsgtr_clr_set_phy(gtr_phy, L0_PLL_SS_STEP_SIZE_3_MSB,
381 STEP_SIZE_3_MASK, (step_size & STEP_SIZE_3_MASK) |
382 FORCE_STEP_SIZE | FORCE_STEPS);
383}
384
385/* Configure the lane protocol. */
386static void xpsgtr_lane_set_protocol(struct xpsgtr_phy *gtr_phy)
387{
388 struct xpsgtr_dev *gtr_dev = gtr_phy->dev;
389 u8 protocol = gtr_phy->protocol;
390
391 switch (gtr_phy->lane) {
392 case 0:
393 xpsgtr_clr_set(gtr_dev, ICM_CFG0, ICM_CFG0_L0_MASK, protocol);
394 break;
395 case 1:
396 xpsgtr_clr_set(gtr_dev, ICM_CFG0, ICM_CFG0_L1_MASK,
397 protocol << ICM_CFG_SHIFT);
398 break;
399 case 2:
400 xpsgtr_clr_set(gtr_dev, ICM_CFG1, ICM_CFG0_L0_MASK, protocol);
401 break;
402 case 3:
403 xpsgtr_clr_set(gtr_dev, ICM_CFG1, ICM_CFG0_L1_MASK,
404 protocol << ICM_CFG_SHIFT);
405 break;
406 default:
407 /* We already checked 0 <= lane <= 3 */
408 break;
409 }
410}
411
412/* Bypass (de)scrambler and 8b/10b decoder and encoder. */
413static void xpsgtr_bypass_scrambler_8b10b(struct xpsgtr_phy *gtr_phy)
414{
415 xpsgtr_write_phy(gtr_phy, L0_TM_DIG_6, L0_TM_DIS_DESCRAMBLE_DECODER);
416 xpsgtr_write_phy(gtr_phy, L0_TX_DIG_61, L0_TM_DISABLE_SCRAMBLE_ENCODER);
417}
418
419/* DP-specific initialization. */
420static void xpsgtr_phy_init_dp(struct xpsgtr_phy *gtr_phy)
421{
422 xpsgtr_write_phy(gtr_phy, L0_TXPMD_TM_45,
423 L0_TXPMD_TM_45_OVER_DP_MAIN |
424 L0_TXPMD_TM_45_ENABLE_DP_MAIN |
425 L0_TXPMD_TM_45_OVER_DP_POST1 |
426 L0_TXPMD_TM_45_OVER_DP_POST2 |
427 L0_TXPMD_TM_45_ENABLE_DP_POST2);
428 xpsgtr_write_phy(gtr_phy, L0_TX_ANA_TM_118,
429 L0_TX_ANA_TM_118_FORCE_17_0);
430}
431
432/* SATA-specific initialization. */
433static void xpsgtr_phy_init_sata(struct xpsgtr_phy *gtr_phy)
434{
435 struct xpsgtr_dev *gtr_dev = gtr_phy->dev;
436
437 xpsgtr_bypass_scrambler_8b10b(gtr_phy);
438
439 writel(gtr_phy->lane, gtr_dev->siou + SATA_CONTROL_OFFSET);
440}
441
442/* SGMII-specific initialization. */
443static void xpsgtr_phy_init_sgmii(struct xpsgtr_phy *gtr_phy)
444{
445 struct xpsgtr_dev *gtr_dev = gtr_phy->dev;
446
447 /* Set SGMII protocol TX and RX bus width to 10 bits. */
448 xpsgtr_write(gtr_dev, TX_PROT_BUS_WIDTH,
449 PROT_BUS_WIDTH_10 << (gtr_phy->lane * PROT_BUS_WIDTH_SHIFT));
450 xpsgtr_write(gtr_dev, RX_PROT_BUS_WIDTH,
451 PROT_BUS_WIDTH_10 << (gtr_phy->lane * PROT_BUS_WIDTH_SHIFT));
452
453 xpsgtr_bypass_scrambler_8b10b(gtr_phy);
454}
455
456/* Configure TX de-emphasis and margining for DP. */
457static void xpsgtr_phy_configure_dp(struct xpsgtr_phy *gtr_phy, unsigned int pre,
458 unsigned int voltage)
459{
460 static const u8 voltage_swing[4][4] = {
461 { 0x2a, 0x27, 0x24, 0x20 },
462 { 0x27, 0x23, 0x20, 0xff },
463 { 0x24, 0x20, 0xff, 0xff },
464 { 0xff, 0xff, 0xff, 0xff }
465 };
466 static const u8 pre_emphasis[4][4] = {
467 { 0x02, 0x02, 0x02, 0x02 },
468 { 0x01, 0x01, 0x01, 0xff },
469 { 0x00, 0x00, 0xff, 0xff },
470 { 0xff, 0xff, 0xff, 0xff }
471 };
472
473 xpsgtr_write_phy(gtr_phy, L0_TXPMD_TM_48, voltage_swing[pre][voltage]);
474 xpsgtr_write_phy(gtr_phy, L0_TX_ANA_TM_18, pre_emphasis[pre][voltage]);
475}
476
477/*
478 * PHY Operations
479 */
480
481static bool xpsgtr_phy_init_required(struct xpsgtr_phy *gtr_phy)
482{
483 /*
484 * As USB may save the snapshot of the states during hibernation, doing
485 * phy_init() will put the USB controller into reset, resulting in the
486 * losing of the saved snapshot. So try to avoid phy_init() for USB
487 * except when gtr_phy->skip_phy_init is false (this happens when FPD is
488 * shutdown during suspend or when gt lane is changed from current one)
489 */
490 if (gtr_phy->protocol == ICM_PROTOCOL_USB && gtr_phy->skip_phy_init)
491 return false;
492 else
493 return true;
494}
495
496/*
497 * There is a functional issue in the GT. The TX termination resistance can be
498 * out of spec due to a issue in the calibration logic. This is the workaround
499 * to fix it, required for XCZU9EG silicon.
500 */
501static int xpsgtr_phy_tx_term_fix(struct xpsgtr_phy *gtr_phy)
502{
503 struct xpsgtr_dev *gtr_dev = gtr_phy->dev;
504 u32 timeout = TIMEOUT_US;
505 u32 nsw;
506
507 /* Enabling Test Mode control for CMN Rest */
508 xpsgtr_clr_set(gtr_dev, TM_CMN_RST, TM_CMN_RST_MASK, TM_CMN_RST_SET);
509
510 /* Set Test Mode reset */
511 xpsgtr_clr_set(gtr_dev, TM_CMN_RST, TM_CMN_RST_MASK, TM_CMN_RST_EN);
512
513 xpsgtr_write(gtr_dev, L3_TM_CALIB_DIG18, 0x00);
514 xpsgtr_write(gtr_dev, L3_TM_CALIB_DIG19, L3_TM_OVERRIDE_NSW_CODE);
515
516 /*
517 * As a part of work around sequence for PMOS calibration fix,
518 * we need to configure any lane ICM_CFG to valid protocol. This
519 * will deassert the CMN_Resetn signal.
520 */
521 xpsgtr_lane_set_protocol(gtr_phy);
522
523 /* Clear Test Mode reset */
524 xpsgtr_clr_set(gtr_dev, TM_CMN_RST, TM_CMN_RST_MASK, TM_CMN_RST_SET);
525
526 dev_dbg(gtr_dev->dev, "calibrating...\n");
527
528 do {
529 u32 reg = xpsgtr_read(gtr_dev, L3_CALIB_DONE_STATUS);
530
531 if ((reg & L3_CALIB_DONE) == L3_CALIB_DONE)
532 break;
533
534 if (!--timeout) {
535 dev_err(gtr_dev->dev, "calibration time out\n");
536 return -ETIMEDOUT;
537 }
538
539 udelay(1);
540 } while (timeout > 0);
541
542 dev_dbg(gtr_dev->dev, "calibration done\n");
543
544 /* Reading NMOS Register Code */
545 nsw = xpsgtr_read(gtr_dev, L0_TXPMA_ST_3) & L0_DN_CALIB_CODE;
546
547 /* Set Test Mode reset */
548 xpsgtr_clr_set(gtr_dev, TM_CMN_RST, TM_CMN_RST_MASK, TM_CMN_RST_EN);
549
550 /* Writing NMOS register values back [5:3] */
551 xpsgtr_write(gtr_dev, L3_TM_CALIB_DIG19, nsw >> L3_NSW_CALIB_SHIFT);
552
553 /* Writing NMOS register value [2:0] */
554 xpsgtr_write(gtr_dev, L3_TM_CALIB_DIG18,
555 ((nsw & L3_TM_CALIB_DIG19_NSW) << L3_NSW_SHIFT) |
556 (1 << L3_NSW_PIPE_SHIFT));
557
558 /* Clear Test Mode reset */
559 xpsgtr_clr_set(gtr_dev, TM_CMN_RST, TM_CMN_RST_MASK, TM_CMN_RST_SET);
560
561 return 0;
562}
563
564static int xpsgtr_phy_init(struct phy *phy)
565{
566 struct xpsgtr_phy *gtr_phy = phy_get_drvdata(phy);
567 struct xpsgtr_dev *gtr_dev = gtr_phy->dev;
568 int ret = 0;
569
570 mutex_lock(>r_dev->gtr_mutex);
571
572 /* Skip initialization if not required. */
573 if (!xpsgtr_phy_init_required(gtr_phy))
574 goto out;
575
576 if (gtr_dev->tx_term_fix) {
577 ret = xpsgtr_phy_tx_term_fix(gtr_phy);
578 if (ret < 0)
579 goto out;
580
581 gtr_dev->tx_term_fix = false;
582 }
583
584 /* Enable coarse code saturation limiting logic. */
585 xpsgtr_write_phy(gtr_phy, L0_TM_PLL_DIG_37, L0_TM_COARSE_CODE_LIMIT);
586
587 /*
588 * Configure the PLL, the lane protocol, and perform protocol-specific
589 * initialization.
590 */
591 xpsgtr_configure_pll(gtr_phy);
592 xpsgtr_lane_set_protocol(gtr_phy);
593
594 switch (gtr_phy->protocol) {
595 case ICM_PROTOCOL_DP:
596 xpsgtr_phy_init_dp(gtr_phy);
597 break;
598
599 case ICM_PROTOCOL_SATA:
600 xpsgtr_phy_init_sata(gtr_phy);
601 break;
602
603 case ICM_PROTOCOL_SGMII:
604 xpsgtr_phy_init_sgmii(gtr_phy);
605 break;
606 }
607
608out:
609 mutex_unlock(>r_dev->gtr_mutex);
610 return ret;
611}
612
613static int xpsgtr_phy_exit(struct phy *phy)
614{
615 struct xpsgtr_phy *gtr_phy = phy_get_drvdata(phy);
616
617 gtr_phy->skip_phy_init = false;
618
619 return 0;
620}
621
622static int xpsgtr_phy_power_on(struct phy *phy)
623{
624 struct xpsgtr_phy *gtr_phy = phy_get_drvdata(phy);
625 int ret = 0;
626
627 /*
628 * Wait for the PLL to lock. For DP, only wait on DP0 to avoid
629 * cumulating waits for both lanes. The user is expected to initialize
630 * lane 0 last.
631 */
632 if (gtr_phy->protocol != ICM_PROTOCOL_DP ||
633 gtr_phy->type == XPSGTR_TYPE_DP_0)
634 ret = xpsgtr_wait_pll_lock(phy);
635
636 return ret;
637}
638
639static int xpsgtr_phy_configure(struct phy *phy, union phy_configure_opts *opts)
640{
641 struct xpsgtr_phy *gtr_phy = phy_get_drvdata(phy);
642
643 if (gtr_phy->protocol != ICM_PROTOCOL_DP)
644 return 0;
645
646 xpsgtr_phy_configure_dp(gtr_phy, opts->dp.pre[0], opts->dp.voltage[0]);
647
648 return 0;
649}
650
651static const struct phy_ops xpsgtr_phyops = {
652 .init = xpsgtr_phy_init,
653 .exit = xpsgtr_phy_exit,
654 .power_on = xpsgtr_phy_power_on,
655 .configure = xpsgtr_phy_configure,
656 .owner = THIS_MODULE,
657};
658
659/*
660 * OF Xlate Support
661 */
662
663/* Set the lane type and protocol based on the PHY type and instance number. */
664static int xpsgtr_set_lane_type(struct xpsgtr_phy *gtr_phy, u8 phy_type,
665 unsigned int phy_instance)
666{
667 unsigned int num_phy_types;
668 const int *phy_types;
669
670 switch (phy_type) {
671 case PHY_TYPE_SATA: {
672 static const int types[] = {
673 XPSGTR_TYPE_SATA_0,
674 XPSGTR_TYPE_SATA_1,
675 };
676
677 phy_types = types;
678 num_phy_types = ARRAY_SIZE(types);
679 gtr_phy->protocol = ICM_PROTOCOL_SATA;
680 break;
681 }
682 case PHY_TYPE_USB3: {
683 static const int types[] = {
684 XPSGTR_TYPE_USB0,
685 XPSGTR_TYPE_USB1,
686 };
687
688 phy_types = types;
689 num_phy_types = ARRAY_SIZE(types);
690 gtr_phy->protocol = ICM_PROTOCOL_USB;
691 break;
692 }
693 case PHY_TYPE_DP: {
694 static const int types[] = {
695 XPSGTR_TYPE_DP_0,
696 XPSGTR_TYPE_DP_1,
697 };
698
699 phy_types = types;
700 num_phy_types = ARRAY_SIZE(types);
701 gtr_phy->protocol = ICM_PROTOCOL_DP;
702 break;
703 }
704 case PHY_TYPE_PCIE: {
705 static const int types[] = {
706 XPSGTR_TYPE_PCIE_0,
707 XPSGTR_TYPE_PCIE_1,
708 XPSGTR_TYPE_PCIE_2,
709 XPSGTR_TYPE_PCIE_3,
710 };
711
712 phy_types = types;
713 num_phy_types = ARRAY_SIZE(types);
714 gtr_phy->protocol = ICM_PROTOCOL_PCIE;
715 break;
716 }
717 case PHY_TYPE_SGMII: {
718 static const int types[] = {
719 XPSGTR_TYPE_SGMII0,
720 XPSGTR_TYPE_SGMII1,
721 XPSGTR_TYPE_SGMII2,
722 XPSGTR_TYPE_SGMII3,
723 };
724
725 phy_types = types;
726 num_phy_types = ARRAY_SIZE(types);
727 gtr_phy->protocol = ICM_PROTOCOL_SGMII;
728 break;
729 }
730 default:
731 return -EINVAL;
732 }
733
734 if (phy_instance >= num_phy_types)
735 return -EINVAL;
736
737 gtr_phy->type = phy_types[phy_instance];
738 return 0;
739}
740
741/*
742 * Valid combinations of controllers and lanes (Interconnect Matrix).
743 */
744static const unsigned int icm_matrix[NUM_LANES][CONTROLLERS_PER_LANE] = {
745 { XPSGTR_TYPE_PCIE_0, XPSGTR_TYPE_SATA_0, XPSGTR_TYPE_USB0,
746 XPSGTR_TYPE_DP_1, XPSGTR_TYPE_SGMII0 },
747 { XPSGTR_TYPE_PCIE_1, XPSGTR_TYPE_SATA_1, XPSGTR_TYPE_USB0,
748 XPSGTR_TYPE_DP_0, XPSGTR_TYPE_SGMII1 },
749 { XPSGTR_TYPE_PCIE_2, XPSGTR_TYPE_SATA_0, XPSGTR_TYPE_USB0,
750 XPSGTR_TYPE_DP_1, XPSGTR_TYPE_SGMII2 },
751 { XPSGTR_TYPE_PCIE_3, XPSGTR_TYPE_SATA_1, XPSGTR_TYPE_USB1,
752 XPSGTR_TYPE_DP_0, XPSGTR_TYPE_SGMII3 }
753};
754
755/* Translate OF phandle and args to PHY instance. */
756static struct phy *xpsgtr_xlate(struct device *dev,
757 struct of_phandle_args *args)
758{
759 struct xpsgtr_dev *gtr_dev = dev_get_drvdata(dev);
760 struct xpsgtr_phy *gtr_phy;
761 unsigned int phy_instance;
762 unsigned int phy_lane;
763 unsigned int phy_type;
764 unsigned int refclk;
765 unsigned int i;
766 int ret;
767
768 if (args->args_count != 4) {
769 dev_err(dev, "Invalid number of cells in 'phy' property\n");
770 return ERR_PTR(-EINVAL);
771 }
772
773 /*
774 * Get the PHY parameters from the OF arguments and derive the lane
775 * type.
776 */
777 phy_lane = args->args[0];
778 if (phy_lane >= ARRAY_SIZE(gtr_dev->phys)) {
779 dev_err(dev, "Invalid lane number %u\n", phy_lane);
780 return ERR_PTR(-ENODEV);
781 }
782
783 gtr_phy = >r_dev->phys[phy_lane];
784 phy_type = args->args[1];
785 phy_instance = args->args[2];
786
787 ret = xpsgtr_set_lane_type(gtr_phy, phy_type, phy_instance);
788 if (ret < 0) {
789 dev_err(gtr_dev->dev, "Invalid PHY type and/or instance\n");
790 return ERR_PTR(ret);
791 }
792
793 refclk = args->args[3];
794 if (refclk >= ARRAY_SIZE(gtr_dev->refclk_sscs) ||
795 !gtr_dev->refclk_sscs[refclk]) {
796 dev_err(dev, "Invalid reference clock number %u\n", refclk);
797 return ERR_PTR(-EINVAL);
798 }
799
800 gtr_phy->refclk = refclk;
801
802 /*
803 * Ensure that the Interconnect Matrix is obeyed, i.e a given lane type
804 * is allowed to operate on the lane.
805 */
806 for (i = 0; i < CONTROLLERS_PER_LANE; i++) {
807 if (icm_matrix[phy_lane][i] == gtr_phy->type)
808 return gtr_phy->phy;
809 }
810
811 return ERR_PTR(-EINVAL);
812}
813
814/*
815 * Power Management
816 */
817
818static int __maybe_unused xpsgtr_suspend(struct device *dev)
819{
820 struct xpsgtr_dev *gtr_dev = dev_get_drvdata(dev);
821
822 /* Save the snapshot ICM_CFG registers. */
823 gtr_dev->saved_icm_cfg0 = xpsgtr_read(gtr_dev, ICM_CFG0);
824 gtr_dev->saved_icm_cfg1 = xpsgtr_read(gtr_dev, ICM_CFG1);
825
826 return 0;
827}
828
829static int __maybe_unused xpsgtr_resume(struct device *dev)
830{
831 struct xpsgtr_dev *gtr_dev = dev_get_drvdata(dev);
832 unsigned int icm_cfg0, icm_cfg1;
833 unsigned int i;
834 bool skip_phy_init;
835
836 icm_cfg0 = xpsgtr_read(gtr_dev, ICM_CFG0);
837 icm_cfg1 = xpsgtr_read(gtr_dev, ICM_CFG1);
838
839 /* Return if no GT lanes got configured before suspend. */
840 if (!gtr_dev->saved_icm_cfg0 && !gtr_dev->saved_icm_cfg1)
841 return 0;
842
843 /* Check if the ICM configurations changed after suspend. */
844 if (icm_cfg0 == gtr_dev->saved_icm_cfg0 &&
845 icm_cfg1 == gtr_dev->saved_icm_cfg1)
846 skip_phy_init = true;
847 else
848 skip_phy_init = false;
849
850 /* Update the skip_phy_init for all gtr_phy instances. */
851 for (i = 0; i < ARRAY_SIZE(gtr_dev->phys); i++)
852 gtr_dev->phys[i].skip_phy_init = skip_phy_init;
853
854 return 0;
855}
856
857static const struct dev_pm_ops xpsgtr_pm_ops = {
858 SET_SYSTEM_SLEEP_PM_OPS(xpsgtr_suspend, xpsgtr_resume)
859};
860
861/*
862 * Probe & Platform Driver
863 */
864
865static int xpsgtr_get_ref_clocks(struct xpsgtr_dev *gtr_dev)
866{
867 unsigned int refclk;
868
869 for (refclk = 0; refclk < ARRAY_SIZE(gtr_dev->refclk_sscs); ++refclk) {
870 unsigned long rate;
871 unsigned int i;
872 struct clk *clk;
873 char name[8];
874
875 snprintf(name, sizeof(name), "ref%u", refclk);
876 clk = devm_clk_get_optional(gtr_dev->dev, name);
877 if (IS_ERR(clk)) {
878 if (PTR_ERR(clk) != -EPROBE_DEFER)
879 dev_err(gtr_dev->dev,
880 "Failed to get reference clock %u: %ld\n",
881 refclk, PTR_ERR(clk));
882 return PTR_ERR(clk);
883 }
884
885 if (!clk)
886 continue;
887
888 /*
889 * Get the spread spectrum (SSC) settings for the reference
890 * clock rate.
891 */
892 rate = clk_get_rate(clk);
893
894 for (i = 0 ; i < ARRAY_SIZE(ssc_lookup); i++) {
895 if (rate == ssc_lookup[i].refclk_rate) {
896 gtr_dev->refclk_sscs[refclk] = &ssc_lookup[i];
897 break;
898 }
899 }
900
901 if (i == ARRAY_SIZE(ssc_lookup)) {
902 dev_err(gtr_dev->dev,
903 "Invalid rate %lu for reference clock %u\n",
904 rate, refclk);
905 return -EINVAL;
906 }
907 }
908
909 return 0;
910}
911
912static int xpsgtr_probe(struct platform_device *pdev)
913{
914 struct device_node *np = pdev->dev.of_node;
915 struct xpsgtr_dev *gtr_dev;
916 struct phy_provider *provider;
917 unsigned int port;
918 int ret;
919
920 gtr_dev = devm_kzalloc(&pdev->dev, sizeof(*gtr_dev), GFP_KERNEL);
921 if (!gtr_dev)
922 return -ENOMEM;
923
924 gtr_dev->dev = &pdev->dev;
925 platform_set_drvdata(pdev, gtr_dev);
926
927 mutex_init(>r_dev->gtr_mutex);
928
929 if (of_device_is_compatible(np, "xlnx,zynqmp-psgtr"))
930 gtr_dev->tx_term_fix =
931 of_property_read_bool(np, "xlnx,tx-termination-fix");
932
933 /* Acquire resources. */
934 gtr_dev->serdes = devm_platform_ioremap_resource_byname(pdev, "serdes");
935 if (IS_ERR(gtr_dev->serdes))
936 return PTR_ERR(gtr_dev->serdes);
937
938 gtr_dev->siou = devm_platform_ioremap_resource_byname(pdev, "siou");
939 if (IS_ERR(gtr_dev->siou))
940 return PTR_ERR(gtr_dev->siou);
941
942 ret = xpsgtr_get_ref_clocks(gtr_dev);
943 if (ret)
944 return ret;
945
946 /* Create PHYs. */
947 for (port = 0; port < ARRAY_SIZE(gtr_dev->phys); ++port) {
948 struct xpsgtr_phy *gtr_phy = >r_dev->phys[port];
949 struct phy *phy;
950
951 gtr_phy->lane = port;
952 gtr_phy->dev = gtr_dev;
953
954 phy = devm_phy_create(&pdev->dev, np, &xpsgtr_phyops);
955 if (IS_ERR(phy)) {
956 dev_err(&pdev->dev, "failed to create PHY\n");
957 return PTR_ERR(phy);
958 }
959
960 gtr_phy->phy = phy;
961 phy_set_drvdata(phy, gtr_phy);
962 }
963
964 /* Register the PHY provider. */
965 provider = devm_of_phy_provider_register(&pdev->dev, xpsgtr_xlate);
966 if (IS_ERR(provider)) {
967 dev_err(&pdev->dev, "registering provider failed\n");
968 return PTR_ERR(provider);
969 }
970 return 0;
971}
972
973static const struct of_device_id xpsgtr_of_match[] = {
974 { .compatible = "xlnx,zynqmp-psgtr", },
975 { .compatible = "xlnx,zynqmp-psgtr-v1.1", },
976 {},
977};
978MODULE_DEVICE_TABLE(of, xpsgtr_of_match);
979
980static struct platform_driver xpsgtr_driver = {
981 .probe = xpsgtr_probe,
982 .driver = {
983 .name = "xilinx-psgtr",
984 .of_match_table = xpsgtr_of_match,
985 .pm = &xpsgtr_pm_ops,
986 },
987};
988
989module_platform_driver(xpsgtr_driver);
990
991MODULE_AUTHOR("Xilinx Inc.");
992MODULE_LICENSE("GPL v2");
993MODULE_DESCRIPTION("Xilinx ZynqMP High speed Gigabit Transceiver");