1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Device access for Crystal Cove PMIC
  4 *
  5 * Copyright (C) 2013, 2014 Intel Corporation. All rights reserved.
  6 *
 
 
 
 
 
 
 
 
 
  7 * Author: Yang, Bin <bin.yang@intel.com>
  8 * Author: Zhu, Lejun <lejun.zhu@linux.intel.com>
  9 */
 10
 
 11#include <linux/interrupt.h>
 12#include <linux/regmap.h>
 13#include <linux/mfd/core.h>
 14#include <linux/mfd/intel_soc_pmic.h>
 15
 16#include "intel_soc_pmic_core.h"
 17
 18#define CRYSTAL_COVE_MAX_REGISTER	0xC6
 19
 20#define CRYSTAL_COVE_REG_IRQLVL1	0x02
 21#define CRYSTAL_COVE_REG_MIRQLVL1	0x0E
 22
 23#define CRYSTAL_COVE_IRQ_PWRSRC		0
 24#define CRYSTAL_COVE_IRQ_THRM		1
 25#define CRYSTAL_COVE_IRQ_BCU		2
 26#define CRYSTAL_COVE_IRQ_ADC		3
 27#define CRYSTAL_COVE_IRQ_CHGR		4
 28#define CRYSTAL_COVE_IRQ_GPIO		5
 29#define CRYSTAL_COVE_IRQ_VHDMIOCP	6
 30
 31static struct resource gpio_resources[] = {
 32	DEFINE_RES_IRQ_NAMED(CRYSTAL_COVE_IRQ_GPIO, "GPIO"),
 
 
 
 
 
 33};
 34
 35static struct resource pwrsrc_resources[] = {
 36	DEFINE_RES_IRQ_NAMED(CRYSTAL_COVE_IRQ_PWRSRC, "PWRSRC"),
 
 
 
 
 
 37};
 38
 39static struct resource adc_resources[] = {
 40	DEFINE_RES_IRQ_NAMED(CRYSTAL_COVE_IRQ_ADC, "ADC"),
 
 
 
 
 
 41};
 42
 43static struct resource thermal_resources[] = {
 44	DEFINE_RES_IRQ_NAMED(CRYSTAL_COVE_IRQ_THRM, "THERMAL"),
 
 
 
 
 
 45};
 46
 47static struct resource bcu_resources[] = {
 48	DEFINE_RES_IRQ_NAMED(CRYSTAL_COVE_IRQ_BCU, "BCU"),
 
 
 
 
 
 49};
 50
 51static struct mfd_cell crystal_cove_byt_dev[] = {
 52	{
 53		.name = "crystal_cove_pwrsrc",
 54		.num_resources = ARRAY_SIZE(pwrsrc_resources),
 55		.resources = pwrsrc_resources,
 56	},
 57	{
 58		.name = "crystal_cove_adc",
 59		.num_resources = ARRAY_SIZE(adc_resources),
 60		.resources = adc_resources,
 61	},
 62	{
 63		.name = "crystal_cove_thermal",
 64		.num_resources = ARRAY_SIZE(thermal_resources),
 65		.resources = thermal_resources,
 66	},
 67	{
 68		.name = "crystal_cove_bcu",
 69		.num_resources = ARRAY_SIZE(bcu_resources),
 70		.resources = bcu_resources,
 71	},
 72	{
 73		.name = "crystal_cove_gpio",
 74		.num_resources = ARRAY_SIZE(gpio_resources),
 75		.resources = gpio_resources,
 76	},
 77	{
 78		.name = "byt_crystal_cove_pmic",
 79	},
 80	{
 81		.name = "crystal_cove_pwm",
 82	},
 83};
 84
 85static struct mfd_cell crystal_cove_cht_dev[] = {
 86	{
 87		.name = "crystal_cove_gpio",
 88		.num_resources = ARRAY_SIZE(gpio_resources),
 89		.resources = gpio_resources,
 90	},
 91	{
 92		.name = "cht_crystal_cove_pmic",
 93	},
 94	{
 95		.name = "crystal_cove_pwm",
 96	},
 97};
 98
 99static const struct regmap_config crystal_cove_regmap_config = {
100	.reg_bits = 8,
101	.val_bits = 8,
102
103	.max_register = CRYSTAL_COVE_MAX_REGISTER,
104	.cache_type = REGCACHE_NONE,
105};
106
107static const struct regmap_irq crystal_cove_irqs[] = {
108	REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_PWRSRC, 0, BIT(CRYSTAL_COVE_IRQ_PWRSRC)),
109	REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_THRM, 0, BIT(CRYSTAL_COVE_IRQ_THRM)),
110	REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_BCU, 0, BIT(CRYSTAL_COVE_IRQ_BCU)),
111	REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_ADC, 0, BIT(CRYSTAL_COVE_IRQ_ADC)),
112	REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_CHGR, 0, BIT(CRYSTAL_COVE_IRQ_CHGR)),
113	REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_GPIO, 0, BIT(CRYSTAL_COVE_IRQ_GPIO)),
114	REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_VHDMIOCP, 0, BIT(CRYSTAL_COVE_IRQ_VHDMIOCP)),
 
 
 
 
 
 
 
 
 
 
 
 
 
 
115};
116
117static const struct regmap_irq_chip crystal_cove_irq_chip = {
118	.name = "Crystal Cove",
119	.irqs = crystal_cove_irqs,
120	.num_irqs = ARRAY_SIZE(crystal_cove_irqs),
121	.num_regs = 1,
122	.status_base = CRYSTAL_COVE_REG_IRQLVL1,
123	.mask_base = CRYSTAL_COVE_REG_MIRQLVL1,
124};
125
126struct intel_soc_pmic_config intel_soc_pmic_config_byt_crc = {
127	.irq_flags = IRQF_TRIGGER_RISING,
128	.cell_dev = crystal_cove_byt_dev,
129	.n_cell_devs = ARRAY_SIZE(crystal_cove_byt_dev),
130	.regmap_config = &crystal_cove_regmap_config,
131	.irq_chip = &crystal_cove_irq_chip,
132};
133
134struct intel_soc_pmic_config intel_soc_pmic_config_cht_crc = {
135	.irq_flags = IRQF_TRIGGER_RISING,
136	.cell_dev = crystal_cove_cht_dev,
137	.n_cell_devs = ARRAY_SIZE(crystal_cove_cht_dev),
138	.regmap_config = &crystal_cove_regmap_config,
139	.irq_chip = &crystal_cove_irq_chip,
140};

 
  1/*
  2 * intel_soc_pmic_crc.c - Device access for Crystal Cove PMIC
  3 *
  4 * Copyright (C) 2013, 2014 Intel Corporation. All rights reserved.
  5 *
  6 * This program is free software; you can redistribute it and/or
  7 * modify it under the terms of the GNU General Public License version
  8 * 2 as published by the Free Software Foundation.
  9 *
 10 * This program is distributed in the hope that it will be useful,
 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 13 * GNU General Public License for more details.
 14 *
 15 * Author: Yang, Bin <bin.yang@intel.com>
 16 * Author: Zhu, Lejun <lejun.zhu@linux.intel.com>
 17 */
 18
 19#include <linux/mfd/core.h>
 20#include <linux/interrupt.h>
 21#include <linux/regmap.h>
 
 22#include <linux/mfd/intel_soc_pmic.h>
 
 23#include "intel_soc_pmic_core.h"
 24
 25#define CRYSTAL_COVE_MAX_REGISTER	0xC6
 26
 27#define CRYSTAL_COVE_REG_IRQLVL1	0x02
 28#define CRYSTAL_COVE_REG_MIRQLVL1	0x0E
 29
 30#define CRYSTAL_COVE_IRQ_PWRSRC		0
 31#define CRYSTAL_COVE_IRQ_THRM		1
 32#define CRYSTAL_COVE_IRQ_BCU		2
 33#define CRYSTAL_COVE_IRQ_ADC		3
 34#define CRYSTAL_COVE_IRQ_CHGR		4
 35#define CRYSTAL_COVE_IRQ_GPIO		5
 36#define CRYSTAL_COVE_IRQ_VHDMIOCP	6
 37
 38static struct resource gpio_resources[] = {
 39	{
 40		.name	= "GPIO",
 41		.start	= CRYSTAL_COVE_IRQ_GPIO,
 42		.end	= CRYSTAL_COVE_IRQ_GPIO,
 43		.flags	= IORESOURCE_IRQ,
 44	},
 45};
 46
 47static struct resource pwrsrc_resources[] = {
 48	{
 49		.name  = "PWRSRC",
 50		.start = CRYSTAL_COVE_IRQ_PWRSRC,
 51		.end   = CRYSTAL_COVE_IRQ_PWRSRC,
 52		.flags = IORESOURCE_IRQ,
 53	},
 54};
 55
 56static struct resource adc_resources[] = {
 57	{
 58		.name  = "ADC",
 59		.start = CRYSTAL_COVE_IRQ_ADC,
 60		.end   = CRYSTAL_COVE_IRQ_ADC,
 61		.flags = IORESOURCE_IRQ,
 62	},
 63};
 64
 65static struct resource thermal_resources[] = {
 66	{
 67		.name  = "THERMAL",
 68		.start = CRYSTAL_COVE_IRQ_THRM,
 69		.end   = CRYSTAL_COVE_IRQ_THRM,
 70		.flags = IORESOURCE_IRQ,
 71	},
 72};
 73
 74static struct resource bcu_resources[] = {
 75	{
 76		.name  = "BCU",
 77		.start = CRYSTAL_COVE_IRQ_BCU,
 78		.end   = CRYSTAL_COVE_IRQ_BCU,
 79		.flags = IORESOURCE_IRQ,
 80	},
 81};
 82
 83static struct mfd_cell crystal_cove_byt_dev[] = {
 84	{
 85		.name = "crystal_cove_pwrsrc",
 86		.num_resources = ARRAY_SIZE(pwrsrc_resources),
 87		.resources = pwrsrc_resources,
 88	},
 89	{
 90		.name = "crystal_cove_adc",
 91		.num_resources = ARRAY_SIZE(adc_resources),
 92		.resources = adc_resources,
 93	},
 94	{
 95		.name = "crystal_cove_thermal",
 96		.num_resources = ARRAY_SIZE(thermal_resources),
 97		.resources = thermal_resources,
 98	},
 99	{
100		.name = "crystal_cove_bcu",
101		.num_resources = ARRAY_SIZE(bcu_resources),
102		.resources = bcu_resources,
103	},
104	{
105		.name = "crystal_cove_gpio",
106		.num_resources = ARRAY_SIZE(gpio_resources),
107		.resources = gpio_resources,
108	},
109	{
110		.name = "crystal_cove_pmic",
111	},
112	{
113		.name = "crystal_cove_pwm",
114	},
115};
116
117static struct mfd_cell crystal_cove_cht_dev[] = {
118	{
119		.name = "crystal_cove_gpio",
120		.num_resources = ARRAY_SIZE(gpio_resources),
121		.resources = gpio_resources,
122	},
123	{
 
 
 
124		.name = "crystal_cove_pwm",
125	},
126};
127
128static const struct regmap_config crystal_cove_regmap_config = {
129	.reg_bits = 8,
130	.val_bits = 8,
131
132	.max_register = CRYSTAL_COVE_MAX_REGISTER,
133	.cache_type = REGCACHE_NONE,
134};
135
136static const struct regmap_irq crystal_cove_irqs[] = {
137	[CRYSTAL_COVE_IRQ_PWRSRC] = {
138		.mask = BIT(CRYSTAL_COVE_IRQ_PWRSRC),
139	},
140	[CRYSTAL_COVE_IRQ_THRM] = {
141		.mask = BIT(CRYSTAL_COVE_IRQ_THRM),
142	},
143	[CRYSTAL_COVE_IRQ_BCU] = {
144		.mask = BIT(CRYSTAL_COVE_IRQ_BCU),
145	},
146	[CRYSTAL_COVE_IRQ_ADC] = {
147		.mask = BIT(CRYSTAL_COVE_IRQ_ADC),
148	},
149	[CRYSTAL_COVE_IRQ_CHGR] = {
150		.mask = BIT(CRYSTAL_COVE_IRQ_CHGR),
151	},
152	[CRYSTAL_COVE_IRQ_GPIO] = {
153		.mask = BIT(CRYSTAL_COVE_IRQ_GPIO),
154	},
155	[CRYSTAL_COVE_IRQ_VHDMIOCP] = {
156		.mask = BIT(CRYSTAL_COVE_IRQ_VHDMIOCP),
157	},
158};
159
160static const struct regmap_irq_chip crystal_cove_irq_chip = {
161	.name = "Crystal Cove",
162	.irqs = crystal_cove_irqs,
163	.num_irqs = ARRAY_SIZE(crystal_cove_irqs),
164	.num_regs = 1,
165	.status_base = CRYSTAL_COVE_REG_IRQLVL1,
166	.mask_base = CRYSTAL_COVE_REG_MIRQLVL1,
167};
168
169struct intel_soc_pmic_config intel_soc_pmic_config_byt_crc = {
170	.irq_flags = IRQF_TRIGGER_RISING,
171	.cell_dev = crystal_cove_byt_dev,
172	.n_cell_devs = ARRAY_SIZE(crystal_cove_byt_dev),
173	.regmap_config = &crystal_cove_regmap_config,
174	.irq_chip = &crystal_cove_irq_chip,
175};
176
177struct intel_soc_pmic_config intel_soc_pmic_config_cht_crc = {
178	.irq_flags = IRQF_TRIGGER_RISING,
179	.cell_dev = crystal_cove_cht_dev,
180	.n_cell_devs = ARRAY_SIZE(crystal_cove_cht_dev),
181	.regmap_config = &crystal_cove_regmap_config,
182	.irq_chip = &crystal_cove_irq_chip,
183};