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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved.
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 */
6
7#include <linux/acpi.h>
8#include <linux/acpi_iort.h>
9#include <linux/bitfield.h>
10#include <linux/bitmap.h>
11#include <linux/cpu.h>
12#include <linux/crash_dump.h>
13#include <linux/delay.h>
14#include <linux/dma-iommu.h>
15#include <linux/efi.h>
16#include <linux/interrupt.h>
17#include <linux/iopoll.h>
18#include <linux/irqdomain.h>
19#include <linux/list.h>
20#include <linux/log2.h>
21#include <linux/memblock.h>
22#include <linux/mm.h>
23#include <linux/msi.h>
24#include <linux/of.h>
25#include <linux/of_address.h>
26#include <linux/of_irq.h>
27#include <linux/of_pci.h>
28#include <linux/of_platform.h>
29#include <linux/percpu.h>
30#include <linux/slab.h>
31#include <linux/syscore_ops.h>
32
33#include <linux/irqchip.h>
34#include <linux/irqchip/arm-gic-v3.h>
35#include <linux/irqchip/arm-gic-v4.h>
36
37#include <asm/cputype.h>
38#include <asm/exception.h>
39
40#include "irq-gic-common.h"
41
42#define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1ULL << 0)
43#define ITS_FLAGS_WORKAROUND_CAVIUM_22375 (1ULL << 1)
44#define ITS_FLAGS_WORKAROUND_CAVIUM_23144 (1ULL << 2)
45#define ITS_FLAGS_SAVE_SUSPEND_STATE (1ULL << 3)
46
47#define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING (1 << 0)
48#define RDIST_FLAGS_RD_TABLES_PREALLOCATED (1 << 1)
49
50static u32 lpi_id_bits;
51
52/*
53 * We allocate memory for PROPBASE to cover 2 ^ lpi_id_bits LPIs to
54 * deal with (one configuration byte per interrupt). PENDBASE has to
55 * be 64kB aligned (one bit per LPI, plus 8192 bits for SPI/PPI/SGI).
56 */
57#define LPI_NRBITS lpi_id_bits
58#define LPI_PROPBASE_SZ ALIGN(BIT(LPI_NRBITS), SZ_64K)
59#define LPI_PENDBASE_SZ ALIGN(BIT(LPI_NRBITS) / 8, SZ_64K)
60
61#define LPI_PROP_DEFAULT_PRIO GICD_INT_DEF_PRI
62
63/*
64 * Collection structure - just an ID, and a redistributor address to
65 * ping. We use one per CPU as a bag of interrupts assigned to this
66 * CPU.
67 */
68struct its_collection {
69 u64 target_address;
70 u16 col_id;
71};
72
73/*
74 * The ITS_BASER structure - contains memory information, cached
75 * value of BASER register configuration and ITS page size.
76 */
77struct its_baser {
78 void *base;
79 u64 val;
80 u32 order;
81 u32 psz;
82};
83
84struct its_device;
85
86/*
87 * The ITS structure - contains most of the infrastructure, with the
88 * top-level MSI domain, the command queue, the collections, and the
89 * list of devices writing to it.
90 *
91 * dev_alloc_lock has to be taken for device allocations, while the
92 * spinlock must be taken to parse data structures such as the device
93 * list.
94 */
95struct its_node {
96 raw_spinlock_t lock;
97 struct mutex dev_alloc_lock;
98 struct list_head entry;
99 void __iomem *base;
100 void __iomem *sgir_base;
101 phys_addr_t phys_base;
102 struct its_cmd_block *cmd_base;
103 struct its_cmd_block *cmd_write;
104 struct its_baser tables[GITS_BASER_NR_REGS];
105 struct its_collection *collections;
106 struct fwnode_handle *fwnode_handle;
107 u64 (*get_msi_base)(struct its_device *its_dev);
108 u64 typer;
109 u64 cbaser_save;
110 u32 ctlr_save;
111 u32 mpidr;
112 struct list_head its_device_list;
113 u64 flags;
114 unsigned long list_nr;
115 int numa_node;
116 unsigned int msi_domain_flags;
117 u32 pre_its_base; /* for Socionext Synquacer */
118 int vlpi_redist_offset;
119};
120
121#define is_v4(its) (!!((its)->typer & GITS_TYPER_VLPIS))
122#define is_v4_1(its) (!!((its)->typer & GITS_TYPER_VMAPP))
123#define device_ids(its) (FIELD_GET(GITS_TYPER_DEVBITS, (its)->typer) + 1)
124
125#define ITS_ITT_ALIGN SZ_256
126
127/* The maximum number of VPEID bits supported by VLPI commands */
128#define ITS_MAX_VPEID_BITS \
129 ({ \
130 int nvpeid = 16; \
131 if (gic_rdists->has_rvpeid && \
132 gic_rdists->gicd_typer2 & GICD_TYPER2_VIL) \
133 nvpeid = 1 + (gic_rdists->gicd_typer2 & \
134 GICD_TYPER2_VID); \
135 \
136 nvpeid; \
137 })
138#define ITS_MAX_VPEID (1 << (ITS_MAX_VPEID_BITS))
139
140/* Convert page order to size in bytes */
141#define PAGE_ORDER_TO_SIZE(o) (PAGE_SIZE << (o))
142
143struct event_lpi_map {
144 unsigned long *lpi_map;
145 u16 *col_map;
146 irq_hw_number_t lpi_base;
147 int nr_lpis;
148 raw_spinlock_t vlpi_lock;
149 struct its_vm *vm;
150 struct its_vlpi_map *vlpi_maps;
151 int nr_vlpis;
152};
153
154/*
155 * The ITS view of a device - belongs to an ITS, owns an interrupt
156 * translation table, and a list of interrupts. If it some of its
157 * LPIs are injected into a guest (GICv4), the event_map.vm field
158 * indicates which one.
159 */
160struct its_device {
161 struct list_head entry;
162 struct its_node *its;
163 struct event_lpi_map event_map;
164 void *itt;
165 u32 nr_ites;
166 u32 device_id;
167 bool shared;
168};
169
170static struct {
171 raw_spinlock_t lock;
172 struct its_device *dev;
173 struct its_vpe **vpes;
174 int next_victim;
175} vpe_proxy;
176
177struct cpu_lpi_count {
178 atomic_t managed;
179 atomic_t unmanaged;
180};
181
182static DEFINE_PER_CPU(struct cpu_lpi_count, cpu_lpi_count);
183
184static LIST_HEAD(its_nodes);
185static DEFINE_RAW_SPINLOCK(its_lock);
186static struct rdists *gic_rdists;
187static struct irq_domain *its_parent;
188
189static unsigned long its_list_map;
190static u16 vmovp_seq_num;
191static DEFINE_RAW_SPINLOCK(vmovp_lock);
192
193static DEFINE_IDA(its_vpeid_ida);
194
195#define gic_data_rdist() (raw_cpu_ptr(gic_rdists->rdist))
196#define gic_data_rdist_cpu(cpu) (per_cpu_ptr(gic_rdists->rdist, cpu))
197#define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base)
198#define gic_data_rdist_vlpi_base() (gic_data_rdist_rd_base() + SZ_128K)
199
200/*
201 * Skip ITSs that have no vLPIs mapped, unless we're on GICv4.1, as we
202 * always have vSGIs mapped.
203 */
204static bool require_its_list_vmovp(struct its_vm *vm, struct its_node *its)
205{
206 return (gic_rdists->has_rvpeid || vm->vlpi_count[its->list_nr]);
207}
208
209static u16 get_its_list(struct its_vm *vm)
210{
211 struct its_node *its;
212 unsigned long its_list = 0;
213
214 list_for_each_entry(its, &its_nodes, entry) {
215 if (!is_v4(its))
216 continue;
217
218 if (require_its_list_vmovp(vm, its))
219 __set_bit(its->list_nr, &its_list);
220 }
221
222 return (u16)its_list;
223}
224
225static inline u32 its_get_event_id(struct irq_data *d)
226{
227 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
228 return d->hwirq - its_dev->event_map.lpi_base;
229}
230
231static struct its_collection *dev_event_to_col(struct its_device *its_dev,
232 u32 event)
233{
234 struct its_node *its = its_dev->its;
235
236 return its->collections + its_dev->event_map.col_map[event];
237}
238
239static struct its_vlpi_map *dev_event_to_vlpi_map(struct its_device *its_dev,
240 u32 event)
241{
242 if (WARN_ON_ONCE(event >= its_dev->event_map.nr_lpis))
243 return NULL;
244
245 return &its_dev->event_map.vlpi_maps[event];
246}
247
248static struct its_vlpi_map *get_vlpi_map(struct irq_data *d)
249{
250 if (irqd_is_forwarded_to_vcpu(d)) {
251 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
252 u32 event = its_get_event_id(d);
253
254 return dev_event_to_vlpi_map(its_dev, event);
255 }
256
257 return NULL;
258}
259
260static int vpe_to_cpuid_lock(struct its_vpe *vpe, unsigned long *flags)
261{
262 raw_spin_lock_irqsave(&vpe->vpe_lock, *flags);
263 return vpe->col_idx;
264}
265
266static void vpe_to_cpuid_unlock(struct its_vpe *vpe, unsigned long flags)
267{
268 raw_spin_unlock_irqrestore(&vpe->vpe_lock, flags);
269}
270
271static int irq_to_cpuid_lock(struct irq_data *d, unsigned long *flags)
272{
273 struct its_vlpi_map *map = get_vlpi_map(d);
274 int cpu;
275
276 if (map) {
277 cpu = vpe_to_cpuid_lock(map->vpe, flags);
278 } else {
279 /* Physical LPIs are already locked via the irq_desc lock */
280 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
281 cpu = its_dev->event_map.col_map[its_get_event_id(d)];
282 /* Keep GCC quiet... */
283 *flags = 0;
284 }
285
286 return cpu;
287}
288
289static void irq_to_cpuid_unlock(struct irq_data *d, unsigned long flags)
290{
291 struct its_vlpi_map *map = get_vlpi_map(d);
292
293 if (map)
294 vpe_to_cpuid_unlock(map->vpe, flags);
295}
296
297static struct its_collection *valid_col(struct its_collection *col)
298{
299 if (WARN_ON_ONCE(col->target_address & GENMASK_ULL(15, 0)))
300 return NULL;
301
302 return col;
303}
304
305static struct its_vpe *valid_vpe(struct its_node *its, struct its_vpe *vpe)
306{
307 if (valid_col(its->collections + vpe->col_idx))
308 return vpe;
309
310 return NULL;
311}
312
313/*
314 * ITS command descriptors - parameters to be encoded in a command
315 * block.
316 */
317struct its_cmd_desc {
318 union {
319 struct {
320 struct its_device *dev;
321 u32 event_id;
322 } its_inv_cmd;
323
324 struct {
325 struct its_device *dev;
326 u32 event_id;
327 } its_clear_cmd;
328
329 struct {
330 struct its_device *dev;
331 u32 event_id;
332 } its_int_cmd;
333
334 struct {
335 struct its_device *dev;
336 int valid;
337 } its_mapd_cmd;
338
339 struct {
340 struct its_collection *col;
341 int valid;
342 } its_mapc_cmd;
343
344 struct {
345 struct its_device *dev;
346 u32 phys_id;
347 u32 event_id;
348 } its_mapti_cmd;
349
350 struct {
351 struct its_device *dev;
352 struct its_collection *col;
353 u32 event_id;
354 } its_movi_cmd;
355
356 struct {
357 struct its_device *dev;
358 u32 event_id;
359 } its_discard_cmd;
360
361 struct {
362 struct its_collection *col;
363 } its_invall_cmd;
364
365 struct {
366 struct its_vpe *vpe;
367 } its_vinvall_cmd;
368
369 struct {
370 struct its_vpe *vpe;
371 struct its_collection *col;
372 bool valid;
373 } its_vmapp_cmd;
374
375 struct {
376 struct its_vpe *vpe;
377 struct its_device *dev;
378 u32 virt_id;
379 u32 event_id;
380 bool db_enabled;
381 } its_vmapti_cmd;
382
383 struct {
384 struct its_vpe *vpe;
385 struct its_device *dev;
386 u32 event_id;
387 bool db_enabled;
388 } its_vmovi_cmd;
389
390 struct {
391 struct its_vpe *vpe;
392 struct its_collection *col;
393 u16 seq_num;
394 u16 its_list;
395 } its_vmovp_cmd;
396
397 struct {
398 struct its_vpe *vpe;
399 } its_invdb_cmd;
400
401 struct {
402 struct its_vpe *vpe;
403 u8 sgi;
404 u8 priority;
405 bool enable;
406 bool group;
407 bool clear;
408 } its_vsgi_cmd;
409 };
410};
411
412/*
413 * The ITS command block, which is what the ITS actually parses.
414 */
415struct its_cmd_block {
416 union {
417 u64 raw_cmd[4];
418 __le64 raw_cmd_le[4];
419 };
420};
421
422#define ITS_CMD_QUEUE_SZ SZ_64K
423#define ITS_CMD_QUEUE_NR_ENTRIES (ITS_CMD_QUEUE_SZ / sizeof(struct its_cmd_block))
424
425typedef struct its_collection *(*its_cmd_builder_t)(struct its_node *,
426 struct its_cmd_block *,
427 struct its_cmd_desc *);
428
429typedef struct its_vpe *(*its_cmd_vbuilder_t)(struct its_node *,
430 struct its_cmd_block *,
431 struct its_cmd_desc *);
432
433static void its_mask_encode(u64 *raw_cmd, u64 val, int h, int l)
434{
435 u64 mask = GENMASK_ULL(h, l);
436 *raw_cmd &= ~mask;
437 *raw_cmd |= (val << l) & mask;
438}
439
440static void its_encode_cmd(struct its_cmd_block *cmd, u8 cmd_nr)
441{
442 its_mask_encode(&cmd->raw_cmd[0], cmd_nr, 7, 0);
443}
444
445static void its_encode_devid(struct its_cmd_block *cmd, u32 devid)
446{
447 its_mask_encode(&cmd->raw_cmd[0], devid, 63, 32);
448}
449
450static void its_encode_event_id(struct its_cmd_block *cmd, u32 id)
451{
452 its_mask_encode(&cmd->raw_cmd[1], id, 31, 0);
453}
454
455static void its_encode_phys_id(struct its_cmd_block *cmd, u32 phys_id)
456{
457 its_mask_encode(&cmd->raw_cmd[1], phys_id, 63, 32);
458}
459
460static void its_encode_size(struct its_cmd_block *cmd, u8 size)
461{
462 its_mask_encode(&cmd->raw_cmd[1], size, 4, 0);
463}
464
465static void its_encode_itt(struct its_cmd_block *cmd, u64 itt_addr)
466{
467 its_mask_encode(&cmd->raw_cmd[2], itt_addr >> 8, 51, 8);
468}
469
470static void its_encode_valid(struct its_cmd_block *cmd, int valid)
471{
472 its_mask_encode(&cmd->raw_cmd[2], !!valid, 63, 63);
473}
474
475static void its_encode_target(struct its_cmd_block *cmd, u64 target_addr)
476{
477 its_mask_encode(&cmd->raw_cmd[2], target_addr >> 16, 51, 16);
478}
479
480static void its_encode_collection(struct its_cmd_block *cmd, u16 col)
481{
482 its_mask_encode(&cmd->raw_cmd[2], col, 15, 0);
483}
484
485static void its_encode_vpeid(struct its_cmd_block *cmd, u16 vpeid)
486{
487 its_mask_encode(&cmd->raw_cmd[1], vpeid, 47, 32);
488}
489
490static void its_encode_virt_id(struct its_cmd_block *cmd, u32 virt_id)
491{
492 its_mask_encode(&cmd->raw_cmd[2], virt_id, 31, 0);
493}
494
495static void its_encode_db_phys_id(struct its_cmd_block *cmd, u32 db_phys_id)
496{
497 its_mask_encode(&cmd->raw_cmd[2], db_phys_id, 63, 32);
498}
499
500static void its_encode_db_valid(struct its_cmd_block *cmd, bool db_valid)
501{
502 its_mask_encode(&cmd->raw_cmd[2], db_valid, 0, 0);
503}
504
505static void its_encode_seq_num(struct its_cmd_block *cmd, u16 seq_num)
506{
507 its_mask_encode(&cmd->raw_cmd[0], seq_num, 47, 32);
508}
509
510static void its_encode_its_list(struct its_cmd_block *cmd, u16 its_list)
511{
512 its_mask_encode(&cmd->raw_cmd[1], its_list, 15, 0);
513}
514
515static void its_encode_vpt_addr(struct its_cmd_block *cmd, u64 vpt_pa)
516{
517 its_mask_encode(&cmd->raw_cmd[3], vpt_pa >> 16, 51, 16);
518}
519
520static void its_encode_vpt_size(struct its_cmd_block *cmd, u8 vpt_size)
521{
522 its_mask_encode(&cmd->raw_cmd[3], vpt_size, 4, 0);
523}
524
525static void its_encode_vconf_addr(struct its_cmd_block *cmd, u64 vconf_pa)
526{
527 its_mask_encode(&cmd->raw_cmd[0], vconf_pa >> 16, 51, 16);
528}
529
530static void its_encode_alloc(struct its_cmd_block *cmd, bool alloc)
531{
532 its_mask_encode(&cmd->raw_cmd[0], alloc, 8, 8);
533}
534
535static void its_encode_ptz(struct its_cmd_block *cmd, bool ptz)
536{
537 its_mask_encode(&cmd->raw_cmd[0], ptz, 9, 9);
538}
539
540static void its_encode_vmapp_default_db(struct its_cmd_block *cmd,
541 u32 vpe_db_lpi)
542{
543 its_mask_encode(&cmd->raw_cmd[1], vpe_db_lpi, 31, 0);
544}
545
546static void its_encode_vmovp_default_db(struct its_cmd_block *cmd,
547 u32 vpe_db_lpi)
548{
549 its_mask_encode(&cmd->raw_cmd[3], vpe_db_lpi, 31, 0);
550}
551
552static void its_encode_db(struct its_cmd_block *cmd, bool db)
553{
554 its_mask_encode(&cmd->raw_cmd[2], db, 63, 63);
555}
556
557static void its_encode_sgi_intid(struct its_cmd_block *cmd, u8 sgi)
558{
559 its_mask_encode(&cmd->raw_cmd[0], sgi, 35, 32);
560}
561
562static void its_encode_sgi_priority(struct its_cmd_block *cmd, u8 prio)
563{
564 its_mask_encode(&cmd->raw_cmd[0], prio >> 4, 23, 20);
565}
566
567static void its_encode_sgi_group(struct its_cmd_block *cmd, bool grp)
568{
569 its_mask_encode(&cmd->raw_cmd[0], grp, 10, 10);
570}
571
572static void its_encode_sgi_clear(struct its_cmd_block *cmd, bool clr)
573{
574 its_mask_encode(&cmd->raw_cmd[0], clr, 9, 9);
575}
576
577static void its_encode_sgi_enable(struct its_cmd_block *cmd, bool en)
578{
579 its_mask_encode(&cmd->raw_cmd[0], en, 8, 8);
580}
581
582static inline void its_fixup_cmd(struct its_cmd_block *cmd)
583{
584 /* Let's fixup BE commands */
585 cmd->raw_cmd_le[0] = cpu_to_le64(cmd->raw_cmd[0]);
586 cmd->raw_cmd_le[1] = cpu_to_le64(cmd->raw_cmd[1]);
587 cmd->raw_cmd_le[2] = cpu_to_le64(cmd->raw_cmd[2]);
588 cmd->raw_cmd_le[3] = cpu_to_le64(cmd->raw_cmd[3]);
589}
590
591static struct its_collection *its_build_mapd_cmd(struct its_node *its,
592 struct its_cmd_block *cmd,
593 struct its_cmd_desc *desc)
594{
595 unsigned long itt_addr;
596 u8 size = ilog2(desc->its_mapd_cmd.dev->nr_ites);
597
598 itt_addr = virt_to_phys(desc->its_mapd_cmd.dev->itt);
599 itt_addr = ALIGN(itt_addr, ITS_ITT_ALIGN);
600
601 its_encode_cmd(cmd, GITS_CMD_MAPD);
602 its_encode_devid(cmd, desc->its_mapd_cmd.dev->device_id);
603 its_encode_size(cmd, size - 1);
604 its_encode_itt(cmd, itt_addr);
605 its_encode_valid(cmd, desc->its_mapd_cmd.valid);
606
607 its_fixup_cmd(cmd);
608
609 return NULL;
610}
611
612static struct its_collection *its_build_mapc_cmd(struct its_node *its,
613 struct its_cmd_block *cmd,
614 struct its_cmd_desc *desc)
615{
616 its_encode_cmd(cmd, GITS_CMD_MAPC);
617 its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id);
618 its_encode_target(cmd, desc->its_mapc_cmd.col->target_address);
619 its_encode_valid(cmd, desc->its_mapc_cmd.valid);
620
621 its_fixup_cmd(cmd);
622
623 return desc->its_mapc_cmd.col;
624}
625
626static struct its_collection *its_build_mapti_cmd(struct its_node *its,
627 struct its_cmd_block *cmd,
628 struct its_cmd_desc *desc)
629{
630 struct its_collection *col;
631
632 col = dev_event_to_col(desc->its_mapti_cmd.dev,
633 desc->its_mapti_cmd.event_id);
634
635 its_encode_cmd(cmd, GITS_CMD_MAPTI);
636 its_encode_devid(cmd, desc->its_mapti_cmd.dev->device_id);
637 its_encode_event_id(cmd, desc->its_mapti_cmd.event_id);
638 its_encode_phys_id(cmd, desc->its_mapti_cmd.phys_id);
639 its_encode_collection(cmd, col->col_id);
640
641 its_fixup_cmd(cmd);
642
643 return valid_col(col);
644}
645
646static struct its_collection *its_build_movi_cmd(struct its_node *its,
647 struct its_cmd_block *cmd,
648 struct its_cmd_desc *desc)
649{
650 struct its_collection *col;
651
652 col = dev_event_to_col(desc->its_movi_cmd.dev,
653 desc->its_movi_cmd.event_id);
654
655 its_encode_cmd(cmd, GITS_CMD_MOVI);
656 its_encode_devid(cmd, desc->its_movi_cmd.dev->device_id);
657 its_encode_event_id(cmd, desc->its_movi_cmd.event_id);
658 its_encode_collection(cmd, desc->its_movi_cmd.col->col_id);
659
660 its_fixup_cmd(cmd);
661
662 return valid_col(col);
663}
664
665static struct its_collection *its_build_discard_cmd(struct its_node *its,
666 struct its_cmd_block *cmd,
667 struct its_cmd_desc *desc)
668{
669 struct its_collection *col;
670
671 col = dev_event_to_col(desc->its_discard_cmd.dev,
672 desc->its_discard_cmd.event_id);
673
674 its_encode_cmd(cmd, GITS_CMD_DISCARD);
675 its_encode_devid(cmd, desc->its_discard_cmd.dev->device_id);
676 its_encode_event_id(cmd, desc->its_discard_cmd.event_id);
677
678 its_fixup_cmd(cmd);
679
680 return valid_col(col);
681}
682
683static struct its_collection *its_build_inv_cmd(struct its_node *its,
684 struct its_cmd_block *cmd,
685 struct its_cmd_desc *desc)
686{
687 struct its_collection *col;
688
689 col = dev_event_to_col(desc->its_inv_cmd.dev,
690 desc->its_inv_cmd.event_id);
691
692 its_encode_cmd(cmd, GITS_CMD_INV);
693 its_encode_devid(cmd, desc->its_inv_cmd.dev->device_id);
694 its_encode_event_id(cmd, desc->its_inv_cmd.event_id);
695
696 its_fixup_cmd(cmd);
697
698 return valid_col(col);
699}
700
701static struct its_collection *its_build_int_cmd(struct its_node *its,
702 struct its_cmd_block *cmd,
703 struct its_cmd_desc *desc)
704{
705 struct its_collection *col;
706
707 col = dev_event_to_col(desc->its_int_cmd.dev,
708 desc->its_int_cmd.event_id);
709
710 its_encode_cmd(cmd, GITS_CMD_INT);
711 its_encode_devid(cmd, desc->its_int_cmd.dev->device_id);
712 its_encode_event_id(cmd, desc->its_int_cmd.event_id);
713
714 its_fixup_cmd(cmd);
715
716 return valid_col(col);
717}
718
719static struct its_collection *its_build_clear_cmd(struct its_node *its,
720 struct its_cmd_block *cmd,
721 struct its_cmd_desc *desc)
722{
723 struct its_collection *col;
724
725 col = dev_event_to_col(desc->its_clear_cmd.dev,
726 desc->its_clear_cmd.event_id);
727
728 its_encode_cmd(cmd, GITS_CMD_CLEAR);
729 its_encode_devid(cmd, desc->its_clear_cmd.dev->device_id);
730 its_encode_event_id(cmd, desc->its_clear_cmd.event_id);
731
732 its_fixup_cmd(cmd);
733
734 return valid_col(col);
735}
736
737static struct its_collection *its_build_invall_cmd(struct its_node *its,
738 struct its_cmd_block *cmd,
739 struct its_cmd_desc *desc)
740{
741 its_encode_cmd(cmd, GITS_CMD_INVALL);
742 its_encode_collection(cmd, desc->its_invall_cmd.col->col_id);
743
744 its_fixup_cmd(cmd);
745
746 return NULL;
747}
748
749static struct its_vpe *its_build_vinvall_cmd(struct its_node *its,
750 struct its_cmd_block *cmd,
751 struct its_cmd_desc *desc)
752{
753 its_encode_cmd(cmd, GITS_CMD_VINVALL);
754 its_encode_vpeid(cmd, desc->its_vinvall_cmd.vpe->vpe_id);
755
756 its_fixup_cmd(cmd);
757
758 return valid_vpe(its, desc->its_vinvall_cmd.vpe);
759}
760
761static struct its_vpe *its_build_vmapp_cmd(struct its_node *its,
762 struct its_cmd_block *cmd,
763 struct its_cmd_desc *desc)
764{
765 unsigned long vpt_addr, vconf_addr;
766 u64 target;
767 bool alloc;
768
769 its_encode_cmd(cmd, GITS_CMD_VMAPP);
770 its_encode_vpeid(cmd, desc->its_vmapp_cmd.vpe->vpe_id);
771 its_encode_valid(cmd, desc->its_vmapp_cmd.valid);
772
773 if (!desc->its_vmapp_cmd.valid) {
774 if (is_v4_1(its)) {
775 alloc = !atomic_dec_return(&desc->its_vmapp_cmd.vpe->vmapp_count);
776 its_encode_alloc(cmd, alloc);
777 }
778
779 goto out;
780 }
781
782 vpt_addr = virt_to_phys(page_address(desc->its_vmapp_cmd.vpe->vpt_page));
783 target = desc->its_vmapp_cmd.col->target_address + its->vlpi_redist_offset;
784
785 its_encode_target(cmd, target);
786 its_encode_vpt_addr(cmd, vpt_addr);
787 its_encode_vpt_size(cmd, LPI_NRBITS - 1);
788
789 if (!is_v4_1(its))
790 goto out;
791
792 vconf_addr = virt_to_phys(page_address(desc->its_vmapp_cmd.vpe->its_vm->vprop_page));
793
794 alloc = !atomic_fetch_inc(&desc->its_vmapp_cmd.vpe->vmapp_count);
795
796 its_encode_alloc(cmd, alloc);
797
798 /* We can only signal PTZ when alloc==1. Why do we have two bits? */
799 its_encode_ptz(cmd, alloc);
800 its_encode_vconf_addr(cmd, vconf_addr);
801 its_encode_vmapp_default_db(cmd, desc->its_vmapp_cmd.vpe->vpe_db_lpi);
802
803out:
804 its_fixup_cmd(cmd);
805
806 return valid_vpe(its, desc->its_vmapp_cmd.vpe);
807}
808
809static struct its_vpe *its_build_vmapti_cmd(struct its_node *its,
810 struct its_cmd_block *cmd,
811 struct its_cmd_desc *desc)
812{
813 u32 db;
814
815 if (!is_v4_1(its) && desc->its_vmapti_cmd.db_enabled)
816 db = desc->its_vmapti_cmd.vpe->vpe_db_lpi;
817 else
818 db = 1023;
819
820 its_encode_cmd(cmd, GITS_CMD_VMAPTI);
821 its_encode_devid(cmd, desc->its_vmapti_cmd.dev->device_id);
822 its_encode_vpeid(cmd, desc->its_vmapti_cmd.vpe->vpe_id);
823 its_encode_event_id(cmd, desc->its_vmapti_cmd.event_id);
824 its_encode_db_phys_id(cmd, db);
825 its_encode_virt_id(cmd, desc->its_vmapti_cmd.virt_id);
826
827 its_fixup_cmd(cmd);
828
829 return valid_vpe(its, desc->its_vmapti_cmd.vpe);
830}
831
832static struct its_vpe *its_build_vmovi_cmd(struct its_node *its,
833 struct its_cmd_block *cmd,
834 struct its_cmd_desc *desc)
835{
836 u32 db;
837
838 if (!is_v4_1(its) && desc->its_vmovi_cmd.db_enabled)
839 db = desc->its_vmovi_cmd.vpe->vpe_db_lpi;
840 else
841 db = 1023;
842
843 its_encode_cmd(cmd, GITS_CMD_VMOVI);
844 its_encode_devid(cmd, desc->its_vmovi_cmd.dev->device_id);
845 its_encode_vpeid(cmd, desc->its_vmovi_cmd.vpe->vpe_id);
846 its_encode_event_id(cmd, desc->its_vmovi_cmd.event_id);
847 its_encode_db_phys_id(cmd, db);
848 its_encode_db_valid(cmd, true);
849
850 its_fixup_cmd(cmd);
851
852 return valid_vpe(its, desc->its_vmovi_cmd.vpe);
853}
854
855static struct its_vpe *its_build_vmovp_cmd(struct its_node *its,
856 struct its_cmd_block *cmd,
857 struct its_cmd_desc *desc)
858{
859 u64 target;
860
861 target = desc->its_vmovp_cmd.col->target_address + its->vlpi_redist_offset;
862 its_encode_cmd(cmd, GITS_CMD_VMOVP);
863 its_encode_seq_num(cmd, desc->its_vmovp_cmd.seq_num);
864 its_encode_its_list(cmd, desc->its_vmovp_cmd.its_list);
865 its_encode_vpeid(cmd, desc->its_vmovp_cmd.vpe->vpe_id);
866 its_encode_target(cmd, target);
867
868 if (is_v4_1(its)) {
869 its_encode_db(cmd, true);
870 its_encode_vmovp_default_db(cmd, desc->its_vmovp_cmd.vpe->vpe_db_lpi);
871 }
872
873 its_fixup_cmd(cmd);
874
875 return valid_vpe(its, desc->its_vmovp_cmd.vpe);
876}
877
878static struct its_vpe *its_build_vinv_cmd(struct its_node *its,
879 struct its_cmd_block *cmd,
880 struct its_cmd_desc *desc)
881{
882 struct its_vlpi_map *map;
883
884 map = dev_event_to_vlpi_map(desc->its_inv_cmd.dev,
885 desc->its_inv_cmd.event_id);
886
887 its_encode_cmd(cmd, GITS_CMD_INV);
888 its_encode_devid(cmd, desc->its_inv_cmd.dev->device_id);
889 its_encode_event_id(cmd, desc->its_inv_cmd.event_id);
890
891 its_fixup_cmd(cmd);
892
893 return valid_vpe(its, map->vpe);
894}
895
896static struct its_vpe *its_build_vint_cmd(struct its_node *its,
897 struct its_cmd_block *cmd,
898 struct its_cmd_desc *desc)
899{
900 struct its_vlpi_map *map;
901
902 map = dev_event_to_vlpi_map(desc->its_int_cmd.dev,
903 desc->its_int_cmd.event_id);
904
905 its_encode_cmd(cmd, GITS_CMD_INT);
906 its_encode_devid(cmd, desc->its_int_cmd.dev->device_id);
907 its_encode_event_id(cmd, desc->its_int_cmd.event_id);
908
909 its_fixup_cmd(cmd);
910
911 return valid_vpe(its, map->vpe);
912}
913
914static struct its_vpe *its_build_vclear_cmd(struct its_node *its,
915 struct its_cmd_block *cmd,
916 struct its_cmd_desc *desc)
917{
918 struct its_vlpi_map *map;
919
920 map = dev_event_to_vlpi_map(desc->its_clear_cmd.dev,
921 desc->its_clear_cmd.event_id);
922
923 its_encode_cmd(cmd, GITS_CMD_CLEAR);
924 its_encode_devid(cmd, desc->its_clear_cmd.dev->device_id);
925 its_encode_event_id(cmd, desc->its_clear_cmd.event_id);
926
927 its_fixup_cmd(cmd);
928
929 return valid_vpe(its, map->vpe);
930}
931
932static struct its_vpe *its_build_invdb_cmd(struct its_node *its,
933 struct its_cmd_block *cmd,
934 struct its_cmd_desc *desc)
935{
936 if (WARN_ON(!is_v4_1(its)))
937 return NULL;
938
939 its_encode_cmd(cmd, GITS_CMD_INVDB);
940 its_encode_vpeid(cmd, desc->its_invdb_cmd.vpe->vpe_id);
941
942 its_fixup_cmd(cmd);
943
944 return valid_vpe(its, desc->its_invdb_cmd.vpe);
945}
946
947static struct its_vpe *its_build_vsgi_cmd(struct its_node *its,
948 struct its_cmd_block *cmd,
949 struct its_cmd_desc *desc)
950{
951 if (WARN_ON(!is_v4_1(its)))
952 return NULL;
953
954 its_encode_cmd(cmd, GITS_CMD_VSGI);
955 its_encode_vpeid(cmd, desc->its_vsgi_cmd.vpe->vpe_id);
956 its_encode_sgi_intid(cmd, desc->its_vsgi_cmd.sgi);
957 its_encode_sgi_priority(cmd, desc->its_vsgi_cmd.priority);
958 its_encode_sgi_group(cmd, desc->its_vsgi_cmd.group);
959 its_encode_sgi_clear(cmd, desc->its_vsgi_cmd.clear);
960 its_encode_sgi_enable(cmd, desc->its_vsgi_cmd.enable);
961
962 its_fixup_cmd(cmd);
963
964 return valid_vpe(its, desc->its_vsgi_cmd.vpe);
965}
966
967static u64 its_cmd_ptr_to_offset(struct its_node *its,
968 struct its_cmd_block *ptr)
969{
970 return (ptr - its->cmd_base) * sizeof(*ptr);
971}
972
973static int its_queue_full(struct its_node *its)
974{
975 int widx;
976 int ridx;
977
978 widx = its->cmd_write - its->cmd_base;
979 ridx = readl_relaxed(its->base + GITS_CREADR) / sizeof(struct its_cmd_block);
980
981 /* This is incredibly unlikely to happen, unless the ITS locks up. */
982 if (((widx + 1) % ITS_CMD_QUEUE_NR_ENTRIES) == ridx)
983 return 1;
984
985 return 0;
986}
987
988static struct its_cmd_block *its_allocate_entry(struct its_node *its)
989{
990 struct its_cmd_block *cmd;
991 u32 count = 1000000; /* 1s! */
992
993 while (its_queue_full(its)) {
994 count--;
995 if (!count) {
996 pr_err_ratelimited("ITS queue not draining\n");
997 return NULL;
998 }
999 cpu_relax();
1000 udelay(1);
1001 }
1002
1003 cmd = its->cmd_write++;
1004
1005 /* Handle queue wrapping */
1006 if (its->cmd_write == (its->cmd_base + ITS_CMD_QUEUE_NR_ENTRIES))
1007 its->cmd_write = its->cmd_base;
1008
1009 /* Clear command */
1010 cmd->raw_cmd[0] = 0;
1011 cmd->raw_cmd[1] = 0;
1012 cmd->raw_cmd[2] = 0;
1013 cmd->raw_cmd[3] = 0;
1014
1015 return cmd;
1016}
1017
1018static struct its_cmd_block *its_post_commands(struct its_node *its)
1019{
1020 u64 wr = its_cmd_ptr_to_offset(its, its->cmd_write);
1021
1022 writel_relaxed(wr, its->base + GITS_CWRITER);
1023
1024 return its->cmd_write;
1025}
1026
1027static void its_flush_cmd(struct its_node *its, struct its_cmd_block *cmd)
1028{
1029 /*
1030 * Make sure the commands written to memory are observable by
1031 * the ITS.
1032 */
1033 if (its->flags & ITS_FLAGS_CMDQ_NEEDS_FLUSHING)
1034 gic_flush_dcache_to_poc(cmd, sizeof(*cmd));
1035 else
1036 dsb(ishst);
1037}
1038
1039static int its_wait_for_range_completion(struct its_node *its,
1040 u64 prev_idx,
1041 struct its_cmd_block *to)
1042{
1043 u64 rd_idx, to_idx, linear_idx;
1044 u32 count = 1000000; /* 1s! */
1045
1046 /* Linearize to_idx if the command set has wrapped around */
1047 to_idx = its_cmd_ptr_to_offset(its, to);
1048 if (to_idx < prev_idx)
1049 to_idx += ITS_CMD_QUEUE_SZ;
1050
1051 linear_idx = prev_idx;
1052
1053 while (1) {
1054 s64 delta;
1055
1056 rd_idx = readl_relaxed(its->base + GITS_CREADR);
1057
1058 /*
1059 * Compute the read pointer progress, taking the
1060 * potential wrap-around into account.
1061 */
1062 delta = rd_idx - prev_idx;
1063 if (rd_idx < prev_idx)
1064 delta += ITS_CMD_QUEUE_SZ;
1065
1066 linear_idx += delta;
1067 if (linear_idx >= to_idx)
1068 break;
1069
1070 count--;
1071 if (!count) {
1072 pr_err_ratelimited("ITS queue timeout (%llu %llu)\n",
1073 to_idx, linear_idx);
1074 return -1;
1075 }
1076 prev_idx = rd_idx;
1077 cpu_relax();
1078 udelay(1);
1079 }
1080
1081 return 0;
1082}
1083
1084/* Warning, macro hell follows */
1085#define BUILD_SINGLE_CMD_FUNC(name, buildtype, synctype, buildfn) \
1086void name(struct its_node *its, \
1087 buildtype builder, \
1088 struct its_cmd_desc *desc) \
1089{ \
1090 struct its_cmd_block *cmd, *sync_cmd, *next_cmd; \
1091 synctype *sync_obj; \
1092 unsigned long flags; \
1093 u64 rd_idx; \
1094 \
1095 raw_spin_lock_irqsave(&its->lock, flags); \
1096 \
1097 cmd = its_allocate_entry(its); \
1098 if (!cmd) { /* We're soooooo screewed... */ \
1099 raw_spin_unlock_irqrestore(&its->lock, flags); \
1100 return; \
1101 } \
1102 sync_obj = builder(its, cmd, desc); \
1103 its_flush_cmd(its, cmd); \
1104 \
1105 if (sync_obj) { \
1106 sync_cmd = its_allocate_entry(its); \
1107 if (!sync_cmd) \
1108 goto post; \
1109 \
1110 buildfn(its, sync_cmd, sync_obj); \
1111 its_flush_cmd(its, sync_cmd); \
1112 } \
1113 \
1114post: \
1115 rd_idx = readl_relaxed(its->base + GITS_CREADR); \
1116 next_cmd = its_post_commands(its); \
1117 raw_spin_unlock_irqrestore(&its->lock, flags); \
1118 \
1119 if (its_wait_for_range_completion(its, rd_idx, next_cmd)) \
1120 pr_err_ratelimited("ITS cmd %ps failed\n", builder); \
1121}
1122
1123static void its_build_sync_cmd(struct its_node *its,
1124 struct its_cmd_block *sync_cmd,
1125 struct its_collection *sync_col)
1126{
1127 its_encode_cmd(sync_cmd, GITS_CMD_SYNC);
1128 its_encode_target(sync_cmd, sync_col->target_address);
1129
1130 its_fixup_cmd(sync_cmd);
1131}
1132
1133static BUILD_SINGLE_CMD_FUNC(its_send_single_command, its_cmd_builder_t,
1134 struct its_collection, its_build_sync_cmd)
1135
1136static void its_build_vsync_cmd(struct its_node *its,
1137 struct its_cmd_block *sync_cmd,
1138 struct its_vpe *sync_vpe)
1139{
1140 its_encode_cmd(sync_cmd, GITS_CMD_VSYNC);
1141 its_encode_vpeid(sync_cmd, sync_vpe->vpe_id);
1142
1143 its_fixup_cmd(sync_cmd);
1144}
1145
1146static BUILD_SINGLE_CMD_FUNC(its_send_single_vcommand, its_cmd_vbuilder_t,
1147 struct its_vpe, its_build_vsync_cmd)
1148
1149static void its_send_int(struct its_device *dev, u32 event_id)
1150{
1151 struct its_cmd_desc desc;
1152
1153 desc.its_int_cmd.dev = dev;
1154 desc.its_int_cmd.event_id = event_id;
1155
1156 its_send_single_command(dev->its, its_build_int_cmd, &desc);
1157}
1158
1159static void its_send_clear(struct its_device *dev, u32 event_id)
1160{
1161 struct its_cmd_desc desc;
1162
1163 desc.its_clear_cmd.dev = dev;
1164 desc.its_clear_cmd.event_id = event_id;
1165
1166 its_send_single_command(dev->its, its_build_clear_cmd, &desc);
1167}
1168
1169static void its_send_inv(struct its_device *dev, u32 event_id)
1170{
1171 struct its_cmd_desc desc;
1172
1173 desc.its_inv_cmd.dev = dev;
1174 desc.its_inv_cmd.event_id = event_id;
1175
1176 its_send_single_command(dev->its, its_build_inv_cmd, &desc);
1177}
1178
1179static void its_send_mapd(struct its_device *dev, int valid)
1180{
1181 struct its_cmd_desc desc;
1182
1183 desc.its_mapd_cmd.dev = dev;
1184 desc.its_mapd_cmd.valid = !!valid;
1185
1186 its_send_single_command(dev->its, its_build_mapd_cmd, &desc);
1187}
1188
1189static void its_send_mapc(struct its_node *its, struct its_collection *col,
1190 int valid)
1191{
1192 struct its_cmd_desc desc;
1193
1194 desc.its_mapc_cmd.col = col;
1195 desc.its_mapc_cmd.valid = !!valid;
1196
1197 its_send_single_command(its, its_build_mapc_cmd, &desc);
1198}
1199
1200static void its_send_mapti(struct its_device *dev, u32 irq_id, u32 id)
1201{
1202 struct its_cmd_desc desc;
1203
1204 desc.its_mapti_cmd.dev = dev;
1205 desc.its_mapti_cmd.phys_id = irq_id;
1206 desc.its_mapti_cmd.event_id = id;
1207
1208 its_send_single_command(dev->its, its_build_mapti_cmd, &desc);
1209}
1210
1211static void its_send_movi(struct its_device *dev,
1212 struct its_collection *col, u32 id)
1213{
1214 struct its_cmd_desc desc;
1215
1216 desc.its_movi_cmd.dev = dev;
1217 desc.its_movi_cmd.col = col;
1218 desc.its_movi_cmd.event_id = id;
1219
1220 its_send_single_command(dev->its, its_build_movi_cmd, &desc);
1221}
1222
1223static void its_send_discard(struct its_device *dev, u32 id)
1224{
1225 struct its_cmd_desc desc;
1226
1227 desc.its_discard_cmd.dev = dev;
1228 desc.its_discard_cmd.event_id = id;
1229
1230 its_send_single_command(dev->its, its_build_discard_cmd, &desc);
1231}
1232
1233static void its_send_invall(struct its_node *its, struct its_collection *col)
1234{
1235 struct its_cmd_desc desc;
1236
1237 desc.its_invall_cmd.col = col;
1238
1239 its_send_single_command(its, its_build_invall_cmd, &desc);
1240}
1241
1242static void its_send_vmapti(struct its_device *dev, u32 id)
1243{
1244 struct its_vlpi_map *map = dev_event_to_vlpi_map(dev, id);
1245 struct its_cmd_desc desc;
1246
1247 desc.its_vmapti_cmd.vpe = map->vpe;
1248 desc.its_vmapti_cmd.dev = dev;
1249 desc.its_vmapti_cmd.virt_id = map->vintid;
1250 desc.its_vmapti_cmd.event_id = id;
1251 desc.its_vmapti_cmd.db_enabled = map->db_enabled;
1252
1253 its_send_single_vcommand(dev->its, its_build_vmapti_cmd, &desc);
1254}
1255
1256static void its_send_vmovi(struct its_device *dev, u32 id)
1257{
1258 struct its_vlpi_map *map = dev_event_to_vlpi_map(dev, id);
1259 struct its_cmd_desc desc;
1260
1261 desc.its_vmovi_cmd.vpe = map->vpe;
1262 desc.its_vmovi_cmd.dev = dev;
1263 desc.its_vmovi_cmd.event_id = id;
1264 desc.its_vmovi_cmd.db_enabled = map->db_enabled;
1265
1266 its_send_single_vcommand(dev->its, its_build_vmovi_cmd, &desc);
1267}
1268
1269static void its_send_vmapp(struct its_node *its,
1270 struct its_vpe *vpe, bool valid)
1271{
1272 struct its_cmd_desc desc;
1273
1274 desc.its_vmapp_cmd.vpe = vpe;
1275 desc.its_vmapp_cmd.valid = valid;
1276 desc.its_vmapp_cmd.col = &its->collections[vpe->col_idx];
1277
1278 its_send_single_vcommand(its, its_build_vmapp_cmd, &desc);
1279}
1280
1281static void its_send_vmovp(struct its_vpe *vpe)
1282{
1283 struct its_cmd_desc desc = {};
1284 struct its_node *its;
1285 unsigned long flags;
1286 int col_id = vpe->col_idx;
1287
1288 desc.its_vmovp_cmd.vpe = vpe;
1289
1290 if (!its_list_map) {
1291 its = list_first_entry(&its_nodes, struct its_node, entry);
1292 desc.its_vmovp_cmd.col = &its->collections[col_id];
1293 its_send_single_vcommand(its, its_build_vmovp_cmd, &desc);
1294 return;
1295 }
1296
1297 /*
1298 * Yet another marvel of the architecture. If using the
1299 * its_list "feature", we need to make sure that all ITSs
1300 * receive all VMOVP commands in the same order. The only way
1301 * to guarantee this is to make vmovp a serialization point.
1302 *
1303 * Wall <-- Head.
1304 */
1305 raw_spin_lock_irqsave(&vmovp_lock, flags);
1306
1307 desc.its_vmovp_cmd.seq_num = vmovp_seq_num++;
1308 desc.its_vmovp_cmd.its_list = get_its_list(vpe->its_vm);
1309
1310 /* Emit VMOVPs */
1311 list_for_each_entry(its, &its_nodes, entry) {
1312 if (!is_v4(its))
1313 continue;
1314
1315 if (!require_its_list_vmovp(vpe->its_vm, its))
1316 continue;
1317
1318 desc.its_vmovp_cmd.col = &its->collections[col_id];
1319 its_send_single_vcommand(its, its_build_vmovp_cmd, &desc);
1320 }
1321
1322 raw_spin_unlock_irqrestore(&vmovp_lock, flags);
1323}
1324
1325static void its_send_vinvall(struct its_node *its, struct its_vpe *vpe)
1326{
1327 struct its_cmd_desc desc;
1328
1329 desc.its_vinvall_cmd.vpe = vpe;
1330 its_send_single_vcommand(its, its_build_vinvall_cmd, &desc);
1331}
1332
1333static void its_send_vinv(struct its_device *dev, u32 event_id)
1334{
1335 struct its_cmd_desc desc;
1336
1337 /*
1338 * There is no real VINV command. This is just a normal INV,
1339 * with a VSYNC instead of a SYNC.
1340 */
1341 desc.its_inv_cmd.dev = dev;
1342 desc.its_inv_cmd.event_id = event_id;
1343
1344 its_send_single_vcommand(dev->its, its_build_vinv_cmd, &desc);
1345}
1346
1347static void its_send_vint(struct its_device *dev, u32 event_id)
1348{
1349 struct its_cmd_desc desc;
1350
1351 /*
1352 * There is no real VINT command. This is just a normal INT,
1353 * with a VSYNC instead of a SYNC.
1354 */
1355 desc.its_int_cmd.dev = dev;
1356 desc.its_int_cmd.event_id = event_id;
1357
1358 its_send_single_vcommand(dev->its, its_build_vint_cmd, &desc);
1359}
1360
1361static void its_send_vclear(struct its_device *dev, u32 event_id)
1362{
1363 struct its_cmd_desc desc;
1364
1365 /*
1366 * There is no real VCLEAR command. This is just a normal CLEAR,
1367 * with a VSYNC instead of a SYNC.
1368 */
1369 desc.its_clear_cmd.dev = dev;
1370 desc.its_clear_cmd.event_id = event_id;
1371
1372 its_send_single_vcommand(dev->its, its_build_vclear_cmd, &desc);
1373}
1374
1375static void its_send_invdb(struct its_node *its, struct its_vpe *vpe)
1376{
1377 struct its_cmd_desc desc;
1378
1379 desc.its_invdb_cmd.vpe = vpe;
1380 its_send_single_vcommand(its, its_build_invdb_cmd, &desc);
1381}
1382
1383/*
1384 * irqchip functions - assumes MSI, mostly.
1385 */
1386static void lpi_write_config(struct irq_data *d, u8 clr, u8 set)
1387{
1388 struct its_vlpi_map *map = get_vlpi_map(d);
1389 irq_hw_number_t hwirq;
1390 void *va;
1391 u8 *cfg;
1392
1393 if (map) {
1394 va = page_address(map->vm->vprop_page);
1395 hwirq = map->vintid;
1396
1397 /* Remember the updated property */
1398 map->properties &= ~clr;
1399 map->properties |= set | LPI_PROP_GROUP1;
1400 } else {
1401 va = gic_rdists->prop_table_va;
1402 hwirq = d->hwirq;
1403 }
1404
1405 cfg = va + hwirq - 8192;
1406 *cfg &= ~clr;
1407 *cfg |= set | LPI_PROP_GROUP1;
1408
1409 /*
1410 * Make the above write visible to the redistributors.
1411 * And yes, we're flushing exactly: One. Single. Byte.
1412 * Humpf...
1413 */
1414 if (gic_rdists->flags & RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING)
1415 gic_flush_dcache_to_poc(cfg, sizeof(*cfg));
1416 else
1417 dsb(ishst);
1418}
1419
1420static void wait_for_syncr(void __iomem *rdbase)
1421{
1422 while (readl_relaxed(rdbase + GICR_SYNCR) & 1)
1423 cpu_relax();
1424}
1425
1426static void direct_lpi_inv(struct irq_data *d)
1427{
1428 struct its_vlpi_map *map = get_vlpi_map(d);
1429 void __iomem *rdbase;
1430 unsigned long flags;
1431 u64 val;
1432 int cpu;
1433
1434 if (map) {
1435 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1436
1437 WARN_ON(!is_v4_1(its_dev->its));
1438
1439 val = GICR_INVLPIR_V;
1440 val |= FIELD_PREP(GICR_INVLPIR_VPEID, map->vpe->vpe_id);
1441 val |= FIELD_PREP(GICR_INVLPIR_INTID, map->vintid);
1442 } else {
1443 val = d->hwirq;
1444 }
1445
1446 /* Target the redistributor this LPI is currently routed to */
1447 cpu = irq_to_cpuid_lock(d, &flags);
1448 raw_spin_lock(&gic_data_rdist_cpu(cpu)->rd_lock);
1449 rdbase = per_cpu_ptr(gic_rdists->rdist, cpu)->rd_base;
1450 gic_write_lpir(val, rdbase + GICR_INVLPIR);
1451
1452 wait_for_syncr(rdbase);
1453 raw_spin_unlock(&gic_data_rdist_cpu(cpu)->rd_lock);
1454 irq_to_cpuid_unlock(d, flags);
1455}
1456
1457static void lpi_update_config(struct irq_data *d, u8 clr, u8 set)
1458{
1459 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1460
1461 lpi_write_config(d, clr, set);
1462 if (gic_rdists->has_direct_lpi &&
1463 (is_v4_1(its_dev->its) || !irqd_is_forwarded_to_vcpu(d)))
1464 direct_lpi_inv(d);
1465 else if (!irqd_is_forwarded_to_vcpu(d))
1466 its_send_inv(its_dev, its_get_event_id(d));
1467 else
1468 its_send_vinv(its_dev, its_get_event_id(d));
1469}
1470
1471static void its_vlpi_set_doorbell(struct irq_data *d, bool enable)
1472{
1473 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1474 u32 event = its_get_event_id(d);
1475 struct its_vlpi_map *map;
1476
1477 /*
1478 * GICv4.1 does away with the per-LPI nonsense, nothing to do
1479 * here.
1480 */
1481 if (is_v4_1(its_dev->its))
1482 return;
1483
1484 map = dev_event_to_vlpi_map(its_dev, event);
1485
1486 if (map->db_enabled == enable)
1487 return;
1488
1489 map->db_enabled = enable;
1490
1491 /*
1492 * More fun with the architecture:
1493 *
1494 * Ideally, we'd issue a VMAPTI to set the doorbell to its LPI
1495 * value or to 1023, depending on the enable bit. But that
1496 * would be issueing a mapping for an /existing/ DevID+EventID
1497 * pair, which is UNPREDICTABLE. Instead, let's issue a VMOVI
1498 * to the /same/ vPE, using this opportunity to adjust the
1499 * doorbell. Mouahahahaha. We loves it, Precious.
1500 */
1501 its_send_vmovi(its_dev, event);
1502}
1503
1504static void its_mask_irq(struct irq_data *d)
1505{
1506 if (irqd_is_forwarded_to_vcpu(d))
1507 its_vlpi_set_doorbell(d, false);
1508
1509 lpi_update_config(d, LPI_PROP_ENABLED, 0);
1510}
1511
1512static void its_unmask_irq(struct irq_data *d)
1513{
1514 if (irqd_is_forwarded_to_vcpu(d))
1515 its_vlpi_set_doorbell(d, true);
1516
1517 lpi_update_config(d, 0, LPI_PROP_ENABLED);
1518}
1519
1520static __maybe_unused u32 its_read_lpi_count(struct irq_data *d, int cpu)
1521{
1522 if (irqd_affinity_is_managed(d))
1523 return atomic_read(&per_cpu_ptr(&cpu_lpi_count, cpu)->managed);
1524
1525 return atomic_read(&per_cpu_ptr(&cpu_lpi_count, cpu)->unmanaged);
1526}
1527
1528static void its_inc_lpi_count(struct irq_data *d, int cpu)
1529{
1530 if (irqd_affinity_is_managed(d))
1531 atomic_inc(&per_cpu_ptr(&cpu_lpi_count, cpu)->managed);
1532 else
1533 atomic_inc(&per_cpu_ptr(&cpu_lpi_count, cpu)->unmanaged);
1534}
1535
1536static void its_dec_lpi_count(struct irq_data *d, int cpu)
1537{
1538 if (irqd_affinity_is_managed(d))
1539 atomic_dec(&per_cpu_ptr(&cpu_lpi_count, cpu)->managed);
1540 else
1541 atomic_dec(&per_cpu_ptr(&cpu_lpi_count, cpu)->unmanaged);
1542}
1543
1544static unsigned int cpumask_pick_least_loaded(struct irq_data *d,
1545 const struct cpumask *cpu_mask)
1546{
1547 unsigned int cpu = nr_cpu_ids, tmp;
1548 int count = S32_MAX;
1549
1550 for_each_cpu(tmp, cpu_mask) {
1551 int this_count = its_read_lpi_count(d, tmp);
1552 if (this_count < count) {
1553 cpu = tmp;
1554 count = this_count;
1555 }
1556 }
1557
1558 return cpu;
1559}
1560
1561/*
1562 * As suggested by Thomas Gleixner in:
1563 * https://lore.kernel.org/r/87h80q2aoc.fsf@nanos.tec.linutronix.de
1564 */
1565static int its_select_cpu(struct irq_data *d,
1566 const struct cpumask *aff_mask)
1567{
1568 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1569 cpumask_var_t tmpmask;
1570 int cpu, node;
1571
1572 if (!alloc_cpumask_var(&tmpmask, GFP_ATOMIC))
1573 return -ENOMEM;
1574
1575 node = its_dev->its->numa_node;
1576
1577 if (!irqd_affinity_is_managed(d)) {
1578 /* First try the NUMA node */
1579 if (node != NUMA_NO_NODE) {
1580 /*
1581 * Try the intersection of the affinity mask and the
1582 * node mask (and the online mask, just to be safe).
1583 */
1584 cpumask_and(tmpmask, cpumask_of_node(node), aff_mask);
1585 cpumask_and(tmpmask, tmpmask, cpu_online_mask);
1586
1587 /*
1588 * Ideally, we would check if the mask is empty, and
1589 * try again on the full node here.
1590 *
1591 * But it turns out that the way ACPI describes the
1592 * affinity for ITSs only deals about memory, and
1593 * not target CPUs, so it cannot describe a single
1594 * ITS placed next to two NUMA nodes.
1595 *
1596 * Instead, just fallback on the online mask. This
1597 * diverges from Thomas' suggestion above.
1598 */
1599 cpu = cpumask_pick_least_loaded(d, tmpmask);
1600 if (cpu < nr_cpu_ids)
1601 goto out;
1602
1603 /* If we can't cross sockets, give up */
1604 if ((its_dev->its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144))
1605 goto out;
1606
1607 /* If the above failed, expand the search */
1608 }
1609
1610 /* Try the intersection of the affinity and online masks */
1611 cpumask_and(tmpmask, aff_mask, cpu_online_mask);
1612
1613 /* If that doesn't fly, the online mask is the last resort */
1614 if (cpumask_empty(tmpmask))
1615 cpumask_copy(tmpmask, cpu_online_mask);
1616
1617 cpu = cpumask_pick_least_loaded(d, tmpmask);
1618 } else {
1619 cpumask_and(tmpmask, irq_data_get_affinity_mask(d), cpu_online_mask);
1620
1621 /* If we cannot cross sockets, limit the search to that node */
1622 if ((its_dev->its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) &&
1623 node != NUMA_NO_NODE)
1624 cpumask_and(tmpmask, tmpmask, cpumask_of_node(node));
1625
1626 cpu = cpumask_pick_least_loaded(d, tmpmask);
1627 }
1628out:
1629 free_cpumask_var(tmpmask);
1630
1631 pr_debug("IRQ%d -> %*pbl CPU%d\n", d->irq, cpumask_pr_args(aff_mask), cpu);
1632 return cpu;
1633}
1634
1635static int its_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
1636 bool force)
1637{
1638 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1639 struct its_collection *target_col;
1640 u32 id = its_get_event_id(d);
1641 int cpu, prev_cpu;
1642
1643 /* A forwarded interrupt should use irq_set_vcpu_affinity */
1644 if (irqd_is_forwarded_to_vcpu(d))
1645 return -EINVAL;
1646
1647 prev_cpu = its_dev->event_map.col_map[id];
1648 its_dec_lpi_count(d, prev_cpu);
1649
1650 if (!force)
1651 cpu = its_select_cpu(d, mask_val);
1652 else
1653 cpu = cpumask_pick_least_loaded(d, mask_val);
1654
1655 if (cpu < 0 || cpu >= nr_cpu_ids)
1656 goto err;
1657
1658 /* don't set the affinity when the target cpu is same as current one */
1659 if (cpu != prev_cpu) {
1660 target_col = &its_dev->its->collections[cpu];
1661 its_send_movi(its_dev, target_col, id);
1662 its_dev->event_map.col_map[id] = cpu;
1663 irq_data_update_effective_affinity(d, cpumask_of(cpu));
1664 }
1665
1666 its_inc_lpi_count(d, cpu);
1667
1668 return IRQ_SET_MASK_OK_DONE;
1669
1670err:
1671 its_inc_lpi_count(d, prev_cpu);
1672 return -EINVAL;
1673}
1674
1675static u64 its_irq_get_msi_base(struct its_device *its_dev)
1676{
1677 struct its_node *its = its_dev->its;
1678
1679 return its->phys_base + GITS_TRANSLATER;
1680}
1681
1682static void its_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *msg)
1683{
1684 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1685 struct its_node *its;
1686 u64 addr;
1687
1688 its = its_dev->its;
1689 addr = its->get_msi_base(its_dev);
1690
1691 msg->address_lo = lower_32_bits(addr);
1692 msg->address_hi = upper_32_bits(addr);
1693 msg->data = its_get_event_id(d);
1694
1695 iommu_dma_compose_msi_msg(irq_data_get_msi_desc(d), msg);
1696}
1697
1698static int its_irq_set_irqchip_state(struct irq_data *d,
1699 enum irqchip_irq_state which,
1700 bool state)
1701{
1702 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1703 u32 event = its_get_event_id(d);
1704
1705 if (which != IRQCHIP_STATE_PENDING)
1706 return -EINVAL;
1707
1708 if (irqd_is_forwarded_to_vcpu(d)) {
1709 if (state)
1710 its_send_vint(its_dev, event);
1711 else
1712 its_send_vclear(its_dev, event);
1713 } else {
1714 if (state)
1715 its_send_int(its_dev, event);
1716 else
1717 its_send_clear(its_dev, event);
1718 }
1719
1720 return 0;
1721}
1722
1723/*
1724 * Two favourable cases:
1725 *
1726 * (a) Either we have a GICv4.1, and all vPEs have to be mapped at all times
1727 * for vSGI delivery
1728 *
1729 * (b) Or the ITSs do not use a list map, meaning that VMOVP is cheap enough
1730 * and we're better off mapping all VPEs always
1731 *
1732 * If neither (a) nor (b) is true, then we map vPEs on demand.
1733 *
1734 */
1735static bool gic_requires_eager_mapping(void)
1736{
1737 if (!its_list_map || gic_rdists->has_rvpeid)
1738 return true;
1739
1740 return false;
1741}
1742
1743static void its_map_vm(struct its_node *its, struct its_vm *vm)
1744{
1745 unsigned long flags;
1746
1747 if (gic_requires_eager_mapping())
1748 return;
1749
1750 raw_spin_lock_irqsave(&vmovp_lock, flags);
1751
1752 /*
1753 * If the VM wasn't mapped yet, iterate over the vpes and get
1754 * them mapped now.
1755 */
1756 vm->vlpi_count[its->list_nr]++;
1757
1758 if (vm->vlpi_count[its->list_nr] == 1) {
1759 int i;
1760
1761 for (i = 0; i < vm->nr_vpes; i++) {
1762 struct its_vpe *vpe = vm->vpes[i];
1763 struct irq_data *d = irq_get_irq_data(vpe->irq);
1764
1765 /* Map the VPE to the first possible CPU */
1766 vpe->col_idx = cpumask_first(cpu_online_mask);
1767 its_send_vmapp(its, vpe, true);
1768 its_send_vinvall(its, vpe);
1769 irq_data_update_effective_affinity(d, cpumask_of(vpe->col_idx));
1770 }
1771 }
1772
1773 raw_spin_unlock_irqrestore(&vmovp_lock, flags);
1774}
1775
1776static void its_unmap_vm(struct its_node *its, struct its_vm *vm)
1777{
1778 unsigned long flags;
1779
1780 /* Not using the ITS list? Everything is always mapped. */
1781 if (gic_requires_eager_mapping())
1782 return;
1783
1784 raw_spin_lock_irqsave(&vmovp_lock, flags);
1785
1786 if (!--vm->vlpi_count[its->list_nr]) {
1787 int i;
1788
1789 for (i = 0; i < vm->nr_vpes; i++)
1790 its_send_vmapp(its, vm->vpes[i], false);
1791 }
1792
1793 raw_spin_unlock_irqrestore(&vmovp_lock, flags);
1794}
1795
1796static int its_vlpi_map(struct irq_data *d, struct its_cmd_info *info)
1797{
1798 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1799 u32 event = its_get_event_id(d);
1800 int ret = 0;
1801
1802 if (!info->map)
1803 return -EINVAL;
1804
1805 raw_spin_lock(&its_dev->event_map.vlpi_lock);
1806
1807 if (!its_dev->event_map.vm) {
1808 struct its_vlpi_map *maps;
1809
1810 maps = kcalloc(its_dev->event_map.nr_lpis, sizeof(*maps),
1811 GFP_ATOMIC);
1812 if (!maps) {
1813 ret = -ENOMEM;
1814 goto out;
1815 }
1816
1817 its_dev->event_map.vm = info->map->vm;
1818 its_dev->event_map.vlpi_maps = maps;
1819 } else if (its_dev->event_map.vm != info->map->vm) {
1820 ret = -EINVAL;
1821 goto out;
1822 }
1823
1824 /* Get our private copy of the mapping information */
1825 its_dev->event_map.vlpi_maps[event] = *info->map;
1826
1827 if (irqd_is_forwarded_to_vcpu(d)) {
1828 /* Already mapped, move it around */
1829 its_send_vmovi(its_dev, event);
1830 } else {
1831 /* Ensure all the VPEs are mapped on this ITS */
1832 its_map_vm(its_dev->its, info->map->vm);
1833
1834 /*
1835 * Flag the interrupt as forwarded so that we can
1836 * start poking the virtual property table.
1837 */
1838 irqd_set_forwarded_to_vcpu(d);
1839
1840 /* Write out the property to the prop table */
1841 lpi_write_config(d, 0xff, info->map->properties);
1842
1843 /* Drop the physical mapping */
1844 its_send_discard(its_dev, event);
1845
1846 /* and install the virtual one */
1847 its_send_vmapti(its_dev, event);
1848
1849 /* Increment the number of VLPIs */
1850 its_dev->event_map.nr_vlpis++;
1851 }
1852
1853out:
1854 raw_spin_unlock(&its_dev->event_map.vlpi_lock);
1855 return ret;
1856}
1857
1858static int its_vlpi_get(struct irq_data *d, struct its_cmd_info *info)
1859{
1860 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1861 struct its_vlpi_map *map;
1862 int ret = 0;
1863
1864 raw_spin_lock(&its_dev->event_map.vlpi_lock);
1865
1866 map = get_vlpi_map(d);
1867
1868 if (!its_dev->event_map.vm || !map) {
1869 ret = -EINVAL;
1870 goto out;
1871 }
1872
1873 /* Copy our mapping information to the incoming request */
1874 *info->map = *map;
1875
1876out:
1877 raw_spin_unlock(&its_dev->event_map.vlpi_lock);
1878 return ret;
1879}
1880
1881static int its_vlpi_unmap(struct irq_data *d)
1882{
1883 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1884 u32 event = its_get_event_id(d);
1885 int ret = 0;
1886
1887 raw_spin_lock(&its_dev->event_map.vlpi_lock);
1888
1889 if (!its_dev->event_map.vm || !irqd_is_forwarded_to_vcpu(d)) {
1890 ret = -EINVAL;
1891 goto out;
1892 }
1893
1894 /* Drop the virtual mapping */
1895 its_send_discard(its_dev, event);
1896
1897 /* and restore the physical one */
1898 irqd_clr_forwarded_to_vcpu(d);
1899 its_send_mapti(its_dev, d->hwirq, event);
1900 lpi_update_config(d, 0xff, (LPI_PROP_DEFAULT_PRIO |
1901 LPI_PROP_ENABLED |
1902 LPI_PROP_GROUP1));
1903
1904 /* Potentially unmap the VM from this ITS */
1905 its_unmap_vm(its_dev->its, its_dev->event_map.vm);
1906
1907 /*
1908 * Drop the refcount and make the device available again if
1909 * this was the last VLPI.
1910 */
1911 if (!--its_dev->event_map.nr_vlpis) {
1912 its_dev->event_map.vm = NULL;
1913 kfree(its_dev->event_map.vlpi_maps);
1914 }
1915
1916out:
1917 raw_spin_unlock(&its_dev->event_map.vlpi_lock);
1918 return ret;
1919}
1920
1921static int its_vlpi_prop_update(struct irq_data *d, struct its_cmd_info *info)
1922{
1923 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1924
1925 if (!its_dev->event_map.vm || !irqd_is_forwarded_to_vcpu(d))
1926 return -EINVAL;
1927
1928 if (info->cmd_type == PROP_UPDATE_AND_INV_VLPI)
1929 lpi_update_config(d, 0xff, info->config);
1930 else
1931 lpi_write_config(d, 0xff, info->config);
1932 its_vlpi_set_doorbell(d, !!(info->config & LPI_PROP_ENABLED));
1933
1934 return 0;
1935}
1936
1937static int its_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
1938{
1939 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1940 struct its_cmd_info *info = vcpu_info;
1941
1942 /* Need a v4 ITS */
1943 if (!is_v4(its_dev->its))
1944 return -EINVAL;
1945
1946 /* Unmap request? */
1947 if (!info)
1948 return its_vlpi_unmap(d);
1949
1950 switch (info->cmd_type) {
1951 case MAP_VLPI:
1952 return its_vlpi_map(d, info);
1953
1954 case GET_VLPI:
1955 return its_vlpi_get(d, info);
1956
1957 case PROP_UPDATE_VLPI:
1958 case PROP_UPDATE_AND_INV_VLPI:
1959 return its_vlpi_prop_update(d, info);
1960
1961 default:
1962 return -EINVAL;
1963 }
1964}
1965
1966static struct irq_chip its_irq_chip = {
1967 .name = "ITS",
1968 .irq_mask = its_mask_irq,
1969 .irq_unmask = its_unmask_irq,
1970 .irq_eoi = irq_chip_eoi_parent,
1971 .irq_set_affinity = its_set_affinity,
1972 .irq_compose_msi_msg = its_irq_compose_msi_msg,
1973 .irq_set_irqchip_state = its_irq_set_irqchip_state,
1974 .irq_set_vcpu_affinity = its_irq_set_vcpu_affinity,
1975};
1976
1977
1978/*
1979 * How we allocate LPIs:
1980 *
1981 * lpi_range_list contains ranges of LPIs that are to available to
1982 * allocate from. To allocate LPIs, just pick the first range that
1983 * fits the required allocation, and reduce it by the required
1984 * amount. Once empty, remove the range from the list.
1985 *
1986 * To free a range of LPIs, add a free range to the list, sort it and
1987 * merge the result if the new range happens to be adjacent to an
1988 * already free block.
1989 *
1990 * The consequence of the above is that allocation is cost is low, but
1991 * freeing is expensive. We assumes that freeing rarely occurs.
1992 */
1993#define ITS_MAX_LPI_NRBITS 16 /* 64K LPIs */
1994
1995static DEFINE_MUTEX(lpi_range_lock);
1996static LIST_HEAD(lpi_range_list);
1997
1998struct lpi_range {
1999 struct list_head entry;
2000 u32 base_id;
2001 u32 span;
2002};
2003
2004static struct lpi_range *mk_lpi_range(u32 base, u32 span)
2005{
2006 struct lpi_range *range;
2007
2008 range = kmalloc(sizeof(*range), GFP_KERNEL);
2009 if (range) {
2010 range->base_id = base;
2011 range->span = span;
2012 }
2013
2014 return range;
2015}
2016
2017static int alloc_lpi_range(u32 nr_lpis, u32 *base)
2018{
2019 struct lpi_range *range, *tmp;
2020 int err = -ENOSPC;
2021
2022 mutex_lock(&lpi_range_lock);
2023
2024 list_for_each_entry_safe(range, tmp, &lpi_range_list, entry) {
2025 if (range->span >= nr_lpis) {
2026 *base = range->base_id;
2027 range->base_id += nr_lpis;
2028 range->span -= nr_lpis;
2029
2030 if (range->span == 0) {
2031 list_del(&range->entry);
2032 kfree(range);
2033 }
2034
2035 err = 0;
2036 break;
2037 }
2038 }
2039
2040 mutex_unlock(&lpi_range_lock);
2041
2042 pr_debug("ITS: alloc %u:%u\n", *base, nr_lpis);
2043 return err;
2044}
2045
2046static void merge_lpi_ranges(struct lpi_range *a, struct lpi_range *b)
2047{
2048 if (&a->entry == &lpi_range_list || &b->entry == &lpi_range_list)
2049 return;
2050 if (a->base_id + a->span != b->base_id)
2051 return;
2052 b->base_id = a->base_id;
2053 b->span += a->span;
2054 list_del(&a->entry);
2055 kfree(a);
2056}
2057
2058static int free_lpi_range(u32 base, u32 nr_lpis)
2059{
2060 struct lpi_range *new, *old;
2061
2062 new = mk_lpi_range(base, nr_lpis);
2063 if (!new)
2064 return -ENOMEM;
2065
2066 mutex_lock(&lpi_range_lock);
2067
2068 list_for_each_entry_reverse(old, &lpi_range_list, entry) {
2069 if (old->base_id < base)
2070 break;
2071 }
2072 /*
2073 * old is the last element with ->base_id smaller than base,
2074 * so new goes right after it. If there are no elements with
2075 * ->base_id smaller than base, &old->entry ends up pointing
2076 * at the head of the list, and inserting new it the start of
2077 * the list is the right thing to do in that case as well.
2078 */
2079 list_add(&new->entry, &old->entry);
2080 /*
2081 * Now check if we can merge with the preceding and/or
2082 * following ranges.
2083 */
2084 merge_lpi_ranges(old, new);
2085 merge_lpi_ranges(new, list_next_entry(new, entry));
2086
2087 mutex_unlock(&lpi_range_lock);
2088 return 0;
2089}
2090
2091static int __init its_lpi_init(u32 id_bits)
2092{
2093 u32 lpis = (1UL << id_bits) - 8192;
2094 u32 numlpis;
2095 int err;
2096
2097 numlpis = 1UL << GICD_TYPER_NUM_LPIS(gic_rdists->gicd_typer);
2098
2099 if (numlpis > 2 && !WARN_ON(numlpis > lpis)) {
2100 lpis = numlpis;
2101 pr_info("ITS: Using hypervisor restricted LPI range [%u]\n",
2102 lpis);
2103 }
2104
2105 /*
2106 * Initializing the allocator is just the same as freeing the
2107 * full range of LPIs.
2108 */
2109 err = free_lpi_range(8192, lpis);
2110 pr_debug("ITS: Allocator initialized for %u LPIs\n", lpis);
2111 return err;
2112}
2113
2114static unsigned long *its_lpi_alloc(int nr_irqs, u32 *base, int *nr_ids)
2115{
2116 unsigned long *bitmap = NULL;
2117 int err = 0;
2118
2119 do {
2120 err = alloc_lpi_range(nr_irqs, base);
2121 if (!err)
2122 break;
2123
2124 nr_irqs /= 2;
2125 } while (nr_irqs > 0);
2126
2127 if (!nr_irqs)
2128 err = -ENOSPC;
2129
2130 if (err)
2131 goto out;
2132
2133 bitmap = kcalloc(BITS_TO_LONGS(nr_irqs), sizeof (long), GFP_ATOMIC);
2134 if (!bitmap)
2135 goto out;
2136
2137 *nr_ids = nr_irqs;
2138
2139out:
2140 if (!bitmap)
2141 *base = *nr_ids = 0;
2142
2143 return bitmap;
2144}
2145
2146static void its_lpi_free(unsigned long *bitmap, u32 base, u32 nr_ids)
2147{
2148 WARN_ON(free_lpi_range(base, nr_ids));
2149 kfree(bitmap);
2150}
2151
2152static void gic_reset_prop_table(void *va)
2153{
2154 /* Priority 0xa0, Group-1, disabled */
2155 memset(va, LPI_PROP_DEFAULT_PRIO | LPI_PROP_GROUP1, LPI_PROPBASE_SZ);
2156
2157 /* Make sure the GIC will observe the written configuration */
2158 gic_flush_dcache_to_poc(va, LPI_PROPBASE_SZ);
2159}
2160
2161static struct page *its_allocate_prop_table(gfp_t gfp_flags)
2162{
2163 struct page *prop_page;
2164
2165 prop_page = alloc_pages(gfp_flags, get_order(LPI_PROPBASE_SZ));
2166 if (!prop_page)
2167 return NULL;
2168
2169 gic_reset_prop_table(page_address(prop_page));
2170
2171 return prop_page;
2172}
2173
2174static void its_free_prop_table(struct page *prop_page)
2175{
2176 free_pages((unsigned long)page_address(prop_page),
2177 get_order(LPI_PROPBASE_SZ));
2178}
2179
2180static bool gic_check_reserved_range(phys_addr_t addr, unsigned long size)
2181{
2182 phys_addr_t start, end, addr_end;
2183 u64 i;
2184
2185 /*
2186 * We don't bother checking for a kdump kernel as by
2187 * construction, the LPI tables are out of this kernel's
2188 * memory map.
2189 */
2190 if (is_kdump_kernel())
2191 return true;
2192
2193 addr_end = addr + size - 1;
2194
2195 for_each_reserved_mem_region(i, &start, &end) {
2196 if (addr >= start && addr_end <= end)
2197 return true;
2198 }
2199
2200 /* Not found, not a good sign... */
2201 pr_warn("GICv3: Expected reserved range [%pa:%pa], not found\n",
2202 &addr, &addr_end);
2203 add_taint(TAINT_CRAP, LOCKDEP_STILL_OK);
2204 return false;
2205}
2206
2207static int gic_reserve_range(phys_addr_t addr, unsigned long size)
2208{
2209 if (efi_enabled(EFI_CONFIG_TABLES))
2210 return efi_mem_reserve_persistent(addr, size);
2211
2212 return 0;
2213}
2214
2215static int __init its_setup_lpi_prop_table(void)
2216{
2217 if (gic_rdists->flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED) {
2218 u64 val;
2219
2220 val = gicr_read_propbaser(gic_data_rdist_rd_base() + GICR_PROPBASER);
2221 lpi_id_bits = (val & GICR_PROPBASER_IDBITS_MASK) + 1;
2222
2223 gic_rdists->prop_table_pa = val & GENMASK_ULL(51, 12);
2224 gic_rdists->prop_table_va = memremap(gic_rdists->prop_table_pa,
2225 LPI_PROPBASE_SZ,
2226 MEMREMAP_WB);
2227 gic_reset_prop_table(gic_rdists->prop_table_va);
2228 } else {
2229 struct page *page;
2230
2231 lpi_id_bits = min_t(u32,
2232 GICD_TYPER_ID_BITS(gic_rdists->gicd_typer),
2233 ITS_MAX_LPI_NRBITS);
2234 page = its_allocate_prop_table(GFP_NOWAIT);
2235 if (!page) {
2236 pr_err("Failed to allocate PROPBASE\n");
2237 return -ENOMEM;
2238 }
2239
2240 gic_rdists->prop_table_pa = page_to_phys(page);
2241 gic_rdists->prop_table_va = page_address(page);
2242 WARN_ON(gic_reserve_range(gic_rdists->prop_table_pa,
2243 LPI_PROPBASE_SZ));
2244 }
2245
2246 pr_info("GICv3: using LPI property table @%pa\n",
2247 &gic_rdists->prop_table_pa);
2248
2249 return its_lpi_init(lpi_id_bits);
2250}
2251
2252static const char *its_base_type_string[] = {
2253 [GITS_BASER_TYPE_DEVICE] = "Devices",
2254 [GITS_BASER_TYPE_VCPU] = "Virtual CPUs",
2255 [GITS_BASER_TYPE_RESERVED3] = "Reserved (3)",
2256 [GITS_BASER_TYPE_COLLECTION] = "Interrupt Collections",
2257 [GITS_BASER_TYPE_RESERVED5] = "Reserved (5)",
2258 [GITS_BASER_TYPE_RESERVED6] = "Reserved (6)",
2259 [GITS_BASER_TYPE_RESERVED7] = "Reserved (7)",
2260};
2261
2262static u64 its_read_baser(struct its_node *its, struct its_baser *baser)
2263{
2264 u32 idx = baser - its->tables;
2265
2266 return gits_read_baser(its->base + GITS_BASER + (idx << 3));
2267}
2268
2269static void its_write_baser(struct its_node *its, struct its_baser *baser,
2270 u64 val)
2271{
2272 u32 idx = baser - its->tables;
2273
2274 gits_write_baser(val, its->base + GITS_BASER + (idx << 3));
2275 baser->val = its_read_baser(its, baser);
2276}
2277
2278static int its_setup_baser(struct its_node *its, struct its_baser *baser,
2279 u64 cache, u64 shr, u32 order, bool indirect)
2280{
2281 u64 val = its_read_baser(its, baser);
2282 u64 esz = GITS_BASER_ENTRY_SIZE(val);
2283 u64 type = GITS_BASER_TYPE(val);
2284 u64 baser_phys, tmp;
2285 u32 alloc_pages, psz;
2286 struct page *page;
2287 void *base;
2288
2289 psz = baser->psz;
2290 alloc_pages = (PAGE_ORDER_TO_SIZE(order) / psz);
2291 if (alloc_pages > GITS_BASER_PAGES_MAX) {
2292 pr_warn("ITS@%pa: %s too large, reduce ITS pages %u->%u\n",
2293 &its->phys_base, its_base_type_string[type],
2294 alloc_pages, GITS_BASER_PAGES_MAX);
2295 alloc_pages = GITS_BASER_PAGES_MAX;
2296 order = get_order(GITS_BASER_PAGES_MAX * psz);
2297 }
2298
2299 page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, order);
2300 if (!page)
2301 return -ENOMEM;
2302
2303 base = (void *)page_address(page);
2304 baser_phys = virt_to_phys(base);
2305
2306 /* Check if the physical address of the memory is above 48bits */
2307 if (IS_ENABLED(CONFIG_ARM64_64K_PAGES) && (baser_phys >> 48)) {
2308
2309 /* 52bit PA is supported only when PageSize=64K */
2310 if (psz != SZ_64K) {
2311 pr_err("ITS: no 52bit PA support when psz=%d\n", psz);
2312 free_pages((unsigned long)base, order);
2313 return -ENXIO;
2314 }
2315
2316 /* Convert 52bit PA to 48bit field */
2317 baser_phys = GITS_BASER_PHYS_52_to_48(baser_phys);
2318 }
2319
2320retry_baser:
2321 val = (baser_phys |
2322 (type << GITS_BASER_TYPE_SHIFT) |
2323 ((esz - 1) << GITS_BASER_ENTRY_SIZE_SHIFT) |
2324 ((alloc_pages - 1) << GITS_BASER_PAGES_SHIFT) |
2325 cache |
2326 shr |
2327 GITS_BASER_VALID);
2328
2329 val |= indirect ? GITS_BASER_INDIRECT : 0x0;
2330
2331 switch (psz) {
2332 case SZ_4K:
2333 val |= GITS_BASER_PAGE_SIZE_4K;
2334 break;
2335 case SZ_16K:
2336 val |= GITS_BASER_PAGE_SIZE_16K;
2337 break;
2338 case SZ_64K:
2339 val |= GITS_BASER_PAGE_SIZE_64K;
2340 break;
2341 }
2342
2343 its_write_baser(its, baser, val);
2344 tmp = baser->val;
2345
2346 if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) {
2347 /*
2348 * Shareability didn't stick. Just use
2349 * whatever the read reported, which is likely
2350 * to be the only thing this redistributor
2351 * supports. If that's zero, make it
2352 * non-cacheable as well.
2353 */
2354 shr = tmp & GITS_BASER_SHAREABILITY_MASK;
2355 if (!shr) {
2356 cache = GITS_BASER_nC;
2357 gic_flush_dcache_to_poc(base, PAGE_ORDER_TO_SIZE(order));
2358 }
2359 goto retry_baser;
2360 }
2361
2362 if (val != tmp) {
2363 pr_err("ITS@%pa: %s doesn't stick: %llx %llx\n",
2364 &its->phys_base, its_base_type_string[type],
2365 val, tmp);
2366 free_pages((unsigned long)base, order);
2367 return -ENXIO;
2368 }
2369
2370 baser->order = order;
2371 baser->base = base;
2372 baser->psz = psz;
2373 tmp = indirect ? GITS_LVL1_ENTRY_SIZE : esz;
2374
2375 pr_info("ITS@%pa: allocated %d %s @%lx (%s, esz %d, psz %dK, shr %d)\n",
2376 &its->phys_base, (int)(PAGE_ORDER_TO_SIZE(order) / (int)tmp),
2377 its_base_type_string[type],
2378 (unsigned long)virt_to_phys(base),
2379 indirect ? "indirect" : "flat", (int)esz,
2380 psz / SZ_1K, (int)shr >> GITS_BASER_SHAREABILITY_SHIFT);
2381
2382 return 0;
2383}
2384
2385static bool its_parse_indirect_baser(struct its_node *its,
2386 struct its_baser *baser,
2387 u32 *order, u32 ids)
2388{
2389 u64 tmp = its_read_baser(its, baser);
2390 u64 type = GITS_BASER_TYPE(tmp);
2391 u64 esz = GITS_BASER_ENTRY_SIZE(tmp);
2392 u64 val = GITS_BASER_InnerShareable | GITS_BASER_RaWaWb;
2393 u32 new_order = *order;
2394 u32 psz = baser->psz;
2395 bool indirect = false;
2396
2397 /* No need to enable Indirection if memory requirement < (psz*2)bytes */
2398 if ((esz << ids) > (psz * 2)) {
2399 /*
2400 * Find out whether hw supports a single or two-level table by
2401 * table by reading bit at offset '62' after writing '1' to it.
2402 */
2403 its_write_baser(its, baser, val | GITS_BASER_INDIRECT);
2404 indirect = !!(baser->val & GITS_BASER_INDIRECT);
2405
2406 if (indirect) {
2407 /*
2408 * The size of the lvl2 table is equal to ITS page size
2409 * which is 'psz'. For computing lvl1 table size,
2410 * subtract ID bits that sparse lvl2 table from 'ids'
2411 * which is reported by ITS hardware times lvl1 table
2412 * entry size.
2413 */
2414 ids -= ilog2(psz / (int)esz);
2415 esz = GITS_LVL1_ENTRY_SIZE;
2416 }
2417 }
2418
2419 /*
2420 * Allocate as many entries as required to fit the
2421 * range of device IDs that the ITS can grok... The ID
2422 * space being incredibly sparse, this results in a
2423 * massive waste of memory if two-level device table
2424 * feature is not supported by hardware.
2425 */
2426 new_order = max_t(u32, get_order(esz << ids), new_order);
2427 if (new_order >= MAX_ORDER) {
2428 new_order = MAX_ORDER - 1;
2429 ids = ilog2(PAGE_ORDER_TO_SIZE(new_order) / (int)esz);
2430 pr_warn("ITS@%pa: %s Table too large, reduce ids %llu->%u\n",
2431 &its->phys_base, its_base_type_string[type],
2432 device_ids(its), ids);
2433 }
2434
2435 *order = new_order;
2436
2437 return indirect;
2438}
2439
2440static u32 compute_common_aff(u64 val)
2441{
2442 u32 aff, clpiaff;
2443
2444 aff = FIELD_GET(GICR_TYPER_AFFINITY, val);
2445 clpiaff = FIELD_GET(GICR_TYPER_COMMON_LPI_AFF, val);
2446
2447 return aff & ~(GENMASK(31, 0) >> (clpiaff * 8));
2448}
2449
2450static u32 compute_its_aff(struct its_node *its)
2451{
2452 u64 val;
2453 u32 svpet;
2454
2455 /*
2456 * Reencode the ITS SVPET and MPIDR as a GICR_TYPER, and compute
2457 * the resulting affinity. We then use that to see if this match
2458 * our own affinity.
2459 */
2460 svpet = FIELD_GET(GITS_TYPER_SVPET, its->typer);
2461 val = FIELD_PREP(GICR_TYPER_COMMON_LPI_AFF, svpet);
2462 val |= FIELD_PREP(GICR_TYPER_AFFINITY, its->mpidr);
2463 return compute_common_aff(val);
2464}
2465
2466static struct its_node *find_sibling_its(struct its_node *cur_its)
2467{
2468 struct its_node *its;
2469 u32 aff;
2470
2471 if (!FIELD_GET(GITS_TYPER_SVPET, cur_its->typer))
2472 return NULL;
2473
2474 aff = compute_its_aff(cur_its);
2475
2476 list_for_each_entry(its, &its_nodes, entry) {
2477 u64 baser;
2478
2479 if (!is_v4_1(its) || its == cur_its)
2480 continue;
2481
2482 if (!FIELD_GET(GITS_TYPER_SVPET, its->typer))
2483 continue;
2484
2485 if (aff != compute_its_aff(its))
2486 continue;
2487
2488 /* GICv4.1 guarantees that the vPE table is GITS_BASER2 */
2489 baser = its->tables[2].val;
2490 if (!(baser & GITS_BASER_VALID))
2491 continue;
2492
2493 return its;
2494 }
2495
2496 return NULL;
2497}
2498
2499static void its_free_tables(struct its_node *its)
2500{
2501 int i;
2502
2503 for (i = 0; i < GITS_BASER_NR_REGS; i++) {
2504 if (its->tables[i].base) {
2505 free_pages((unsigned long)its->tables[i].base,
2506 its->tables[i].order);
2507 its->tables[i].base = NULL;
2508 }
2509 }
2510}
2511
2512static int its_probe_baser_psz(struct its_node *its, struct its_baser *baser)
2513{
2514 u64 psz = SZ_64K;
2515
2516 while (psz) {
2517 u64 val, gpsz;
2518
2519 val = its_read_baser(its, baser);
2520 val &= ~GITS_BASER_PAGE_SIZE_MASK;
2521
2522 switch (psz) {
2523 case SZ_64K:
2524 gpsz = GITS_BASER_PAGE_SIZE_64K;
2525 break;
2526 case SZ_16K:
2527 gpsz = GITS_BASER_PAGE_SIZE_16K;
2528 break;
2529 case SZ_4K:
2530 default:
2531 gpsz = GITS_BASER_PAGE_SIZE_4K;
2532 break;
2533 }
2534
2535 gpsz >>= GITS_BASER_PAGE_SIZE_SHIFT;
2536
2537 val |= FIELD_PREP(GITS_BASER_PAGE_SIZE_MASK, gpsz);
2538 its_write_baser(its, baser, val);
2539
2540 if (FIELD_GET(GITS_BASER_PAGE_SIZE_MASK, baser->val) == gpsz)
2541 break;
2542
2543 switch (psz) {
2544 case SZ_64K:
2545 psz = SZ_16K;
2546 break;
2547 case SZ_16K:
2548 psz = SZ_4K;
2549 break;
2550 case SZ_4K:
2551 default:
2552 return -1;
2553 }
2554 }
2555
2556 baser->psz = psz;
2557 return 0;
2558}
2559
2560static int its_alloc_tables(struct its_node *its)
2561{
2562 u64 shr = GITS_BASER_InnerShareable;
2563 u64 cache = GITS_BASER_RaWaWb;
2564 int err, i;
2565
2566 if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_22375)
2567 /* erratum 24313: ignore memory access type */
2568 cache = GITS_BASER_nCnB;
2569
2570 for (i = 0; i < GITS_BASER_NR_REGS; i++) {
2571 struct its_baser *baser = its->tables + i;
2572 u64 val = its_read_baser(its, baser);
2573 u64 type = GITS_BASER_TYPE(val);
2574 bool indirect = false;
2575 u32 order;
2576
2577 if (type == GITS_BASER_TYPE_NONE)
2578 continue;
2579
2580 if (its_probe_baser_psz(its, baser)) {
2581 its_free_tables(its);
2582 return -ENXIO;
2583 }
2584
2585 order = get_order(baser->psz);
2586
2587 switch (type) {
2588 case GITS_BASER_TYPE_DEVICE:
2589 indirect = its_parse_indirect_baser(its, baser, &order,
2590 device_ids(its));
2591 break;
2592
2593 case GITS_BASER_TYPE_VCPU:
2594 if (is_v4_1(its)) {
2595 struct its_node *sibling;
2596
2597 WARN_ON(i != 2);
2598 if ((sibling = find_sibling_its(its))) {
2599 *baser = sibling->tables[2];
2600 its_write_baser(its, baser, baser->val);
2601 continue;
2602 }
2603 }
2604
2605 indirect = its_parse_indirect_baser(its, baser, &order,
2606 ITS_MAX_VPEID_BITS);
2607 break;
2608 }
2609
2610 err = its_setup_baser(its, baser, cache, shr, order, indirect);
2611 if (err < 0) {
2612 its_free_tables(its);
2613 return err;
2614 }
2615
2616 /* Update settings which will be used for next BASERn */
2617 cache = baser->val & GITS_BASER_CACHEABILITY_MASK;
2618 shr = baser->val & GITS_BASER_SHAREABILITY_MASK;
2619 }
2620
2621 return 0;
2622}
2623
2624static u64 inherit_vpe_l1_table_from_its(void)
2625{
2626 struct its_node *its;
2627 u64 val;
2628 u32 aff;
2629
2630 val = gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER);
2631 aff = compute_common_aff(val);
2632
2633 list_for_each_entry(its, &its_nodes, entry) {
2634 u64 baser, addr;
2635
2636 if (!is_v4_1(its))
2637 continue;
2638
2639 if (!FIELD_GET(GITS_TYPER_SVPET, its->typer))
2640 continue;
2641
2642 if (aff != compute_its_aff(its))
2643 continue;
2644
2645 /* GICv4.1 guarantees that the vPE table is GITS_BASER2 */
2646 baser = its->tables[2].val;
2647 if (!(baser & GITS_BASER_VALID))
2648 continue;
2649
2650 /* We have a winner! */
2651 gic_data_rdist()->vpe_l1_base = its->tables[2].base;
2652
2653 val = GICR_VPROPBASER_4_1_VALID;
2654 if (baser & GITS_BASER_INDIRECT)
2655 val |= GICR_VPROPBASER_4_1_INDIRECT;
2656 val |= FIELD_PREP(GICR_VPROPBASER_4_1_PAGE_SIZE,
2657 FIELD_GET(GITS_BASER_PAGE_SIZE_MASK, baser));
2658 switch (FIELD_GET(GITS_BASER_PAGE_SIZE_MASK, baser)) {
2659 case GIC_PAGE_SIZE_64K:
2660 addr = GITS_BASER_ADDR_48_to_52(baser);
2661 break;
2662 default:
2663 addr = baser & GENMASK_ULL(47, 12);
2664 break;
2665 }
2666 val |= FIELD_PREP(GICR_VPROPBASER_4_1_ADDR, addr >> 12);
2667 val |= FIELD_PREP(GICR_VPROPBASER_SHAREABILITY_MASK,
2668 FIELD_GET(GITS_BASER_SHAREABILITY_MASK, baser));
2669 val |= FIELD_PREP(GICR_VPROPBASER_INNER_CACHEABILITY_MASK,
2670 FIELD_GET(GITS_BASER_INNER_CACHEABILITY_MASK, baser));
2671 val |= FIELD_PREP(GICR_VPROPBASER_4_1_SIZE, GITS_BASER_NR_PAGES(baser) - 1);
2672
2673 return val;
2674 }
2675
2676 return 0;
2677}
2678
2679static u64 inherit_vpe_l1_table_from_rd(cpumask_t **mask)
2680{
2681 u32 aff;
2682 u64 val;
2683 int cpu;
2684
2685 val = gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER);
2686 aff = compute_common_aff(val);
2687
2688 for_each_possible_cpu(cpu) {
2689 void __iomem *base = gic_data_rdist_cpu(cpu)->rd_base;
2690
2691 if (!base || cpu == smp_processor_id())
2692 continue;
2693
2694 val = gic_read_typer(base + GICR_TYPER);
2695 if (aff != compute_common_aff(val))
2696 continue;
2697
2698 /*
2699 * At this point, we have a victim. This particular CPU
2700 * has already booted, and has an affinity that matches
2701 * ours wrt CommonLPIAff. Let's use its own VPROPBASER.
2702 * Make sure we don't write the Z bit in that case.
2703 */
2704 val = gicr_read_vpropbaser(base + SZ_128K + GICR_VPROPBASER);
2705 val &= ~GICR_VPROPBASER_4_1_Z;
2706
2707 gic_data_rdist()->vpe_l1_base = gic_data_rdist_cpu(cpu)->vpe_l1_base;
2708 *mask = gic_data_rdist_cpu(cpu)->vpe_table_mask;
2709
2710 return val;
2711 }
2712
2713 return 0;
2714}
2715
2716static bool allocate_vpe_l2_table(int cpu, u32 id)
2717{
2718 void __iomem *base = gic_data_rdist_cpu(cpu)->rd_base;
2719 unsigned int psz, esz, idx, npg, gpsz;
2720 u64 val;
2721 struct page *page;
2722 __le64 *table;
2723
2724 if (!gic_rdists->has_rvpeid)
2725 return true;
2726
2727 /* Skip non-present CPUs */
2728 if (!base)
2729 return true;
2730
2731 val = gicr_read_vpropbaser(base + SZ_128K + GICR_VPROPBASER);
2732
2733 esz = FIELD_GET(GICR_VPROPBASER_4_1_ENTRY_SIZE, val) + 1;
2734 gpsz = FIELD_GET(GICR_VPROPBASER_4_1_PAGE_SIZE, val);
2735 npg = FIELD_GET(GICR_VPROPBASER_4_1_SIZE, val) + 1;
2736
2737 switch (gpsz) {
2738 default:
2739 WARN_ON(1);
2740 fallthrough;
2741 case GIC_PAGE_SIZE_4K:
2742 psz = SZ_4K;
2743 break;
2744 case GIC_PAGE_SIZE_16K:
2745 psz = SZ_16K;
2746 break;
2747 case GIC_PAGE_SIZE_64K:
2748 psz = SZ_64K;
2749 break;
2750 }
2751
2752 /* Don't allow vpe_id that exceeds single, flat table limit */
2753 if (!(val & GICR_VPROPBASER_4_1_INDIRECT))
2754 return (id < (npg * psz / (esz * SZ_8)));
2755
2756 /* Compute 1st level table index & check if that exceeds table limit */
2757 idx = id >> ilog2(psz / (esz * SZ_8));
2758 if (idx >= (npg * psz / GITS_LVL1_ENTRY_SIZE))
2759 return false;
2760
2761 table = gic_data_rdist_cpu(cpu)->vpe_l1_base;
2762
2763 /* Allocate memory for 2nd level table */
2764 if (!table[idx]) {
2765 page = alloc_pages(GFP_KERNEL | __GFP_ZERO, get_order(psz));
2766 if (!page)
2767 return false;
2768
2769 /* Flush Lvl2 table to PoC if hw doesn't support coherency */
2770 if (!(val & GICR_VPROPBASER_SHAREABILITY_MASK))
2771 gic_flush_dcache_to_poc(page_address(page), psz);
2772
2773 table[idx] = cpu_to_le64(page_to_phys(page) | GITS_BASER_VALID);
2774
2775 /* Flush Lvl1 entry to PoC if hw doesn't support coherency */
2776 if (!(val & GICR_VPROPBASER_SHAREABILITY_MASK))
2777 gic_flush_dcache_to_poc(table + idx, GITS_LVL1_ENTRY_SIZE);
2778
2779 /* Ensure updated table contents are visible to RD hardware */
2780 dsb(sy);
2781 }
2782
2783 return true;
2784}
2785
2786static int allocate_vpe_l1_table(void)
2787{
2788 void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
2789 u64 val, gpsz, npg, pa;
2790 unsigned int psz = SZ_64K;
2791 unsigned int np, epp, esz;
2792 struct page *page;
2793
2794 if (!gic_rdists->has_rvpeid)
2795 return 0;
2796
2797 /*
2798 * if VPENDBASER.Valid is set, disable any previously programmed
2799 * VPE by setting PendingLast while clearing Valid. This has the
2800 * effect of making sure no doorbell will be generated and we can
2801 * then safely clear VPROPBASER.Valid.
2802 */
2803 if (gicr_read_vpendbaser(vlpi_base + GICR_VPENDBASER) & GICR_VPENDBASER_Valid)
2804 gicr_write_vpendbaser(GICR_VPENDBASER_PendingLast,
2805 vlpi_base + GICR_VPENDBASER);
2806
2807 /*
2808 * If we can inherit the configuration from another RD, let's do
2809 * so. Otherwise, we have to go through the allocation process. We
2810 * assume that all RDs have the exact same requirements, as
2811 * nothing will work otherwise.
2812 */
2813 val = inherit_vpe_l1_table_from_rd(&gic_data_rdist()->vpe_table_mask);
2814 if (val & GICR_VPROPBASER_4_1_VALID)
2815 goto out;
2816
2817 gic_data_rdist()->vpe_table_mask = kzalloc(sizeof(cpumask_t), GFP_ATOMIC);
2818 if (!gic_data_rdist()->vpe_table_mask)
2819 return -ENOMEM;
2820
2821 val = inherit_vpe_l1_table_from_its();
2822 if (val & GICR_VPROPBASER_4_1_VALID)
2823 goto out;
2824
2825 /* First probe the page size */
2826 val = FIELD_PREP(GICR_VPROPBASER_4_1_PAGE_SIZE, GIC_PAGE_SIZE_64K);
2827 gicr_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER);
2828 val = gicr_read_vpropbaser(vlpi_base + GICR_VPROPBASER);
2829 gpsz = FIELD_GET(GICR_VPROPBASER_4_1_PAGE_SIZE, val);
2830 esz = FIELD_GET(GICR_VPROPBASER_4_1_ENTRY_SIZE, val);
2831
2832 switch (gpsz) {
2833 default:
2834 gpsz = GIC_PAGE_SIZE_4K;
2835 fallthrough;
2836 case GIC_PAGE_SIZE_4K:
2837 psz = SZ_4K;
2838 break;
2839 case GIC_PAGE_SIZE_16K:
2840 psz = SZ_16K;
2841 break;
2842 case GIC_PAGE_SIZE_64K:
2843 psz = SZ_64K;
2844 break;
2845 }
2846
2847 /*
2848 * Start populating the register from scratch, including RO fields
2849 * (which we want to print in debug cases...)
2850 */
2851 val = 0;
2852 val |= FIELD_PREP(GICR_VPROPBASER_4_1_PAGE_SIZE, gpsz);
2853 val |= FIELD_PREP(GICR_VPROPBASER_4_1_ENTRY_SIZE, esz);
2854
2855 /* How many entries per GIC page? */
2856 esz++;
2857 epp = psz / (esz * SZ_8);
2858
2859 /*
2860 * If we need more than just a single L1 page, flag the table
2861 * as indirect and compute the number of required L1 pages.
2862 */
2863 if (epp < ITS_MAX_VPEID) {
2864 int nl2;
2865
2866 val |= GICR_VPROPBASER_4_1_INDIRECT;
2867
2868 /* Number of L2 pages required to cover the VPEID space */
2869 nl2 = DIV_ROUND_UP(ITS_MAX_VPEID, epp);
2870
2871 /* Number of L1 pages to point to the L2 pages */
2872 npg = DIV_ROUND_UP(nl2 * SZ_8, psz);
2873 } else {
2874 npg = 1;
2875 }
2876
2877 val |= FIELD_PREP(GICR_VPROPBASER_4_1_SIZE, npg - 1);
2878
2879 /* Right, that's the number of CPU pages we need for L1 */
2880 np = DIV_ROUND_UP(npg * psz, PAGE_SIZE);
2881
2882 pr_debug("np = %d, npg = %lld, psz = %d, epp = %d, esz = %d\n",
2883 np, npg, psz, epp, esz);
2884 page = alloc_pages(GFP_ATOMIC | __GFP_ZERO, get_order(np * PAGE_SIZE));
2885 if (!page)
2886 return -ENOMEM;
2887
2888 gic_data_rdist()->vpe_l1_base = page_address(page);
2889 pa = virt_to_phys(page_address(page));
2890 WARN_ON(!IS_ALIGNED(pa, psz));
2891
2892 val |= FIELD_PREP(GICR_VPROPBASER_4_1_ADDR, pa >> 12);
2893 val |= GICR_VPROPBASER_RaWb;
2894 val |= GICR_VPROPBASER_InnerShareable;
2895 val |= GICR_VPROPBASER_4_1_Z;
2896 val |= GICR_VPROPBASER_4_1_VALID;
2897
2898out:
2899 gicr_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER);
2900 cpumask_set_cpu(smp_processor_id(), gic_data_rdist()->vpe_table_mask);
2901
2902 pr_debug("CPU%d: VPROPBASER = %llx %*pbl\n",
2903 smp_processor_id(), val,
2904 cpumask_pr_args(gic_data_rdist()->vpe_table_mask));
2905
2906 return 0;
2907}
2908
2909static int its_alloc_collections(struct its_node *its)
2910{
2911 int i;
2912
2913 its->collections = kcalloc(nr_cpu_ids, sizeof(*its->collections),
2914 GFP_KERNEL);
2915 if (!its->collections)
2916 return -ENOMEM;
2917
2918 for (i = 0; i < nr_cpu_ids; i++)
2919 its->collections[i].target_address = ~0ULL;
2920
2921 return 0;
2922}
2923
2924static struct page *its_allocate_pending_table(gfp_t gfp_flags)
2925{
2926 struct page *pend_page;
2927
2928 pend_page = alloc_pages(gfp_flags | __GFP_ZERO,
2929 get_order(LPI_PENDBASE_SZ));
2930 if (!pend_page)
2931 return NULL;
2932
2933 /* Make sure the GIC will observe the zero-ed page */
2934 gic_flush_dcache_to_poc(page_address(pend_page), LPI_PENDBASE_SZ);
2935
2936 return pend_page;
2937}
2938
2939static void its_free_pending_table(struct page *pt)
2940{
2941 free_pages((unsigned long)page_address(pt), get_order(LPI_PENDBASE_SZ));
2942}
2943
2944/*
2945 * Booting with kdump and LPIs enabled is generally fine. Any other
2946 * case is wrong in the absence of firmware/EFI support.
2947 */
2948static bool enabled_lpis_allowed(void)
2949{
2950 phys_addr_t addr;
2951 u64 val;
2952
2953 /* Check whether the property table is in a reserved region */
2954 val = gicr_read_propbaser(gic_data_rdist_rd_base() + GICR_PROPBASER);
2955 addr = val & GENMASK_ULL(51, 12);
2956
2957 return gic_check_reserved_range(addr, LPI_PROPBASE_SZ);
2958}
2959
2960static int __init allocate_lpi_tables(void)
2961{
2962 u64 val;
2963 int err, cpu;
2964
2965 /*
2966 * If LPIs are enabled while we run this from the boot CPU,
2967 * flag the RD tables as pre-allocated if the stars do align.
2968 */
2969 val = readl_relaxed(gic_data_rdist_rd_base() + GICR_CTLR);
2970 if ((val & GICR_CTLR_ENABLE_LPIS) && enabled_lpis_allowed()) {
2971 gic_rdists->flags |= (RDIST_FLAGS_RD_TABLES_PREALLOCATED |
2972 RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING);
2973 pr_info("GICv3: Using preallocated redistributor tables\n");
2974 }
2975
2976 err = its_setup_lpi_prop_table();
2977 if (err)
2978 return err;
2979
2980 /*
2981 * We allocate all the pending tables anyway, as we may have a
2982 * mix of RDs that have had LPIs enabled, and some that
2983 * don't. We'll free the unused ones as each CPU comes online.
2984 */
2985 for_each_possible_cpu(cpu) {
2986 struct page *pend_page;
2987
2988 pend_page = its_allocate_pending_table(GFP_NOWAIT);
2989 if (!pend_page) {
2990 pr_err("Failed to allocate PENDBASE for CPU%d\n", cpu);
2991 return -ENOMEM;
2992 }
2993
2994 gic_data_rdist_cpu(cpu)->pend_page = pend_page;
2995 }
2996
2997 return 0;
2998}
2999
3000static u64 its_clear_vpend_valid(void __iomem *vlpi_base, u64 clr, u64 set)
3001{
3002 u32 count = 1000000; /* 1s! */
3003 bool clean;
3004 u64 val;
3005
3006 val = gicr_read_vpendbaser(vlpi_base + GICR_VPENDBASER);
3007 val &= ~GICR_VPENDBASER_Valid;
3008 val &= ~clr;
3009 val |= set;
3010 gicr_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER);
3011
3012 do {
3013 val = gicr_read_vpendbaser(vlpi_base + GICR_VPENDBASER);
3014 clean = !(val & GICR_VPENDBASER_Dirty);
3015 if (!clean) {
3016 count--;
3017 cpu_relax();
3018 udelay(1);
3019 }
3020 } while (!clean && count);
3021
3022 if (unlikely(val & GICR_VPENDBASER_Dirty)) {
3023 pr_err_ratelimited("ITS virtual pending table not cleaning\n");
3024 val |= GICR_VPENDBASER_PendingLast;
3025 }
3026
3027 return val;
3028}
3029
3030static void its_cpu_init_lpis(void)
3031{
3032 void __iomem *rbase = gic_data_rdist_rd_base();
3033 struct page *pend_page;
3034 phys_addr_t paddr;
3035 u64 val, tmp;
3036
3037 if (gic_data_rdist()->lpi_enabled)
3038 return;
3039
3040 val = readl_relaxed(rbase + GICR_CTLR);
3041 if ((gic_rdists->flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED) &&
3042 (val & GICR_CTLR_ENABLE_LPIS)) {
3043 /*
3044 * Check that we get the same property table on all
3045 * RDs. If we don't, this is hopeless.
3046 */
3047 paddr = gicr_read_propbaser(rbase + GICR_PROPBASER);
3048 paddr &= GENMASK_ULL(51, 12);
3049 if (WARN_ON(gic_rdists->prop_table_pa != paddr))
3050 add_taint(TAINT_CRAP, LOCKDEP_STILL_OK);
3051
3052 paddr = gicr_read_pendbaser(rbase + GICR_PENDBASER);
3053 paddr &= GENMASK_ULL(51, 16);
3054
3055 WARN_ON(!gic_check_reserved_range(paddr, LPI_PENDBASE_SZ));
3056 its_free_pending_table(gic_data_rdist()->pend_page);
3057 gic_data_rdist()->pend_page = NULL;
3058
3059 goto out;
3060 }
3061
3062 pend_page = gic_data_rdist()->pend_page;
3063 paddr = page_to_phys(pend_page);
3064 WARN_ON(gic_reserve_range(paddr, LPI_PENDBASE_SZ));
3065
3066 /* set PROPBASE */
3067 val = (gic_rdists->prop_table_pa |
3068 GICR_PROPBASER_InnerShareable |
3069 GICR_PROPBASER_RaWaWb |
3070 ((LPI_NRBITS - 1) & GICR_PROPBASER_IDBITS_MASK));
3071
3072 gicr_write_propbaser(val, rbase + GICR_PROPBASER);
3073 tmp = gicr_read_propbaser(rbase + GICR_PROPBASER);
3074
3075 if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) {
3076 if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) {
3077 /*
3078 * The HW reports non-shareable, we must
3079 * remove the cacheability attributes as
3080 * well.
3081 */
3082 val &= ~(GICR_PROPBASER_SHAREABILITY_MASK |
3083 GICR_PROPBASER_CACHEABILITY_MASK);
3084 val |= GICR_PROPBASER_nC;
3085 gicr_write_propbaser(val, rbase + GICR_PROPBASER);
3086 }
3087 pr_info_once("GIC: using cache flushing for LPI property table\n");
3088 gic_rdists->flags |= RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING;
3089 }
3090
3091 /* set PENDBASE */
3092 val = (page_to_phys(pend_page) |
3093 GICR_PENDBASER_InnerShareable |
3094 GICR_PENDBASER_RaWaWb);
3095
3096 gicr_write_pendbaser(val, rbase + GICR_PENDBASER);
3097 tmp = gicr_read_pendbaser(rbase + GICR_PENDBASER);
3098
3099 if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) {
3100 /*
3101 * The HW reports non-shareable, we must remove the
3102 * cacheability attributes as well.
3103 */
3104 val &= ~(GICR_PENDBASER_SHAREABILITY_MASK |
3105 GICR_PENDBASER_CACHEABILITY_MASK);
3106 val |= GICR_PENDBASER_nC;
3107 gicr_write_pendbaser(val, rbase + GICR_PENDBASER);
3108 }
3109
3110 /* Enable LPIs */
3111 val = readl_relaxed(rbase + GICR_CTLR);
3112 val |= GICR_CTLR_ENABLE_LPIS;
3113 writel_relaxed(val, rbase + GICR_CTLR);
3114
3115 if (gic_rdists->has_vlpis && !gic_rdists->has_rvpeid) {
3116 void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
3117
3118 /*
3119 * It's possible for CPU to receive VLPIs before it is
3120 * sheduled as a vPE, especially for the first CPU, and the
3121 * VLPI with INTID larger than 2^(IDbits+1) will be considered
3122 * as out of range and dropped by GIC.
3123 * So we initialize IDbits to known value to avoid VLPI drop.
3124 */
3125 val = (LPI_NRBITS - 1) & GICR_VPROPBASER_IDBITS_MASK;
3126 pr_debug("GICv4: CPU%d: Init IDbits to 0x%llx for GICR_VPROPBASER\n",
3127 smp_processor_id(), val);
3128 gicr_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER);
3129
3130 /*
3131 * Also clear Valid bit of GICR_VPENDBASER, in case some
3132 * ancient programming gets left in and has possibility of
3133 * corrupting memory.
3134 */
3135 val = its_clear_vpend_valid(vlpi_base, 0, 0);
3136 }
3137
3138 if (allocate_vpe_l1_table()) {
3139 /*
3140 * If the allocation has failed, we're in massive trouble.
3141 * Disable direct injection, and pray that no VM was
3142 * already running...
3143 */
3144 gic_rdists->has_rvpeid = false;
3145 gic_rdists->has_vlpis = false;
3146 }
3147
3148 /* Make sure the GIC has seen the above */
3149 dsb(sy);
3150out:
3151 gic_data_rdist()->lpi_enabled = true;
3152 pr_info("GICv3: CPU%d: using %s LPI pending table @%pa\n",
3153 smp_processor_id(),
3154 gic_data_rdist()->pend_page ? "allocated" : "reserved",
3155 &paddr);
3156}
3157
3158static void its_cpu_init_collection(struct its_node *its)
3159{
3160 int cpu = smp_processor_id();
3161 u64 target;
3162
3163 /* avoid cross node collections and its mapping */
3164 if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) {
3165 struct device_node *cpu_node;
3166
3167 cpu_node = of_get_cpu_node(cpu, NULL);
3168 if (its->numa_node != NUMA_NO_NODE &&
3169 its->numa_node != of_node_to_nid(cpu_node))
3170 return;
3171 }
3172
3173 /*
3174 * We now have to bind each collection to its target
3175 * redistributor.
3176 */
3177 if (gic_read_typer(its->base + GITS_TYPER) & GITS_TYPER_PTA) {
3178 /*
3179 * This ITS wants the physical address of the
3180 * redistributor.
3181 */
3182 target = gic_data_rdist()->phys_base;
3183 } else {
3184 /* This ITS wants a linear CPU number. */
3185 target = gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER);
3186 target = GICR_TYPER_CPU_NUMBER(target) << 16;
3187 }
3188
3189 /* Perform collection mapping */
3190 its->collections[cpu].target_address = target;
3191 its->collections[cpu].col_id = cpu;
3192
3193 its_send_mapc(its, &its->collections[cpu], 1);
3194 its_send_invall(its, &its->collections[cpu]);
3195}
3196
3197static void its_cpu_init_collections(void)
3198{
3199 struct its_node *its;
3200
3201 raw_spin_lock(&its_lock);
3202
3203 list_for_each_entry(its, &its_nodes, entry)
3204 its_cpu_init_collection(its);
3205
3206 raw_spin_unlock(&its_lock);
3207}
3208
3209static struct its_device *its_find_device(struct its_node *its, u32 dev_id)
3210{
3211 struct its_device *its_dev = NULL, *tmp;
3212 unsigned long flags;
3213
3214 raw_spin_lock_irqsave(&its->lock, flags);
3215
3216 list_for_each_entry(tmp, &its->its_device_list, entry) {
3217 if (tmp->device_id == dev_id) {
3218 its_dev = tmp;
3219 break;
3220 }
3221 }
3222
3223 raw_spin_unlock_irqrestore(&its->lock, flags);
3224
3225 return its_dev;
3226}
3227
3228static struct its_baser *its_get_baser(struct its_node *its, u32 type)
3229{
3230 int i;
3231
3232 for (i = 0; i < GITS_BASER_NR_REGS; i++) {
3233 if (GITS_BASER_TYPE(its->tables[i].val) == type)
3234 return &its->tables[i];
3235 }
3236
3237 return NULL;
3238}
3239
3240static bool its_alloc_table_entry(struct its_node *its,
3241 struct its_baser *baser, u32 id)
3242{
3243 struct page *page;
3244 u32 esz, idx;
3245 __le64 *table;
3246
3247 /* Don't allow device id that exceeds single, flat table limit */
3248 esz = GITS_BASER_ENTRY_SIZE(baser->val);
3249 if (!(baser->val & GITS_BASER_INDIRECT))
3250 return (id < (PAGE_ORDER_TO_SIZE(baser->order) / esz));
3251
3252 /* Compute 1st level table index & check if that exceeds table limit */
3253 idx = id >> ilog2(baser->psz / esz);
3254 if (idx >= (PAGE_ORDER_TO_SIZE(baser->order) / GITS_LVL1_ENTRY_SIZE))
3255 return false;
3256
3257 table = baser->base;
3258
3259 /* Allocate memory for 2nd level table */
3260 if (!table[idx]) {
3261 page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO,
3262 get_order(baser->psz));
3263 if (!page)
3264 return false;
3265
3266 /* Flush Lvl2 table to PoC if hw doesn't support coherency */
3267 if (!(baser->val & GITS_BASER_SHAREABILITY_MASK))
3268 gic_flush_dcache_to_poc(page_address(page), baser->psz);
3269
3270 table[idx] = cpu_to_le64(page_to_phys(page) | GITS_BASER_VALID);
3271
3272 /* Flush Lvl1 entry to PoC if hw doesn't support coherency */
3273 if (!(baser->val & GITS_BASER_SHAREABILITY_MASK))
3274 gic_flush_dcache_to_poc(table + idx, GITS_LVL1_ENTRY_SIZE);
3275
3276 /* Ensure updated table contents are visible to ITS hardware */
3277 dsb(sy);
3278 }
3279
3280 return true;
3281}
3282
3283static bool its_alloc_device_table(struct its_node *its, u32 dev_id)
3284{
3285 struct its_baser *baser;
3286
3287 baser = its_get_baser(its, GITS_BASER_TYPE_DEVICE);
3288
3289 /* Don't allow device id that exceeds ITS hardware limit */
3290 if (!baser)
3291 return (ilog2(dev_id) < device_ids(its));
3292
3293 return its_alloc_table_entry(its, baser, dev_id);
3294}
3295
3296static bool its_alloc_vpe_table(u32 vpe_id)
3297{
3298 struct its_node *its;
3299 int cpu;
3300
3301 /*
3302 * Make sure the L2 tables are allocated on *all* v4 ITSs. We
3303 * could try and only do it on ITSs corresponding to devices
3304 * that have interrupts targeted at this VPE, but the
3305 * complexity becomes crazy (and you have tons of memory
3306 * anyway, right?).
3307 */
3308 list_for_each_entry(its, &its_nodes, entry) {
3309 struct its_baser *baser;
3310
3311 if (!is_v4(its))
3312 continue;
3313
3314 baser = its_get_baser(its, GITS_BASER_TYPE_VCPU);
3315 if (!baser)
3316 return false;
3317
3318 if (!its_alloc_table_entry(its, baser, vpe_id))
3319 return false;
3320 }
3321
3322 /* Non v4.1? No need to iterate RDs and go back early. */
3323 if (!gic_rdists->has_rvpeid)
3324 return true;
3325
3326 /*
3327 * Make sure the L2 tables are allocated for all copies of
3328 * the L1 table on *all* v4.1 RDs.
3329 */
3330 for_each_possible_cpu(cpu) {
3331 if (!allocate_vpe_l2_table(cpu, vpe_id))
3332 return false;
3333 }
3334
3335 return true;
3336}
3337
3338static struct its_device *its_create_device(struct its_node *its, u32 dev_id,
3339 int nvecs, bool alloc_lpis)
3340{
3341 struct its_device *dev;
3342 unsigned long *lpi_map = NULL;
3343 unsigned long flags;
3344 u16 *col_map = NULL;
3345 void *itt;
3346 int lpi_base;
3347 int nr_lpis;
3348 int nr_ites;
3349 int sz;
3350
3351 if (!its_alloc_device_table(its, dev_id))
3352 return NULL;
3353
3354 if (WARN_ON(!is_power_of_2(nvecs)))
3355 nvecs = roundup_pow_of_two(nvecs);
3356
3357 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
3358 /*
3359 * Even if the device wants a single LPI, the ITT must be
3360 * sized as a power of two (and you need at least one bit...).
3361 */
3362 nr_ites = max(2, nvecs);
3363 sz = nr_ites * (FIELD_GET(GITS_TYPER_ITT_ENTRY_SIZE, its->typer) + 1);
3364 sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1;
3365 itt = kzalloc_node(sz, GFP_KERNEL, its->numa_node);
3366 if (alloc_lpis) {
3367 lpi_map = its_lpi_alloc(nvecs, &lpi_base, &nr_lpis);
3368 if (lpi_map)
3369 col_map = kcalloc(nr_lpis, sizeof(*col_map),
3370 GFP_KERNEL);
3371 } else {
3372 col_map = kcalloc(nr_ites, sizeof(*col_map), GFP_KERNEL);
3373 nr_lpis = 0;
3374 lpi_base = 0;
3375 }
3376
3377 if (!dev || !itt || !col_map || (!lpi_map && alloc_lpis)) {
3378 kfree(dev);
3379 kfree(itt);
3380 kfree(lpi_map);
3381 kfree(col_map);
3382 return NULL;
3383 }
3384
3385 gic_flush_dcache_to_poc(itt, sz);
3386
3387 dev->its = its;
3388 dev->itt = itt;
3389 dev->nr_ites = nr_ites;
3390 dev->event_map.lpi_map = lpi_map;
3391 dev->event_map.col_map = col_map;
3392 dev->event_map.lpi_base = lpi_base;
3393 dev->event_map.nr_lpis = nr_lpis;
3394 raw_spin_lock_init(&dev->event_map.vlpi_lock);
3395 dev->device_id = dev_id;
3396 INIT_LIST_HEAD(&dev->entry);
3397
3398 raw_spin_lock_irqsave(&its->lock, flags);
3399 list_add(&dev->entry, &its->its_device_list);
3400 raw_spin_unlock_irqrestore(&its->lock, flags);
3401
3402 /* Map device to its ITT */
3403 its_send_mapd(dev, 1);
3404
3405 return dev;
3406}
3407
3408static void its_free_device(struct its_device *its_dev)
3409{
3410 unsigned long flags;
3411
3412 raw_spin_lock_irqsave(&its_dev->its->lock, flags);
3413 list_del(&its_dev->entry);
3414 raw_spin_unlock_irqrestore(&its_dev->its->lock, flags);
3415 kfree(its_dev->event_map.col_map);
3416 kfree(its_dev->itt);
3417 kfree(its_dev);
3418}
3419
3420static int its_alloc_device_irq(struct its_device *dev, int nvecs, irq_hw_number_t *hwirq)
3421{
3422 int idx;
3423
3424 /* Find a free LPI region in lpi_map and allocate them. */
3425 idx = bitmap_find_free_region(dev->event_map.lpi_map,
3426 dev->event_map.nr_lpis,
3427 get_count_order(nvecs));
3428 if (idx < 0)
3429 return -ENOSPC;
3430
3431 *hwirq = dev->event_map.lpi_base + idx;
3432
3433 return 0;
3434}
3435
3436static int its_msi_prepare(struct irq_domain *domain, struct device *dev,
3437 int nvec, msi_alloc_info_t *info)
3438{
3439 struct its_node *its;
3440 struct its_device *its_dev;
3441 struct msi_domain_info *msi_info;
3442 u32 dev_id;
3443 int err = 0;
3444
3445 /*
3446 * We ignore "dev" entirely, and rely on the dev_id that has
3447 * been passed via the scratchpad. This limits this domain's
3448 * usefulness to upper layers that definitely know that they
3449 * are built on top of the ITS.
3450 */
3451 dev_id = info->scratchpad[0].ul;
3452
3453 msi_info = msi_get_domain_info(domain);
3454 its = msi_info->data;
3455
3456 if (!gic_rdists->has_direct_lpi &&
3457 vpe_proxy.dev &&
3458 vpe_proxy.dev->its == its &&
3459 dev_id == vpe_proxy.dev->device_id) {
3460 /* Bad luck. Get yourself a better implementation */
3461 WARN_ONCE(1, "DevId %x clashes with GICv4 VPE proxy device\n",
3462 dev_id);
3463 return -EINVAL;
3464 }
3465
3466 mutex_lock(&its->dev_alloc_lock);
3467 its_dev = its_find_device(its, dev_id);
3468 if (its_dev) {
3469 /*
3470 * We already have seen this ID, probably through
3471 * another alias (PCI bridge of some sort). No need to
3472 * create the device.
3473 */
3474 its_dev->shared = true;
3475 pr_debug("Reusing ITT for devID %x\n", dev_id);
3476 goto out;
3477 }
3478
3479 its_dev = its_create_device(its, dev_id, nvec, true);
3480 if (!its_dev) {
3481 err = -ENOMEM;
3482 goto out;
3483 }
3484
3485 pr_debug("ITT %d entries, %d bits\n", nvec, ilog2(nvec));
3486out:
3487 mutex_unlock(&its->dev_alloc_lock);
3488 info->scratchpad[0].ptr = its_dev;
3489 return err;
3490}
3491
3492static struct msi_domain_ops its_msi_domain_ops = {
3493 .msi_prepare = its_msi_prepare,
3494};
3495
3496static int its_irq_gic_domain_alloc(struct irq_domain *domain,
3497 unsigned int virq,
3498 irq_hw_number_t hwirq)
3499{
3500 struct irq_fwspec fwspec;
3501
3502 if (irq_domain_get_of_node(domain->parent)) {
3503 fwspec.fwnode = domain->parent->fwnode;
3504 fwspec.param_count = 3;
3505 fwspec.param[0] = GIC_IRQ_TYPE_LPI;
3506 fwspec.param[1] = hwirq;
3507 fwspec.param[2] = IRQ_TYPE_EDGE_RISING;
3508 } else if (is_fwnode_irqchip(domain->parent->fwnode)) {
3509 fwspec.fwnode = domain->parent->fwnode;
3510 fwspec.param_count = 2;
3511 fwspec.param[0] = hwirq;
3512 fwspec.param[1] = IRQ_TYPE_EDGE_RISING;
3513 } else {
3514 return -EINVAL;
3515 }
3516
3517 return irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
3518}
3519
3520static int its_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
3521 unsigned int nr_irqs, void *args)
3522{
3523 msi_alloc_info_t *info = args;
3524 struct its_device *its_dev = info->scratchpad[0].ptr;
3525 struct its_node *its = its_dev->its;
3526 struct irq_data *irqd;
3527 irq_hw_number_t hwirq;
3528 int err;
3529 int i;
3530
3531 err = its_alloc_device_irq(its_dev, nr_irqs, &hwirq);
3532 if (err)
3533 return err;
3534
3535 err = iommu_dma_prepare_msi(info->desc, its->get_msi_base(its_dev));
3536 if (err)
3537 return err;
3538
3539 for (i = 0; i < nr_irqs; i++) {
3540 err = its_irq_gic_domain_alloc(domain, virq + i, hwirq + i);
3541 if (err)
3542 return err;
3543
3544 irq_domain_set_hwirq_and_chip(domain, virq + i,
3545 hwirq + i, &its_irq_chip, its_dev);
3546 irqd = irq_get_irq_data(virq + i);
3547 irqd_set_single_target(irqd);
3548 irqd_set_affinity_on_activate(irqd);
3549 pr_debug("ID:%d pID:%d vID:%d\n",
3550 (int)(hwirq + i - its_dev->event_map.lpi_base),
3551 (int)(hwirq + i), virq + i);
3552 }
3553
3554 return 0;
3555}
3556
3557static int its_irq_domain_activate(struct irq_domain *domain,
3558 struct irq_data *d, bool reserve)
3559{
3560 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
3561 u32 event = its_get_event_id(d);
3562 int cpu;
3563
3564 cpu = its_select_cpu(d, cpu_online_mask);
3565 if (cpu < 0 || cpu >= nr_cpu_ids)
3566 return -EINVAL;
3567
3568 its_inc_lpi_count(d, cpu);
3569 its_dev->event_map.col_map[event] = cpu;
3570 irq_data_update_effective_affinity(d, cpumask_of(cpu));
3571
3572 /* Map the GIC IRQ and event to the device */
3573 its_send_mapti(its_dev, d->hwirq, event);
3574 return 0;
3575}
3576
3577static void its_irq_domain_deactivate(struct irq_domain *domain,
3578 struct irq_data *d)
3579{
3580 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
3581 u32 event = its_get_event_id(d);
3582
3583 its_dec_lpi_count(d, its_dev->event_map.col_map[event]);
3584 /* Stop the delivery of interrupts */
3585 its_send_discard(its_dev, event);
3586}
3587
3588static void its_irq_domain_free(struct irq_domain *domain, unsigned int virq,
3589 unsigned int nr_irqs)
3590{
3591 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
3592 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
3593 struct its_node *its = its_dev->its;
3594 int i;
3595
3596 bitmap_release_region(its_dev->event_map.lpi_map,
3597 its_get_event_id(irq_domain_get_irq_data(domain, virq)),
3598 get_count_order(nr_irqs));
3599
3600 for (i = 0; i < nr_irqs; i++) {
3601 struct irq_data *data = irq_domain_get_irq_data(domain,
3602 virq + i);
3603 /* Nuke the entry in the domain */
3604 irq_domain_reset_irq_data(data);
3605 }
3606
3607 mutex_lock(&its->dev_alloc_lock);
3608
3609 /*
3610 * If all interrupts have been freed, start mopping the
3611 * floor. This is conditionned on the device not being shared.
3612 */
3613 if (!its_dev->shared &&
3614 bitmap_empty(its_dev->event_map.lpi_map,
3615 its_dev->event_map.nr_lpis)) {
3616 its_lpi_free(its_dev->event_map.lpi_map,
3617 its_dev->event_map.lpi_base,
3618 its_dev->event_map.nr_lpis);
3619
3620 /* Unmap device/itt */
3621 its_send_mapd(its_dev, 0);
3622 its_free_device(its_dev);
3623 }
3624
3625 mutex_unlock(&its->dev_alloc_lock);
3626
3627 irq_domain_free_irqs_parent(domain, virq, nr_irqs);
3628}
3629
3630static const struct irq_domain_ops its_domain_ops = {
3631 .alloc = its_irq_domain_alloc,
3632 .free = its_irq_domain_free,
3633 .activate = its_irq_domain_activate,
3634 .deactivate = its_irq_domain_deactivate,
3635};
3636
3637/*
3638 * This is insane.
3639 *
3640 * If a GICv4.0 doesn't implement Direct LPIs (which is extremely
3641 * likely), the only way to perform an invalidate is to use a fake
3642 * device to issue an INV command, implying that the LPI has first
3643 * been mapped to some event on that device. Since this is not exactly
3644 * cheap, we try to keep that mapping around as long as possible, and
3645 * only issue an UNMAP if we're short on available slots.
3646 *
3647 * Broken by design(tm).
3648 *
3649 * GICv4.1, on the other hand, mandates that we're able to invalidate
3650 * by writing to a MMIO register. It doesn't implement the whole of
3651 * DirectLPI, but that's good enough. And most of the time, we don't
3652 * even have to invalidate anything, as the redistributor can be told
3653 * whether to generate a doorbell or not (we thus leave it enabled,
3654 * always).
3655 */
3656static void its_vpe_db_proxy_unmap_locked(struct its_vpe *vpe)
3657{
3658 /* GICv4.1 doesn't use a proxy, so nothing to do here */
3659 if (gic_rdists->has_rvpeid)
3660 return;
3661
3662 /* Already unmapped? */
3663 if (vpe->vpe_proxy_event == -1)
3664 return;
3665
3666 its_send_discard(vpe_proxy.dev, vpe->vpe_proxy_event);
3667 vpe_proxy.vpes[vpe->vpe_proxy_event] = NULL;
3668
3669 /*
3670 * We don't track empty slots at all, so let's move the
3671 * next_victim pointer if we can quickly reuse that slot
3672 * instead of nuking an existing entry. Not clear that this is
3673 * always a win though, and this might just generate a ripple
3674 * effect... Let's just hope VPEs don't migrate too often.
3675 */
3676 if (vpe_proxy.vpes[vpe_proxy.next_victim])
3677 vpe_proxy.next_victim = vpe->vpe_proxy_event;
3678
3679 vpe->vpe_proxy_event = -1;
3680}
3681
3682static void its_vpe_db_proxy_unmap(struct its_vpe *vpe)
3683{
3684 /* GICv4.1 doesn't use a proxy, so nothing to do here */
3685 if (gic_rdists->has_rvpeid)
3686 return;
3687
3688 if (!gic_rdists->has_direct_lpi) {
3689 unsigned long flags;
3690
3691 raw_spin_lock_irqsave(&vpe_proxy.lock, flags);
3692 its_vpe_db_proxy_unmap_locked(vpe);
3693 raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags);
3694 }
3695}
3696
3697static void its_vpe_db_proxy_map_locked(struct its_vpe *vpe)
3698{
3699 /* GICv4.1 doesn't use a proxy, so nothing to do here */
3700 if (gic_rdists->has_rvpeid)
3701 return;
3702
3703 /* Already mapped? */
3704 if (vpe->vpe_proxy_event != -1)
3705 return;
3706
3707 /* This slot was already allocated. Kick the other VPE out. */
3708 if (vpe_proxy.vpes[vpe_proxy.next_victim])
3709 its_vpe_db_proxy_unmap_locked(vpe_proxy.vpes[vpe_proxy.next_victim]);
3710
3711 /* Map the new VPE instead */
3712 vpe_proxy.vpes[vpe_proxy.next_victim] = vpe;
3713 vpe->vpe_proxy_event = vpe_proxy.next_victim;
3714 vpe_proxy.next_victim = (vpe_proxy.next_victim + 1) % vpe_proxy.dev->nr_ites;
3715
3716 vpe_proxy.dev->event_map.col_map[vpe->vpe_proxy_event] = vpe->col_idx;
3717 its_send_mapti(vpe_proxy.dev, vpe->vpe_db_lpi, vpe->vpe_proxy_event);
3718}
3719
3720static void its_vpe_db_proxy_move(struct its_vpe *vpe, int from, int to)
3721{
3722 unsigned long flags;
3723 struct its_collection *target_col;
3724
3725 /* GICv4.1 doesn't use a proxy, so nothing to do here */
3726 if (gic_rdists->has_rvpeid)
3727 return;
3728
3729 if (gic_rdists->has_direct_lpi) {
3730 void __iomem *rdbase;
3731
3732 rdbase = per_cpu_ptr(gic_rdists->rdist, from)->rd_base;
3733 gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_CLRLPIR);
3734 wait_for_syncr(rdbase);
3735
3736 return;
3737 }
3738
3739 raw_spin_lock_irqsave(&vpe_proxy.lock, flags);
3740
3741 its_vpe_db_proxy_map_locked(vpe);
3742
3743 target_col = &vpe_proxy.dev->its->collections[to];
3744 its_send_movi(vpe_proxy.dev, target_col, vpe->vpe_proxy_event);
3745 vpe_proxy.dev->event_map.col_map[vpe->vpe_proxy_event] = to;
3746
3747 raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags);
3748}
3749
3750static int its_vpe_set_affinity(struct irq_data *d,
3751 const struct cpumask *mask_val,
3752 bool force)
3753{
3754 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
3755 int from, cpu = cpumask_first(mask_val);
3756 unsigned long flags;
3757
3758 /*
3759 * Changing affinity is mega expensive, so let's be as lazy as
3760 * we can and only do it if we really have to. Also, if mapped
3761 * into the proxy device, we need to move the doorbell
3762 * interrupt to its new location.
3763 *
3764 * Another thing is that changing the affinity of a vPE affects
3765 * *other interrupts* such as all the vLPIs that are routed to
3766 * this vPE. This means that the irq_desc lock is not enough to
3767 * protect us, and that we must ensure nobody samples vpe->col_idx
3768 * during the update, hence the lock below which must also be
3769 * taken on any vLPI handling path that evaluates vpe->col_idx.
3770 */
3771 from = vpe_to_cpuid_lock(vpe, &flags);
3772 if (from == cpu)
3773 goto out;
3774
3775 vpe->col_idx = cpu;
3776
3777 /*
3778 * GICv4.1 allows us to skip VMOVP if moving to a cpu whose RD
3779 * is sharing its VPE table with the current one.
3780 */
3781 if (gic_data_rdist_cpu(cpu)->vpe_table_mask &&
3782 cpumask_test_cpu(from, gic_data_rdist_cpu(cpu)->vpe_table_mask))
3783 goto out;
3784
3785 its_send_vmovp(vpe);
3786 its_vpe_db_proxy_move(vpe, from, cpu);
3787
3788out:
3789 irq_data_update_effective_affinity(d, cpumask_of(cpu));
3790 vpe_to_cpuid_unlock(vpe, flags);
3791
3792 return IRQ_SET_MASK_OK_DONE;
3793}
3794
3795static void its_wait_vpt_parse_complete(void)
3796{
3797 void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
3798 u64 val;
3799
3800 if (!gic_rdists->has_vpend_valid_dirty)
3801 return;
3802
3803 WARN_ON_ONCE(readq_relaxed_poll_timeout_atomic(vlpi_base + GICR_VPENDBASER,
3804 val,
3805 !(val & GICR_VPENDBASER_Dirty),
3806 10, 500));
3807}
3808
3809static void its_vpe_schedule(struct its_vpe *vpe)
3810{
3811 void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
3812 u64 val;
3813
3814 /* Schedule the VPE */
3815 val = virt_to_phys(page_address(vpe->its_vm->vprop_page)) &
3816 GENMASK_ULL(51, 12);
3817 val |= (LPI_NRBITS - 1) & GICR_VPROPBASER_IDBITS_MASK;
3818 val |= GICR_VPROPBASER_RaWb;
3819 val |= GICR_VPROPBASER_InnerShareable;
3820 gicr_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER);
3821
3822 val = virt_to_phys(page_address(vpe->vpt_page)) &
3823 GENMASK_ULL(51, 16);
3824 val |= GICR_VPENDBASER_RaWaWb;
3825 val |= GICR_VPENDBASER_InnerShareable;
3826 /*
3827 * There is no good way of finding out if the pending table is
3828 * empty as we can race against the doorbell interrupt very
3829 * easily. So in the end, vpe->pending_last is only an
3830 * indication that the vcpu has something pending, not one
3831 * that the pending table is empty. A good implementation
3832 * would be able to read its coarse map pretty quickly anyway,
3833 * making this a tolerable issue.
3834 */
3835 val |= GICR_VPENDBASER_PendingLast;
3836 val |= vpe->idai ? GICR_VPENDBASER_IDAI : 0;
3837 val |= GICR_VPENDBASER_Valid;
3838 gicr_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER);
3839
3840 its_wait_vpt_parse_complete();
3841}
3842
3843static void its_vpe_deschedule(struct its_vpe *vpe)
3844{
3845 void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
3846 u64 val;
3847
3848 val = its_clear_vpend_valid(vlpi_base, 0, 0);
3849
3850 vpe->idai = !!(val & GICR_VPENDBASER_IDAI);
3851 vpe->pending_last = !!(val & GICR_VPENDBASER_PendingLast);
3852}
3853
3854static void its_vpe_invall(struct its_vpe *vpe)
3855{
3856 struct its_node *its;
3857
3858 list_for_each_entry(its, &its_nodes, entry) {
3859 if (!is_v4(its))
3860 continue;
3861
3862 if (its_list_map && !vpe->its_vm->vlpi_count[its->list_nr])
3863 continue;
3864
3865 /*
3866 * Sending a VINVALL to a single ITS is enough, as all
3867 * we need is to reach the redistributors.
3868 */
3869 its_send_vinvall(its, vpe);
3870 return;
3871 }
3872}
3873
3874static int its_vpe_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
3875{
3876 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
3877 struct its_cmd_info *info = vcpu_info;
3878
3879 switch (info->cmd_type) {
3880 case SCHEDULE_VPE:
3881 its_vpe_schedule(vpe);
3882 return 0;
3883
3884 case DESCHEDULE_VPE:
3885 its_vpe_deschedule(vpe);
3886 return 0;
3887
3888 case INVALL_VPE:
3889 its_vpe_invall(vpe);
3890 return 0;
3891
3892 default:
3893 return -EINVAL;
3894 }
3895}
3896
3897static void its_vpe_send_cmd(struct its_vpe *vpe,
3898 void (*cmd)(struct its_device *, u32))
3899{
3900 unsigned long flags;
3901
3902 raw_spin_lock_irqsave(&vpe_proxy.lock, flags);
3903
3904 its_vpe_db_proxy_map_locked(vpe);
3905 cmd(vpe_proxy.dev, vpe->vpe_proxy_event);
3906
3907 raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags);
3908}
3909
3910static void its_vpe_send_inv(struct irq_data *d)
3911{
3912 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
3913
3914 if (gic_rdists->has_direct_lpi) {
3915 void __iomem *rdbase;
3916
3917 /* Target the redistributor this VPE is currently known on */
3918 raw_spin_lock(&gic_data_rdist_cpu(vpe->col_idx)->rd_lock);
3919 rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base;
3920 gic_write_lpir(d->parent_data->hwirq, rdbase + GICR_INVLPIR);
3921 wait_for_syncr(rdbase);
3922 raw_spin_unlock(&gic_data_rdist_cpu(vpe->col_idx)->rd_lock);
3923 } else {
3924 its_vpe_send_cmd(vpe, its_send_inv);
3925 }
3926}
3927
3928static void its_vpe_mask_irq(struct irq_data *d)
3929{
3930 /*
3931 * We need to unmask the LPI, which is described by the parent
3932 * irq_data. Instead of calling into the parent (which won't
3933 * exactly do the right thing, let's simply use the
3934 * parent_data pointer. Yes, I'm naughty.
3935 */
3936 lpi_write_config(d->parent_data, LPI_PROP_ENABLED, 0);
3937 its_vpe_send_inv(d);
3938}
3939
3940static void its_vpe_unmask_irq(struct irq_data *d)
3941{
3942 /* Same hack as above... */
3943 lpi_write_config(d->parent_data, 0, LPI_PROP_ENABLED);
3944 its_vpe_send_inv(d);
3945}
3946
3947static int its_vpe_set_irqchip_state(struct irq_data *d,
3948 enum irqchip_irq_state which,
3949 bool state)
3950{
3951 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
3952
3953 if (which != IRQCHIP_STATE_PENDING)
3954 return -EINVAL;
3955
3956 if (gic_rdists->has_direct_lpi) {
3957 void __iomem *rdbase;
3958
3959 rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base;
3960 if (state) {
3961 gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_SETLPIR);
3962 } else {
3963 gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_CLRLPIR);
3964 wait_for_syncr(rdbase);
3965 }
3966 } else {
3967 if (state)
3968 its_vpe_send_cmd(vpe, its_send_int);
3969 else
3970 its_vpe_send_cmd(vpe, its_send_clear);
3971 }
3972
3973 return 0;
3974}
3975
3976static int its_vpe_retrigger(struct irq_data *d)
3977{
3978 return !its_vpe_set_irqchip_state(d, IRQCHIP_STATE_PENDING, true);
3979}
3980
3981static struct irq_chip its_vpe_irq_chip = {
3982 .name = "GICv4-vpe",
3983 .irq_mask = its_vpe_mask_irq,
3984 .irq_unmask = its_vpe_unmask_irq,
3985 .irq_eoi = irq_chip_eoi_parent,
3986 .irq_set_affinity = its_vpe_set_affinity,
3987 .irq_retrigger = its_vpe_retrigger,
3988 .irq_set_irqchip_state = its_vpe_set_irqchip_state,
3989 .irq_set_vcpu_affinity = its_vpe_set_vcpu_affinity,
3990};
3991
3992static struct its_node *find_4_1_its(void)
3993{
3994 static struct its_node *its = NULL;
3995
3996 if (!its) {
3997 list_for_each_entry(its, &its_nodes, entry) {
3998 if (is_v4_1(its))
3999 return its;
4000 }
4001
4002 /* Oops? */
4003 its = NULL;
4004 }
4005
4006 return its;
4007}
4008
4009static void its_vpe_4_1_send_inv(struct irq_data *d)
4010{
4011 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4012 struct its_node *its;
4013
4014 /*
4015 * GICv4.1 wants doorbells to be invalidated using the
4016 * INVDB command in order to be broadcast to all RDs. Send
4017 * it to the first valid ITS, and let the HW do its magic.
4018 */
4019 its = find_4_1_its();
4020 if (its)
4021 its_send_invdb(its, vpe);
4022}
4023
4024static void its_vpe_4_1_mask_irq(struct irq_data *d)
4025{
4026 lpi_write_config(d->parent_data, LPI_PROP_ENABLED, 0);
4027 its_vpe_4_1_send_inv(d);
4028}
4029
4030static void its_vpe_4_1_unmask_irq(struct irq_data *d)
4031{
4032 lpi_write_config(d->parent_data, 0, LPI_PROP_ENABLED);
4033 its_vpe_4_1_send_inv(d);
4034}
4035
4036static void its_vpe_4_1_schedule(struct its_vpe *vpe,
4037 struct its_cmd_info *info)
4038{
4039 void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
4040 u64 val = 0;
4041
4042 /* Schedule the VPE */
4043 val |= GICR_VPENDBASER_Valid;
4044 val |= info->g0en ? GICR_VPENDBASER_4_1_VGRP0EN : 0;
4045 val |= info->g1en ? GICR_VPENDBASER_4_1_VGRP1EN : 0;
4046 val |= FIELD_PREP(GICR_VPENDBASER_4_1_VPEID, vpe->vpe_id);
4047
4048 gicr_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER);
4049
4050 its_wait_vpt_parse_complete();
4051}
4052
4053static void its_vpe_4_1_deschedule(struct its_vpe *vpe,
4054 struct its_cmd_info *info)
4055{
4056 void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
4057 u64 val;
4058
4059 if (info->req_db) {
4060 unsigned long flags;
4061
4062 /*
4063 * vPE is going to block: make the vPE non-resident with
4064 * PendingLast clear and DB set. The GIC guarantees that if
4065 * we read-back PendingLast clear, then a doorbell will be
4066 * delivered when an interrupt comes.
4067 *
4068 * Note the locking to deal with the concurrent update of
4069 * pending_last from the doorbell interrupt handler that can
4070 * run concurrently.
4071 */
4072 raw_spin_lock_irqsave(&vpe->vpe_lock, flags);
4073 val = its_clear_vpend_valid(vlpi_base,
4074 GICR_VPENDBASER_PendingLast,
4075 GICR_VPENDBASER_4_1_DB);
4076 vpe->pending_last = !!(val & GICR_VPENDBASER_PendingLast);
4077 raw_spin_unlock_irqrestore(&vpe->vpe_lock, flags);
4078 } else {
4079 /*
4080 * We're not blocking, so just make the vPE non-resident
4081 * with PendingLast set, indicating that we'll be back.
4082 */
4083 val = its_clear_vpend_valid(vlpi_base,
4084 0,
4085 GICR_VPENDBASER_PendingLast);
4086 vpe->pending_last = true;
4087 }
4088}
4089
4090static void its_vpe_4_1_invall(struct its_vpe *vpe)
4091{
4092 void __iomem *rdbase;
4093 unsigned long flags;
4094 u64 val;
4095 int cpu;
4096
4097 val = GICR_INVALLR_V;
4098 val |= FIELD_PREP(GICR_INVALLR_VPEID, vpe->vpe_id);
4099
4100 /* Target the redistributor this vPE is currently known on */
4101 cpu = vpe_to_cpuid_lock(vpe, &flags);
4102 raw_spin_lock(&gic_data_rdist_cpu(cpu)->rd_lock);
4103 rdbase = per_cpu_ptr(gic_rdists->rdist, cpu)->rd_base;
4104 gic_write_lpir(val, rdbase + GICR_INVALLR);
4105
4106 wait_for_syncr(rdbase);
4107 raw_spin_unlock(&gic_data_rdist_cpu(cpu)->rd_lock);
4108 vpe_to_cpuid_unlock(vpe, flags);
4109}
4110
4111static int its_vpe_4_1_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
4112{
4113 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4114 struct its_cmd_info *info = vcpu_info;
4115
4116 switch (info->cmd_type) {
4117 case SCHEDULE_VPE:
4118 its_vpe_4_1_schedule(vpe, info);
4119 return 0;
4120
4121 case DESCHEDULE_VPE:
4122 its_vpe_4_1_deschedule(vpe, info);
4123 return 0;
4124
4125 case INVALL_VPE:
4126 its_vpe_4_1_invall(vpe);
4127 return 0;
4128
4129 default:
4130 return -EINVAL;
4131 }
4132}
4133
4134static struct irq_chip its_vpe_4_1_irq_chip = {
4135 .name = "GICv4.1-vpe",
4136 .irq_mask = its_vpe_4_1_mask_irq,
4137 .irq_unmask = its_vpe_4_1_unmask_irq,
4138 .irq_eoi = irq_chip_eoi_parent,
4139 .irq_set_affinity = its_vpe_set_affinity,
4140 .irq_set_vcpu_affinity = its_vpe_4_1_set_vcpu_affinity,
4141};
4142
4143static void its_configure_sgi(struct irq_data *d, bool clear)
4144{
4145 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4146 struct its_cmd_desc desc;
4147
4148 desc.its_vsgi_cmd.vpe = vpe;
4149 desc.its_vsgi_cmd.sgi = d->hwirq;
4150 desc.its_vsgi_cmd.priority = vpe->sgi_config[d->hwirq].priority;
4151 desc.its_vsgi_cmd.enable = vpe->sgi_config[d->hwirq].enabled;
4152 desc.its_vsgi_cmd.group = vpe->sgi_config[d->hwirq].group;
4153 desc.its_vsgi_cmd.clear = clear;
4154
4155 /*
4156 * GICv4.1 allows us to send VSGI commands to any ITS as long as the
4157 * destination VPE is mapped there. Since we map them eagerly at
4158 * activation time, we're pretty sure the first GICv4.1 ITS will do.
4159 */
4160 its_send_single_vcommand(find_4_1_its(), its_build_vsgi_cmd, &desc);
4161}
4162
4163static void its_sgi_mask_irq(struct irq_data *d)
4164{
4165 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4166
4167 vpe->sgi_config[d->hwirq].enabled = false;
4168 its_configure_sgi(d, false);
4169}
4170
4171static void its_sgi_unmask_irq(struct irq_data *d)
4172{
4173 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4174
4175 vpe->sgi_config[d->hwirq].enabled = true;
4176 its_configure_sgi(d, false);
4177}
4178
4179static int its_sgi_set_affinity(struct irq_data *d,
4180 const struct cpumask *mask_val,
4181 bool force)
4182{
4183 /*
4184 * There is no notion of affinity for virtual SGIs, at least
4185 * not on the host (since they can only be targetting a vPE).
4186 * Tell the kernel we've done whatever it asked for.
4187 */
4188 irq_data_update_effective_affinity(d, mask_val);
4189 return IRQ_SET_MASK_OK;
4190}
4191
4192static int its_sgi_set_irqchip_state(struct irq_data *d,
4193 enum irqchip_irq_state which,
4194 bool state)
4195{
4196 if (which != IRQCHIP_STATE_PENDING)
4197 return -EINVAL;
4198
4199 if (state) {
4200 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4201 struct its_node *its = find_4_1_its();
4202 u64 val;
4203
4204 val = FIELD_PREP(GITS_SGIR_VPEID, vpe->vpe_id);
4205 val |= FIELD_PREP(GITS_SGIR_VINTID, d->hwirq);
4206 writeq_relaxed(val, its->sgir_base + GITS_SGIR - SZ_128K);
4207 } else {
4208 its_configure_sgi(d, true);
4209 }
4210
4211 return 0;
4212}
4213
4214static int its_sgi_get_irqchip_state(struct irq_data *d,
4215 enum irqchip_irq_state which, bool *val)
4216{
4217 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4218 void __iomem *base;
4219 unsigned long flags;
4220 u32 count = 1000000; /* 1s! */
4221 u32 status;
4222 int cpu;
4223
4224 if (which != IRQCHIP_STATE_PENDING)
4225 return -EINVAL;
4226
4227 /*
4228 * Locking galore! We can race against two different events:
4229 *
4230 * - Concurent vPE affinity change: we must make sure it cannot
4231 * happen, or we'll talk to the wrong redistributor. This is
4232 * identical to what happens with vLPIs.
4233 *
4234 * - Concurrent VSGIPENDR access: As it involves accessing two
4235 * MMIO registers, this must be made atomic one way or another.
4236 */
4237 cpu = vpe_to_cpuid_lock(vpe, &flags);
4238 raw_spin_lock(&gic_data_rdist_cpu(cpu)->rd_lock);
4239 base = gic_data_rdist_cpu(cpu)->rd_base + SZ_128K;
4240 writel_relaxed(vpe->vpe_id, base + GICR_VSGIR);
4241 do {
4242 status = readl_relaxed(base + GICR_VSGIPENDR);
4243 if (!(status & GICR_VSGIPENDR_BUSY))
4244 goto out;
4245
4246 count--;
4247 if (!count) {
4248 pr_err_ratelimited("Unable to get SGI status\n");
4249 goto out;
4250 }
4251 cpu_relax();
4252 udelay(1);
4253 } while (count);
4254
4255out:
4256 raw_spin_unlock(&gic_data_rdist_cpu(cpu)->rd_lock);
4257 vpe_to_cpuid_unlock(vpe, flags);
4258
4259 if (!count)
4260 return -ENXIO;
4261
4262 *val = !!(status & (1 << d->hwirq));
4263
4264 return 0;
4265}
4266
4267static int its_sgi_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
4268{
4269 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4270 struct its_cmd_info *info = vcpu_info;
4271
4272 switch (info->cmd_type) {
4273 case PROP_UPDATE_VSGI:
4274 vpe->sgi_config[d->hwirq].priority = info->priority;
4275 vpe->sgi_config[d->hwirq].group = info->group;
4276 its_configure_sgi(d, false);
4277 return 0;
4278
4279 default:
4280 return -EINVAL;
4281 }
4282}
4283
4284static struct irq_chip its_sgi_irq_chip = {
4285 .name = "GICv4.1-sgi",
4286 .irq_mask = its_sgi_mask_irq,
4287 .irq_unmask = its_sgi_unmask_irq,
4288 .irq_set_affinity = its_sgi_set_affinity,
4289 .irq_set_irqchip_state = its_sgi_set_irqchip_state,
4290 .irq_get_irqchip_state = its_sgi_get_irqchip_state,
4291 .irq_set_vcpu_affinity = its_sgi_set_vcpu_affinity,
4292};
4293
4294static int its_sgi_irq_domain_alloc(struct irq_domain *domain,
4295 unsigned int virq, unsigned int nr_irqs,
4296 void *args)
4297{
4298 struct its_vpe *vpe = args;
4299 int i;
4300
4301 /* Yes, we do want 16 SGIs */
4302 WARN_ON(nr_irqs != 16);
4303
4304 for (i = 0; i < 16; i++) {
4305 vpe->sgi_config[i].priority = 0;
4306 vpe->sgi_config[i].enabled = false;
4307 vpe->sgi_config[i].group = false;
4308
4309 irq_domain_set_hwirq_and_chip(domain, virq + i, i,
4310 &its_sgi_irq_chip, vpe);
4311 irq_set_status_flags(virq + i, IRQ_DISABLE_UNLAZY);
4312 }
4313
4314 return 0;
4315}
4316
4317static void its_sgi_irq_domain_free(struct irq_domain *domain,
4318 unsigned int virq,
4319 unsigned int nr_irqs)
4320{
4321 /* Nothing to do */
4322}
4323
4324static int its_sgi_irq_domain_activate(struct irq_domain *domain,
4325 struct irq_data *d, bool reserve)
4326{
4327 /* Write out the initial SGI configuration */
4328 its_configure_sgi(d, false);
4329 return 0;
4330}
4331
4332static void its_sgi_irq_domain_deactivate(struct irq_domain *domain,
4333 struct irq_data *d)
4334{
4335 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4336
4337 /*
4338 * The VSGI command is awkward:
4339 *
4340 * - To change the configuration, CLEAR must be set to false,
4341 * leaving the pending bit unchanged.
4342 * - To clear the pending bit, CLEAR must be set to true, leaving
4343 * the configuration unchanged.
4344 *
4345 * You just can't do both at once, hence the two commands below.
4346 */
4347 vpe->sgi_config[d->hwirq].enabled = false;
4348 its_configure_sgi(d, false);
4349 its_configure_sgi(d, true);
4350}
4351
4352static const struct irq_domain_ops its_sgi_domain_ops = {
4353 .alloc = its_sgi_irq_domain_alloc,
4354 .free = its_sgi_irq_domain_free,
4355 .activate = its_sgi_irq_domain_activate,
4356 .deactivate = its_sgi_irq_domain_deactivate,
4357};
4358
4359static int its_vpe_id_alloc(void)
4360{
4361 return ida_simple_get(&its_vpeid_ida, 0, ITS_MAX_VPEID, GFP_KERNEL);
4362}
4363
4364static void its_vpe_id_free(u16 id)
4365{
4366 ida_simple_remove(&its_vpeid_ida, id);
4367}
4368
4369static int its_vpe_init(struct its_vpe *vpe)
4370{
4371 struct page *vpt_page;
4372 int vpe_id;
4373
4374 /* Allocate vpe_id */
4375 vpe_id = its_vpe_id_alloc();
4376 if (vpe_id < 0)
4377 return vpe_id;
4378
4379 /* Allocate VPT */
4380 vpt_page = its_allocate_pending_table(GFP_KERNEL);
4381 if (!vpt_page) {
4382 its_vpe_id_free(vpe_id);
4383 return -ENOMEM;
4384 }
4385
4386 if (!its_alloc_vpe_table(vpe_id)) {
4387 its_vpe_id_free(vpe_id);
4388 its_free_pending_table(vpt_page);
4389 return -ENOMEM;
4390 }
4391
4392 raw_spin_lock_init(&vpe->vpe_lock);
4393 vpe->vpe_id = vpe_id;
4394 vpe->vpt_page = vpt_page;
4395 if (gic_rdists->has_rvpeid)
4396 atomic_set(&vpe->vmapp_count, 0);
4397 else
4398 vpe->vpe_proxy_event = -1;
4399
4400 return 0;
4401}
4402
4403static void its_vpe_teardown(struct its_vpe *vpe)
4404{
4405 its_vpe_db_proxy_unmap(vpe);
4406 its_vpe_id_free(vpe->vpe_id);
4407 its_free_pending_table(vpe->vpt_page);
4408}
4409
4410static void its_vpe_irq_domain_free(struct irq_domain *domain,
4411 unsigned int virq,
4412 unsigned int nr_irqs)
4413{
4414 struct its_vm *vm = domain->host_data;
4415 int i;
4416
4417 irq_domain_free_irqs_parent(domain, virq, nr_irqs);
4418
4419 for (i = 0; i < nr_irqs; i++) {
4420 struct irq_data *data = irq_domain_get_irq_data(domain,
4421 virq + i);
4422 struct its_vpe *vpe = irq_data_get_irq_chip_data(data);
4423
4424 BUG_ON(vm != vpe->its_vm);
4425
4426 clear_bit(data->hwirq, vm->db_bitmap);
4427 its_vpe_teardown(vpe);
4428 irq_domain_reset_irq_data(data);
4429 }
4430
4431 if (bitmap_empty(vm->db_bitmap, vm->nr_db_lpis)) {
4432 its_lpi_free(vm->db_bitmap, vm->db_lpi_base, vm->nr_db_lpis);
4433 its_free_prop_table(vm->vprop_page);
4434 }
4435}
4436
4437static int its_vpe_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
4438 unsigned int nr_irqs, void *args)
4439{
4440 struct irq_chip *irqchip = &its_vpe_irq_chip;
4441 struct its_vm *vm = args;
4442 unsigned long *bitmap;
4443 struct page *vprop_page;
4444 int base, nr_ids, i, err = 0;
4445
4446 BUG_ON(!vm);
4447
4448 bitmap = its_lpi_alloc(roundup_pow_of_two(nr_irqs), &base, &nr_ids);
4449 if (!bitmap)
4450 return -ENOMEM;
4451
4452 if (nr_ids < nr_irqs) {
4453 its_lpi_free(bitmap, base, nr_ids);
4454 return -ENOMEM;
4455 }
4456
4457 vprop_page = its_allocate_prop_table(GFP_KERNEL);
4458 if (!vprop_page) {
4459 its_lpi_free(bitmap, base, nr_ids);
4460 return -ENOMEM;
4461 }
4462
4463 vm->db_bitmap = bitmap;
4464 vm->db_lpi_base = base;
4465 vm->nr_db_lpis = nr_ids;
4466 vm->vprop_page = vprop_page;
4467
4468 if (gic_rdists->has_rvpeid)
4469 irqchip = &its_vpe_4_1_irq_chip;
4470
4471 for (i = 0; i < nr_irqs; i++) {
4472 vm->vpes[i]->vpe_db_lpi = base + i;
4473 err = its_vpe_init(vm->vpes[i]);
4474 if (err)
4475 break;
4476 err = its_irq_gic_domain_alloc(domain, virq + i,
4477 vm->vpes[i]->vpe_db_lpi);
4478 if (err)
4479 break;
4480 irq_domain_set_hwirq_and_chip(domain, virq + i, i,
4481 irqchip, vm->vpes[i]);
4482 set_bit(i, bitmap);
4483 }
4484
4485 if (err) {
4486 if (i > 0)
4487 its_vpe_irq_domain_free(domain, virq, i - 1);
4488
4489 its_lpi_free(bitmap, base, nr_ids);
4490 its_free_prop_table(vprop_page);
4491 }
4492
4493 return err;
4494}
4495
4496static int its_vpe_irq_domain_activate(struct irq_domain *domain,
4497 struct irq_data *d, bool reserve)
4498{
4499 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4500 struct its_node *its;
4501
4502 /*
4503 * If we use the list map, we issue VMAPP on demand... Unless
4504 * we're on a GICv4.1 and we eagerly map the VPE on all ITSs
4505 * so that VSGIs can work.
4506 */
4507 if (!gic_requires_eager_mapping())
4508 return 0;
4509
4510 /* Map the VPE to the first possible CPU */
4511 vpe->col_idx = cpumask_first(cpu_online_mask);
4512
4513 list_for_each_entry(its, &its_nodes, entry) {
4514 if (!is_v4(its))
4515 continue;
4516
4517 its_send_vmapp(its, vpe, true);
4518 its_send_vinvall(its, vpe);
4519 }
4520
4521 irq_data_update_effective_affinity(d, cpumask_of(vpe->col_idx));
4522
4523 return 0;
4524}
4525
4526static void its_vpe_irq_domain_deactivate(struct irq_domain *domain,
4527 struct irq_data *d)
4528{
4529 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4530 struct its_node *its;
4531
4532 /*
4533 * If we use the list map on GICv4.0, we unmap the VPE once no
4534 * VLPIs are associated with the VM.
4535 */
4536 if (!gic_requires_eager_mapping())
4537 return;
4538
4539 list_for_each_entry(its, &its_nodes, entry) {
4540 if (!is_v4(its))
4541 continue;
4542
4543 its_send_vmapp(its, vpe, false);
4544 }
4545}
4546
4547static const struct irq_domain_ops its_vpe_domain_ops = {
4548 .alloc = its_vpe_irq_domain_alloc,
4549 .free = its_vpe_irq_domain_free,
4550 .activate = its_vpe_irq_domain_activate,
4551 .deactivate = its_vpe_irq_domain_deactivate,
4552};
4553
4554static int its_force_quiescent(void __iomem *base)
4555{
4556 u32 count = 1000000; /* 1s */
4557 u32 val;
4558
4559 val = readl_relaxed(base + GITS_CTLR);
4560 /*
4561 * GIC architecture specification requires the ITS to be both
4562 * disabled and quiescent for writes to GITS_BASER<n> or
4563 * GITS_CBASER to not have UNPREDICTABLE results.
4564 */
4565 if ((val & GITS_CTLR_QUIESCENT) && !(val & GITS_CTLR_ENABLE))
4566 return 0;
4567
4568 /* Disable the generation of all interrupts to this ITS */
4569 val &= ~(GITS_CTLR_ENABLE | GITS_CTLR_ImDe);
4570 writel_relaxed(val, base + GITS_CTLR);
4571
4572 /* Poll GITS_CTLR and wait until ITS becomes quiescent */
4573 while (1) {
4574 val = readl_relaxed(base + GITS_CTLR);
4575 if (val & GITS_CTLR_QUIESCENT)
4576 return 0;
4577
4578 count--;
4579 if (!count)
4580 return -EBUSY;
4581
4582 cpu_relax();
4583 udelay(1);
4584 }
4585}
4586
4587static bool __maybe_unused its_enable_quirk_cavium_22375(void *data)
4588{
4589 struct its_node *its = data;
4590
4591 /* erratum 22375: only alloc 8MB table size (20 bits) */
4592 its->typer &= ~GITS_TYPER_DEVBITS;
4593 its->typer |= FIELD_PREP(GITS_TYPER_DEVBITS, 20 - 1);
4594 its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_22375;
4595
4596 return true;
4597}
4598
4599static bool __maybe_unused its_enable_quirk_cavium_23144(void *data)
4600{
4601 struct its_node *its = data;
4602
4603 its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_23144;
4604
4605 return true;
4606}
4607
4608static bool __maybe_unused its_enable_quirk_qdf2400_e0065(void *data)
4609{
4610 struct its_node *its = data;
4611
4612 /* On QDF2400, the size of the ITE is 16Bytes */
4613 its->typer &= ~GITS_TYPER_ITT_ENTRY_SIZE;
4614 its->typer |= FIELD_PREP(GITS_TYPER_ITT_ENTRY_SIZE, 16 - 1);
4615
4616 return true;
4617}
4618
4619static u64 its_irq_get_msi_base_pre_its(struct its_device *its_dev)
4620{
4621 struct its_node *its = its_dev->its;
4622
4623 /*
4624 * The Socionext Synquacer SoC has a so-called 'pre-ITS',
4625 * which maps 32-bit writes targeted at a separate window of
4626 * size '4 << device_id_bits' onto writes to GITS_TRANSLATER
4627 * with device ID taken from bits [device_id_bits + 1:2] of
4628 * the window offset.
4629 */
4630 return its->pre_its_base + (its_dev->device_id << 2);
4631}
4632
4633static bool __maybe_unused its_enable_quirk_socionext_synquacer(void *data)
4634{
4635 struct its_node *its = data;
4636 u32 pre_its_window[2];
4637 u32 ids;
4638
4639 if (!fwnode_property_read_u32_array(its->fwnode_handle,
4640 "socionext,synquacer-pre-its",
4641 pre_its_window,
4642 ARRAY_SIZE(pre_its_window))) {
4643
4644 its->pre_its_base = pre_its_window[0];
4645 its->get_msi_base = its_irq_get_msi_base_pre_its;
4646
4647 ids = ilog2(pre_its_window[1]) - 2;
4648 if (device_ids(its) > ids) {
4649 its->typer &= ~GITS_TYPER_DEVBITS;
4650 its->typer |= FIELD_PREP(GITS_TYPER_DEVBITS, ids - 1);
4651 }
4652
4653 /* the pre-ITS breaks isolation, so disable MSI remapping */
4654 its->msi_domain_flags &= ~IRQ_DOMAIN_FLAG_MSI_REMAP;
4655 return true;
4656 }
4657 return false;
4658}
4659
4660static bool __maybe_unused its_enable_quirk_hip07_161600802(void *data)
4661{
4662 struct its_node *its = data;
4663
4664 /*
4665 * Hip07 insists on using the wrong address for the VLPI
4666 * page. Trick it into doing the right thing...
4667 */
4668 its->vlpi_redist_offset = SZ_128K;
4669 return true;
4670}
4671
4672static const struct gic_quirk its_quirks[] = {
4673#ifdef CONFIG_CAVIUM_ERRATUM_22375
4674 {
4675 .desc = "ITS: Cavium errata 22375, 24313",
4676 .iidr = 0xa100034c, /* ThunderX pass 1.x */
4677 .mask = 0xffff0fff,
4678 .init = its_enable_quirk_cavium_22375,
4679 },
4680#endif
4681#ifdef CONFIG_CAVIUM_ERRATUM_23144
4682 {
4683 .desc = "ITS: Cavium erratum 23144",
4684 .iidr = 0xa100034c, /* ThunderX pass 1.x */
4685 .mask = 0xffff0fff,
4686 .init = its_enable_quirk_cavium_23144,
4687 },
4688#endif
4689#ifdef CONFIG_QCOM_QDF2400_ERRATUM_0065
4690 {
4691 .desc = "ITS: QDF2400 erratum 0065",
4692 .iidr = 0x00001070, /* QDF2400 ITS rev 1.x */
4693 .mask = 0xffffffff,
4694 .init = its_enable_quirk_qdf2400_e0065,
4695 },
4696#endif
4697#ifdef CONFIG_SOCIONEXT_SYNQUACER_PREITS
4698 {
4699 /*
4700 * The Socionext Synquacer SoC incorporates ARM's own GIC-500
4701 * implementation, but with a 'pre-ITS' added that requires
4702 * special handling in software.
4703 */
4704 .desc = "ITS: Socionext Synquacer pre-ITS",
4705 .iidr = 0x0001143b,
4706 .mask = 0xffffffff,
4707 .init = its_enable_quirk_socionext_synquacer,
4708 },
4709#endif
4710#ifdef CONFIG_HISILICON_ERRATUM_161600802
4711 {
4712 .desc = "ITS: Hip07 erratum 161600802",
4713 .iidr = 0x00000004,
4714 .mask = 0xffffffff,
4715 .init = its_enable_quirk_hip07_161600802,
4716 },
4717#endif
4718 {
4719 }
4720};
4721
4722static void its_enable_quirks(struct its_node *its)
4723{
4724 u32 iidr = readl_relaxed(its->base + GITS_IIDR);
4725
4726 gic_enable_quirks(iidr, its_quirks, its);
4727}
4728
4729static int its_save_disable(void)
4730{
4731 struct its_node *its;
4732 int err = 0;
4733
4734 raw_spin_lock(&its_lock);
4735 list_for_each_entry(its, &its_nodes, entry) {
4736 void __iomem *base;
4737
4738 if (!(its->flags & ITS_FLAGS_SAVE_SUSPEND_STATE))
4739 continue;
4740
4741 base = its->base;
4742 its->ctlr_save = readl_relaxed(base + GITS_CTLR);
4743 err = its_force_quiescent(base);
4744 if (err) {
4745 pr_err("ITS@%pa: failed to quiesce: %d\n",
4746 &its->phys_base, err);
4747 writel_relaxed(its->ctlr_save, base + GITS_CTLR);
4748 goto err;
4749 }
4750
4751 its->cbaser_save = gits_read_cbaser(base + GITS_CBASER);
4752 }
4753
4754err:
4755 if (err) {
4756 list_for_each_entry_continue_reverse(its, &its_nodes, entry) {
4757 void __iomem *base;
4758
4759 if (!(its->flags & ITS_FLAGS_SAVE_SUSPEND_STATE))
4760 continue;
4761
4762 base = its->base;
4763 writel_relaxed(its->ctlr_save, base + GITS_CTLR);
4764 }
4765 }
4766 raw_spin_unlock(&its_lock);
4767
4768 return err;
4769}
4770
4771static void its_restore_enable(void)
4772{
4773 struct its_node *its;
4774 int ret;
4775
4776 raw_spin_lock(&its_lock);
4777 list_for_each_entry(its, &its_nodes, entry) {
4778 void __iomem *base;
4779 int i;
4780
4781 if (!(its->flags & ITS_FLAGS_SAVE_SUSPEND_STATE))
4782 continue;
4783
4784 base = its->base;
4785
4786 /*
4787 * Make sure that the ITS is disabled. If it fails to quiesce,
4788 * don't restore it since writing to CBASER or BASER<n>
4789 * registers is undefined according to the GIC v3 ITS
4790 * Specification.
4791 */
4792 ret = its_force_quiescent(base);
4793 if (ret) {
4794 pr_err("ITS@%pa: failed to quiesce on resume: %d\n",
4795 &its->phys_base, ret);
4796 continue;
4797 }
4798
4799 gits_write_cbaser(its->cbaser_save, base + GITS_CBASER);
4800
4801 /*
4802 * Writing CBASER resets CREADR to 0, so make CWRITER and
4803 * cmd_write line up with it.
4804 */
4805 its->cmd_write = its->cmd_base;
4806 gits_write_cwriter(0, base + GITS_CWRITER);
4807
4808 /* Restore GITS_BASER from the value cache. */
4809 for (i = 0; i < GITS_BASER_NR_REGS; i++) {
4810 struct its_baser *baser = &its->tables[i];
4811
4812 if (!(baser->val & GITS_BASER_VALID))
4813 continue;
4814
4815 its_write_baser(its, baser, baser->val);
4816 }
4817 writel_relaxed(its->ctlr_save, base + GITS_CTLR);
4818
4819 /*
4820 * Reinit the collection if it's stored in the ITS. This is
4821 * indicated by the col_id being less than the HCC field.
4822 * CID < HCC as specified in the GIC v3 Documentation.
4823 */
4824 if (its->collections[smp_processor_id()].col_id <
4825 GITS_TYPER_HCC(gic_read_typer(base + GITS_TYPER)))
4826 its_cpu_init_collection(its);
4827 }
4828 raw_spin_unlock(&its_lock);
4829}
4830
4831static struct syscore_ops its_syscore_ops = {
4832 .suspend = its_save_disable,
4833 .resume = its_restore_enable,
4834};
4835
4836static int its_init_domain(struct fwnode_handle *handle, struct its_node *its)
4837{
4838 struct irq_domain *inner_domain;
4839 struct msi_domain_info *info;
4840
4841 info = kzalloc(sizeof(*info), GFP_KERNEL);
4842 if (!info)
4843 return -ENOMEM;
4844
4845 inner_domain = irq_domain_create_tree(handle, &its_domain_ops, its);
4846 if (!inner_domain) {
4847 kfree(info);
4848 return -ENOMEM;
4849 }
4850
4851 inner_domain->parent = its_parent;
4852 irq_domain_update_bus_token(inner_domain, DOMAIN_BUS_NEXUS);
4853 inner_domain->flags |= its->msi_domain_flags;
4854 info->ops = &its_msi_domain_ops;
4855 info->data = its;
4856 inner_domain->host_data = info;
4857
4858 return 0;
4859}
4860
4861static int its_init_vpe_domain(void)
4862{
4863 struct its_node *its;
4864 u32 devid;
4865 int entries;
4866
4867 if (gic_rdists->has_direct_lpi) {
4868 pr_info("ITS: Using DirectLPI for VPE invalidation\n");
4869 return 0;
4870 }
4871
4872 /* Any ITS will do, even if not v4 */
4873 its = list_first_entry(&its_nodes, struct its_node, entry);
4874
4875 entries = roundup_pow_of_two(nr_cpu_ids);
4876 vpe_proxy.vpes = kcalloc(entries, sizeof(*vpe_proxy.vpes),
4877 GFP_KERNEL);
4878 if (!vpe_proxy.vpes) {
4879 pr_err("ITS: Can't allocate GICv4 proxy device array\n");
4880 return -ENOMEM;
4881 }
4882
4883 /* Use the last possible DevID */
4884 devid = GENMASK(device_ids(its) - 1, 0);
4885 vpe_proxy.dev = its_create_device(its, devid, entries, false);
4886 if (!vpe_proxy.dev) {
4887 kfree(vpe_proxy.vpes);
4888 pr_err("ITS: Can't allocate GICv4 proxy device\n");
4889 return -ENOMEM;
4890 }
4891
4892 BUG_ON(entries > vpe_proxy.dev->nr_ites);
4893
4894 raw_spin_lock_init(&vpe_proxy.lock);
4895 vpe_proxy.next_victim = 0;
4896 pr_info("ITS: Allocated DevID %x as GICv4 proxy device (%d slots)\n",
4897 devid, vpe_proxy.dev->nr_ites);
4898
4899 return 0;
4900}
4901
4902static int __init its_compute_its_list_map(struct resource *res,
4903 void __iomem *its_base)
4904{
4905 int its_number;
4906 u32 ctlr;
4907
4908 /*
4909 * This is assumed to be done early enough that we're
4910 * guaranteed to be single-threaded, hence no
4911 * locking. Should this change, we should address
4912 * this.
4913 */
4914 its_number = find_first_zero_bit(&its_list_map, GICv4_ITS_LIST_MAX);
4915 if (its_number >= GICv4_ITS_LIST_MAX) {
4916 pr_err("ITS@%pa: No ITSList entry available!\n",
4917 &res->start);
4918 return -EINVAL;
4919 }
4920
4921 ctlr = readl_relaxed(its_base + GITS_CTLR);
4922 ctlr &= ~GITS_CTLR_ITS_NUMBER;
4923 ctlr |= its_number << GITS_CTLR_ITS_NUMBER_SHIFT;
4924 writel_relaxed(ctlr, its_base + GITS_CTLR);
4925 ctlr = readl_relaxed(its_base + GITS_CTLR);
4926 if ((ctlr & GITS_CTLR_ITS_NUMBER) != (its_number << GITS_CTLR_ITS_NUMBER_SHIFT)) {
4927 its_number = ctlr & GITS_CTLR_ITS_NUMBER;
4928 its_number >>= GITS_CTLR_ITS_NUMBER_SHIFT;
4929 }
4930
4931 if (test_and_set_bit(its_number, &its_list_map)) {
4932 pr_err("ITS@%pa: Duplicate ITSList entry %d\n",
4933 &res->start, its_number);
4934 return -EINVAL;
4935 }
4936
4937 return its_number;
4938}
4939
4940static int __init its_probe_one(struct resource *res,
4941 struct fwnode_handle *handle, int numa_node)
4942{
4943 struct its_node *its;
4944 void __iomem *its_base;
4945 u32 val, ctlr;
4946 u64 baser, tmp, typer;
4947 struct page *page;
4948 int err;
4949
4950 its_base = ioremap(res->start, SZ_64K);
4951 if (!its_base) {
4952 pr_warn("ITS@%pa: Unable to map ITS registers\n", &res->start);
4953 return -ENOMEM;
4954 }
4955
4956 val = readl_relaxed(its_base + GITS_PIDR2) & GIC_PIDR2_ARCH_MASK;
4957 if (val != 0x30 && val != 0x40) {
4958 pr_warn("ITS@%pa: No ITS detected, giving up\n", &res->start);
4959 err = -ENODEV;
4960 goto out_unmap;
4961 }
4962
4963 err = its_force_quiescent(its_base);
4964 if (err) {
4965 pr_warn("ITS@%pa: Failed to quiesce, giving up\n", &res->start);
4966 goto out_unmap;
4967 }
4968
4969 pr_info("ITS %pR\n", res);
4970
4971 its = kzalloc(sizeof(*its), GFP_KERNEL);
4972 if (!its) {
4973 err = -ENOMEM;
4974 goto out_unmap;
4975 }
4976
4977 raw_spin_lock_init(&its->lock);
4978 mutex_init(&its->dev_alloc_lock);
4979 INIT_LIST_HEAD(&its->entry);
4980 INIT_LIST_HEAD(&its->its_device_list);
4981 typer = gic_read_typer(its_base + GITS_TYPER);
4982 its->typer = typer;
4983 its->base = its_base;
4984 its->phys_base = res->start;
4985 if (is_v4(its)) {
4986 if (!(typer & GITS_TYPER_VMOVP)) {
4987 err = its_compute_its_list_map(res, its_base);
4988 if (err < 0)
4989 goto out_free_its;
4990
4991 its->list_nr = err;
4992
4993 pr_info("ITS@%pa: Using ITS number %d\n",
4994 &res->start, err);
4995 } else {
4996 pr_info("ITS@%pa: Single VMOVP capable\n", &res->start);
4997 }
4998
4999 if (is_v4_1(its)) {
5000 u32 svpet = FIELD_GET(GITS_TYPER_SVPET, typer);
5001
5002 its->sgir_base = ioremap(res->start + SZ_128K, SZ_64K);
5003 if (!its->sgir_base) {
5004 err = -ENOMEM;
5005 goto out_free_its;
5006 }
5007
5008 its->mpidr = readl_relaxed(its_base + GITS_MPIDR);
5009
5010 pr_info("ITS@%pa: Using GICv4.1 mode %08x %08x\n",
5011 &res->start, its->mpidr, svpet);
5012 }
5013 }
5014
5015 its->numa_node = numa_node;
5016
5017 page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO,
5018 get_order(ITS_CMD_QUEUE_SZ));
5019 if (!page) {
5020 err = -ENOMEM;
5021 goto out_unmap_sgir;
5022 }
5023 its->cmd_base = (void *)page_address(page);
5024 its->cmd_write = its->cmd_base;
5025 its->fwnode_handle = handle;
5026 its->get_msi_base = its_irq_get_msi_base;
5027 its->msi_domain_flags = IRQ_DOMAIN_FLAG_MSI_REMAP;
5028
5029 its_enable_quirks(its);
5030
5031 err = its_alloc_tables(its);
5032 if (err)
5033 goto out_free_cmd;
5034
5035 err = its_alloc_collections(its);
5036 if (err)
5037 goto out_free_tables;
5038
5039 baser = (virt_to_phys(its->cmd_base) |
5040 GITS_CBASER_RaWaWb |
5041 GITS_CBASER_InnerShareable |
5042 (ITS_CMD_QUEUE_SZ / SZ_4K - 1) |
5043 GITS_CBASER_VALID);
5044
5045 gits_write_cbaser(baser, its->base + GITS_CBASER);
5046 tmp = gits_read_cbaser(its->base + GITS_CBASER);
5047
5048 if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) {
5049 if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) {
5050 /*
5051 * The HW reports non-shareable, we must
5052 * remove the cacheability attributes as
5053 * well.
5054 */
5055 baser &= ~(GITS_CBASER_SHAREABILITY_MASK |
5056 GITS_CBASER_CACHEABILITY_MASK);
5057 baser |= GITS_CBASER_nC;
5058 gits_write_cbaser(baser, its->base + GITS_CBASER);
5059 }
5060 pr_info("ITS: using cache flushing for cmd queue\n");
5061 its->flags |= ITS_FLAGS_CMDQ_NEEDS_FLUSHING;
5062 }
5063
5064 gits_write_cwriter(0, its->base + GITS_CWRITER);
5065 ctlr = readl_relaxed(its->base + GITS_CTLR);
5066 ctlr |= GITS_CTLR_ENABLE;
5067 if (is_v4(its))
5068 ctlr |= GITS_CTLR_ImDe;
5069 writel_relaxed(ctlr, its->base + GITS_CTLR);
5070
5071 if (GITS_TYPER_HCC(typer))
5072 its->flags |= ITS_FLAGS_SAVE_SUSPEND_STATE;
5073
5074 err = its_init_domain(handle, its);
5075 if (err)
5076 goto out_free_tables;
5077
5078 raw_spin_lock(&its_lock);
5079 list_add(&its->entry, &its_nodes);
5080 raw_spin_unlock(&its_lock);
5081
5082 return 0;
5083
5084out_free_tables:
5085 its_free_tables(its);
5086out_free_cmd:
5087 free_pages((unsigned long)its->cmd_base, get_order(ITS_CMD_QUEUE_SZ));
5088out_unmap_sgir:
5089 if (its->sgir_base)
5090 iounmap(its->sgir_base);
5091out_free_its:
5092 kfree(its);
5093out_unmap:
5094 iounmap(its_base);
5095 pr_err("ITS@%pa: failed probing (%d)\n", &res->start, err);
5096 return err;
5097}
5098
5099static bool gic_rdists_supports_plpis(void)
5100{
5101 return !!(gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER) & GICR_TYPER_PLPIS);
5102}
5103
5104static int redist_disable_lpis(void)
5105{
5106 void __iomem *rbase = gic_data_rdist_rd_base();
5107 u64 timeout = USEC_PER_SEC;
5108 u64 val;
5109
5110 if (!gic_rdists_supports_plpis()) {
5111 pr_info("CPU%d: LPIs not supported\n", smp_processor_id());
5112 return -ENXIO;
5113 }
5114
5115 val = readl_relaxed(rbase + GICR_CTLR);
5116 if (!(val & GICR_CTLR_ENABLE_LPIS))
5117 return 0;
5118
5119 /*
5120 * If coming via a CPU hotplug event, we don't need to disable
5121 * LPIs before trying to re-enable them. They are already
5122 * configured and all is well in the world.
5123 *
5124 * If running with preallocated tables, there is nothing to do.
5125 */
5126 if (gic_data_rdist()->lpi_enabled ||
5127 (gic_rdists->flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED))
5128 return 0;
5129
5130 /*
5131 * From that point on, we only try to do some damage control.
5132 */
5133 pr_warn("GICv3: CPU%d: Booted with LPIs enabled, memory probably corrupted\n",
5134 smp_processor_id());
5135 add_taint(TAINT_CRAP, LOCKDEP_STILL_OK);
5136
5137 /* Disable LPIs */
5138 val &= ~GICR_CTLR_ENABLE_LPIS;
5139 writel_relaxed(val, rbase + GICR_CTLR);
5140
5141 /* Make sure any change to GICR_CTLR is observable by the GIC */
5142 dsb(sy);
5143
5144 /*
5145 * Software must observe RWP==0 after clearing GICR_CTLR.EnableLPIs
5146 * from 1 to 0 before programming GICR_PEND{PROP}BASER registers.
5147 * Error out if we time out waiting for RWP to clear.
5148 */
5149 while (readl_relaxed(rbase + GICR_CTLR) & GICR_CTLR_RWP) {
5150 if (!timeout) {
5151 pr_err("CPU%d: Timeout while disabling LPIs\n",
5152 smp_processor_id());
5153 return -ETIMEDOUT;
5154 }
5155 udelay(1);
5156 timeout--;
5157 }
5158
5159 /*
5160 * After it has been written to 1, it is IMPLEMENTATION
5161 * DEFINED whether GICR_CTLR.EnableLPI becomes RES1 or can be
5162 * cleared to 0. Error out if clearing the bit failed.
5163 */
5164 if (readl_relaxed(rbase + GICR_CTLR) & GICR_CTLR_ENABLE_LPIS) {
5165 pr_err("CPU%d: Failed to disable LPIs\n", smp_processor_id());
5166 return -EBUSY;
5167 }
5168
5169 return 0;
5170}
5171
5172int its_cpu_init(void)
5173{
5174 if (!list_empty(&its_nodes)) {
5175 int ret;
5176
5177 ret = redist_disable_lpis();
5178 if (ret)
5179 return ret;
5180
5181 its_cpu_init_lpis();
5182 its_cpu_init_collections();
5183 }
5184
5185 return 0;
5186}
5187
5188static const struct of_device_id its_device_id[] = {
5189 { .compatible = "arm,gic-v3-its", },
5190 {},
5191};
5192
5193static int __init its_of_probe(struct device_node *node)
5194{
5195 struct device_node *np;
5196 struct resource res;
5197
5198 for (np = of_find_matching_node(node, its_device_id); np;
5199 np = of_find_matching_node(np, its_device_id)) {
5200 if (!of_device_is_available(np))
5201 continue;
5202 if (!of_property_read_bool(np, "msi-controller")) {
5203 pr_warn("%pOF: no msi-controller property, ITS ignored\n",
5204 np);
5205 continue;
5206 }
5207
5208 if (of_address_to_resource(np, 0, &res)) {
5209 pr_warn("%pOF: no regs?\n", np);
5210 continue;
5211 }
5212
5213 its_probe_one(&res, &np->fwnode, of_node_to_nid(np));
5214 }
5215 return 0;
5216}
5217
5218#ifdef CONFIG_ACPI
5219
5220#define ACPI_GICV3_ITS_MEM_SIZE (SZ_128K)
5221
5222#ifdef CONFIG_ACPI_NUMA
5223struct its_srat_map {
5224 /* numa node id */
5225 u32 numa_node;
5226 /* GIC ITS ID */
5227 u32 its_id;
5228};
5229
5230static struct its_srat_map *its_srat_maps __initdata;
5231static int its_in_srat __initdata;
5232
5233static int __init acpi_get_its_numa_node(u32 its_id)
5234{
5235 int i;
5236
5237 for (i = 0; i < its_in_srat; i++) {
5238 if (its_id == its_srat_maps[i].its_id)
5239 return its_srat_maps[i].numa_node;
5240 }
5241 return NUMA_NO_NODE;
5242}
5243
5244static int __init gic_acpi_match_srat_its(union acpi_subtable_headers *header,
5245 const unsigned long end)
5246{
5247 return 0;
5248}
5249
5250static int __init gic_acpi_parse_srat_its(union acpi_subtable_headers *header,
5251 const unsigned long end)
5252{
5253 int node;
5254 struct acpi_srat_gic_its_affinity *its_affinity;
5255
5256 its_affinity = (struct acpi_srat_gic_its_affinity *)header;
5257 if (!its_affinity)
5258 return -EINVAL;
5259
5260 if (its_affinity->header.length < sizeof(*its_affinity)) {
5261 pr_err("SRAT: Invalid header length %d in ITS affinity\n",
5262 its_affinity->header.length);
5263 return -EINVAL;
5264 }
5265
5266 node = acpi_map_pxm_to_node(its_affinity->proximity_domain);
5267
5268 if (node == NUMA_NO_NODE || node >= MAX_NUMNODES) {
5269 pr_err("SRAT: Invalid NUMA node %d in ITS affinity\n", node);
5270 return 0;
5271 }
5272
5273 its_srat_maps[its_in_srat].numa_node = node;
5274 its_srat_maps[its_in_srat].its_id = its_affinity->its_id;
5275 its_in_srat++;
5276 pr_info("SRAT: PXM %d -> ITS %d -> Node %d\n",
5277 its_affinity->proximity_domain, its_affinity->its_id, node);
5278
5279 return 0;
5280}
5281
5282static void __init acpi_table_parse_srat_its(void)
5283{
5284 int count;
5285
5286 count = acpi_table_parse_entries(ACPI_SIG_SRAT,
5287 sizeof(struct acpi_table_srat),
5288 ACPI_SRAT_TYPE_GIC_ITS_AFFINITY,
5289 gic_acpi_match_srat_its, 0);
5290 if (count <= 0)
5291 return;
5292
5293 its_srat_maps = kmalloc_array(count, sizeof(struct its_srat_map),
5294 GFP_KERNEL);
5295 if (!its_srat_maps) {
5296 pr_warn("SRAT: Failed to allocate memory for its_srat_maps!\n");
5297 return;
5298 }
5299
5300 acpi_table_parse_entries(ACPI_SIG_SRAT,
5301 sizeof(struct acpi_table_srat),
5302 ACPI_SRAT_TYPE_GIC_ITS_AFFINITY,
5303 gic_acpi_parse_srat_its, 0);
5304}
5305
5306/* free the its_srat_maps after ITS probing */
5307static void __init acpi_its_srat_maps_free(void)
5308{
5309 kfree(its_srat_maps);
5310}
5311#else
5312static void __init acpi_table_parse_srat_its(void) { }
5313static int __init acpi_get_its_numa_node(u32 its_id) { return NUMA_NO_NODE; }
5314static void __init acpi_its_srat_maps_free(void) { }
5315#endif
5316
5317static int __init gic_acpi_parse_madt_its(union acpi_subtable_headers *header,
5318 const unsigned long end)
5319{
5320 struct acpi_madt_generic_translator *its_entry;
5321 struct fwnode_handle *dom_handle;
5322 struct resource res;
5323 int err;
5324
5325 its_entry = (struct acpi_madt_generic_translator *)header;
5326 memset(&res, 0, sizeof(res));
5327 res.start = its_entry->base_address;
5328 res.end = its_entry->base_address + ACPI_GICV3_ITS_MEM_SIZE - 1;
5329 res.flags = IORESOURCE_MEM;
5330
5331 dom_handle = irq_domain_alloc_fwnode(&res.start);
5332 if (!dom_handle) {
5333 pr_err("ITS@%pa: Unable to allocate GICv3 ITS domain token\n",
5334 &res.start);
5335 return -ENOMEM;
5336 }
5337
5338 err = iort_register_domain_token(its_entry->translation_id, res.start,
5339 dom_handle);
5340 if (err) {
5341 pr_err("ITS@%pa: Unable to register GICv3 ITS domain token (ITS ID %d) to IORT\n",
5342 &res.start, its_entry->translation_id);
5343 goto dom_err;
5344 }
5345
5346 err = its_probe_one(&res, dom_handle,
5347 acpi_get_its_numa_node(its_entry->translation_id));
5348 if (!err)
5349 return 0;
5350
5351 iort_deregister_domain_token(its_entry->translation_id);
5352dom_err:
5353 irq_domain_free_fwnode(dom_handle);
5354 return err;
5355}
5356
5357static void __init its_acpi_probe(void)
5358{
5359 acpi_table_parse_srat_its();
5360 acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_TRANSLATOR,
5361 gic_acpi_parse_madt_its, 0);
5362 acpi_its_srat_maps_free();
5363}
5364#else
5365static void __init its_acpi_probe(void) { }
5366#endif
5367
5368int __init its_init(struct fwnode_handle *handle, struct rdists *rdists,
5369 struct irq_domain *parent_domain)
5370{
5371 struct device_node *of_node;
5372 struct its_node *its;
5373 bool has_v4 = false;
5374 bool has_v4_1 = false;
5375 int err;
5376
5377 gic_rdists = rdists;
5378
5379 its_parent = parent_domain;
5380 of_node = to_of_node(handle);
5381 if (of_node)
5382 its_of_probe(of_node);
5383 else
5384 its_acpi_probe();
5385
5386 if (list_empty(&its_nodes)) {
5387 pr_warn("ITS: No ITS available, not enabling LPIs\n");
5388 return -ENXIO;
5389 }
5390
5391 err = allocate_lpi_tables();
5392 if (err)
5393 return err;
5394
5395 list_for_each_entry(its, &its_nodes, entry) {
5396 has_v4 |= is_v4(its);
5397 has_v4_1 |= is_v4_1(its);
5398 }
5399
5400 /* Don't bother with inconsistent systems */
5401 if (WARN_ON(!has_v4_1 && rdists->has_rvpeid))
5402 rdists->has_rvpeid = false;
5403
5404 if (has_v4 & rdists->has_vlpis) {
5405 const struct irq_domain_ops *sgi_ops;
5406
5407 if (has_v4_1)
5408 sgi_ops = &its_sgi_domain_ops;
5409 else
5410 sgi_ops = NULL;
5411
5412 if (its_init_vpe_domain() ||
5413 its_init_v4(parent_domain, &its_vpe_domain_ops, sgi_ops)) {
5414 rdists->has_vlpis = false;
5415 pr_err("ITS: Disabling GICv4 support\n");
5416 }
5417 }
5418
5419 register_syscore_ops(&its_syscore_ops);
5420
5421 return 0;
5422}
1/*
2 * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved.
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18#include <linux/acpi.h>
19#include <linux/acpi_iort.h>
20#include <linux/bitmap.h>
21#include <linux/cpu.h>
22#include <linux/delay.h>
23#include <linux/dma-iommu.h>
24#include <linux/interrupt.h>
25#include <linux/irqdomain.h>
26#include <linux/log2.h>
27#include <linux/mm.h>
28#include <linux/msi.h>
29#include <linux/of.h>
30#include <linux/of_address.h>
31#include <linux/of_irq.h>
32#include <linux/of_pci.h>
33#include <linux/of_platform.h>
34#include <linux/percpu.h>
35#include <linux/slab.h>
36#include <linux/syscore_ops.h>
37
38#include <linux/irqchip.h>
39#include <linux/irqchip/arm-gic-v3.h>
40#include <linux/irqchip/arm-gic-v4.h>
41
42#include <asm/cputype.h>
43#include <asm/exception.h>
44
45#include "irq-gic-common.h"
46
47#define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1ULL << 0)
48#define ITS_FLAGS_WORKAROUND_CAVIUM_22375 (1ULL << 1)
49#define ITS_FLAGS_WORKAROUND_CAVIUM_23144 (1ULL << 2)
50#define ITS_FLAGS_SAVE_SUSPEND_STATE (1ULL << 3)
51
52#define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING (1 << 0)
53
54static u32 lpi_id_bits;
55
56/*
57 * We allocate memory for PROPBASE to cover 2 ^ lpi_id_bits LPIs to
58 * deal with (one configuration byte per interrupt). PENDBASE has to
59 * be 64kB aligned (one bit per LPI, plus 8192 bits for SPI/PPI/SGI).
60 */
61#define LPI_NRBITS lpi_id_bits
62#define LPI_PROPBASE_SZ ALIGN(BIT(LPI_NRBITS), SZ_64K)
63#define LPI_PENDBASE_SZ ALIGN(BIT(LPI_NRBITS) / 8, SZ_64K)
64
65#define LPI_PROP_DEFAULT_PRIO 0xa0
66
67/*
68 * Collection structure - just an ID, and a redistributor address to
69 * ping. We use one per CPU as a bag of interrupts assigned to this
70 * CPU.
71 */
72struct its_collection {
73 u64 target_address;
74 u16 col_id;
75};
76
77/*
78 * The ITS_BASER structure - contains memory information, cached
79 * value of BASER register configuration and ITS page size.
80 */
81struct its_baser {
82 void *base;
83 u64 val;
84 u32 order;
85 u32 psz;
86};
87
88struct its_device;
89
90/*
91 * The ITS structure - contains most of the infrastructure, with the
92 * top-level MSI domain, the command queue, the collections, and the
93 * list of devices writing to it.
94 */
95struct its_node {
96 raw_spinlock_t lock;
97 struct list_head entry;
98 void __iomem *base;
99 phys_addr_t phys_base;
100 struct its_cmd_block *cmd_base;
101 struct its_cmd_block *cmd_write;
102 struct its_baser tables[GITS_BASER_NR_REGS];
103 struct its_collection *collections;
104 struct fwnode_handle *fwnode_handle;
105 u64 (*get_msi_base)(struct its_device *its_dev);
106 u64 cbaser_save;
107 u32 ctlr_save;
108 struct list_head its_device_list;
109 u64 flags;
110 unsigned long list_nr;
111 u32 ite_size;
112 u32 device_ids;
113 int numa_node;
114 unsigned int msi_domain_flags;
115 u32 pre_its_base; /* for Socionext Synquacer */
116 bool is_v4;
117 int vlpi_redist_offset;
118};
119
120#define ITS_ITT_ALIGN SZ_256
121
122/* The maximum number of VPEID bits supported by VLPI commands */
123#define ITS_MAX_VPEID_BITS (16)
124#define ITS_MAX_VPEID (1 << (ITS_MAX_VPEID_BITS))
125
126/* Convert page order to size in bytes */
127#define PAGE_ORDER_TO_SIZE(o) (PAGE_SIZE << (o))
128
129struct event_lpi_map {
130 unsigned long *lpi_map;
131 u16 *col_map;
132 irq_hw_number_t lpi_base;
133 int nr_lpis;
134 struct mutex vlpi_lock;
135 struct its_vm *vm;
136 struct its_vlpi_map *vlpi_maps;
137 int nr_vlpis;
138};
139
140/*
141 * The ITS view of a device - belongs to an ITS, owns an interrupt
142 * translation table, and a list of interrupts. If it some of its
143 * LPIs are injected into a guest (GICv4), the event_map.vm field
144 * indicates which one.
145 */
146struct its_device {
147 struct list_head entry;
148 struct its_node *its;
149 struct event_lpi_map event_map;
150 void *itt;
151 u32 nr_ites;
152 u32 device_id;
153};
154
155static struct {
156 raw_spinlock_t lock;
157 struct its_device *dev;
158 struct its_vpe **vpes;
159 int next_victim;
160} vpe_proxy;
161
162static LIST_HEAD(its_nodes);
163static DEFINE_SPINLOCK(its_lock);
164static struct rdists *gic_rdists;
165static struct irq_domain *its_parent;
166
167static unsigned long its_list_map;
168static u16 vmovp_seq_num;
169static DEFINE_RAW_SPINLOCK(vmovp_lock);
170
171static DEFINE_IDA(its_vpeid_ida);
172
173#define gic_data_rdist() (raw_cpu_ptr(gic_rdists->rdist))
174#define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base)
175#define gic_data_rdist_vlpi_base() (gic_data_rdist_rd_base() + SZ_128K)
176
177static struct its_collection *dev_event_to_col(struct its_device *its_dev,
178 u32 event)
179{
180 struct its_node *its = its_dev->its;
181
182 return its->collections + its_dev->event_map.col_map[event];
183}
184
185/*
186 * ITS command descriptors - parameters to be encoded in a command
187 * block.
188 */
189struct its_cmd_desc {
190 union {
191 struct {
192 struct its_device *dev;
193 u32 event_id;
194 } its_inv_cmd;
195
196 struct {
197 struct its_device *dev;
198 u32 event_id;
199 } its_clear_cmd;
200
201 struct {
202 struct its_device *dev;
203 u32 event_id;
204 } its_int_cmd;
205
206 struct {
207 struct its_device *dev;
208 int valid;
209 } its_mapd_cmd;
210
211 struct {
212 struct its_collection *col;
213 int valid;
214 } its_mapc_cmd;
215
216 struct {
217 struct its_device *dev;
218 u32 phys_id;
219 u32 event_id;
220 } its_mapti_cmd;
221
222 struct {
223 struct its_device *dev;
224 struct its_collection *col;
225 u32 event_id;
226 } its_movi_cmd;
227
228 struct {
229 struct its_device *dev;
230 u32 event_id;
231 } its_discard_cmd;
232
233 struct {
234 struct its_collection *col;
235 } its_invall_cmd;
236
237 struct {
238 struct its_vpe *vpe;
239 } its_vinvall_cmd;
240
241 struct {
242 struct its_vpe *vpe;
243 struct its_collection *col;
244 bool valid;
245 } its_vmapp_cmd;
246
247 struct {
248 struct its_vpe *vpe;
249 struct its_device *dev;
250 u32 virt_id;
251 u32 event_id;
252 bool db_enabled;
253 } its_vmapti_cmd;
254
255 struct {
256 struct its_vpe *vpe;
257 struct its_device *dev;
258 u32 event_id;
259 bool db_enabled;
260 } its_vmovi_cmd;
261
262 struct {
263 struct its_vpe *vpe;
264 struct its_collection *col;
265 u16 seq_num;
266 u16 its_list;
267 } its_vmovp_cmd;
268 };
269};
270
271/*
272 * The ITS command block, which is what the ITS actually parses.
273 */
274struct its_cmd_block {
275 u64 raw_cmd[4];
276};
277
278#define ITS_CMD_QUEUE_SZ SZ_64K
279#define ITS_CMD_QUEUE_NR_ENTRIES (ITS_CMD_QUEUE_SZ / sizeof(struct its_cmd_block))
280
281typedef struct its_collection *(*its_cmd_builder_t)(struct its_node *,
282 struct its_cmd_block *,
283 struct its_cmd_desc *);
284
285typedef struct its_vpe *(*its_cmd_vbuilder_t)(struct its_node *,
286 struct its_cmd_block *,
287 struct its_cmd_desc *);
288
289static void its_mask_encode(u64 *raw_cmd, u64 val, int h, int l)
290{
291 u64 mask = GENMASK_ULL(h, l);
292 *raw_cmd &= ~mask;
293 *raw_cmd |= (val << l) & mask;
294}
295
296static void its_encode_cmd(struct its_cmd_block *cmd, u8 cmd_nr)
297{
298 its_mask_encode(&cmd->raw_cmd[0], cmd_nr, 7, 0);
299}
300
301static void its_encode_devid(struct its_cmd_block *cmd, u32 devid)
302{
303 its_mask_encode(&cmd->raw_cmd[0], devid, 63, 32);
304}
305
306static void its_encode_event_id(struct its_cmd_block *cmd, u32 id)
307{
308 its_mask_encode(&cmd->raw_cmd[1], id, 31, 0);
309}
310
311static void its_encode_phys_id(struct its_cmd_block *cmd, u32 phys_id)
312{
313 its_mask_encode(&cmd->raw_cmd[1], phys_id, 63, 32);
314}
315
316static void its_encode_size(struct its_cmd_block *cmd, u8 size)
317{
318 its_mask_encode(&cmd->raw_cmd[1], size, 4, 0);
319}
320
321static void its_encode_itt(struct its_cmd_block *cmd, u64 itt_addr)
322{
323 its_mask_encode(&cmd->raw_cmd[2], itt_addr >> 8, 51, 8);
324}
325
326static void its_encode_valid(struct its_cmd_block *cmd, int valid)
327{
328 its_mask_encode(&cmd->raw_cmd[2], !!valid, 63, 63);
329}
330
331static void its_encode_target(struct its_cmd_block *cmd, u64 target_addr)
332{
333 its_mask_encode(&cmd->raw_cmd[2], target_addr >> 16, 51, 16);
334}
335
336static void its_encode_collection(struct its_cmd_block *cmd, u16 col)
337{
338 its_mask_encode(&cmd->raw_cmd[2], col, 15, 0);
339}
340
341static void its_encode_vpeid(struct its_cmd_block *cmd, u16 vpeid)
342{
343 its_mask_encode(&cmd->raw_cmd[1], vpeid, 47, 32);
344}
345
346static void its_encode_virt_id(struct its_cmd_block *cmd, u32 virt_id)
347{
348 its_mask_encode(&cmd->raw_cmd[2], virt_id, 31, 0);
349}
350
351static void its_encode_db_phys_id(struct its_cmd_block *cmd, u32 db_phys_id)
352{
353 its_mask_encode(&cmd->raw_cmd[2], db_phys_id, 63, 32);
354}
355
356static void its_encode_db_valid(struct its_cmd_block *cmd, bool db_valid)
357{
358 its_mask_encode(&cmd->raw_cmd[2], db_valid, 0, 0);
359}
360
361static void its_encode_seq_num(struct its_cmd_block *cmd, u16 seq_num)
362{
363 its_mask_encode(&cmd->raw_cmd[0], seq_num, 47, 32);
364}
365
366static void its_encode_its_list(struct its_cmd_block *cmd, u16 its_list)
367{
368 its_mask_encode(&cmd->raw_cmd[1], its_list, 15, 0);
369}
370
371static void its_encode_vpt_addr(struct its_cmd_block *cmd, u64 vpt_pa)
372{
373 its_mask_encode(&cmd->raw_cmd[3], vpt_pa >> 16, 51, 16);
374}
375
376static void its_encode_vpt_size(struct its_cmd_block *cmd, u8 vpt_size)
377{
378 its_mask_encode(&cmd->raw_cmd[3], vpt_size, 4, 0);
379}
380
381static inline void its_fixup_cmd(struct its_cmd_block *cmd)
382{
383 /* Let's fixup BE commands */
384 cmd->raw_cmd[0] = cpu_to_le64(cmd->raw_cmd[0]);
385 cmd->raw_cmd[1] = cpu_to_le64(cmd->raw_cmd[1]);
386 cmd->raw_cmd[2] = cpu_to_le64(cmd->raw_cmd[2]);
387 cmd->raw_cmd[3] = cpu_to_le64(cmd->raw_cmd[3]);
388}
389
390static struct its_collection *its_build_mapd_cmd(struct its_node *its,
391 struct its_cmd_block *cmd,
392 struct its_cmd_desc *desc)
393{
394 unsigned long itt_addr;
395 u8 size = ilog2(desc->its_mapd_cmd.dev->nr_ites);
396
397 itt_addr = virt_to_phys(desc->its_mapd_cmd.dev->itt);
398 itt_addr = ALIGN(itt_addr, ITS_ITT_ALIGN);
399
400 its_encode_cmd(cmd, GITS_CMD_MAPD);
401 its_encode_devid(cmd, desc->its_mapd_cmd.dev->device_id);
402 its_encode_size(cmd, size - 1);
403 its_encode_itt(cmd, itt_addr);
404 its_encode_valid(cmd, desc->its_mapd_cmd.valid);
405
406 its_fixup_cmd(cmd);
407
408 return NULL;
409}
410
411static struct its_collection *its_build_mapc_cmd(struct its_node *its,
412 struct its_cmd_block *cmd,
413 struct its_cmd_desc *desc)
414{
415 its_encode_cmd(cmd, GITS_CMD_MAPC);
416 its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id);
417 its_encode_target(cmd, desc->its_mapc_cmd.col->target_address);
418 its_encode_valid(cmd, desc->its_mapc_cmd.valid);
419
420 its_fixup_cmd(cmd);
421
422 return desc->its_mapc_cmd.col;
423}
424
425static struct its_collection *its_build_mapti_cmd(struct its_node *its,
426 struct its_cmd_block *cmd,
427 struct its_cmd_desc *desc)
428{
429 struct its_collection *col;
430
431 col = dev_event_to_col(desc->its_mapti_cmd.dev,
432 desc->its_mapti_cmd.event_id);
433
434 its_encode_cmd(cmd, GITS_CMD_MAPTI);
435 its_encode_devid(cmd, desc->its_mapti_cmd.dev->device_id);
436 its_encode_event_id(cmd, desc->its_mapti_cmd.event_id);
437 its_encode_phys_id(cmd, desc->its_mapti_cmd.phys_id);
438 its_encode_collection(cmd, col->col_id);
439
440 its_fixup_cmd(cmd);
441
442 return col;
443}
444
445static struct its_collection *its_build_movi_cmd(struct its_node *its,
446 struct its_cmd_block *cmd,
447 struct its_cmd_desc *desc)
448{
449 struct its_collection *col;
450
451 col = dev_event_to_col(desc->its_movi_cmd.dev,
452 desc->its_movi_cmd.event_id);
453
454 its_encode_cmd(cmd, GITS_CMD_MOVI);
455 its_encode_devid(cmd, desc->its_movi_cmd.dev->device_id);
456 its_encode_event_id(cmd, desc->its_movi_cmd.event_id);
457 its_encode_collection(cmd, desc->its_movi_cmd.col->col_id);
458
459 its_fixup_cmd(cmd);
460
461 return col;
462}
463
464static struct its_collection *its_build_discard_cmd(struct its_node *its,
465 struct its_cmd_block *cmd,
466 struct its_cmd_desc *desc)
467{
468 struct its_collection *col;
469
470 col = dev_event_to_col(desc->its_discard_cmd.dev,
471 desc->its_discard_cmd.event_id);
472
473 its_encode_cmd(cmd, GITS_CMD_DISCARD);
474 its_encode_devid(cmd, desc->its_discard_cmd.dev->device_id);
475 its_encode_event_id(cmd, desc->its_discard_cmd.event_id);
476
477 its_fixup_cmd(cmd);
478
479 return col;
480}
481
482static struct its_collection *its_build_inv_cmd(struct its_node *its,
483 struct its_cmd_block *cmd,
484 struct its_cmd_desc *desc)
485{
486 struct its_collection *col;
487
488 col = dev_event_to_col(desc->its_inv_cmd.dev,
489 desc->its_inv_cmd.event_id);
490
491 its_encode_cmd(cmd, GITS_CMD_INV);
492 its_encode_devid(cmd, desc->its_inv_cmd.dev->device_id);
493 its_encode_event_id(cmd, desc->its_inv_cmd.event_id);
494
495 its_fixup_cmd(cmd);
496
497 return col;
498}
499
500static struct its_collection *its_build_int_cmd(struct its_node *its,
501 struct its_cmd_block *cmd,
502 struct its_cmd_desc *desc)
503{
504 struct its_collection *col;
505
506 col = dev_event_to_col(desc->its_int_cmd.dev,
507 desc->its_int_cmd.event_id);
508
509 its_encode_cmd(cmd, GITS_CMD_INT);
510 its_encode_devid(cmd, desc->its_int_cmd.dev->device_id);
511 its_encode_event_id(cmd, desc->its_int_cmd.event_id);
512
513 its_fixup_cmd(cmd);
514
515 return col;
516}
517
518static struct its_collection *its_build_clear_cmd(struct its_node *its,
519 struct its_cmd_block *cmd,
520 struct its_cmd_desc *desc)
521{
522 struct its_collection *col;
523
524 col = dev_event_to_col(desc->its_clear_cmd.dev,
525 desc->its_clear_cmd.event_id);
526
527 its_encode_cmd(cmd, GITS_CMD_CLEAR);
528 its_encode_devid(cmd, desc->its_clear_cmd.dev->device_id);
529 its_encode_event_id(cmd, desc->its_clear_cmd.event_id);
530
531 its_fixup_cmd(cmd);
532
533 return col;
534}
535
536static struct its_collection *its_build_invall_cmd(struct its_node *its,
537 struct its_cmd_block *cmd,
538 struct its_cmd_desc *desc)
539{
540 its_encode_cmd(cmd, GITS_CMD_INVALL);
541 its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id);
542
543 its_fixup_cmd(cmd);
544
545 return NULL;
546}
547
548static struct its_vpe *its_build_vinvall_cmd(struct its_node *its,
549 struct its_cmd_block *cmd,
550 struct its_cmd_desc *desc)
551{
552 its_encode_cmd(cmd, GITS_CMD_VINVALL);
553 its_encode_vpeid(cmd, desc->its_vinvall_cmd.vpe->vpe_id);
554
555 its_fixup_cmd(cmd);
556
557 return desc->its_vinvall_cmd.vpe;
558}
559
560static struct its_vpe *its_build_vmapp_cmd(struct its_node *its,
561 struct its_cmd_block *cmd,
562 struct its_cmd_desc *desc)
563{
564 unsigned long vpt_addr;
565 u64 target;
566
567 vpt_addr = virt_to_phys(page_address(desc->its_vmapp_cmd.vpe->vpt_page));
568 target = desc->its_vmapp_cmd.col->target_address + its->vlpi_redist_offset;
569
570 its_encode_cmd(cmd, GITS_CMD_VMAPP);
571 its_encode_vpeid(cmd, desc->its_vmapp_cmd.vpe->vpe_id);
572 its_encode_valid(cmd, desc->its_vmapp_cmd.valid);
573 its_encode_target(cmd, target);
574 its_encode_vpt_addr(cmd, vpt_addr);
575 its_encode_vpt_size(cmd, LPI_NRBITS - 1);
576
577 its_fixup_cmd(cmd);
578
579 return desc->its_vmapp_cmd.vpe;
580}
581
582static struct its_vpe *its_build_vmapti_cmd(struct its_node *its,
583 struct its_cmd_block *cmd,
584 struct its_cmd_desc *desc)
585{
586 u32 db;
587
588 if (desc->its_vmapti_cmd.db_enabled)
589 db = desc->its_vmapti_cmd.vpe->vpe_db_lpi;
590 else
591 db = 1023;
592
593 its_encode_cmd(cmd, GITS_CMD_VMAPTI);
594 its_encode_devid(cmd, desc->its_vmapti_cmd.dev->device_id);
595 its_encode_vpeid(cmd, desc->its_vmapti_cmd.vpe->vpe_id);
596 its_encode_event_id(cmd, desc->its_vmapti_cmd.event_id);
597 its_encode_db_phys_id(cmd, db);
598 its_encode_virt_id(cmd, desc->its_vmapti_cmd.virt_id);
599
600 its_fixup_cmd(cmd);
601
602 return desc->its_vmapti_cmd.vpe;
603}
604
605static struct its_vpe *its_build_vmovi_cmd(struct its_node *its,
606 struct its_cmd_block *cmd,
607 struct its_cmd_desc *desc)
608{
609 u32 db;
610
611 if (desc->its_vmovi_cmd.db_enabled)
612 db = desc->its_vmovi_cmd.vpe->vpe_db_lpi;
613 else
614 db = 1023;
615
616 its_encode_cmd(cmd, GITS_CMD_VMOVI);
617 its_encode_devid(cmd, desc->its_vmovi_cmd.dev->device_id);
618 its_encode_vpeid(cmd, desc->its_vmovi_cmd.vpe->vpe_id);
619 its_encode_event_id(cmd, desc->its_vmovi_cmd.event_id);
620 its_encode_db_phys_id(cmd, db);
621 its_encode_db_valid(cmd, true);
622
623 its_fixup_cmd(cmd);
624
625 return desc->its_vmovi_cmd.vpe;
626}
627
628static struct its_vpe *its_build_vmovp_cmd(struct its_node *its,
629 struct its_cmd_block *cmd,
630 struct its_cmd_desc *desc)
631{
632 u64 target;
633
634 target = desc->its_vmovp_cmd.col->target_address + its->vlpi_redist_offset;
635 its_encode_cmd(cmd, GITS_CMD_VMOVP);
636 its_encode_seq_num(cmd, desc->its_vmovp_cmd.seq_num);
637 its_encode_its_list(cmd, desc->its_vmovp_cmd.its_list);
638 its_encode_vpeid(cmd, desc->its_vmovp_cmd.vpe->vpe_id);
639 its_encode_target(cmd, target);
640
641 its_fixup_cmd(cmd);
642
643 return desc->its_vmovp_cmd.vpe;
644}
645
646static u64 its_cmd_ptr_to_offset(struct its_node *its,
647 struct its_cmd_block *ptr)
648{
649 return (ptr - its->cmd_base) * sizeof(*ptr);
650}
651
652static int its_queue_full(struct its_node *its)
653{
654 int widx;
655 int ridx;
656
657 widx = its->cmd_write - its->cmd_base;
658 ridx = readl_relaxed(its->base + GITS_CREADR) / sizeof(struct its_cmd_block);
659
660 /* This is incredibly unlikely to happen, unless the ITS locks up. */
661 if (((widx + 1) % ITS_CMD_QUEUE_NR_ENTRIES) == ridx)
662 return 1;
663
664 return 0;
665}
666
667static struct its_cmd_block *its_allocate_entry(struct its_node *its)
668{
669 struct its_cmd_block *cmd;
670 u32 count = 1000000; /* 1s! */
671
672 while (its_queue_full(its)) {
673 count--;
674 if (!count) {
675 pr_err_ratelimited("ITS queue not draining\n");
676 return NULL;
677 }
678 cpu_relax();
679 udelay(1);
680 }
681
682 cmd = its->cmd_write++;
683
684 /* Handle queue wrapping */
685 if (its->cmd_write == (its->cmd_base + ITS_CMD_QUEUE_NR_ENTRIES))
686 its->cmd_write = its->cmd_base;
687
688 /* Clear command */
689 cmd->raw_cmd[0] = 0;
690 cmd->raw_cmd[1] = 0;
691 cmd->raw_cmd[2] = 0;
692 cmd->raw_cmd[3] = 0;
693
694 return cmd;
695}
696
697static struct its_cmd_block *its_post_commands(struct its_node *its)
698{
699 u64 wr = its_cmd_ptr_to_offset(its, its->cmd_write);
700
701 writel_relaxed(wr, its->base + GITS_CWRITER);
702
703 return its->cmd_write;
704}
705
706static void its_flush_cmd(struct its_node *its, struct its_cmd_block *cmd)
707{
708 /*
709 * Make sure the commands written to memory are observable by
710 * the ITS.
711 */
712 if (its->flags & ITS_FLAGS_CMDQ_NEEDS_FLUSHING)
713 gic_flush_dcache_to_poc(cmd, sizeof(*cmd));
714 else
715 dsb(ishst);
716}
717
718static int its_wait_for_range_completion(struct its_node *its,
719 struct its_cmd_block *from,
720 struct its_cmd_block *to)
721{
722 u64 rd_idx, from_idx, to_idx;
723 u32 count = 1000000; /* 1s! */
724
725 from_idx = its_cmd_ptr_to_offset(its, from);
726 to_idx = its_cmd_ptr_to_offset(its, to);
727
728 while (1) {
729 rd_idx = readl_relaxed(its->base + GITS_CREADR);
730
731 /* Direct case */
732 if (from_idx < to_idx && rd_idx >= to_idx)
733 break;
734
735 /* Wrapped case */
736 if (from_idx >= to_idx && rd_idx >= to_idx && rd_idx < from_idx)
737 break;
738
739 count--;
740 if (!count) {
741 pr_err_ratelimited("ITS queue timeout (%llu %llu %llu)\n",
742 from_idx, to_idx, rd_idx);
743 return -1;
744 }
745 cpu_relax();
746 udelay(1);
747 }
748
749 return 0;
750}
751
752/* Warning, macro hell follows */
753#define BUILD_SINGLE_CMD_FUNC(name, buildtype, synctype, buildfn) \
754void name(struct its_node *its, \
755 buildtype builder, \
756 struct its_cmd_desc *desc) \
757{ \
758 struct its_cmd_block *cmd, *sync_cmd, *next_cmd; \
759 synctype *sync_obj; \
760 unsigned long flags; \
761 \
762 raw_spin_lock_irqsave(&its->lock, flags); \
763 \
764 cmd = its_allocate_entry(its); \
765 if (!cmd) { /* We're soooooo screewed... */ \
766 raw_spin_unlock_irqrestore(&its->lock, flags); \
767 return; \
768 } \
769 sync_obj = builder(its, cmd, desc); \
770 its_flush_cmd(its, cmd); \
771 \
772 if (sync_obj) { \
773 sync_cmd = its_allocate_entry(its); \
774 if (!sync_cmd) \
775 goto post; \
776 \
777 buildfn(its, sync_cmd, sync_obj); \
778 its_flush_cmd(its, sync_cmd); \
779 } \
780 \
781post: \
782 next_cmd = its_post_commands(its); \
783 raw_spin_unlock_irqrestore(&its->lock, flags); \
784 \
785 if (its_wait_for_range_completion(its, cmd, next_cmd)) \
786 pr_err_ratelimited("ITS cmd %ps failed\n", builder); \
787}
788
789static void its_build_sync_cmd(struct its_node *its,
790 struct its_cmd_block *sync_cmd,
791 struct its_collection *sync_col)
792{
793 its_encode_cmd(sync_cmd, GITS_CMD_SYNC);
794 its_encode_target(sync_cmd, sync_col->target_address);
795
796 its_fixup_cmd(sync_cmd);
797}
798
799static BUILD_SINGLE_CMD_FUNC(its_send_single_command, its_cmd_builder_t,
800 struct its_collection, its_build_sync_cmd)
801
802static void its_build_vsync_cmd(struct its_node *its,
803 struct its_cmd_block *sync_cmd,
804 struct its_vpe *sync_vpe)
805{
806 its_encode_cmd(sync_cmd, GITS_CMD_VSYNC);
807 its_encode_vpeid(sync_cmd, sync_vpe->vpe_id);
808
809 its_fixup_cmd(sync_cmd);
810}
811
812static BUILD_SINGLE_CMD_FUNC(its_send_single_vcommand, its_cmd_vbuilder_t,
813 struct its_vpe, its_build_vsync_cmd)
814
815static void its_send_int(struct its_device *dev, u32 event_id)
816{
817 struct its_cmd_desc desc;
818
819 desc.its_int_cmd.dev = dev;
820 desc.its_int_cmd.event_id = event_id;
821
822 its_send_single_command(dev->its, its_build_int_cmd, &desc);
823}
824
825static void its_send_clear(struct its_device *dev, u32 event_id)
826{
827 struct its_cmd_desc desc;
828
829 desc.its_clear_cmd.dev = dev;
830 desc.its_clear_cmd.event_id = event_id;
831
832 its_send_single_command(dev->its, its_build_clear_cmd, &desc);
833}
834
835static void its_send_inv(struct its_device *dev, u32 event_id)
836{
837 struct its_cmd_desc desc;
838
839 desc.its_inv_cmd.dev = dev;
840 desc.its_inv_cmd.event_id = event_id;
841
842 its_send_single_command(dev->its, its_build_inv_cmd, &desc);
843}
844
845static void its_send_mapd(struct its_device *dev, int valid)
846{
847 struct its_cmd_desc desc;
848
849 desc.its_mapd_cmd.dev = dev;
850 desc.its_mapd_cmd.valid = !!valid;
851
852 its_send_single_command(dev->its, its_build_mapd_cmd, &desc);
853}
854
855static void its_send_mapc(struct its_node *its, struct its_collection *col,
856 int valid)
857{
858 struct its_cmd_desc desc;
859
860 desc.its_mapc_cmd.col = col;
861 desc.its_mapc_cmd.valid = !!valid;
862
863 its_send_single_command(its, its_build_mapc_cmd, &desc);
864}
865
866static void its_send_mapti(struct its_device *dev, u32 irq_id, u32 id)
867{
868 struct its_cmd_desc desc;
869
870 desc.its_mapti_cmd.dev = dev;
871 desc.its_mapti_cmd.phys_id = irq_id;
872 desc.its_mapti_cmd.event_id = id;
873
874 its_send_single_command(dev->its, its_build_mapti_cmd, &desc);
875}
876
877static void its_send_movi(struct its_device *dev,
878 struct its_collection *col, u32 id)
879{
880 struct its_cmd_desc desc;
881
882 desc.its_movi_cmd.dev = dev;
883 desc.its_movi_cmd.col = col;
884 desc.its_movi_cmd.event_id = id;
885
886 its_send_single_command(dev->its, its_build_movi_cmd, &desc);
887}
888
889static void its_send_discard(struct its_device *dev, u32 id)
890{
891 struct its_cmd_desc desc;
892
893 desc.its_discard_cmd.dev = dev;
894 desc.its_discard_cmd.event_id = id;
895
896 its_send_single_command(dev->its, its_build_discard_cmd, &desc);
897}
898
899static void its_send_invall(struct its_node *its, struct its_collection *col)
900{
901 struct its_cmd_desc desc;
902
903 desc.its_invall_cmd.col = col;
904
905 its_send_single_command(its, its_build_invall_cmd, &desc);
906}
907
908static void its_send_vmapti(struct its_device *dev, u32 id)
909{
910 struct its_vlpi_map *map = &dev->event_map.vlpi_maps[id];
911 struct its_cmd_desc desc;
912
913 desc.its_vmapti_cmd.vpe = map->vpe;
914 desc.its_vmapti_cmd.dev = dev;
915 desc.its_vmapti_cmd.virt_id = map->vintid;
916 desc.its_vmapti_cmd.event_id = id;
917 desc.its_vmapti_cmd.db_enabled = map->db_enabled;
918
919 its_send_single_vcommand(dev->its, its_build_vmapti_cmd, &desc);
920}
921
922static void its_send_vmovi(struct its_device *dev, u32 id)
923{
924 struct its_vlpi_map *map = &dev->event_map.vlpi_maps[id];
925 struct its_cmd_desc desc;
926
927 desc.its_vmovi_cmd.vpe = map->vpe;
928 desc.its_vmovi_cmd.dev = dev;
929 desc.its_vmovi_cmd.event_id = id;
930 desc.its_vmovi_cmd.db_enabled = map->db_enabled;
931
932 its_send_single_vcommand(dev->its, its_build_vmovi_cmd, &desc);
933}
934
935static void its_send_vmapp(struct its_node *its,
936 struct its_vpe *vpe, bool valid)
937{
938 struct its_cmd_desc desc;
939
940 desc.its_vmapp_cmd.vpe = vpe;
941 desc.its_vmapp_cmd.valid = valid;
942 desc.its_vmapp_cmd.col = &its->collections[vpe->col_idx];
943
944 its_send_single_vcommand(its, its_build_vmapp_cmd, &desc);
945}
946
947static void its_send_vmovp(struct its_vpe *vpe)
948{
949 struct its_cmd_desc desc;
950 struct its_node *its;
951 unsigned long flags;
952 int col_id = vpe->col_idx;
953
954 desc.its_vmovp_cmd.vpe = vpe;
955 desc.its_vmovp_cmd.its_list = (u16)its_list_map;
956
957 if (!its_list_map) {
958 its = list_first_entry(&its_nodes, struct its_node, entry);
959 desc.its_vmovp_cmd.seq_num = 0;
960 desc.its_vmovp_cmd.col = &its->collections[col_id];
961 its_send_single_vcommand(its, its_build_vmovp_cmd, &desc);
962 return;
963 }
964
965 /*
966 * Yet another marvel of the architecture. If using the
967 * its_list "feature", we need to make sure that all ITSs
968 * receive all VMOVP commands in the same order. The only way
969 * to guarantee this is to make vmovp a serialization point.
970 *
971 * Wall <-- Head.
972 */
973 raw_spin_lock_irqsave(&vmovp_lock, flags);
974
975 desc.its_vmovp_cmd.seq_num = vmovp_seq_num++;
976
977 /* Emit VMOVPs */
978 list_for_each_entry(its, &its_nodes, entry) {
979 if (!its->is_v4)
980 continue;
981
982 if (!vpe->its_vm->vlpi_count[its->list_nr])
983 continue;
984
985 desc.its_vmovp_cmd.col = &its->collections[col_id];
986 its_send_single_vcommand(its, its_build_vmovp_cmd, &desc);
987 }
988
989 raw_spin_unlock_irqrestore(&vmovp_lock, flags);
990}
991
992static void its_send_vinvall(struct its_node *its, struct its_vpe *vpe)
993{
994 struct its_cmd_desc desc;
995
996 desc.its_vinvall_cmd.vpe = vpe;
997 its_send_single_vcommand(its, its_build_vinvall_cmd, &desc);
998}
999
1000/*
1001 * irqchip functions - assumes MSI, mostly.
1002 */
1003
1004static inline u32 its_get_event_id(struct irq_data *d)
1005{
1006 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1007 return d->hwirq - its_dev->event_map.lpi_base;
1008}
1009
1010static void lpi_write_config(struct irq_data *d, u8 clr, u8 set)
1011{
1012 irq_hw_number_t hwirq;
1013 struct page *prop_page;
1014 u8 *cfg;
1015
1016 if (irqd_is_forwarded_to_vcpu(d)) {
1017 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1018 u32 event = its_get_event_id(d);
1019 struct its_vlpi_map *map;
1020
1021 prop_page = its_dev->event_map.vm->vprop_page;
1022 map = &its_dev->event_map.vlpi_maps[event];
1023 hwirq = map->vintid;
1024
1025 /* Remember the updated property */
1026 map->properties &= ~clr;
1027 map->properties |= set | LPI_PROP_GROUP1;
1028 } else {
1029 prop_page = gic_rdists->prop_page;
1030 hwirq = d->hwirq;
1031 }
1032
1033 cfg = page_address(prop_page) + hwirq - 8192;
1034 *cfg &= ~clr;
1035 *cfg |= set | LPI_PROP_GROUP1;
1036
1037 /*
1038 * Make the above write visible to the redistributors.
1039 * And yes, we're flushing exactly: One. Single. Byte.
1040 * Humpf...
1041 */
1042 if (gic_rdists->flags & RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING)
1043 gic_flush_dcache_to_poc(cfg, sizeof(*cfg));
1044 else
1045 dsb(ishst);
1046}
1047
1048static void lpi_update_config(struct irq_data *d, u8 clr, u8 set)
1049{
1050 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1051
1052 lpi_write_config(d, clr, set);
1053 its_send_inv(its_dev, its_get_event_id(d));
1054}
1055
1056static void its_vlpi_set_doorbell(struct irq_data *d, bool enable)
1057{
1058 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1059 u32 event = its_get_event_id(d);
1060
1061 if (its_dev->event_map.vlpi_maps[event].db_enabled == enable)
1062 return;
1063
1064 its_dev->event_map.vlpi_maps[event].db_enabled = enable;
1065
1066 /*
1067 * More fun with the architecture:
1068 *
1069 * Ideally, we'd issue a VMAPTI to set the doorbell to its LPI
1070 * value or to 1023, depending on the enable bit. But that
1071 * would be issueing a mapping for an /existing/ DevID+EventID
1072 * pair, which is UNPREDICTABLE. Instead, let's issue a VMOVI
1073 * to the /same/ vPE, using this opportunity to adjust the
1074 * doorbell. Mouahahahaha. We loves it, Precious.
1075 */
1076 its_send_vmovi(its_dev, event);
1077}
1078
1079static void its_mask_irq(struct irq_data *d)
1080{
1081 if (irqd_is_forwarded_to_vcpu(d))
1082 its_vlpi_set_doorbell(d, false);
1083
1084 lpi_update_config(d, LPI_PROP_ENABLED, 0);
1085}
1086
1087static void its_unmask_irq(struct irq_data *d)
1088{
1089 if (irqd_is_forwarded_to_vcpu(d))
1090 its_vlpi_set_doorbell(d, true);
1091
1092 lpi_update_config(d, 0, LPI_PROP_ENABLED);
1093}
1094
1095static int its_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
1096 bool force)
1097{
1098 unsigned int cpu;
1099 const struct cpumask *cpu_mask = cpu_online_mask;
1100 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1101 struct its_collection *target_col;
1102 u32 id = its_get_event_id(d);
1103
1104 /* A forwarded interrupt should use irq_set_vcpu_affinity */
1105 if (irqd_is_forwarded_to_vcpu(d))
1106 return -EINVAL;
1107
1108 /* lpi cannot be routed to a redistributor that is on a foreign node */
1109 if (its_dev->its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) {
1110 if (its_dev->its->numa_node >= 0) {
1111 cpu_mask = cpumask_of_node(its_dev->its->numa_node);
1112 if (!cpumask_intersects(mask_val, cpu_mask))
1113 return -EINVAL;
1114 }
1115 }
1116
1117 cpu = cpumask_any_and(mask_val, cpu_mask);
1118
1119 if (cpu >= nr_cpu_ids)
1120 return -EINVAL;
1121
1122 /* don't set the affinity when the target cpu is same as current one */
1123 if (cpu != its_dev->event_map.col_map[id]) {
1124 target_col = &its_dev->its->collections[cpu];
1125 its_send_movi(its_dev, target_col, id);
1126 its_dev->event_map.col_map[id] = cpu;
1127 irq_data_update_effective_affinity(d, cpumask_of(cpu));
1128 }
1129
1130 return IRQ_SET_MASK_OK_DONE;
1131}
1132
1133static u64 its_irq_get_msi_base(struct its_device *its_dev)
1134{
1135 struct its_node *its = its_dev->its;
1136
1137 return its->phys_base + GITS_TRANSLATER;
1138}
1139
1140static void its_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *msg)
1141{
1142 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1143 struct its_node *its;
1144 u64 addr;
1145
1146 its = its_dev->its;
1147 addr = its->get_msi_base(its_dev);
1148
1149 msg->address_lo = lower_32_bits(addr);
1150 msg->address_hi = upper_32_bits(addr);
1151 msg->data = its_get_event_id(d);
1152
1153 iommu_dma_map_msi_msg(d->irq, msg);
1154}
1155
1156static int its_irq_set_irqchip_state(struct irq_data *d,
1157 enum irqchip_irq_state which,
1158 bool state)
1159{
1160 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1161 u32 event = its_get_event_id(d);
1162
1163 if (which != IRQCHIP_STATE_PENDING)
1164 return -EINVAL;
1165
1166 if (state)
1167 its_send_int(its_dev, event);
1168 else
1169 its_send_clear(its_dev, event);
1170
1171 return 0;
1172}
1173
1174static void its_map_vm(struct its_node *its, struct its_vm *vm)
1175{
1176 unsigned long flags;
1177
1178 /* Not using the ITS list? Everything is always mapped. */
1179 if (!its_list_map)
1180 return;
1181
1182 raw_spin_lock_irqsave(&vmovp_lock, flags);
1183
1184 /*
1185 * If the VM wasn't mapped yet, iterate over the vpes and get
1186 * them mapped now.
1187 */
1188 vm->vlpi_count[its->list_nr]++;
1189
1190 if (vm->vlpi_count[its->list_nr] == 1) {
1191 int i;
1192
1193 for (i = 0; i < vm->nr_vpes; i++) {
1194 struct its_vpe *vpe = vm->vpes[i];
1195 struct irq_data *d = irq_get_irq_data(vpe->irq);
1196
1197 /* Map the VPE to the first possible CPU */
1198 vpe->col_idx = cpumask_first(cpu_online_mask);
1199 its_send_vmapp(its, vpe, true);
1200 its_send_vinvall(its, vpe);
1201 irq_data_update_effective_affinity(d, cpumask_of(vpe->col_idx));
1202 }
1203 }
1204
1205 raw_spin_unlock_irqrestore(&vmovp_lock, flags);
1206}
1207
1208static void its_unmap_vm(struct its_node *its, struct its_vm *vm)
1209{
1210 unsigned long flags;
1211
1212 /* Not using the ITS list? Everything is always mapped. */
1213 if (!its_list_map)
1214 return;
1215
1216 raw_spin_lock_irqsave(&vmovp_lock, flags);
1217
1218 if (!--vm->vlpi_count[its->list_nr]) {
1219 int i;
1220
1221 for (i = 0; i < vm->nr_vpes; i++)
1222 its_send_vmapp(its, vm->vpes[i], false);
1223 }
1224
1225 raw_spin_unlock_irqrestore(&vmovp_lock, flags);
1226}
1227
1228static int its_vlpi_map(struct irq_data *d, struct its_cmd_info *info)
1229{
1230 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1231 u32 event = its_get_event_id(d);
1232 int ret = 0;
1233
1234 if (!info->map)
1235 return -EINVAL;
1236
1237 mutex_lock(&its_dev->event_map.vlpi_lock);
1238
1239 if (!its_dev->event_map.vm) {
1240 struct its_vlpi_map *maps;
1241
1242 maps = kzalloc(sizeof(*maps) * its_dev->event_map.nr_lpis,
1243 GFP_KERNEL);
1244 if (!maps) {
1245 ret = -ENOMEM;
1246 goto out;
1247 }
1248
1249 its_dev->event_map.vm = info->map->vm;
1250 its_dev->event_map.vlpi_maps = maps;
1251 } else if (its_dev->event_map.vm != info->map->vm) {
1252 ret = -EINVAL;
1253 goto out;
1254 }
1255
1256 /* Get our private copy of the mapping information */
1257 its_dev->event_map.vlpi_maps[event] = *info->map;
1258
1259 if (irqd_is_forwarded_to_vcpu(d)) {
1260 /* Already mapped, move it around */
1261 its_send_vmovi(its_dev, event);
1262 } else {
1263 /* Ensure all the VPEs are mapped on this ITS */
1264 its_map_vm(its_dev->its, info->map->vm);
1265
1266 /*
1267 * Flag the interrupt as forwarded so that we can
1268 * start poking the virtual property table.
1269 */
1270 irqd_set_forwarded_to_vcpu(d);
1271
1272 /* Write out the property to the prop table */
1273 lpi_write_config(d, 0xff, info->map->properties);
1274
1275 /* Drop the physical mapping */
1276 its_send_discard(its_dev, event);
1277
1278 /* and install the virtual one */
1279 its_send_vmapti(its_dev, event);
1280
1281 /* Increment the number of VLPIs */
1282 its_dev->event_map.nr_vlpis++;
1283 }
1284
1285out:
1286 mutex_unlock(&its_dev->event_map.vlpi_lock);
1287 return ret;
1288}
1289
1290static int its_vlpi_get(struct irq_data *d, struct its_cmd_info *info)
1291{
1292 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1293 u32 event = its_get_event_id(d);
1294 int ret = 0;
1295
1296 mutex_lock(&its_dev->event_map.vlpi_lock);
1297
1298 if (!its_dev->event_map.vm ||
1299 !its_dev->event_map.vlpi_maps[event].vm) {
1300 ret = -EINVAL;
1301 goto out;
1302 }
1303
1304 /* Copy our mapping information to the incoming request */
1305 *info->map = its_dev->event_map.vlpi_maps[event];
1306
1307out:
1308 mutex_unlock(&its_dev->event_map.vlpi_lock);
1309 return ret;
1310}
1311
1312static int its_vlpi_unmap(struct irq_data *d)
1313{
1314 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1315 u32 event = its_get_event_id(d);
1316 int ret = 0;
1317
1318 mutex_lock(&its_dev->event_map.vlpi_lock);
1319
1320 if (!its_dev->event_map.vm || !irqd_is_forwarded_to_vcpu(d)) {
1321 ret = -EINVAL;
1322 goto out;
1323 }
1324
1325 /* Drop the virtual mapping */
1326 its_send_discard(its_dev, event);
1327
1328 /* and restore the physical one */
1329 irqd_clr_forwarded_to_vcpu(d);
1330 its_send_mapti(its_dev, d->hwirq, event);
1331 lpi_update_config(d, 0xff, (LPI_PROP_DEFAULT_PRIO |
1332 LPI_PROP_ENABLED |
1333 LPI_PROP_GROUP1));
1334
1335 /* Potentially unmap the VM from this ITS */
1336 its_unmap_vm(its_dev->its, its_dev->event_map.vm);
1337
1338 /*
1339 * Drop the refcount and make the device available again if
1340 * this was the last VLPI.
1341 */
1342 if (!--its_dev->event_map.nr_vlpis) {
1343 its_dev->event_map.vm = NULL;
1344 kfree(its_dev->event_map.vlpi_maps);
1345 }
1346
1347out:
1348 mutex_unlock(&its_dev->event_map.vlpi_lock);
1349 return ret;
1350}
1351
1352static int its_vlpi_prop_update(struct irq_data *d, struct its_cmd_info *info)
1353{
1354 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1355
1356 if (!its_dev->event_map.vm || !irqd_is_forwarded_to_vcpu(d))
1357 return -EINVAL;
1358
1359 if (info->cmd_type == PROP_UPDATE_AND_INV_VLPI)
1360 lpi_update_config(d, 0xff, info->config);
1361 else
1362 lpi_write_config(d, 0xff, info->config);
1363 its_vlpi_set_doorbell(d, !!(info->config & LPI_PROP_ENABLED));
1364
1365 return 0;
1366}
1367
1368static int its_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
1369{
1370 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1371 struct its_cmd_info *info = vcpu_info;
1372
1373 /* Need a v4 ITS */
1374 if (!its_dev->its->is_v4)
1375 return -EINVAL;
1376
1377 /* Unmap request? */
1378 if (!info)
1379 return its_vlpi_unmap(d);
1380
1381 switch (info->cmd_type) {
1382 case MAP_VLPI:
1383 return its_vlpi_map(d, info);
1384
1385 case GET_VLPI:
1386 return its_vlpi_get(d, info);
1387
1388 case PROP_UPDATE_VLPI:
1389 case PROP_UPDATE_AND_INV_VLPI:
1390 return its_vlpi_prop_update(d, info);
1391
1392 default:
1393 return -EINVAL;
1394 }
1395}
1396
1397static struct irq_chip its_irq_chip = {
1398 .name = "ITS",
1399 .irq_mask = its_mask_irq,
1400 .irq_unmask = its_unmask_irq,
1401 .irq_eoi = irq_chip_eoi_parent,
1402 .irq_set_affinity = its_set_affinity,
1403 .irq_compose_msi_msg = its_irq_compose_msi_msg,
1404 .irq_set_irqchip_state = its_irq_set_irqchip_state,
1405 .irq_set_vcpu_affinity = its_irq_set_vcpu_affinity,
1406};
1407
1408/*
1409 * How we allocate LPIs:
1410 *
1411 * The GIC has id_bits bits for interrupt identifiers. From there, we
1412 * must subtract 8192 which are reserved for SGIs/PPIs/SPIs. Then, as
1413 * we allocate LPIs by chunks of 32, we can shift the whole thing by 5
1414 * bits to the right.
1415 *
1416 * This gives us (((1UL << id_bits) - 8192) >> 5) possible allocations.
1417 */
1418#define IRQS_PER_CHUNK_SHIFT 5
1419#define IRQS_PER_CHUNK (1UL << IRQS_PER_CHUNK_SHIFT)
1420#define ITS_MAX_LPI_NRBITS 16 /* 64K LPIs */
1421
1422static unsigned long *lpi_bitmap;
1423static u32 lpi_chunks;
1424static DEFINE_SPINLOCK(lpi_lock);
1425
1426static int its_lpi_to_chunk(int lpi)
1427{
1428 return (lpi - 8192) >> IRQS_PER_CHUNK_SHIFT;
1429}
1430
1431static int its_chunk_to_lpi(int chunk)
1432{
1433 return (chunk << IRQS_PER_CHUNK_SHIFT) + 8192;
1434}
1435
1436static int __init its_lpi_init(u32 id_bits)
1437{
1438 lpi_chunks = its_lpi_to_chunk(1UL << id_bits);
1439
1440 lpi_bitmap = kzalloc(BITS_TO_LONGS(lpi_chunks) * sizeof(long),
1441 GFP_KERNEL);
1442 if (!lpi_bitmap) {
1443 lpi_chunks = 0;
1444 return -ENOMEM;
1445 }
1446
1447 pr_info("ITS: Allocated %d chunks for LPIs\n", (int)lpi_chunks);
1448 return 0;
1449}
1450
1451static unsigned long *its_lpi_alloc_chunks(int nr_irqs, int *base, int *nr_ids)
1452{
1453 unsigned long *bitmap = NULL;
1454 int chunk_id;
1455 int nr_chunks;
1456 int i;
1457
1458 nr_chunks = DIV_ROUND_UP(nr_irqs, IRQS_PER_CHUNK);
1459
1460 spin_lock(&lpi_lock);
1461
1462 do {
1463 chunk_id = bitmap_find_next_zero_area(lpi_bitmap, lpi_chunks,
1464 0, nr_chunks, 0);
1465 if (chunk_id < lpi_chunks)
1466 break;
1467
1468 nr_chunks--;
1469 } while (nr_chunks > 0);
1470
1471 if (!nr_chunks)
1472 goto out;
1473
1474 bitmap = kzalloc(BITS_TO_LONGS(nr_chunks * IRQS_PER_CHUNK) * sizeof (long),
1475 GFP_ATOMIC);
1476 if (!bitmap)
1477 goto out;
1478
1479 for (i = 0; i < nr_chunks; i++)
1480 set_bit(chunk_id + i, lpi_bitmap);
1481
1482 *base = its_chunk_to_lpi(chunk_id);
1483 *nr_ids = nr_chunks * IRQS_PER_CHUNK;
1484
1485out:
1486 spin_unlock(&lpi_lock);
1487
1488 if (!bitmap)
1489 *base = *nr_ids = 0;
1490
1491 return bitmap;
1492}
1493
1494static void its_lpi_free_chunks(unsigned long *bitmap, int base, int nr_ids)
1495{
1496 int lpi;
1497
1498 spin_lock(&lpi_lock);
1499
1500 for (lpi = base; lpi < (base + nr_ids); lpi += IRQS_PER_CHUNK) {
1501 int chunk = its_lpi_to_chunk(lpi);
1502
1503 BUG_ON(chunk > lpi_chunks);
1504 if (test_bit(chunk, lpi_bitmap)) {
1505 clear_bit(chunk, lpi_bitmap);
1506 } else {
1507 pr_err("Bad LPI chunk %d\n", chunk);
1508 }
1509 }
1510
1511 spin_unlock(&lpi_lock);
1512
1513 kfree(bitmap);
1514}
1515
1516static struct page *its_allocate_prop_table(gfp_t gfp_flags)
1517{
1518 struct page *prop_page;
1519
1520 prop_page = alloc_pages(gfp_flags, get_order(LPI_PROPBASE_SZ));
1521 if (!prop_page)
1522 return NULL;
1523
1524 /* Priority 0xa0, Group-1, disabled */
1525 memset(page_address(prop_page),
1526 LPI_PROP_DEFAULT_PRIO | LPI_PROP_GROUP1,
1527 LPI_PROPBASE_SZ);
1528
1529 /* Make sure the GIC will observe the written configuration */
1530 gic_flush_dcache_to_poc(page_address(prop_page), LPI_PROPBASE_SZ);
1531
1532 return prop_page;
1533}
1534
1535static void its_free_prop_table(struct page *prop_page)
1536{
1537 free_pages((unsigned long)page_address(prop_page),
1538 get_order(LPI_PROPBASE_SZ));
1539}
1540
1541static int __init its_alloc_lpi_tables(void)
1542{
1543 phys_addr_t paddr;
1544
1545 lpi_id_bits = min_t(u32, gic_rdists->id_bits, ITS_MAX_LPI_NRBITS);
1546 gic_rdists->prop_page = its_allocate_prop_table(GFP_NOWAIT);
1547 if (!gic_rdists->prop_page) {
1548 pr_err("Failed to allocate PROPBASE\n");
1549 return -ENOMEM;
1550 }
1551
1552 paddr = page_to_phys(gic_rdists->prop_page);
1553 pr_info("GIC: using LPI property table @%pa\n", &paddr);
1554
1555 return its_lpi_init(lpi_id_bits);
1556}
1557
1558static const char *its_base_type_string[] = {
1559 [GITS_BASER_TYPE_DEVICE] = "Devices",
1560 [GITS_BASER_TYPE_VCPU] = "Virtual CPUs",
1561 [GITS_BASER_TYPE_RESERVED3] = "Reserved (3)",
1562 [GITS_BASER_TYPE_COLLECTION] = "Interrupt Collections",
1563 [GITS_BASER_TYPE_RESERVED5] = "Reserved (5)",
1564 [GITS_BASER_TYPE_RESERVED6] = "Reserved (6)",
1565 [GITS_BASER_TYPE_RESERVED7] = "Reserved (7)",
1566};
1567
1568static u64 its_read_baser(struct its_node *its, struct its_baser *baser)
1569{
1570 u32 idx = baser - its->tables;
1571
1572 return gits_read_baser(its->base + GITS_BASER + (idx << 3));
1573}
1574
1575static void its_write_baser(struct its_node *its, struct its_baser *baser,
1576 u64 val)
1577{
1578 u32 idx = baser - its->tables;
1579
1580 gits_write_baser(val, its->base + GITS_BASER + (idx << 3));
1581 baser->val = its_read_baser(its, baser);
1582}
1583
1584static int its_setup_baser(struct its_node *its, struct its_baser *baser,
1585 u64 cache, u64 shr, u32 psz, u32 order,
1586 bool indirect)
1587{
1588 u64 val = its_read_baser(its, baser);
1589 u64 esz = GITS_BASER_ENTRY_SIZE(val);
1590 u64 type = GITS_BASER_TYPE(val);
1591 u64 baser_phys, tmp;
1592 u32 alloc_pages;
1593 void *base;
1594
1595retry_alloc_baser:
1596 alloc_pages = (PAGE_ORDER_TO_SIZE(order) / psz);
1597 if (alloc_pages > GITS_BASER_PAGES_MAX) {
1598 pr_warn("ITS@%pa: %s too large, reduce ITS pages %u->%u\n",
1599 &its->phys_base, its_base_type_string[type],
1600 alloc_pages, GITS_BASER_PAGES_MAX);
1601 alloc_pages = GITS_BASER_PAGES_MAX;
1602 order = get_order(GITS_BASER_PAGES_MAX * psz);
1603 }
1604
1605 base = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, order);
1606 if (!base)
1607 return -ENOMEM;
1608
1609 baser_phys = virt_to_phys(base);
1610
1611 /* Check if the physical address of the memory is above 48bits */
1612 if (IS_ENABLED(CONFIG_ARM64_64K_PAGES) && (baser_phys >> 48)) {
1613
1614 /* 52bit PA is supported only when PageSize=64K */
1615 if (psz != SZ_64K) {
1616 pr_err("ITS: no 52bit PA support when psz=%d\n", psz);
1617 free_pages((unsigned long)base, order);
1618 return -ENXIO;
1619 }
1620
1621 /* Convert 52bit PA to 48bit field */
1622 baser_phys = GITS_BASER_PHYS_52_to_48(baser_phys);
1623 }
1624
1625retry_baser:
1626 val = (baser_phys |
1627 (type << GITS_BASER_TYPE_SHIFT) |
1628 ((esz - 1) << GITS_BASER_ENTRY_SIZE_SHIFT) |
1629 ((alloc_pages - 1) << GITS_BASER_PAGES_SHIFT) |
1630 cache |
1631 shr |
1632 GITS_BASER_VALID);
1633
1634 val |= indirect ? GITS_BASER_INDIRECT : 0x0;
1635
1636 switch (psz) {
1637 case SZ_4K:
1638 val |= GITS_BASER_PAGE_SIZE_4K;
1639 break;
1640 case SZ_16K:
1641 val |= GITS_BASER_PAGE_SIZE_16K;
1642 break;
1643 case SZ_64K:
1644 val |= GITS_BASER_PAGE_SIZE_64K;
1645 break;
1646 }
1647
1648 its_write_baser(its, baser, val);
1649 tmp = baser->val;
1650
1651 if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) {
1652 /*
1653 * Shareability didn't stick. Just use
1654 * whatever the read reported, which is likely
1655 * to be the only thing this redistributor
1656 * supports. If that's zero, make it
1657 * non-cacheable as well.
1658 */
1659 shr = tmp & GITS_BASER_SHAREABILITY_MASK;
1660 if (!shr) {
1661 cache = GITS_BASER_nC;
1662 gic_flush_dcache_to_poc(base, PAGE_ORDER_TO_SIZE(order));
1663 }
1664 goto retry_baser;
1665 }
1666
1667 if ((val ^ tmp) & GITS_BASER_PAGE_SIZE_MASK) {
1668 /*
1669 * Page size didn't stick. Let's try a smaller
1670 * size and retry. If we reach 4K, then
1671 * something is horribly wrong...
1672 */
1673 free_pages((unsigned long)base, order);
1674 baser->base = NULL;
1675
1676 switch (psz) {
1677 case SZ_16K:
1678 psz = SZ_4K;
1679 goto retry_alloc_baser;
1680 case SZ_64K:
1681 psz = SZ_16K;
1682 goto retry_alloc_baser;
1683 }
1684 }
1685
1686 if (val != tmp) {
1687 pr_err("ITS@%pa: %s doesn't stick: %llx %llx\n",
1688 &its->phys_base, its_base_type_string[type],
1689 val, tmp);
1690 free_pages((unsigned long)base, order);
1691 return -ENXIO;
1692 }
1693
1694 baser->order = order;
1695 baser->base = base;
1696 baser->psz = psz;
1697 tmp = indirect ? GITS_LVL1_ENTRY_SIZE : esz;
1698
1699 pr_info("ITS@%pa: allocated %d %s @%lx (%s, esz %d, psz %dK, shr %d)\n",
1700 &its->phys_base, (int)(PAGE_ORDER_TO_SIZE(order) / (int)tmp),
1701 its_base_type_string[type],
1702 (unsigned long)virt_to_phys(base),
1703 indirect ? "indirect" : "flat", (int)esz,
1704 psz / SZ_1K, (int)shr >> GITS_BASER_SHAREABILITY_SHIFT);
1705
1706 return 0;
1707}
1708
1709static bool its_parse_indirect_baser(struct its_node *its,
1710 struct its_baser *baser,
1711 u32 psz, u32 *order, u32 ids)
1712{
1713 u64 tmp = its_read_baser(its, baser);
1714 u64 type = GITS_BASER_TYPE(tmp);
1715 u64 esz = GITS_BASER_ENTRY_SIZE(tmp);
1716 u64 val = GITS_BASER_InnerShareable | GITS_BASER_RaWaWb;
1717 u32 new_order = *order;
1718 bool indirect = false;
1719
1720 /* No need to enable Indirection if memory requirement < (psz*2)bytes */
1721 if ((esz << ids) > (psz * 2)) {
1722 /*
1723 * Find out whether hw supports a single or two-level table by
1724 * table by reading bit at offset '62' after writing '1' to it.
1725 */
1726 its_write_baser(its, baser, val | GITS_BASER_INDIRECT);
1727 indirect = !!(baser->val & GITS_BASER_INDIRECT);
1728
1729 if (indirect) {
1730 /*
1731 * The size of the lvl2 table is equal to ITS page size
1732 * which is 'psz'. For computing lvl1 table size,
1733 * subtract ID bits that sparse lvl2 table from 'ids'
1734 * which is reported by ITS hardware times lvl1 table
1735 * entry size.
1736 */
1737 ids -= ilog2(psz / (int)esz);
1738 esz = GITS_LVL1_ENTRY_SIZE;
1739 }
1740 }
1741
1742 /*
1743 * Allocate as many entries as required to fit the
1744 * range of device IDs that the ITS can grok... The ID
1745 * space being incredibly sparse, this results in a
1746 * massive waste of memory if two-level device table
1747 * feature is not supported by hardware.
1748 */
1749 new_order = max_t(u32, get_order(esz << ids), new_order);
1750 if (new_order >= MAX_ORDER) {
1751 new_order = MAX_ORDER - 1;
1752 ids = ilog2(PAGE_ORDER_TO_SIZE(new_order) / (int)esz);
1753 pr_warn("ITS@%pa: %s Table too large, reduce ids %u->%u\n",
1754 &its->phys_base, its_base_type_string[type],
1755 its->device_ids, ids);
1756 }
1757
1758 *order = new_order;
1759
1760 return indirect;
1761}
1762
1763static void its_free_tables(struct its_node *its)
1764{
1765 int i;
1766
1767 for (i = 0; i < GITS_BASER_NR_REGS; i++) {
1768 if (its->tables[i].base) {
1769 free_pages((unsigned long)its->tables[i].base,
1770 its->tables[i].order);
1771 its->tables[i].base = NULL;
1772 }
1773 }
1774}
1775
1776static int its_alloc_tables(struct its_node *its)
1777{
1778 u64 shr = GITS_BASER_InnerShareable;
1779 u64 cache = GITS_BASER_RaWaWb;
1780 u32 psz = SZ_64K;
1781 int err, i;
1782
1783 if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_22375)
1784 /* erratum 24313: ignore memory access type */
1785 cache = GITS_BASER_nCnB;
1786
1787 for (i = 0; i < GITS_BASER_NR_REGS; i++) {
1788 struct its_baser *baser = its->tables + i;
1789 u64 val = its_read_baser(its, baser);
1790 u64 type = GITS_BASER_TYPE(val);
1791 u32 order = get_order(psz);
1792 bool indirect = false;
1793
1794 switch (type) {
1795 case GITS_BASER_TYPE_NONE:
1796 continue;
1797
1798 case GITS_BASER_TYPE_DEVICE:
1799 indirect = its_parse_indirect_baser(its, baser,
1800 psz, &order,
1801 its->device_ids);
1802 case GITS_BASER_TYPE_VCPU:
1803 indirect = its_parse_indirect_baser(its, baser,
1804 psz, &order,
1805 ITS_MAX_VPEID_BITS);
1806 break;
1807 }
1808
1809 err = its_setup_baser(its, baser, cache, shr, psz, order, indirect);
1810 if (err < 0) {
1811 its_free_tables(its);
1812 return err;
1813 }
1814
1815 /* Update settings which will be used for next BASERn */
1816 psz = baser->psz;
1817 cache = baser->val & GITS_BASER_CACHEABILITY_MASK;
1818 shr = baser->val & GITS_BASER_SHAREABILITY_MASK;
1819 }
1820
1821 return 0;
1822}
1823
1824static int its_alloc_collections(struct its_node *its)
1825{
1826 its->collections = kzalloc(nr_cpu_ids * sizeof(*its->collections),
1827 GFP_KERNEL);
1828 if (!its->collections)
1829 return -ENOMEM;
1830
1831 return 0;
1832}
1833
1834static struct page *its_allocate_pending_table(gfp_t gfp_flags)
1835{
1836 struct page *pend_page;
1837 /*
1838 * The pending pages have to be at least 64kB aligned,
1839 * hence the 'max(LPI_PENDBASE_SZ, SZ_64K)' below.
1840 */
1841 pend_page = alloc_pages(gfp_flags | __GFP_ZERO,
1842 get_order(max_t(u32, LPI_PENDBASE_SZ, SZ_64K)));
1843 if (!pend_page)
1844 return NULL;
1845
1846 /* Make sure the GIC will observe the zero-ed page */
1847 gic_flush_dcache_to_poc(page_address(pend_page), LPI_PENDBASE_SZ);
1848
1849 return pend_page;
1850}
1851
1852static void its_free_pending_table(struct page *pt)
1853{
1854 free_pages((unsigned long)page_address(pt),
1855 get_order(max_t(u32, LPI_PENDBASE_SZ, SZ_64K)));
1856}
1857
1858static void its_cpu_init_lpis(void)
1859{
1860 void __iomem *rbase = gic_data_rdist_rd_base();
1861 struct page *pend_page;
1862 u64 val, tmp;
1863
1864 /* If we didn't allocate the pending table yet, do it now */
1865 pend_page = gic_data_rdist()->pend_page;
1866 if (!pend_page) {
1867 phys_addr_t paddr;
1868
1869 pend_page = its_allocate_pending_table(GFP_NOWAIT);
1870 if (!pend_page) {
1871 pr_err("Failed to allocate PENDBASE for CPU%d\n",
1872 smp_processor_id());
1873 return;
1874 }
1875
1876 paddr = page_to_phys(pend_page);
1877 pr_info("CPU%d: using LPI pending table @%pa\n",
1878 smp_processor_id(), &paddr);
1879 gic_data_rdist()->pend_page = pend_page;
1880 }
1881
1882 /* set PROPBASE */
1883 val = (page_to_phys(gic_rdists->prop_page) |
1884 GICR_PROPBASER_InnerShareable |
1885 GICR_PROPBASER_RaWaWb |
1886 ((LPI_NRBITS - 1) & GICR_PROPBASER_IDBITS_MASK));
1887
1888 gicr_write_propbaser(val, rbase + GICR_PROPBASER);
1889 tmp = gicr_read_propbaser(rbase + GICR_PROPBASER);
1890
1891 if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) {
1892 if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) {
1893 /*
1894 * The HW reports non-shareable, we must
1895 * remove the cacheability attributes as
1896 * well.
1897 */
1898 val &= ~(GICR_PROPBASER_SHAREABILITY_MASK |
1899 GICR_PROPBASER_CACHEABILITY_MASK);
1900 val |= GICR_PROPBASER_nC;
1901 gicr_write_propbaser(val, rbase + GICR_PROPBASER);
1902 }
1903 pr_info_once("GIC: using cache flushing for LPI property table\n");
1904 gic_rdists->flags |= RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING;
1905 }
1906
1907 /* set PENDBASE */
1908 val = (page_to_phys(pend_page) |
1909 GICR_PENDBASER_InnerShareable |
1910 GICR_PENDBASER_RaWaWb);
1911
1912 gicr_write_pendbaser(val, rbase + GICR_PENDBASER);
1913 tmp = gicr_read_pendbaser(rbase + GICR_PENDBASER);
1914
1915 if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) {
1916 /*
1917 * The HW reports non-shareable, we must remove the
1918 * cacheability attributes as well.
1919 */
1920 val &= ~(GICR_PENDBASER_SHAREABILITY_MASK |
1921 GICR_PENDBASER_CACHEABILITY_MASK);
1922 val |= GICR_PENDBASER_nC;
1923 gicr_write_pendbaser(val, rbase + GICR_PENDBASER);
1924 }
1925
1926 /* Enable LPIs */
1927 val = readl_relaxed(rbase + GICR_CTLR);
1928 val |= GICR_CTLR_ENABLE_LPIS;
1929 writel_relaxed(val, rbase + GICR_CTLR);
1930
1931 /* Make sure the GIC has seen the above */
1932 dsb(sy);
1933}
1934
1935static void its_cpu_init_collection(struct its_node *its)
1936{
1937 int cpu = smp_processor_id();
1938 u64 target;
1939
1940 /* avoid cross node collections and its mapping */
1941 if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) {
1942 struct device_node *cpu_node;
1943
1944 cpu_node = of_get_cpu_node(cpu, NULL);
1945 if (its->numa_node != NUMA_NO_NODE &&
1946 its->numa_node != of_node_to_nid(cpu_node))
1947 return;
1948 }
1949
1950 /*
1951 * We now have to bind each collection to its target
1952 * redistributor.
1953 */
1954 if (gic_read_typer(its->base + GITS_TYPER) & GITS_TYPER_PTA) {
1955 /*
1956 * This ITS wants the physical address of the
1957 * redistributor.
1958 */
1959 target = gic_data_rdist()->phys_base;
1960 } else {
1961 /* This ITS wants a linear CPU number. */
1962 target = gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER);
1963 target = GICR_TYPER_CPU_NUMBER(target) << 16;
1964 }
1965
1966 /* Perform collection mapping */
1967 its->collections[cpu].target_address = target;
1968 its->collections[cpu].col_id = cpu;
1969
1970 its_send_mapc(its, &its->collections[cpu], 1);
1971 its_send_invall(its, &its->collections[cpu]);
1972}
1973
1974static void its_cpu_init_collections(void)
1975{
1976 struct its_node *its;
1977
1978 spin_lock(&its_lock);
1979
1980 list_for_each_entry(its, &its_nodes, entry)
1981 its_cpu_init_collection(its);
1982
1983 spin_unlock(&its_lock);
1984}
1985
1986static struct its_device *its_find_device(struct its_node *its, u32 dev_id)
1987{
1988 struct its_device *its_dev = NULL, *tmp;
1989 unsigned long flags;
1990
1991 raw_spin_lock_irqsave(&its->lock, flags);
1992
1993 list_for_each_entry(tmp, &its->its_device_list, entry) {
1994 if (tmp->device_id == dev_id) {
1995 its_dev = tmp;
1996 break;
1997 }
1998 }
1999
2000 raw_spin_unlock_irqrestore(&its->lock, flags);
2001
2002 return its_dev;
2003}
2004
2005static struct its_baser *its_get_baser(struct its_node *its, u32 type)
2006{
2007 int i;
2008
2009 for (i = 0; i < GITS_BASER_NR_REGS; i++) {
2010 if (GITS_BASER_TYPE(its->tables[i].val) == type)
2011 return &its->tables[i];
2012 }
2013
2014 return NULL;
2015}
2016
2017static bool its_alloc_table_entry(struct its_baser *baser, u32 id)
2018{
2019 struct page *page;
2020 u32 esz, idx;
2021 __le64 *table;
2022
2023 /* Don't allow device id that exceeds single, flat table limit */
2024 esz = GITS_BASER_ENTRY_SIZE(baser->val);
2025 if (!(baser->val & GITS_BASER_INDIRECT))
2026 return (id < (PAGE_ORDER_TO_SIZE(baser->order) / esz));
2027
2028 /* Compute 1st level table index & check if that exceeds table limit */
2029 idx = id >> ilog2(baser->psz / esz);
2030 if (idx >= (PAGE_ORDER_TO_SIZE(baser->order) / GITS_LVL1_ENTRY_SIZE))
2031 return false;
2032
2033 table = baser->base;
2034
2035 /* Allocate memory for 2nd level table */
2036 if (!table[idx]) {
2037 page = alloc_pages(GFP_KERNEL | __GFP_ZERO, get_order(baser->psz));
2038 if (!page)
2039 return false;
2040
2041 /* Flush Lvl2 table to PoC if hw doesn't support coherency */
2042 if (!(baser->val & GITS_BASER_SHAREABILITY_MASK))
2043 gic_flush_dcache_to_poc(page_address(page), baser->psz);
2044
2045 table[idx] = cpu_to_le64(page_to_phys(page) | GITS_BASER_VALID);
2046
2047 /* Flush Lvl1 entry to PoC if hw doesn't support coherency */
2048 if (!(baser->val & GITS_BASER_SHAREABILITY_MASK))
2049 gic_flush_dcache_to_poc(table + idx, GITS_LVL1_ENTRY_SIZE);
2050
2051 /* Ensure updated table contents are visible to ITS hardware */
2052 dsb(sy);
2053 }
2054
2055 return true;
2056}
2057
2058static bool its_alloc_device_table(struct its_node *its, u32 dev_id)
2059{
2060 struct its_baser *baser;
2061
2062 baser = its_get_baser(its, GITS_BASER_TYPE_DEVICE);
2063
2064 /* Don't allow device id that exceeds ITS hardware limit */
2065 if (!baser)
2066 return (ilog2(dev_id) < its->device_ids);
2067
2068 return its_alloc_table_entry(baser, dev_id);
2069}
2070
2071static bool its_alloc_vpe_table(u32 vpe_id)
2072{
2073 struct its_node *its;
2074
2075 /*
2076 * Make sure the L2 tables are allocated on *all* v4 ITSs. We
2077 * could try and only do it on ITSs corresponding to devices
2078 * that have interrupts targeted at this VPE, but the
2079 * complexity becomes crazy (and you have tons of memory
2080 * anyway, right?).
2081 */
2082 list_for_each_entry(its, &its_nodes, entry) {
2083 struct its_baser *baser;
2084
2085 if (!its->is_v4)
2086 continue;
2087
2088 baser = its_get_baser(its, GITS_BASER_TYPE_VCPU);
2089 if (!baser)
2090 return false;
2091
2092 if (!its_alloc_table_entry(baser, vpe_id))
2093 return false;
2094 }
2095
2096 return true;
2097}
2098
2099static struct its_device *its_create_device(struct its_node *its, u32 dev_id,
2100 int nvecs, bool alloc_lpis)
2101{
2102 struct its_device *dev;
2103 unsigned long *lpi_map = NULL;
2104 unsigned long flags;
2105 u16 *col_map = NULL;
2106 void *itt;
2107 int lpi_base;
2108 int nr_lpis;
2109 int nr_ites;
2110 int sz;
2111
2112 if (!its_alloc_device_table(its, dev_id))
2113 return NULL;
2114
2115 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
2116 /*
2117 * We allocate at least one chunk worth of LPIs bet device,
2118 * and thus that many ITEs. The device may require less though.
2119 */
2120 nr_ites = max(IRQS_PER_CHUNK, roundup_pow_of_two(nvecs));
2121 sz = nr_ites * its->ite_size;
2122 sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1;
2123 itt = kzalloc(sz, GFP_KERNEL);
2124 if (alloc_lpis) {
2125 lpi_map = its_lpi_alloc_chunks(nvecs, &lpi_base, &nr_lpis);
2126 if (lpi_map)
2127 col_map = kzalloc(sizeof(*col_map) * nr_lpis,
2128 GFP_KERNEL);
2129 } else {
2130 col_map = kzalloc(sizeof(*col_map) * nr_ites, GFP_KERNEL);
2131 nr_lpis = 0;
2132 lpi_base = 0;
2133 }
2134
2135 if (!dev || !itt || !col_map || (!lpi_map && alloc_lpis)) {
2136 kfree(dev);
2137 kfree(itt);
2138 kfree(lpi_map);
2139 kfree(col_map);
2140 return NULL;
2141 }
2142
2143 gic_flush_dcache_to_poc(itt, sz);
2144
2145 dev->its = its;
2146 dev->itt = itt;
2147 dev->nr_ites = nr_ites;
2148 dev->event_map.lpi_map = lpi_map;
2149 dev->event_map.col_map = col_map;
2150 dev->event_map.lpi_base = lpi_base;
2151 dev->event_map.nr_lpis = nr_lpis;
2152 mutex_init(&dev->event_map.vlpi_lock);
2153 dev->device_id = dev_id;
2154 INIT_LIST_HEAD(&dev->entry);
2155
2156 raw_spin_lock_irqsave(&its->lock, flags);
2157 list_add(&dev->entry, &its->its_device_list);
2158 raw_spin_unlock_irqrestore(&its->lock, flags);
2159
2160 /* Map device to its ITT */
2161 its_send_mapd(dev, 1);
2162
2163 return dev;
2164}
2165
2166static void its_free_device(struct its_device *its_dev)
2167{
2168 unsigned long flags;
2169
2170 raw_spin_lock_irqsave(&its_dev->its->lock, flags);
2171 list_del(&its_dev->entry);
2172 raw_spin_unlock_irqrestore(&its_dev->its->lock, flags);
2173 kfree(its_dev->itt);
2174 kfree(its_dev);
2175}
2176
2177static int its_alloc_device_irq(struct its_device *dev, irq_hw_number_t *hwirq)
2178{
2179 int idx;
2180
2181 idx = find_first_zero_bit(dev->event_map.lpi_map,
2182 dev->event_map.nr_lpis);
2183 if (idx == dev->event_map.nr_lpis)
2184 return -ENOSPC;
2185
2186 *hwirq = dev->event_map.lpi_base + idx;
2187 set_bit(idx, dev->event_map.lpi_map);
2188
2189 return 0;
2190}
2191
2192static int its_msi_prepare(struct irq_domain *domain, struct device *dev,
2193 int nvec, msi_alloc_info_t *info)
2194{
2195 struct its_node *its;
2196 struct its_device *its_dev;
2197 struct msi_domain_info *msi_info;
2198 u32 dev_id;
2199
2200 /*
2201 * We ignore "dev" entierely, and rely on the dev_id that has
2202 * been passed via the scratchpad. This limits this domain's
2203 * usefulness to upper layers that definitely know that they
2204 * are built on top of the ITS.
2205 */
2206 dev_id = info->scratchpad[0].ul;
2207
2208 msi_info = msi_get_domain_info(domain);
2209 its = msi_info->data;
2210
2211 if (!gic_rdists->has_direct_lpi &&
2212 vpe_proxy.dev &&
2213 vpe_proxy.dev->its == its &&
2214 dev_id == vpe_proxy.dev->device_id) {
2215 /* Bad luck. Get yourself a better implementation */
2216 WARN_ONCE(1, "DevId %x clashes with GICv4 VPE proxy device\n",
2217 dev_id);
2218 return -EINVAL;
2219 }
2220
2221 its_dev = its_find_device(its, dev_id);
2222 if (its_dev) {
2223 /*
2224 * We already have seen this ID, probably through
2225 * another alias (PCI bridge of some sort). No need to
2226 * create the device.
2227 */
2228 pr_debug("Reusing ITT for devID %x\n", dev_id);
2229 goto out;
2230 }
2231
2232 its_dev = its_create_device(its, dev_id, nvec, true);
2233 if (!its_dev)
2234 return -ENOMEM;
2235
2236 pr_debug("ITT %d entries, %d bits\n", nvec, ilog2(nvec));
2237out:
2238 info->scratchpad[0].ptr = its_dev;
2239 return 0;
2240}
2241
2242static struct msi_domain_ops its_msi_domain_ops = {
2243 .msi_prepare = its_msi_prepare,
2244};
2245
2246static int its_irq_gic_domain_alloc(struct irq_domain *domain,
2247 unsigned int virq,
2248 irq_hw_number_t hwirq)
2249{
2250 struct irq_fwspec fwspec;
2251
2252 if (irq_domain_get_of_node(domain->parent)) {
2253 fwspec.fwnode = domain->parent->fwnode;
2254 fwspec.param_count = 3;
2255 fwspec.param[0] = GIC_IRQ_TYPE_LPI;
2256 fwspec.param[1] = hwirq;
2257 fwspec.param[2] = IRQ_TYPE_EDGE_RISING;
2258 } else if (is_fwnode_irqchip(domain->parent->fwnode)) {
2259 fwspec.fwnode = domain->parent->fwnode;
2260 fwspec.param_count = 2;
2261 fwspec.param[0] = hwirq;
2262 fwspec.param[1] = IRQ_TYPE_EDGE_RISING;
2263 } else {
2264 return -EINVAL;
2265 }
2266
2267 return irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
2268}
2269
2270static int its_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
2271 unsigned int nr_irqs, void *args)
2272{
2273 msi_alloc_info_t *info = args;
2274 struct its_device *its_dev = info->scratchpad[0].ptr;
2275 irq_hw_number_t hwirq;
2276 int err;
2277 int i;
2278
2279 for (i = 0; i < nr_irqs; i++) {
2280 err = its_alloc_device_irq(its_dev, &hwirq);
2281 if (err)
2282 return err;
2283
2284 err = its_irq_gic_domain_alloc(domain, virq + i, hwirq);
2285 if (err)
2286 return err;
2287
2288 irq_domain_set_hwirq_and_chip(domain, virq + i,
2289 hwirq, &its_irq_chip, its_dev);
2290 irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(virq + i)));
2291 pr_debug("ID:%d pID:%d vID:%d\n",
2292 (int)(hwirq - its_dev->event_map.lpi_base),
2293 (int) hwirq, virq + i);
2294 }
2295
2296 return 0;
2297}
2298
2299static int its_irq_domain_activate(struct irq_domain *domain,
2300 struct irq_data *d, bool reserve)
2301{
2302 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
2303 u32 event = its_get_event_id(d);
2304 const struct cpumask *cpu_mask = cpu_online_mask;
2305 int cpu;
2306
2307 /* get the cpu_mask of local node */
2308 if (its_dev->its->numa_node >= 0)
2309 cpu_mask = cpumask_of_node(its_dev->its->numa_node);
2310
2311 /* Bind the LPI to the first possible CPU */
2312 cpu = cpumask_first(cpu_mask);
2313 its_dev->event_map.col_map[event] = cpu;
2314 irq_data_update_effective_affinity(d, cpumask_of(cpu));
2315
2316 /* Map the GIC IRQ and event to the device */
2317 its_send_mapti(its_dev, d->hwirq, event);
2318 return 0;
2319}
2320
2321static void its_irq_domain_deactivate(struct irq_domain *domain,
2322 struct irq_data *d)
2323{
2324 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
2325 u32 event = its_get_event_id(d);
2326
2327 /* Stop the delivery of interrupts */
2328 its_send_discard(its_dev, event);
2329}
2330
2331static void its_irq_domain_free(struct irq_domain *domain, unsigned int virq,
2332 unsigned int nr_irqs)
2333{
2334 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
2335 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
2336 int i;
2337
2338 for (i = 0; i < nr_irqs; i++) {
2339 struct irq_data *data = irq_domain_get_irq_data(domain,
2340 virq + i);
2341 u32 event = its_get_event_id(data);
2342
2343 /* Mark interrupt index as unused */
2344 clear_bit(event, its_dev->event_map.lpi_map);
2345
2346 /* Nuke the entry in the domain */
2347 irq_domain_reset_irq_data(data);
2348 }
2349
2350 /* If all interrupts have been freed, start mopping the floor */
2351 if (bitmap_empty(its_dev->event_map.lpi_map,
2352 its_dev->event_map.nr_lpis)) {
2353 its_lpi_free_chunks(its_dev->event_map.lpi_map,
2354 its_dev->event_map.lpi_base,
2355 its_dev->event_map.nr_lpis);
2356 kfree(its_dev->event_map.col_map);
2357
2358 /* Unmap device/itt */
2359 its_send_mapd(its_dev, 0);
2360 its_free_device(its_dev);
2361 }
2362
2363 irq_domain_free_irqs_parent(domain, virq, nr_irqs);
2364}
2365
2366static const struct irq_domain_ops its_domain_ops = {
2367 .alloc = its_irq_domain_alloc,
2368 .free = its_irq_domain_free,
2369 .activate = its_irq_domain_activate,
2370 .deactivate = its_irq_domain_deactivate,
2371};
2372
2373/*
2374 * This is insane.
2375 *
2376 * If a GICv4 doesn't implement Direct LPIs (which is extremely
2377 * likely), the only way to perform an invalidate is to use a fake
2378 * device to issue an INV command, implying that the LPI has first
2379 * been mapped to some event on that device. Since this is not exactly
2380 * cheap, we try to keep that mapping around as long as possible, and
2381 * only issue an UNMAP if we're short on available slots.
2382 *
2383 * Broken by design(tm).
2384 */
2385static void its_vpe_db_proxy_unmap_locked(struct its_vpe *vpe)
2386{
2387 /* Already unmapped? */
2388 if (vpe->vpe_proxy_event == -1)
2389 return;
2390
2391 its_send_discard(vpe_proxy.dev, vpe->vpe_proxy_event);
2392 vpe_proxy.vpes[vpe->vpe_proxy_event] = NULL;
2393
2394 /*
2395 * We don't track empty slots at all, so let's move the
2396 * next_victim pointer if we can quickly reuse that slot
2397 * instead of nuking an existing entry. Not clear that this is
2398 * always a win though, and this might just generate a ripple
2399 * effect... Let's just hope VPEs don't migrate too often.
2400 */
2401 if (vpe_proxy.vpes[vpe_proxy.next_victim])
2402 vpe_proxy.next_victim = vpe->vpe_proxy_event;
2403
2404 vpe->vpe_proxy_event = -1;
2405}
2406
2407static void its_vpe_db_proxy_unmap(struct its_vpe *vpe)
2408{
2409 if (!gic_rdists->has_direct_lpi) {
2410 unsigned long flags;
2411
2412 raw_spin_lock_irqsave(&vpe_proxy.lock, flags);
2413 its_vpe_db_proxy_unmap_locked(vpe);
2414 raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags);
2415 }
2416}
2417
2418static void its_vpe_db_proxy_map_locked(struct its_vpe *vpe)
2419{
2420 /* Already mapped? */
2421 if (vpe->vpe_proxy_event != -1)
2422 return;
2423
2424 /* This slot was already allocated. Kick the other VPE out. */
2425 if (vpe_proxy.vpes[vpe_proxy.next_victim])
2426 its_vpe_db_proxy_unmap_locked(vpe_proxy.vpes[vpe_proxy.next_victim]);
2427
2428 /* Map the new VPE instead */
2429 vpe_proxy.vpes[vpe_proxy.next_victim] = vpe;
2430 vpe->vpe_proxy_event = vpe_proxy.next_victim;
2431 vpe_proxy.next_victim = (vpe_proxy.next_victim + 1) % vpe_proxy.dev->nr_ites;
2432
2433 vpe_proxy.dev->event_map.col_map[vpe->vpe_proxy_event] = vpe->col_idx;
2434 its_send_mapti(vpe_proxy.dev, vpe->vpe_db_lpi, vpe->vpe_proxy_event);
2435}
2436
2437static void its_vpe_db_proxy_move(struct its_vpe *vpe, int from, int to)
2438{
2439 unsigned long flags;
2440 struct its_collection *target_col;
2441
2442 if (gic_rdists->has_direct_lpi) {
2443 void __iomem *rdbase;
2444
2445 rdbase = per_cpu_ptr(gic_rdists->rdist, from)->rd_base;
2446 gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_CLRLPIR);
2447 while (gic_read_lpir(rdbase + GICR_SYNCR) & 1)
2448 cpu_relax();
2449
2450 return;
2451 }
2452
2453 raw_spin_lock_irqsave(&vpe_proxy.lock, flags);
2454
2455 its_vpe_db_proxy_map_locked(vpe);
2456
2457 target_col = &vpe_proxy.dev->its->collections[to];
2458 its_send_movi(vpe_proxy.dev, target_col, vpe->vpe_proxy_event);
2459 vpe_proxy.dev->event_map.col_map[vpe->vpe_proxy_event] = to;
2460
2461 raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags);
2462}
2463
2464static int its_vpe_set_affinity(struct irq_data *d,
2465 const struct cpumask *mask_val,
2466 bool force)
2467{
2468 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
2469 int cpu = cpumask_first(mask_val);
2470
2471 /*
2472 * Changing affinity is mega expensive, so let's be as lazy as
2473 * we can and only do it if we really have to. Also, if mapped
2474 * into the proxy device, we need to move the doorbell
2475 * interrupt to its new location.
2476 */
2477 if (vpe->col_idx != cpu) {
2478 int from = vpe->col_idx;
2479
2480 vpe->col_idx = cpu;
2481 its_send_vmovp(vpe);
2482 its_vpe_db_proxy_move(vpe, from, cpu);
2483 }
2484
2485 irq_data_update_effective_affinity(d, cpumask_of(cpu));
2486
2487 return IRQ_SET_MASK_OK_DONE;
2488}
2489
2490static void its_vpe_schedule(struct its_vpe *vpe)
2491{
2492 void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
2493 u64 val;
2494
2495 /* Schedule the VPE */
2496 val = virt_to_phys(page_address(vpe->its_vm->vprop_page)) &
2497 GENMASK_ULL(51, 12);
2498 val |= (LPI_NRBITS - 1) & GICR_VPROPBASER_IDBITS_MASK;
2499 val |= GICR_VPROPBASER_RaWb;
2500 val |= GICR_VPROPBASER_InnerShareable;
2501 gits_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER);
2502
2503 val = virt_to_phys(page_address(vpe->vpt_page)) &
2504 GENMASK_ULL(51, 16);
2505 val |= GICR_VPENDBASER_RaWaWb;
2506 val |= GICR_VPENDBASER_NonShareable;
2507 /*
2508 * There is no good way of finding out if the pending table is
2509 * empty as we can race against the doorbell interrupt very
2510 * easily. So in the end, vpe->pending_last is only an
2511 * indication that the vcpu has something pending, not one
2512 * that the pending table is empty. A good implementation
2513 * would be able to read its coarse map pretty quickly anyway,
2514 * making this a tolerable issue.
2515 */
2516 val |= GICR_VPENDBASER_PendingLast;
2517 val |= vpe->idai ? GICR_VPENDBASER_IDAI : 0;
2518 val |= GICR_VPENDBASER_Valid;
2519 gits_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER);
2520}
2521
2522static void its_vpe_deschedule(struct its_vpe *vpe)
2523{
2524 void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
2525 u32 count = 1000000; /* 1s! */
2526 bool clean;
2527 u64 val;
2528
2529 /* We're being scheduled out */
2530 val = gits_read_vpendbaser(vlpi_base + GICR_VPENDBASER);
2531 val &= ~GICR_VPENDBASER_Valid;
2532 gits_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER);
2533
2534 do {
2535 val = gits_read_vpendbaser(vlpi_base + GICR_VPENDBASER);
2536 clean = !(val & GICR_VPENDBASER_Dirty);
2537 if (!clean) {
2538 count--;
2539 cpu_relax();
2540 udelay(1);
2541 }
2542 } while (!clean && count);
2543
2544 if (unlikely(!clean && !count)) {
2545 pr_err_ratelimited("ITS virtual pending table not cleaning\n");
2546 vpe->idai = false;
2547 vpe->pending_last = true;
2548 } else {
2549 vpe->idai = !!(val & GICR_VPENDBASER_IDAI);
2550 vpe->pending_last = !!(val & GICR_VPENDBASER_PendingLast);
2551 }
2552}
2553
2554static void its_vpe_invall(struct its_vpe *vpe)
2555{
2556 struct its_node *its;
2557
2558 list_for_each_entry(its, &its_nodes, entry) {
2559 if (!its->is_v4)
2560 continue;
2561
2562 if (its_list_map && !vpe->its_vm->vlpi_count[its->list_nr])
2563 continue;
2564
2565 /*
2566 * Sending a VINVALL to a single ITS is enough, as all
2567 * we need is to reach the redistributors.
2568 */
2569 its_send_vinvall(its, vpe);
2570 return;
2571 }
2572}
2573
2574static int its_vpe_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
2575{
2576 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
2577 struct its_cmd_info *info = vcpu_info;
2578
2579 switch (info->cmd_type) {
2580 case SCHEDULE_VPE:
2581 its_vpe_schedule(vpe);
2582 return 0;
2583
2584 case DESCHEDULE_VPE:
2585 its_vpe_deschedule(vpe);
2586 return 0;
2587
2588 case INVALL_VPE:
2589 its_vpe_invall(vpe);
2590 return 0;
2591
2592 default:
2593 return -EINVAL;
2594 }
2595}
2596
2597static void its_vpe_send_cmd(struct its_vpe *vpe,
2598 void (*cmd)(struct its_device *, u32))
2599{
2600 unsigned long flags;
2601
2602 raw_spin_lock_irqsave(&vpe_proxy.lock, flags);
2603
2604 its_vpe_db_proxy_map_locked(vpe);
2605 cmd(vpe_proxy.dev, vpe->vpe_proxy_event);
2606
2607 raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags);
2608}
2609
2610static void its_vpe_send_inv(struct irq_data *d)
2611{
2612 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
2613
2614 if (gic_rdists->has_direct_lpi) {
2615 void __iomem *rdbase;
2616
2617 rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base;
2618 gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_INVLPIR);
2619 while (gic_read_lpir(rdbase + GICR_SYNCR) & 1)
2620 cpu_relax();
2621 } else {
2622 its_vpe_send_cmd(vpe, its_send_inv);
2623 }
2624}
2625
2626static void its_vpe_mask_irq(struct irq_data *d)
2627{
2628 /*
2629 * We need to unmask the LPI, which is described by the parent
2630 * irq_data. Instead of calling into the parent (which won't
2631 * exactly do the right thing, let's simply use the
2632 * parent_data pointer. Yes, I'm naughty.
2633 */
2634 lpi_write_config(d->parent_data, LPI_PROP_ENABLED, 0);
2635 its_vpe_send_inv(d);
2636}
2637
2638static void its_vpe_unmask_irq(struct irq_data *d)
2639{
2640 /* Same hack as above... */
2641 lpi_write_config(d->parent_data, 0, LPI_PROP_ENABLED);
2642 its_vpe_send_inv(d);
2643}
2644
2645static int its_vpe_set_irqchip_state(struct irq_data *d,
2646 enum irqchip_irq_state which,
2647 bool state)
2648{
2649 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
2650
2651 if (which != IRQCHIP_STATE_PENDING)
2652 return -EINVAL;
2653
2654 if (gic_rdists->has_direct_lpi) {
2655 void __iomem *rdbase;
2656
2657 rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base;
2658 if (state) {
2659 gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_SETLPIR);
2660 } else {
2661 gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_CLRLPIR);
2662 while (gic_read_lpir(rdbase + GICR_SYNCR) & 1)
2663 cpu_relax();
2664 }
2665 } else {
2666 if (state)
2667 its_vpe_send_cmd(vpe, its_send_int);
2668 else
2669 its_vpe_send_cmd(vpe, its_send_clear);
2670 }
2671
2672 return 0;
2673}
2674
2675static struct irq_chip its_vpe_irq_chip = {
2676 .name = "GICv4-vpe",
2677 .irq_mask = its_vpe_mask_irq,
2678 .irq_unmask = its_vpe_unmask_irq,
2679 .irq_eoi = irq_chip_eoi_parent,
2680 .irq_set_affinity = its_vpe_set_affinity,
2681 .irq_set_irqchip_state = its_vpe_set_irqchip_state,
2682 .irq_set_vcpu_affinity = its_vpe_set_vcpu_affinity,
2683};
2684
2685static int its_vpe_id_alloc(void)
2686{
2687 return ida_simple_get(&its_vpeid_ida, 0, ITS_MAX_VPEID, GFP_KERNEL);
2688}
2689
2690static void its_vpe_id_free(u16 id)
2691{
2692 ida_simple_remove(&its_vpeid_ida, id);
2693}
2694
2695static int its_vpe_init(struct its_vpe *vpe)
2696{
2697 struct page *vpt_page;
2698 int vpe_id;
2699
2700 /* Allocate vpe_id */
2701 vpe_id = its_vpe_id_alloc();
2702 if (vpe_id < 0)
2703 return vpe_id;
2704
2705 /* Allocate VPT */
2706 vpt_page = its_allocate_pending_table(GFP_KERNEL);
2707 if (!vpt_page) {
2708 its_vpe_id_free(vpe_id);
2709 return -ENOMEM;
2710 }
2711
2712 if (!its_alloc_vpe_table(vpe_id)) {
2713 its_vpe_id_free(vpe_id);
2714 its_free_pending_table(vpe->vpt_page);
2715 return -ENOMEM;
2716 }
2717
2718 vpe->vpe_id = vpe_id;
2719 vpe->vpt_page = vpt_page;
2720 vpe->vpe_proxy_event = -1;
2721
2722 return 0;
2723}
2724
2725static void its_vpe_teardown(struct its_vpe *vpe)
2726{
2727 its_vpe_db_proxy_unmap(vpe);
2728 its_vpe_id_free(vpe->vpe_id);
2729 its_free_pending_table(vpe->vpt_page);
2730}
2731
2732static void its_vpe_irq_domain_free(struct irq_domain *domain,
2733 unsigned int virq,
2734 unsigned int nr_irqs)
2735{
2736 struct its_vm *vm = domain->host_data;
2737 int i;
2738
2739 irq_domain_free_irqs_parent(domain, virq, nr_irqs);
2740
2741 for (i = 0; i < nr_irqs; i++) {
2742 struct irq_data *data = irq_domain_get_irq_data(domain,
2743 virq + i);
2744 struct its_vpe *vpe = irq_data_get_irq_chip_data(data);
2745
2746 BUG_ON(vm != vpe->its_vm);
2747
2748 clear_bit(data->hwirq, vm->db_bitmap);
2749 its_vpe_teardown(vpe);
2750 irq_domain_reset_irq_data(data);
2751 }
2752
2753 if (bitmap_empty(vm->db_bitmap, vm->nr_db_lpis)) {
2754 its_lpi_free_chunks(vm->db_bitmap, vm->db_lpi_base, vm->nr_db_lpis);
2755 its_free_prop_table(vm->vprop_page);
2756 }
2757}
2758
2759static int its_vpe_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
2760 unsigned int nr_irqs, void *args)
2761{
2762 struct its_vm *vm = args;
2763 unsigned long *bitmap;
2764 struct page *vprop_page;
2765 int base, nr_ids, i, err = 0;
2766
2767 BUG_ON(!vm);
2768
2769 bitmap = its_lpi_alloc_chunks(nr_irqs, &base, &nr_ids);
2770 if (!bitmap)
2771 return -ENOMEM;
2772
2773 if (nr_ids < nr_irqs) {
2774 its_lpi_free_chunks(bitmap, base, nr_ids);
2775 return -ENOMEM;
2776 }
2777
2778 vprop_page = its_allocate_prop_table(GFP_KERNEL);
2779 if (!vprop_page) {
2780 its_lpi_free_chunks(bitmap, base, nr_ids);
2781 return -ENOMEM;
2782 }
2783
2784 vm->db_bitmap = bitmap;
2785 vm->db_lpi_base = base;
2786 vm->nr_db_lpis = nr_ids;
2787 vm->vprop_page = vprop_page;
2788
2789 for (i = 0; i < nr_irqs; i++) {
2790 vm->vpes[i]->vpe_db_lpi = base + i;
2791 err = its_vpe_init(vm->vpes[i]);
2792 if (err)
2793 break;
2794 err = its_irq_gic_domain_alloc(domain, virq + i,
2795 vm->vpes[i]->vpe_db_lpi);
2796 if (err)
2797 break;
2798 irq_domain_set_hwirq_and_chip(domain, virq + i, i,
2799 &its_vpe_irq_chip, vm->vpes[i]);
2800 set_bit(i, bitmap);
2801 }
2802
2803 if (err) {
2804 if (i > 0)
2805 its_vpe_irq_domain_free(domain, virq, i - 1);
2806
2807 its_lpi_free_chunks(bitmap, base, nr_ids);
2808 its_free_prop_table(vprop_page);
2809 }
2810
2811 return err;
2812}
2813
2814static int its_vpe_irq_domain_activate(struct irq_domain *domain,
2815 struct irq_data *d, bool reserve)
2816{
2817 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
2818 struct its_node *its;
2819
2820 /* If we use the list map, we issue VMAPP on demand... */
2821 if (its_list_map)
2822 return 0;
2823
2824 /* Map the VPE to the first possible CPU */
2825 vpe->col_idx = cpumask_first(cpu_online_mask);
2826
2827 list_for_each_entry(its, &its_nodes, entry) {
2828 if (!its->is_v4)
2829 continue;
2830
2831 its_send_vmapp(its, vpe, true);
2832 its_send_vinvall(its, vpe);
2833 }
2834
2835 irq_data_update_effective_affinity(d, cpumask_of(vpe->col_idx));
2836
2837 return 0;
2838}
2839
2840static void its_vpe_irq_domain_deactivate(struct irq_domain *domain,
2841 struct irq_data *d)
2842{
2843 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
2844 struct its_node *its;
2845
2846 /*
2847 * If we use the list map, we unmap the VPE once no VLPIs are
2848 * associated with the VM.
2849 */
2850 if (its_list_map)
2851 return;
2852
2853 list_for_each_entry(its, &its_nodes, entry) {
2854 if (!its->is_v4)
2855 continue;
2856
2857 its_send_vmapp(its, vpe, false);
2858 }
2859}
2860
2861static const struct irq_domain_ops its_vpe_domain_ops = {
2862 .alloc = its_vpe_irq_domain_alloc,
2863 .free = its_vpe_irq_domain_free,
2864 .activate = its_vpe_irq_domain_activate,
2865 .deactivate = its_vpe_irq_domain_deactivate,
2866};
2867
2868static int its_force_quiescent(void __iomem *base)
2869{
2870 u32 count = 1000000; /* 1s */
2871 u32 val;
2872
2873 val = readl_relaxed(base + GITS_CTLR);
2874 /*
2875 * GIC architecture specification requires the ITS to be both
2876 * disabled and quiescent for writes to GITS_BASER<n> or
2877 * GITS_CBASER to not have UNPREDICTABLE results.
2878 */
2879 if ((val & GITS_CTLR_QUIESCENT) && !(val & GITS_CTLR_ENABLE))
2880 return 0;
2881
2882 /* Disable the generation of all interrupts to this ITS */
2883 val &= ~(GITS_CTLR_ENABLE | GITS_CTLR_ImDe);
2884 writel_relaxed(val, base + GITS_CTLR);
2885
2886 /* Poll GITS_CTLR and wait until ITS becomes quiescent */
2887 while (1) {
2888 val = readl_relaxed(base + GITS_CTLR);
2889 if (val & GITS_CTLR_QUIESCENT)
2890 return 0;
2891
2892 count--;
2893 if (!count)
2894 return -EBUSY;
2895
2896 cpu_relax();
2897 udelay(1);
2898 }
2899}
2900
2901static bool __maybe_unused its_enable_quirk_cavium_22375(void *data)
2902{
2903 struct its_node *its = data;
2904
2905 /* erratum 22375: only alloc 8MB table size */
2906 its->device_ids = 0x14; /* 20 bits, 8MB */
2907 its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_22375;
2908
2909 return true;
2910}
2911
2912static bool __maybe_unused its_enable_quirk_cavium_23144(void *data)
2913{
2914 struct its_node *its = data;
2915
2916 its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_23144;
2917
2918 return true;
2919}
2920
2921static bool __maybe_unused its_enable_quirk_qdf2400_e0065(void *data)
2922{
2923 struct its_node *its = data;
2924
2925 /* On QDF2400, the size of the ITE is 16Bytes */
2926 its->ite_size = 16;
2927
2928 return true;
2929}
2930
2931static u64 its_irq_get_msi_base_pre_its(struct its_device *its_dev)
2932{
2933 struct its_node *its = its_dev->its;
2934
2935 /*
2936 * The Socionext Synquacer SoC has a so-called 'pre-ITS',
2937 * which maps 32-bit writes targeted at a separate window of
2938 * size '4 << device_id_bits' onto writes to GITS_TRANSLATER
2939 * with device ID taken from bits [device_id_bits + 1:2] of
2940 * the window offset.
2941 */
2942 return its->pre_its_base + (its_dev->device_id << 2);
2943}
2944
2945static bool __maybe_unused its_enable_quirk_socionext_synquacer(void *data)
2946{
2947 struct its_node *its = data;
2948 u32 pre_its_window[2];
2949 u32 ids;
2950
2951 if (!fwnode_property_read_u32_array(its->fwnode_handle,
2952 "socionext,synquacer-pre-its",
2953 pre_its_window,
2954 ARRAY_SIZE(pre_its_window))) {
2955
2956 its->pre_its_base = pre_its_window[0];
2957 its->get_msi_base = its_irq_get_msi_base_pre_its;
2958
2959 ids = ilog2(pre_its_window[1]) - 2;
2960 if (its->device_ids > ids)
2961 its->device_ids = ids;
2962
2963 /* the pre-ITS breaks isolation, so disable MSI remapping */
2964 its->msi_domain_flags &= ~IRQ_DOMAIN_FLAG_MSI_REMAP;
2965 return true;
2966 }
2967 return false;
2968}
2969
2970static bool __maybe_unused its_enable_quirk_hip07_161600802(void *data)
2971{
2972 struct its_node *its = data;
2973
2974 /*
2975 * Hip07 insists on using the wrong address for the VLPI
2976 * page. Trick it into doing the right thing...
2977 */
2978 its->vlpi_redist_offset = SZ_128K;
2979 return true;
2980}
2981
2982static const struct gic_quirk its_quirks[] = {
2983#ifdef CONFIG_CAVIUM_ERRATUM_22375
2984 {
2985 .desc = "ITS: Cavium errata 22375, 24313",
2986 .iidr = 0xa100034c, /* ThunderX pass 1.x */
2987 .mask = 0xffff0fff,
2988 .init = its_enable_quirk_cavium_22375,
2989 },
2990#endif
2991#ifdef CONFIG_CAVIUM_ERRATUM_23144
2992 {
2993 .desc = "ITS: Cavium erratum 23144",
2994 .iidr = 0xa100034c, /* ThunderX pass 1.x */
2995 .mask = 0xffff0fff,
2996 .init = its_enable_quirk_cavium_23144,
2997 },
2998#endif
2999#ifdef CONFIG_QCOM_QDF2400_ERRATUM_0065
3000 {
3001 .desc = "ITS: QDF2400 erratum 0065",
3002 .iidr = 0x00001070, /* QDF2400 ITS rev 1.x */
3003 .mask = 0xffffffff,
3004 .init = its_enable_quirk_qdf2400_e0065,
3005 },
3006#endif
3007#ifdef CONFIG_SOCIONEXT_SYNQUACER_PREITS
3008 {
3009 /*
3010 * The Socionext Synquacer SoC incorporates ARM's own GIC-500
3011 * implementation, but with a 'pre-ITS' added that requires
3012 * special handling in software.
3013 */
3014 .desc = "ITS: Socionext Synquacer pre-ITS",
3015 .iidr = 0x0001143b,
3016 .mask = 0xffffffff,
3017 .init = its_enable_quirk_socionext_synquacer,
3018 },
3019#endif
3020#ifdef CONFIG_HISILICON_ERRATUM_161600802
3021 {
3022 .desc = "ITS: Hip07 erratum 161600802",
3023 .iidr = 0x00000004,
3024 .mask = 0xffffffff,
3025 .init = its_enable_quirk_hip07_161600802,
3026 },
3027#endif
3028 {
3029 }
3030};
3031
3032static void its_enable_quirks(struct its_node *its)
3033{
3034 u32 iidr = readl_relaxed(its->base + GITS_IIDR);
3035
3036 gic_enable_quirks(iidr, its_quirks, its);
3037}
3038
3039static int its_save_disable(void)
3040{
3041 struct its_node *its;
3042 int err = 0;
3043
3044 spin_lock(&its_lock);
3045 list_for_each_entry(its, &its_nodes, entry) {
3046 void __iomem *base;
3047
3048 if (!(its->flags & ITS_FLAGS_SAVE_SUSPEND_STATE))
3049 continue;
3050
3051 base = its->base;
3052 its->ctlr_save = readl_relaxed(base + GITS_CTLR);
3053 err = its_force_quiescent(base);
3054 if (err) {
3055 pr_err("ITS@%pa: failed to quiesce: %d\n",
3056 &its->phys_base, err);
3057 writel_relaxed(its->ctlr_save, base + GITS_CTLR);
3058 goto err;
3059 }
3060
3061 its->cbaser_save = gits_read_cbaser(base + GITS_CBASER);
3062 }
3063
3064err:
3065 if (err) {
3066 list_for_each_entry_continue_reverse(its, &its_nodes, entry) {
3067 void __iomem *base;
3068
3069 if (!(its->flags & ITS_FLAGS_SAVE_SUSPEND_STATE))
3070 continue;
3071
3072 base = its->base;
3073 writel_relaxed(its->ctlr_save, base + GITS_CTLR);
3074 }
3075 }
3076 spin_unlock(&its_lock);
3077
3078 return err;
3079}
3080
3081static void its_restore_enable(void)
3082{
3083 struct its_node *its;
3084 int ret;
3085
3086 spin_lock(&its_lock);
3087 list_for_each_entry(its, &its_nodes, entry) {
3088 void __iomem *base;
3089 int i;
3090
3091 if (!(its->flags & ITS_FLAGS_SAVE_SUSPEND_STATE))
3092 continue;
3093
3094 base = its->base;
3095
3096 /*
3097 * Make sure that the ITS is disabled. If it fails to quiesce,
3098 * don't restore it since writing to CBASER or BASER<n>
3099 * registers is undefined according to the GIC v3 ITS
3100 * Specification.
3101 */
3102 ret = its_force_quiescent(base);
3103 if (ret) {
3104 pr_err("ITS@%pa: failed to quiesce on resume: %d\n",
3105 &its->phys_base, ret);
3106 continue;
3107 }
3108
3109 gits_write_cbaser(its->cbaser_save, base + GITS_CBASER);
3110
3111 /*
3112 * Writing CBASER resets CREADR to 0, so make CWRITER and
3113 * cmd_write line up with it.
3114 */
3115 its->cmd_write = its->cmd_base;
3116 gits_write_cwriter(0, base + GITS_CWRITER);
3117
3118 /* Restore GITS_BASER from the value cache. */
3119 for (i = 0; i < GITS_BASER_NR_REGS; i++) {
3120 struct its_baser *baser = &its->tables[i];
3121
3122 if (!(baser->val & GITS_BASER_VALID))
3123 continue;
3124
3125 its_write_baser(its, baser, baser->val);
3126 }
3127 writel_relaxed(its->ctlr_save, base + GITS_CTLR);
3128
3129 /*
3130 * Reinit the collection if it's stored in the ITS. This is
3131 * indicated by the col_id being less than the HCC field.
3132 * CID < HCC as specified in the GIC v3 Documentation.
3133 */
3134 if (its->collections[smp_processor_id()].col_id <
3135 GITS_TYPER_HCC(gic_read_typer(base + GITS_TYPER)))
3136 its_cpu_init_collection(its);
3137 }
3138 spin_unlock(&its_lock);
3139}
3140
3141static struct syscore_ops its_syscore_ops = {
3142 .suspend = its_save_disable,
3143 .resume = its_restore_enable,
3144};
3145
3146static int its_init_domain(struct fwnode_handle *handle, struct its_node *its)
3147{
3148 struct irq_domain *inner_domain;
3149 struct msi_domain_info *info;
3150
3151 info = kzalloc(sizeof(*info), GFP_KERNEL);
3152 if (!info)
3153 return -ENOMEM;
3154
3155 inner_domain = irq_domain_create_tree(handle, &its_domain_ops, its);
3156 if (!inner_domain) {
3157 kfree(info);
3158 return -ENOMEM;
3159 }
3160
3161 inner_domain->parent = its_parent;
3162 irq_domain_update_bus_token(inner_domain, DOMAIN_BUS_NEXUS);
3163 inner_domain->flags |= its->msi_domain_flags;
3164 info->ops = &its_msi_domain_ops;
3165 info->data = its;
3166 inner_domain->host_data = info;
3167
3168 return 0;
3169}
3170
3171static int its_init_vpe_domain(void)
3172{
3173 struct its_node *its;
3174 u32 devid;
3175 int entries;
3176
3177 if (gic_rdists->has_direct_lpi) {
3178 pr_info("ITS: Using DirectLPI for VPE invalidation\n");
3179 return 0;
3180 }
3181
3182 /* Any ITS will do, even if not v4 */
3183 its = list_first_entry(&its_nodes, struct its_node, entry);
3184
3185 entries = roundup_pow_of_two(nr_cpu_ids);
3186 vpe_proxy.vpes = kzalloc(sizeof(*vpe_proxy.vpes) * entries,
3187 GFP_KERNEL);
3188 if (!vpe_proxy.vpes) {
3189 pr_err("ITS: Can't allocate GICv4 proxy device array\n");
3190 return -ENOMEM;
3191 }
3192
3193 /* Use the last possible DevID */
3194 devid = GENMASK(its->device_ids - 1, 0);
3195 vpe_proxy.dev = its_create_device(its, devid, entries, false);
3196 if (!vpe_proxy.dev) {
3197 kfree(vpe_proxy.vpes);
3198 pr_err("ITS: Can't allocate GICv4 proxy device\n");
3199 return -ENOMEM;
3200 }
3201
3202 BUG_ON(entries > vpe_proxy.dev->nr_ites);
3203
3204 raw_spin_lock_init(&vpe_proxy.lock);
3205 vpe_proxy.next_victim = 0;
3206 pr_info("ITS: Allocated DevID %x as GICv4 proxy device (%d slots)\n",
3207 devid, vpe_proxy.dev->nr_ites);
3208
3209 return 0;
3210}
3211
3212static int __init its_compute_its_list_map(struct resource *res,
3213 void __iomem *its_base)
3214{
3215 int its_number;
3216 u32 ctlr;
3217
3218 /*
3219 * This is assumed to be done early enough that we're
3220 * guaranteed to be single-threaded, hence no
3221 * locking. Should this change, we should address
3222 * this.
3223 */
3224 its_number = find_first_zero_bit(&its_list_map, GICv4_ITS_LIST_MAX);
3225 if (its_number >= GICv4_ITS_LIST_MAX) {
3226 pr_err("ITS@%pa: No ITSList entry available!\n",
3227 &res->start);
3228 return -EINVAL;
3229 }
3230
3231 ctlr = readl_relaxed(its_base + GITS_CTLR);
3232 ctlr &= ~GITS_CTLR_ITS_NUMBER;
3233 ctlr |= its_number << GITS_CTLR_ITS_NUMBER_SHIFT;
3234 writel_relaxed(ctlr, its_base + GITS_CTLR);
3235 ctlr = readl_relaxed(its_base + GITS_CTLR);
3236 if ((ctlr & GITS_CTLR_ITS_NUMBER) != (its_number << GITS_CTLR_ITS_NUMBER_SHIFT)) {
3237 its_number = ctlr & GITS_CTLR_ITS_NUMBER;
3238 its_number >>= GITS_CTLR_ITS_NUMBER_SHIFT;
3239 }
3240
3241 if (test_and_set_bit(its_number, &its_list_map)) {
3242 pr_err("ITS@%pa: Duplicate ITSList entry %d\n",
3243 &res->start, its_number);
3244 return -EINVAL;
3245 }
3246
3247 return its_number;
3248}
3249
3250static int __init its_probe_one(struct resource *res,
3251 struct fwnode_handle *handle, int numa_node)
3252{
3253 struct its_node *its;
3254 void __iomem *its_base;
3255 u32 val, ctlr;
3256 u64 baser, tmp, typer;
3257 int err;
3258
3259 its_base = ioremap(res->start, resource_size(res));
3260 if (!its_base) {
3261 pr_warn("ITS@%pa: Unable to map ITS registers\n", &res->start);
3262 return -ENOMEM;
3263 }
3264
3265 val = readl_relaxed(its_base + GITS_PIDR2) & GIC_PIDR2_ARCH_MASK;
3266 if (val != 0x30 && val != 0x40) {
3267 pr_warn("ITS@%pa: No ITS detected, giving up\n", &res->start);
3268 err = -ENODEV;
3269 goto out_unmap;
3270 }
3271
3272 err = its_force_quiescent(its_base);
3273 if (err) {
3274 pr_warn("ITS@%pa: Failed to quiesce, giving up\n", &res->start);
3275 goto out_unmap;
3276 }
3277
3278 pr_info("ITS %pR\n", res);
3279
3280 its = kzalloc(sizeof(*its), GFP_KERNEL);
3281 if (!its) {
3282 err = -ENOMEM;
3283 goto out_unmap;
3284 }
3285
3286 raw_spin_lock_init(&its->lock);
3287 INIT_LIST_HEAD(&its->entry);
3288 INIT_LIST_HEAD(&its->its_device_list);
3289 typer = gic_read_typer(its_base + GITS_TYPER);
3290 its->base = its_base;
3291 its->phys_base = res->start;
3292 its->ite_size = GITS_TYPER_ITT_ENTRY_SIZE(typer);
3293 its->device_ids = GITS_TYPER_DEVBITS(typer);
3294 its->is_v4 = !!(typer & GITS_TYPER_VLPIS);
3295 if (its->is_v4) {
3296 if (!(typer & GITS_TYPER_VMOVP)) {
3297 err = its_compute_its_list_map(res, its_base);
3298 if (err < 0)
3299 goto out_free_its;
3300
3301 its->list_nr = err;
3302
3303 pr_info("ITS@%pa: Using ITS number %d\n",
3304 &res->start, err);
3305 } else {
3306 pr_info("ITS@%pa: Single VMOVP capable\n", &res->start);
3307 }
3308 }
3309
3310 its->numa_node = numa_node;
3311
3312 its->cmd_base = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
3313 get_order(ITS_CMD_QUEUE_SZ));
3314 if (!its->cmd_base) {
3315 err = -ENOMEM;
3316 goto out_free_its;
3317 }
3318 its->cmd_write = its->cmd_base;
3319 its->fwnode_handle = handle;
3320 its->get_msi_base = its_irq_get_msi_base;
3321 its->msi_domain_flags = IRQ_DOMAIN_FLAG_MSI_REMAP;
3322
3323 its_enable_quirks(its);
3324
3325 err = its_alloc_tables(its);
3326 if (err)
3327 goto out_free_cmd;
3328
3329 err = its_alloc_collections(its);
3330 if (err)
3331 goto out_free_tables;
3332
3333 baser = (virt_to_phys(its->cmd_base) |
3334 GITS_CBASER_RaWaWb |
3335 GITS_CBASER_InnerShareable |
3336 (ITS_CMD_QUEUE_SZ / SZ_4K - 1) |
3337 GITS_CBASER_VALID);
3338
3339 gits_write_cbaser(baser, its->base + GITS_CBASER);
3340 tmp = gits_read_cbaser(its->base + GITS_CBASER);
3341
3342 if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) {
3343 if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) {
3344 /*
3345 * The HW reports non-shareable, we must
3346 * remove the cacheability attributes as
3347 * well.
3348 */
3349 baser &= ~(GITS_CBASER_SHAREABILITY_MASK |
3350 GITS_CBASER_CACHEABILITY_MASK);
3351 baser |= GITS_CBASER_nC;
3352 gits_write_cbaser(baser, its->base + GITS_CBASER);
3353 }
3354 pr_info("ITS: using cache flushing for cmd queue\n");
3355 its->flags |= ITS_FLAGS_CMDQ_NEEDS_FLUSHING;
3356 }
3357
3358 gits_write_cwriter(0, its->base + GITS_CWRITER);
3359 ctlr = readl_relaxed(its->base + GITS_CTLR);
3360 ctlr |= GITS_CTLR_ENABLE;
3361 if (its->is_v4)
3362 ctlr |= GITS_CTLR_ImDe;
3363 writel_relaxed(ctlr, its->base + GITS_CTLR);
3364
3365 if (GITS_TYPER_HCC(typer))
3366 its->flags |= ITS_FLAGS_SAVE_SUSPEND_STATE;
3367
3368 err = its_init_domain(handle, its);
3369 if (err)
3370 goto out_free_tables;
3371
3372 spin_lock(&its_lock);
3373 list_add(&its->entry, &its_nodes);
3374 spin_unlock(&its_lock);
3375
3376 return 0;
3377
3378out_free_tables:
3379 its_free_tables(its);
3380out_free_cmd:
3381 free_pages((unsigned long)its->cmd_base, get_order(ITS_CMD_QUEUE_SZ));
3382out_free_its:
3383 kfree(its);
3384out_unmap:
3385 iounmap(its_base);
3386 pr_err("ITS@%pa: failed probing (%d)\n", &res->start, err);
3387 return err;
3388}
3389
3390static bool gic_rdists_supports_plpis(void)
3391{
3392 return !!(gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER) & GICR_TYPER_PLPIS);
3393}
3394
3395static int redist_disable_lpis(void)
3396{
3397 void __iomem *rbase = gic_data_rdist_rd_base();
3398 u64 timeout = USEC_PER_SEC;
3399 u64 val;
3400
3401 if (!gic_rdists_supports_plpis()) {
3402 pr_info("CPU%d: LPIs not supported\n", smp_processor_id());
3403 return -ENXIO;
3404 }
3405
3406 val = readl_relaxed(rbase + GICR_CTLR);
3407 if (!(val & GICR_CTLR_ENABLE_LPIS))
3408 return 0;
3409
3410 pr_warn("CPU%d: Booted with LPIs enabled, memory probably corrupted\n",
3411 smp_processor_id());
3412 add_taint(TAINT_CRAP, LOCKDEP_STILL_OK);
3413
3414 /* Disable LPIs */
3415 val &= ~GICR_CTLR_ENABLE_LPIS;
3416 writel_relaxed(val, rbase + GICR_CTLR);
3417
3418 /* Make sure any change to GICR_CTLR is observable by the GIC */
3419 dsb(sy);
3420
3421 /*
3422 * Software must observe RWP==0 after clearing GICR_CTLR.EnableLPIs
3423 * from 1 to 0 before programming GICR_PEND{PROP}BASER registers.
3424 * Error out if we time out waiting for RWP to clear.
3425 */
3426 while (readl_relaxed(rbase + GICR_CTLR) & GICR_CTLR_RWP) {
3427 if (!timeout) {
3428 pr_err("CPU%d: Timeout while disabling LPIs\n",
3429 smp_processor_id());
3430 return -ETIMEDOUT;
3431 }
3432 udelay(1);
3433 timeout--;
3434 }
3435
3436 /*
3437 * After it has been written to 1, it is IMPLEMENTATION
3438 * DEFINED whether GICR_CTLR.EnableLPI becomes RES1 or can be
3439 * cleared to 0. Error out if clearing the bit failed.
3440 */
3441 if (readl_relaxed(rbase + GICR_CTLR) & GICR_CTLR_ENABLE_LPIS) {
3442 pr_err("CPU%d: Failed to disable LPIs\n", smp_processor_id());
3443 return -EBUSY;
3444 }
3445
3446 return 0;
3447}
3448
3449int its_cpu_init(void)
3450{
3451 if (!list_empty(&its_nodes)) {
3452 int ret;
3453
3454 ret = redist_disable_lpis();
3455 if (ret)
3456 return ret;
3457
3458 its_cpu_init_lpis();
3459 its_cpu_init_collections();
3460 }
3461
3462 return 0;
3463}
3464
3465static const struct of_device_id its_device_id[] = {
3466 { .compatible = "arm,gic-v3-its", },
3467 {},
3468};
3469
3470static int __init its_of_probe(struct device_node *node)
3471{
3472 struct device_node *np;
3473 struct resource res;
3474
3475 for (np = of_find_matching_node(node, its_device_id); np;
3476 np = of_find_matching_node(np, its_device_id)) {
3477 if (!of_device_is_available(np))
3478 continue;
3479 if (!of_property_read_bool(np, "msi-controller")) {
3480 pr_warn("%pOF: no msi-controller property, ITS ignored\n",
3481 np);
3482 continue;
3483 }
3484
3485 if (of_address_to_resource(np, 0, &res)) {
3486 pr_warn("%pOF: no regs?\n", np);
3487 continue;
3488 }
3489
3490 its_probe_one(&res, &np->fwnode, of_node_to_nid(np));
3491 }
3492 return 0;
3493}
3494
3495#ifdef CONFIG_ACPI
3496
3497#define ACPI_GICV3_ITS_MEM_SIZE (SZ_128K)
3498
3499#ifdef CONFIG_ACPI_NUMA
3500struct its_srat_map {
3501 /* numa node id */
3502 u32 numa_node;
3503 /* GIC ITS ID */
3504 u32 its_id;
3505};
3506
3507static struct its_srat_map *its_srat_maps __initdata;
3508static int its_in_srat __initdata;
3509
3510static int __init acpi_get_its_numa_node(u32 its_id)
3511{
3512 int i;
3513
3514 for (i = 0; i < its_in_srat; i++) {
3515 if (its_id == its_srat_maps[i].its_id)
3516 return its_srat_maps[i].numa_node;
3517 }
3518 return NUMA_NO_NODE;
3519}
3520
3521static int __init gic_acpi_match_srat_its(struct acpi_subtable_header *header,
3522 const unsigned long end)
3523{
3524 return 0;
3525}
3526
3527static int __init gic_acpi_parse_srat_its(struct acpi_subtable_header *header,
3528 const unsigned long end)
3529{
3530 int node;
3531 struct acpi_srat_gic_its_affinity *its_affinity;
3532
3533 its_affinity = (struct acpi_srat_gic_its_affinity *)header;
3534 if (!its_affinity)
3535 return -EINVAL;
3536
3537 if (its_affinity->header.length < sizeof(*its_affinity)) {
3538 pr_err("SRAT: Invalid header length %d in ITS affinity\n",
3539 its_affinity->header.length);
3540 return -EINVAL;
3541 }
3542
3543 node = acpi_map_pxm_to_node(its_affinity->proximity_domain);
3544
3545 if (node == NUMA_NO_NODE || node >= MAX_NUMNODES) {
3546 pr_err("SRAT: Invalid NUMA node %d in ITS affinity\n", node);
3547 return 0;
3548 }
3549
3550 its_srat_maps[its_in_srat].numa_node = node;
3551 its_srat_maps[its_in_srat].its_id = its_affinity->its_id;
3552 its_in_srat++;
3553 pr_info("SRAT: PXM %d -> ITS %d -> Node %d\n",
3554 its_affinity->proximity_domain, its_affinity->its_id, node);
3555
3556 return 0;
3557}
3558
3559static void __init acpi_table_parse_srat_its(void)
3560{
3561 int count;
3562
3563 count = acpi_table_parse_entries(ACPI_SIG_SRAT,
3564 sizeof(struct acpi_table_srat),
3565 ACPI_SRAT_TYPE_GIC_ITS_AFFINITY,
3566 gic_acpi_match_srat_its, 0);
3567 if (count <= 0)
3568 return;
3569
3570 its_srat_maps = kmalloc(count * sizeof(struct its_srat_map),
3571 GFP_KERNEL);
3572 if (!its_srat_maps) {
3573 pr_warn("SRAT: Failed to allocate memory for its_srat_maps!\n");
3574 return;
3575 }
3576
3577 acpi_table_parse_entries(ACPI_SIG_SRAT,
3578 sizeof(struct acpi_table_srat),
3579 ACPI_SRAT_TYPE_GIC_ITS_AFFINITY,
3580 gic_acpi_parse_srat_its, 0);
3581}
3582
3583/* free the its_srat_maps after ITS probing */
3584static void __init acpi_its_srat_maps_free(void)
3585{
3586 kfree(its_srat_maps);
3587}
3588#else
3589static void __init acpi_table_parse_srat_its(void) { }
3590static int __init acpi_get_its_numa_node(u32 its_id) { return NUMA_NO_NODE; }
3591static void __init acpi_its_srat_maps_free(void) { }
3592#endif
3593
3594static int __init gic_acpi_parse_madt_its(struct acpi_subtable_header *header,
3595 const unsigned long end)
3596{
3597 struct acpi_madt_generic_translator *its_entry;
3598 struct fwnode_handle *dom_handle;
3599 struct resource res;
3600 int err;
3601
3602 its_entry = (struct acpi_madt_generic_translator *)header;
3603 memset(&res, 0, sizeof(res));
3604 res.start = its_entry->base_address;
3605 res.end = its_entry->base_address + ACPI_GICV3_ITS_MEM_SIZE - 1;
3606 res.flags = IORESOURCE_MEM;
3607
3608 dom_handle = irq_domain_alloc_fwnode((void *)its_entry->base_address);
3609 if (!dom_handle) {
3610 pr_err("ITS@%pa: Unable to allocate GICv3 ITS domain token\n",
3611 &res.start);
3612 return -ENOMEM;
3613 }
3614
3615 err = iort_register_domain_token(its_entry->translation_id, res.start,
3616 dom_handle);
3617 if (err) {
3618 pr_err("ITS@%pa: Unable to register GICv3 ITS domain token (ITS ID %d) to IORT\n",
3619 &res.start, its_entry->translation_id);
3620 goto dom_err;
3621 }
3622
3623 err = its_probe_one(&res, dom_handle,
3624 acpi_get_its_numa_node(its_entry->translation_id));
3625 if (!err)
3626 return 0;
3627
3628 iort_deregister_domain_token(its_entry->translation_id);
3629dom_err:
3630 irq_domain_free_fwnode(dom_handle);
3631 return err;
3632}
3633
3634static void __init its_acpi_probe(void)
3635{
3636 acpi_table_parse_srat_its();
3637 acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_TRANSLATOR,
3638 gic_acpi_parse_madt_its, 0);
3639 acpi_its_srat_maps_free();
3640}
3641#else
3642static void __init its_acpi_probe(void) { }
3643#endif
3644
3645int __init its_init(struct fwnode_handle *handle, struct rdists *rdists,
3646 struct irq_domain *parent_domain)
3647{
3648 struct device_node *of_node;
3649 struct its_node *its;
3650 bool has_v4 = false;
3651 int err;
3652
3653 its_parent = parent_domain;
3654 of_node = to_of_node(handle);
3655 if (of_node)
3656 its_of_probe(of_node);
3657 else
3658 its_acpi_probe();
3659
3660 if (list_empty(&its_nodes)) {
3661 pr_warn("ITS: No ITS available, not enabling LPIs\n");
3662 return -ENXIO;
3663 }
3664
3665 gic_rdists = rdists;
3666 err = its_alloc_lpi_tables();
3667 if (err)
3668 return err;
3669
3670 list_for_each_entry(its, &its_nodes, entry)
3671 has_v4 |= its->is_v4;
3672
3673 if (has_v4 & rdists->has_vlpis) {
3674 if (its_init_vpe_domain() ||
3675 its_init_v4(parent_domain, &its_vpe_domain_ops)) {
3676 rdists->has_vlpis = false;
3677 pr_err("ITS: Disabling GICv4 support\n");
3678 }
3679 }
3680
3681 register_syscore_ops(&its_syscore_ops);
3682
3683 return 0;
3684}