Loading...
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * rcar_lvds.c -- R-Car LVDS Encoder
4 *
5 * Copyright (C) 2013-2018 Renesas Electronics Corporation
6 *
7 * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
8 */
9
10#include <linux/clk.h>
11#include <linux/delay.h>
12#include <linux/io.h>
13#include <linux/module.h>
14#include <linux/of.h>
15#include <linux/of_device.h>
16#include <linux/of_graph.h>
17#include <linux/platform_device.h>
18#include <linux/slab.h>
19#include <linux/sys_soc.h>
20
21#include <drm/drm_atomic.h>
22#include <drm/drm_atomic_helper.h>
23#include <drm/drm_bridge.h>
24#include <drm/drm_of.h>
25#include <drm/drm_panel.h>
26#include <drm/drm_print.h>
27#include <drm/drm_probe_helper.h>
28
29#include "rcar_lvds.h"
30#include "rcar_lvds_regs.h"
31
32struct rcar_lvds;
33
34/* Keep in sync with the LVDCR0.LVMD hardware register values. */
35enum rcar_lvds_mode {
36 RCAR_LVDS_MODE_JEIDA = 0,
37 RCAR_LVDS_MODE_MIRROR = 1,
38 RCAR_LVDS_MODE_VESA = 4,
39};
40
41enum rcar_lvds_link_type {
42 RCAR_LVDS_SINGLE_LINK = 0,
43 RCAR_LVDS_DUAL_LINK_EVEN_ODD_PIXELS = 1,
44 RCAR_LVDS_DUAL_LINK_ODD_EVEN_PIXELS = 2,
45};
46
47#define RCAR_LVDS_QUIRK_LANES BIT(0) /* LVDS lanes 1 and 3 inverted */
48#define RCAR_LVDS_QUIRK_GEN3_LVEN BIT(1) /* LVEN bit needs to be set on R8A77970/R8A7799x */
49#define RCAR_LVDS_QUIRK_PWD BIT(2) /* PWD bit available (all of Gen3 but E3) */
50#define RCAR_LVDS_QUIRK_EXT_PLL BIT(3) /* Has extended PLL */
51#define RCAR_LVDS_QUIRK_DUAL_LINK BIT(4) /* Supports dual-link operation */
52
53struct rcar_lvds_device_info {
54 unsigned int gen;
55 unsigned int quirks;
56 void (*pll_setup)(struct rcar_lvds *lvds, unsigned int freq);
57};
58
59struct rcar_lvds {
60 struct device *dev;
61 const struct rcar_lvds_device_info *info;
62
63 struct drm_bridge bridge;
64
65 struct drm_bridge *next_bridge;
66 struct drm_connector connector;
67 struct drm_panel *panel;
68
69 void __iomem *mmio;
70 struct {
71 struct clk *mod; /* CPG module clock */
72 struct clk *extal; /* External clock */
73 struct clk *dotclkin[2]; /* External DU clocks */
74 } clocks;
75
76 struct drm_bridge *companion;
77 enum rcar_lvds_link_type link_type;
78};
79
80#define bridge_to_rcar_lvds(b) \
81 container_of(b, struct rcar_lvds, bridge)
82
83#define connector_to_rcar_lvds(c) \
84 container_of(c, struct rcar_lvds, connector)
85
86static void rcar_lvds_write(struct rcar_lvds *lvds, u32 reg, u32 data)
87{
88 iowrite32(data, lvds->mmio + reg);
89}
90
91/* -----------------------------------------------------------------------------
92 * Connector & Panel
93 */
94
95static int rcar_lvds_connector_get_modes(struct drm_connector *connector)
96{
97 struct rcar_lvds *lvds = connector_to_rcar_lvds(connector);
98
99 return drm_panel_get_modes(lvds->panel, connector);
100}
101
102static int rcar_lvds_connector_atomic_check(struct drm_connector *connector,
103 struct drm_atomic_state *state)
104{
105 struct rcar_lvds *lvds = connector_to_rcar_lvds(connector);
106 const struct drm_display_mode *panel_mode;
107 struct drm_connector_state *conn_state;
108 struct drm_crtc_state *crtc_state;
109
110 conn_state = drm_atomic_get_new_connector_state(state, connector);
111 if (!conn_state->crtc)
112 return 0;
113
114 if (list_empty(&connector->modes)) {
115 dev_dbg(lvds->dev, "connector: empty modes list\n");
116 return -EINVAL;
117 }
118
119 panel_mode = list_first_entry(&connector->modes,
120 struct drm_display_mode, head);
121
122 /* We're not allowed to modify the resolution. */
123 crtc_state = drm_atomic_get_crtc_state(state, conn_state->crtc);
124 if (IS_ERR(crtc_state))
125 return PTR_ERR(crtc_state);
126
127 if (crtc_state->mode.hdisplay != panel_mode->hdisplay ||
128 crtc_state->mode.vdisplay != panel_mode->vdisplay)
129 return -EINVAL;
130
131 /* The flat panel mode is fixed, just copy it to the adjusted mode. */
132 drm_mode_copy(&crtc_state->adjusted_mode, panel_mode);
133
134 return 0;
135}
136
137static const struct drm_connector_helper_funcs rcar_lvds_conn_helper_funcs = {
138 .get_modes = rcar_lvds_connector_get_modes,
139 .atomic_check = rcar_lvds_connector_atomic_check,
140};
141
142static const struct drm_connector_funcs rcar_lvds_conn_funcs = {
143 .reset = drm_atomic_helper_connector_reset,
144 .fill_modes = drm_helper_probe_single_connector_modes,
145 .destroy = drm_connector_cleanup,
146 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
147 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
148};
149
150/* -----------------------------------------------------------------------------
151 * PLL Setup
152 */
153
154static void rcar_lvds_pll_setup_gen2(struct rcar_lvds *lvds, unsigned int freq)
155{
156 u32 val;
157
158 if (freq < 39000000)
159 val = LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_38M;
160 else if (freq < 61000000)
161 val = LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_60M;
162 else if (freq < 121000000)
163 val = LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_121M;
164 else
165 val = LVDPLLCR_PLLDLYCNT_150M;
166
167 rcar_lvds_write(lvds, LVDPLLCR, val);
168}
169
170static void rcar_lvds_pll_setup_gen3(struct rcar_lvds *lvds, unsigned int freq)
171{
172 u32 val;
173
174 if (freq < 42000000)
175 val = LVDPLLCR_PLLDIVCNT_42M;
176 else if (freq < 85000000)
177 val = LVDPLLCR_PLLDIVCNT_85M;
178 else if (freq < 128000000)
179 val = LVDPLLCR_PLLDIVCNT_128M;
180 else
181 val = LVDPLLCR_PLLDIVCNT_148M;
182
183 rcar_lvds_write(lvds, LVDPLLCR, val);
184}
185
186struct pll_info {
187 unsigned long diff;
188 unsigned int pll_m;
189 unsigned int pll_n;
190 unsigned int pll_e;
191 unsigned int div;
192 u32 clksel;
193};
194
195static void rcar_lvds_d3_e3_pll_calc(struct rcar_lvds *lvds, struct clk *clk,
196 unsigned long target, struct pll_info *pll,
197 u32 clksel, bool dot_clock_only)
198{
199 unsigned int div7 = dot_clock_only ? 1 : 7;
200 unsigned long output;
201 unsigned long fin;
202 unsigned int m_min;
203 unsigned int m_max;
204 unsigned int m;
205 int error;
206
207 if (!clk)
208 return;
209
210 /*
211 * The LVDS PLL is made of a pre-divider and a multiplier (strangely
212 * enough called M and N respectively), followed by a post-divider E.
213 *
214 * ,-----. ,-----. ,-----. ,-----.
215 * Fin --> | 1/M | -Fpdf-> | PFD | --> | VCO | -Fvco-> | 1/E | --> Fout
216 * `-----' ,-> | | `-----' | `-----'
217 * | `-----' |
218 * | ,-----. |
219 * `-------- | 1/N | <-------'
220 * `-----'
221 *
222 * The clock output by the PLL is then further divided by a programmable
223 * divider DIV to achieve the desired target frequency. Finally, an
224 * optional fixed /7 divider is used to convert the bit clock to a pixel
225 * clock (as LVDS transmits 7 bits per lane per clock sample).
226 *
227 * ,-------. ,-----. |\
228 * Fout --> | 1/DIV | --> | 1/7 | --> | |
229 * `-------' | `-----' | | --> dot clock
230 * `------------> | |
231 * |/
232 *
233 * The /7 divider is optional, it is enabled when the LVDS PLL is used
234 * to drive the LVDS encoder, and disabled when used to generate a dot
235 * clock for the DU RGB output, without using the LVDS encoder.
236 *
237 * The PLL allowed input frequency range is 12 MHz to 192 MHz.
238 */
239
240 fin = clk_get_rate(clk);
241 if (fin < 12000000 || fin > 192000000)
242 return;
243
244 /*
245 * The comparison frequency range is 12 MHz to 24 MHz, which limits the
246 * allowed values for the pre-divider M (normal range 1-8).
247 *
248 * Fpfd = Fin / M
249 */
250 m_min = max_t(unsigned int, 1, DIV_ROUND_UP(fin, 24000000));
251 m_max = min_t(unsigned int, 8, fin / 12000000);
252
253 for (m = m_min; m <= m_max; ++m) {
254 unsigned long fpfd;
255 unsigned int n_min;
256 unsigned int n_max;
257 unsigned int n;
258
259 /*
260 * The VCO operating range is 900 Mhz to 1800 MHz, which limits
261 * the allowed values for the multiplier N (normal range
262 * 60-120).
263 *
264 * Fvco = Fin * N / M
265 */
266 fpfd = fin / m;
267 n_min = max_t(unsigned int, 60, DIV_ROUND_UP(900000000, fpfd));
268 n_max = min_t(unsigned int, 120, 1800000000 / fpfd);
269
270 for (n = n_min; n < n_max; ++n) {
271 unsigned long fvco;
272 unsigned int e_min;
273 unsigned int e;
274
275 /*
276 * The output frequency is limited to 1039.5 MHz,
277 * limiting again the allowed values for the
278 * post-divider E (normal value 1, 2 or 4).
279 *
280 * Fout = Fvco / E
281 */
282 fvco = fpfd * n;
283 e_min = fvco > 1039500000 ? 1 : 0;
284
285 for (e = e_min; e < 3; ++e) {
286 unsigned long fout;
287 unsigned long diff;
288 unsigned int div;
289
290 /*
291 * Finally we have a programable divider after
292 * the PLL, followed by a an optional fixed /7
293 * divider.
294 */
295 fout = fvco / (1 << e) / div7;
296 div = max(1UL, DIV_ROUND_CLOSEST(fout, target));
297 diff = abs(fout / div - target);
298
299 if (diff < pll->diff) {
300 pll->diff = diff;
301 pll->pll_m = m;
302 pll->pll_n = n;
303 pll->pll_e = e;
304 pll->div = div;
305 pll->clksel = clksel;
306
307 if (diff == 0)
308 goto done;
309 }
310 }
311 }
312 }
313
314done:
315 output = fin * pll->pll_n / pll->pll_m / (1 << pll->pll_e)
316 / div7 / pll->div;
317 error = (long)(output - target) * 10000 / (long)target;
318
319 dev_dbg(lvds->dev,
320 "%pC %lu Hz -> Fout %lu Hz (target %lu Hz, error %d.%02u%%), PLL M/N/E/DIV %u/%u/%u/%u\n",
321 clk, fin, output, target, error / 100,
322 error < 0 ? -error % 100 : error % 100,
323 pll->pll_m, pll->pll_n, pll->pll_e, pll->div);
324}
325
326static void __rcar_lvds_pll_setup_d3_e3(struct rcar_lvds *lvds,
327 unsigned int freq, bool dot_clock_only)
328{
329 struct pll_info pll = { .diff = (unsigned long)-1 };
330 u32 lvdpllcr;
331
332 rcar_lvds_d3_e3_pll_calc(lvds, lvds->clocks.dotclkin[0], freq, &pll,
333 LVDPLLCR_CKSEL_DU_DOTCLKIN(0), dot_clock_only);
334 rcar_lvds_d3_e3_pll_calc(lvds, lvds->clocks.dotclkin[1], freq, &pll,
335 LVDPLLCR_CKSEL_DU_DOTCLKIN(1), dot_clock_only);
336 rcar_lvds_d3_e3_pll_calc(lvds, lvds->clocks.extal, freq, &pll,
337 LVDPLLCR_CKSEL_EXTAL, dot_clock_only);
338
339 lvdpllcr = LVDPLLCR_PLLON | pll.clksel | LVDPLLCR_CLKOUT
340 | LVDPLLCR_PLLN(pll.pll_n - 1) | LVDPLLCR_PLLM(pll.pll_m - 1);
341
342 if (pll.pll_e > 0)
343 lvdpllcr |= LVDPLLCR_STP_CLKOUTE | LVDPLLCR_OUTCLKSEL
344 | LVDPLLCR_PLLE(pll.pll_e - 1);
345
346 if (dot_clock_only)
347 lvdpllcr |= LVDPLLCR_OCKSEL;
348
349 rcar_lvds_write(lvds, LVDPLLCR, lvdpllcr);
350
351 if (pll.div > 1)
352 /*
353 * The DIVRESET bit is a misnomer, setting it to 1 deasserts the
354 * divisor reset.
355 */
356 rcar_lvds_write(lvds, LVDDIV, LVDDIV_DIVSEL |
357 LVDDIV_DIVRESET | LVDDIV_DIV(pll.div - 1));
358 else
359 rcar_lvds_write(lvds, LVDDIV, 0);
360}
361
362static void rcar_lvds_pll_setup_d3_e3(struct rcar_lvds *lvds, unsigned int freq)
363{
364 __rcar_lvds_pll_setup_d3_e3(lvds, freq, false);
365}
366
367/* -----------------------------------------------------------------------------
368 * Clock - D3/E3 only
369 */
370
371int rcar_lvds_clk_enable(struct drm_bridge *bridge, unsigned long freq)
372{
373 struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
374 int ret;
375
376 if (WARN_ON(!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)))
377 return -ENODEV;
378
379 dev_dbg(lvds->dev, "enabling LVDS PLL, freq=%luHz\n", freq);
380
381 ret = clk_prepare_enable(lvds->clocks.mod);
382 if (ret < 0)
383 return ret;
384
385 __rcar_lvds_pll_setup_d3_e3(lvds, freq, true);
386
387 return 0;
388}
389EXPORT_SYMBOL_GPL(rcar_lvds_clk_enable);
390
391void rcar_lvds_clk_disable(struct drm_bridge *bridge)
392{
393 struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
394
395 if (WARN_ON(!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)))
396 return;
397
398 dev_dbg(lvds->dev, "disabling LVDS PLL\n");
399
400 rcar_lvds_write(lvds, LVDPLLCR, 0);
401
402 clk_disable_unprepare(lvds->clocks.mod);
403}
404EXPORT_SYMBOL_GPL(rcar_lvds_clk_disable);
405
406/* -----------------------------------------------------------------------------
407 * Bridge
408 */
409
410static enum rcar_lvds_mode rcar_lvds_get_lvds_mode(struct rcar_lvds *lvds,
411 const struct drm_connector *connector)
412{
413 const struct drm_display_info *info;
414 enum rcar_lvds_mode mode;
415
416 /*
417 * There is no API yet to retrieve LVDS mode from a bridge, only panels
418 * are supported.
419 */
420 if (!lvds->panel)
421 return RCAR_LVDS_MODE_JEIDA;
422
423 info = &connector->display_info;
424 if (!info->num_bus_formats || !info->bus_formats) {
425 dev_warn(lvds->dev,
426 "no LVDS bus format reported, using JEIDA\n");
427 return RCAR_LVDS_MODE_JEIDA;
428 }
429
430 switch (info->bus_formats[0]) {
431 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
432 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
433 mode = RCAR_LVDS_MODE_JEIDA;
434 break;
435 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
436 mode = RCAR_LVDS_MODE_VESA;
437 break;
438 default:
439 dev_warn(lvds->dev,
440 "unsupported LVDS bus format 0x%04x, using JEIDA\n",
441 info->bus_formats[0]);
442 return RCAR_LVDS_MODE_JEIDA;
443 }
444
445 if (info->bus_flags & DRM_BUS_FLAG_DATA_LSB_TO_MSB)
446 mode |= RCAR_LVDS_MODE_MIRROR;
447
448 return mode;
449}
450
451static void __rcar_lvds_atomic_enable(struct drm_bridge *bridge,
452 struct drm_atomic_state *state,
453 struct drm_crtc *crtc,
454 struct drm_connector *connector)
455{
456 struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
457 u32 lvdhcr;
458 u32 lvdcr0;
459 int ret;
460
461 ret = clk_prepare_enable(lvds->clocks.mod);
462 if (ret < 0)
463 return;
464
465 /* Enable the companion LVDS encoder in dual-link mode. */
466 if (lvds->link_type != RCAR_LVDS_SINGLE_LINK && lvds->companion)
467 __rcar_lvds_atomic_enable(lvds->companion, state, crtc,
468 connector);
469
470 /*
471 * Hardcode the channels and control signals routing for now.
472 *
473 * HSYNC -> CTRL0
474 * VSYNC -> CTRL1
475 * DISP -> CTRL2
476 * 0 -> CTRL3
477 */
478 rcar_lvds_write(lvds, LVDCTRCR, LVDCTRCR_CTR3SEL_ZERO |
479 LVDCTRCR_CTR2SEL_DISP | LVDCTRCR_CTR1SEL_VSYNC |
480 LVDCTRCR_CTR0SEL_HSYNC);
481
482 if (lvds->info->quirks & RCAR_LVDS_QUIRK_LANES)
483 lvdhcr = LVDCHCR_CHSEL_CH(0, 0) | LVDCHCR_CHSEL_CH(1, 3)
484 | LVDCHCR_CHSEL_CH(2, 2) | LVDCHCR_CHSEL_CH(3, 1);
485 else
486 lvdhcr = LVDCHCR_CHSEL_CH(0, 0) | LVDCHCR_CHSEL_CH(1, 1)
487 | LVDCHCR_CHSEL_CH(2, 2) | LVDCHCR_CHSEL_CH(3, 3);
488
489 rcar_lvds_write(lvds, LVDCHCR, lvdhcr);
490
491 if (lvds->info->quirks & RCAR_LVDS_QUIRK_DUAL_LINK) {
492 u32 lvdstripe = 0;
493
494 if (lvds->link_type != RCAR_LVDS_SINGLE_LINK) {
495 /*
496 * By default we generate even pixels from the primary
497 * encoder and odd pixels from the companion encoder.
498 * Swap pixels around if the sink requires odd pixels
499 * from the primary encoder and even pixels from the
500 * companion encoder.
501 */
502 bool swap_pixels = lvds->link_type ==
503 RCAR_LVDS_DUAL_LINK_ODD_EVEN_PIXELS;
504
505 /*
506 * Configure vertical stripe since we are dealing with
507 * an LVDS dual-link connection.
508 *
509 * ST_SWAP is reserved for the companion encoder, only
510 * set it in the primary encoder.
511 */
512 lvdstripe = LVDSTRIPE_ST_ON
513 | (lvds->companion && swap_pixels ?
514 LVDSTRIPE_ST_SWAP : 0);
515 }
516 rcar_lvds_write(lvds, LVDSTRIPE, lvdstripe);
517 }
518
519 /*
520 * PLL clock configuration on all instances but the companion in
521 * dual-link mode.
522 */
523 if (lvds->link_type == RCAR_LVDS_SINGLE_LINK || lvds->companion) {
524 const struct drm_crtc_state *crtc_state =
525 drm_atomic_get_new_crtc_state(state, crtc);
526 const struct drm_display_mode *mode =
527 &crtc_state->adjusted_mode;
528
529 lvds->info->pll_setup(lvds, mode->clock * 1000);
530 }
531
532 /* Set the LVDS mode and select the input. */
533 lvdcr0 = rcar_lvds_get_lvds_mode(lvds, connector) << LVDCR0_LVMD_SHIFT;
534
535 if (lvds->bridge.encoder) {
536 if (drm_crtc_index(crtc) == 2)
537 lvdcr0 |= LVDCR0_DUSEL;
538 }
539
540 rcar_lvds_write(lvds, LVDCR0, lvdcr0);
541
542 /* Turn all the channels on. */
543 rcar_lvds_write(lvds, LVDCR1,
544 LVDCR1_CHSTBY(3) | LVDCR1_CHSTBY(2) |
545 LVDCR1_CHSTBY(1) | LVDCR1_CHSTBY(0) | LVDCR1_CLKSTBY);
546
547 if (lvds->info->gen < 3) {
548 /* Enable LVDS operation and turn the bias circuitry on. */
549 lvdcr0 |= LVDCR0_BEN | LVDCR0_LVEN;
550 rcar_lvds_write(lvds, LVDCR0, lvdcr0);
551 }
552
553 if (!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)) {
554 /*
555 * Turn the PLL on (simple PLL only, extended PLL is fully
556 * controlled through LVDPLLCR).
557 */
558 lvdcr0 |= LVDCR0_PLLON;
559 rcar_lvds_write(lvds, LVDCR0, lvdcr0);
560 }
561
562 if (lvds->info->quirks & RCAR_LVDS_QUIRK_PWD) {
563 /* Set LVDS normal mode. */
564 lvdcr0 |= LVDCR0_PWD;
565 rcar_lvds_write(lvds, LVDCR0, lvdcr0);
566 }
567
568 if (lvds->info->quirks & RCAR_LVDS_QUIRK_GEN3_LVEN) {
569 /*
570 * Turn on the LVDS PHY. On D3, the LVEN and LVRES bit must be
571 * set at the same time, so don't write the register yet.
572 */
573 lvdcr0 |= LVDCR0_LVEN;
574 if (!(lvds->info->quirks & RCAR_LVDS_QUIRK_PWD))
575 rcar_lvds_write(lvds, LVDCR0, lvdcr0);
576 }
577
578 if (!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)) {
579 /* Wait for the PLL startup delay (simple PLL only). */
580 usleep_range(100, 150);
581 }
582
583 /* Turn the output on. */
584 lvdcr0 |= LVDCR0_LVRES;
585 rcar_lvds_write(lvds, LVDCR0, lvdcr0);
586
587 if (lvds->panel) {
588 drm_panel_prepare(lvds->panel);
589 drm_panel_enable(lvds->panel);
590 }
591}
592
593static void rcar_lvds_atomic_enable(struct drm_bridge *bridge,
594 struct drm_bridge_state *old_bridge_state)
595{
596 struct drm_atomic_state *state = old_bridge_state->base.state;
597 struct drm_connector *connector;
598 struct drm_crtc *crtc;
599
600 connector = drm_atomic_get_new_connector_for_encoder(state,
601 bridge->encoder);
602 crtc = drm_atomic_get_new_connector_state(state, connector)->crtc;
603
604 __rcar_lvds_atomic_enable(bridge, state, crtc, connector);
605}
606
607static void rcar_lvds_atomic_disable(struct drm_bridge *bridge,
608 struct drm_bridge_state *old_bridge_state)
609{
610 struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
611
612 if (lvds->panel) {
613 drm_panel_disable(lvds->panel);
614 drm_panel_unprepare(lvds->panel);
615 }
616
617 rcar_lvds_write(lvds, LVDCR0, 0);
618 rcar_lvds_write(lvds, LVDCR1, 0);
619 rcar_lvds_write(lvds, LVDPLLCR, 0);
620
621 /* Disable the companion LVDS encoder in dual-link mode. */
622 if (lvds->link_type != RCAR_LVDS_SINGLE_LINK && lvds->companion)
623 lvds->companion->funcs->atomic_disable(lvds->companion,
624 old_bridge_state);
625
626 clk_disable_unprepare(lvds->clocks.mod);
627}
628
629static bool rcar_lvds_mode_fixup(struct drm_bridge *bridge,
630 const struct drm_display_mode *mode,
631 struct drm_display_mode *adjusted_mode)
632{
633 struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
634 int min_freq;
635
636 /*
637 * The internal LVDS encoder has a restricted clock frequency operating
638 * range, from 5MHz to 148.5MHz on D3 and E3, and from 31MHz to
639 * 148.5MHz on all other platforms. Clamp the clock accordingly.
640 */
641 min_freq = lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL ? 5000 : 31000;
642 adjusted_mode->clock = clamp(adjusted_mode->clock, min_freq, 148500);
643
644 return true;
645}
646
647static int rcar_lvds_attach(struct drm_bridge *bridge,
648 enum drm_bridge_attach_flags flags)
649{
650 struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
651 struct drm_connector *connector = &lvds->connector;
652 struct drm_encoder *encoder = bridge->encoder;
653 int ret;
654
655 /* If we have a next bridge just attach it. */
656 if (lvds->next_bridge)
657 return drm_bridge_attach(bridge->encoder, lvds->next_bridge,
658 bridge, flags);
659
660 if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) {
661 DRM_ERROR("Fix bridge driver to make connector optional!");
662 return -EINVAL;
663 }
664
665 /* Otherwise if we have a panel, create a connector. */
666 if (!lvds->panel)
667 return 0;
668
669 ret = drm_connector_init(bridge->dev, connector, &rcar_lvds_conn_funcs,
670 DRM_MODE_CONNECTOR_LVDS);
671 if (ret < 0)
672 return ret;
673
674 drm_connector_helper_add(connector, &rcar_lvds_conn_helper_funcs);
675
676 ret = drm_connector_attach_encoder(connector, encoder);
677 if (ret < 0)
678 return ret;
679
680 return drm_panel_attach(lvds->panel, connector);
681}
682
683static void rcar_lvds_detach(struct drm_bridge *bridge)
684{
685 struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
686
687 if (lvds->panel)
688 drm_panel_detach(lvds->panel);
689}
690
691static const struct drm_bridge_funcs rcar_lvds_bridge_ops = {
692 .attach = rcar_lvds_attach,
693 .detach = rcar_lvds_detach,
694 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
695 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
696 .atomic_reset = drm_atomic_helper_bridge_reset,
697 .atomic_enable = rcar_lvds_atomic_enable,
698 .atomic_disable = rcar_lvds_atomic_disable,
699 .mode_fixup = rcar_lvds_mode_fixup,
700};
701
702bool rcar_lvds_dual_link(struct drm_bridge *bridge)
703{
704 struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
705
706 return lvds->link_type != RCAR_LVDS_SINGLE_LINK;
707}
708EXPORT_SYMBOL_GPL(rcar_lvds_dual_link);
709
710/* -----------------------------------------------------------------------------
711 * Probe & Remove
712 */
713
714static int rcar_lvds_parse_dt_companion(struct rcar_lvds *lvds)
715{
716 const struct of_device_id *match;
717 struct device_node *companion;
718 struct device_node *port0, *port1;
719 struct rcar_lvds *companion_lvds;
720 struct device *dev = lvds->dev;
721 int dual_link;
722 int ret = 0;
723
724 /* Locate the companion LVDS encoder for dual-link operation, if any. */
725 companion = of_parse_phandle(dev->of_node, "renesas,companion", 0);
726 if (!companion)
727 return 0;
728
729 /*
730 * Sanity check: the companion encoder must have the same compatible
731 * string.
732 */
733 match = of_match_device(dev->driver->of_match_table, dev);
734 if (!of_device_is_compatible(companion, match->compatible)) {
735 dev_err(dev, "Companion LVDS encoder is invalid\n");
736 ret = -ENXIO;
737 goto done;
738 }
739
740 /*
741 * We need to work out if the sink is expecting us to function in
742 * dual-link mode. We do this by looking at the DT port nodes we are
743 * connected to, if they are marked as expecting even pixels and
744 * odd pixels than we need to enable vertical stripe output.
745 */
746 port0 = of_graph_get_port_by_id(dev->of_node, 1);
747 port1 = of_graph_get_port_by_id(companion, 1);
748 dual_link = drm_of_lvds_get_dual_link_pixel_order(port0, port1);
749 of_node_put(port0);
750 of_node_put(port1);
751
752 switch (dual_link) {
753 case DRM_LVDS_DUAL_LINK_ODD_EVEN_PIXELS:
754 lvds->link_type = RCAR_LVDS_DUAL_LINK_ODD_EVEN_PIXELS;
755 break;
756 case DRM_LVDS_DUAL_LINK_EVEN_ODD_PIXELS:
757 lvds->link_type = RCAR_LVDS_DUAL_LINK_EVEN_ODD_PIXELS;
758 break;
759 default:
760 /*
761 * Early dual-link bridge specific implementations populate the
762 * timings field of drm_bridge. If the flag is set, we assume
763 * that we are expected to generate even pixels from the primary
764 * encoder, and odd pixels from the companion encoder.
765 */
766 if (lvds->next_bridge && lvds->next_bridge->timings &&
767 lvds->next_bridge->timings->dual_link)
768 lvds->link_type = RCAR_LVDS_DUAL_LINK_EVEN_ODD_PIXELS;
769 else
770 lvds->link_type = RCAR_LVDS_SINGLE_LINK;
771 }
772
773 if (lvds->link_type == RCAR_LVDS_SINGLE_LINK) {
774 dev_dbg(dev, "Single-link configuration detected\n");
775 goto done;
776 }
777
778 lvds->companion = of_drm_find_bridge(companion);
779 if (!lvds->companion) {
780 ret = -EPROBE_DEFER;
781 goto done;
782 }
783
784 dev_dbg(dev,
785 "Dual-link configuration detected (companion encoder %pOF)\n",
786 companion);
787
788 if (lvds->link_type == RCAR_LVDS_DUAL_LINK_ODD_EVEN_PIXELS)
789 dev_dbg(dev, "Data swapping required\n");
790
791 /*
792 * FIXME: We should not be messing with the companion encoder private
793 * data from the primary encoder, we should rather let the companion
794 * encoder work things out on its own. However, the companion encoder
795 * doesn't hold a reference to the primary encoder, and
796 * drm_of_lvds_get_dual_link_pixel_order needs to be given references
797 * to the output ports of both encoders, therefore leave it like this
798 * for the time being.
799 */
800 companion_lvds = bridge_to_rcar_lvds(lvds->companion);
801 companion_lvds->link_type = lvds->link_type;
802
803done:
804 of_node_put(companion);
805
806 return ret;
807}
808
809static int rcar_lvds_parse_dt(struct rcar_lvds *lvds)
810{
811 int ret;
812
813 ret = drm_of_find_panel_or_bridge(lvds->dev->of_node, 1, 0,
814 &lvds->panel, &lvds->next_bridge);
815 if (ret)
816 goto done;
817
818 if (lvds->info->quirks & RCAR_LVDS_QUIRK_DUAL_LINK)
819 ret = rcar_lvds_parse_dt_companion(lvds);
820
821done:
822 /*
823 * On D3/E3 the LVDS encoder provides a clock to the DU, which can be
824 * used for the DPAD output even when the LVDS output is not connected.
825 * Don't fail probe in that case as the DU will need the bridge to
826 * control the clock.
827 */
828 if (lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)
829 return ret == -ENODEV ? 0 : ret;
830
831 return ret;
832}
833
834static struct clk *rcar_lvds_get_clock(struct rcar_lvds *lvds, const char *name,
835 bool optional)
836{
837 struct clk *clk;
838
839 clk = devm_clk_get(lvds->dev, name);
840 if (!IS_ERR(clk))
841 return clk;
842
843 if (PTR_ERR(clk) == -ENOENT && optional)
844 return NULL;
845
846 if (PTR_ERR(clk) != -EPROBE_DEFER)
847 dev_err(lvds->dev, "failed to get %s clock\n",
848 name ? name : "module");
849
850 return clk;
851}
852
853static int rcar_lvds_get_clocks(struct rcar_lvds *lvds)
854{
855 lvds->clocks.mod = rcar_lvds_get_clock(lvds, NULL, false);
856 if (IS_ERR(lvds->clocks.mod))
857 return PTR_ERR(lvds->clocks.mod);
858
859 /*
860 * LVDS encoders without an extended PLL have no external clock inputs.
861 */
862 if (!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL))
863 return 0;
864
865 lvds->clocks.extal = rcar_lvds_get_clock(lvds, "extal", true);
866 if (IS_ERR(lvds->clocks.extal))
867 return PTR_ERR(lvds->clocks.extal);
868
869 lvds->clocks.dotclkin[0] = rcar_lvds_get_clock(lvds, "dclkin.0", true);
870 if (IS_ERR(lvds->clocks.dotclkin[0]))
871 return PTR_ERR(lvds->clocks.dotclkin[0]);
872
873 lvds->clocks.dotclkin[1] = rcar_lvds_get_clock(lvds, "dclkin.1", true);
874 if (IS_ERR(lvds->clocks.dotclkin[1]))
875 return PTR_ERR(lvds->clocks.dotclkin[1]);
876
877 /* At least one input to the PLL must be available. */
878 if (!lvds->clocks.extal && !lvds->clocks.dotclkin[0] &&
879 !lvds->clocks.dotclkin[1]) {
880 dev_err(lvds->dev,
881 "no input clock (extal, dclkin.0 or dclkin.1)\n");
882 return -EINVAL;
883 }
884
885 return 0;
886}
887
888static const struct rcar_lvds_device_info rcar_lvds_r8a7790es1_info = {
889 .gen = 2,
890 .quirks = RCAR_LVDS_QUIRK_LANES,
891 .pll_setup = rcar_lvds_pll_setup_gen2,
892};
893
894static const struct soc_device_attribute lvds_quirk_matches[] = {
895 {
896 .soc_id = "r8a7790", .revision = "ES1.*",
897 .data = &rcar_lvds_r8a7790es1_info,
898 },
899 { /* sentinel */ }
900};
901
902static int rcar_lvds_probe(struct platform_device *pdev)
903{
904 const struct soc_device_attribute *attr;
905 struct rcar_lvds *lvds;
906 struct resource *mem;
907 int ret;
908
909 lvds = devm_kzalloc(&pdev->dev, sizeof(*lvds), GFP_KERNEL);
910 if (lvds == NULL)
911 return -ENOMEM;
912
913 platform_set_drvdata(pdev, lvds);
914
915 lvds->dev = &pdev->dev;
916 lvds->info = of_device_get_match_data(&pdev->dev);
917
918 attr = soc_device_match(lvds_quirk_matches);
919 if (attr)
920 lvds->info = attr->data;
921
922 ret = rcar_lvds_parse_dt(lvds);
923 if (ret < 0)
924 return ret;
925
926 lvds->bridge.driver_private = lvds;
927 lvds->bridge.funcs = &rcar_lvds_bridge_ops;
928 lvds->bridge.of_node = pdev->dev.of_node;
929
930 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
931 lvds->mmio = devm_ioremap_resource(&pdev->dev, mem);
932 if (IS_ERR(lvds->mmio))
933 return PTR_ERR(lvds->mmio);
934
935 ret = rcar_lvds_get_clocks(lvds);
936 if (ret < 0)
937 return ret;
938
939 drm_bridge_add(&lvds->bridge);
940
941 return 0;
942}
943
944static int rcar_lvds_remove(struct platform_device *pdev)
945{
946 struct rcar_lvds *lvds = platform_get_drvdata(pdev);
947
948 drm_bridge_remove(&lvds->bridge);
949
950 return 0;
951}
952
953static const struct rcar_lvds_device_info rcar_lvds_gen2_info = {
954 .gen = 2,
955 .pll_setup = rcar_lvds_pll_setup_gen2,
956};
957
958static const struct rcar_lvds_device_info rcar_lvds_gen3_info = {
959 .gen = 3,
960 .quirks = RCAR_LVDS_QUIRK_PWD,
961 .pll_setup = rcar_lvds_pll_setup_gen3,
962};
963
964static const struct rcar_lvds_device_info rcar_lvds_r8a77970_info = {
965 .gen = 3,
966 .quirks = RCAR_LVDS_QUIRK_PWD | RCAR_LVDS_QUIRK_GEN3_LVEN,
967 .pll_setup = rcar_lvds_pll_setup_gen2,
968};
969
970static const struct rcar_lvds_device_info rcar_lvds_r8a77990_info = {
971 .gen = 3,
972 .quirks = RCAR_LVDS_QUIRK_GEN3_LVEN | RCAR_LVDS_QUIRK_EXT_PLL
973 | RCAR_LVDS_QUIRK_DUAL_LINK,
974 .pll_setup = rcar_lvds_pll_setup_d3_e3,
975};
976
977static const struct rcar_lvds_device_info rcar_lvds_r8a77995_info = {
978 .gen = 3,
979 .quirks = RCAR_LVDS_QUIRK_GEN3_LVEN | RCAR_LVDS_QUIRK_PWD
980 | RCAR_LVDS_QUIRK_EXT_PLL | RCAR_LVDS_QUIRK_DUAL_LINK,
981 .pll_setup = rcar_lvds_pll_setup_d3_e3,
982};
983
984static const struct of_device_id rcar_lvds_of_table[] = {
985 { .compatible = "renesas,r8a7743-lvds", .data = &rcar_lvds_gen2_info },
986 { .compatible = "renesas,r8a7744-lvds", .data = &rcar_lvds_gen2_info },
987 { .compatible = "renesas,r8a774a1-lvds", .data = &rcar_lvds_gen3_info },
988 { .compatible = "renesas,r8a774b1-lvds", .data = &rcar_lvds_gen3_info },
989 { .compatible = "renesas,r8a774c0-lvds", .data = &rcar_lvds_r8a77990_info },
990 { .compatible = "renesas,r8a7790-lvds", .data = &rcar_lvds_gen2_info },
991 { .compatible = "renesas,r8a7791-lvds", .data = &rcar_lvds_gen2_info },
992 { .compatible = "renesas,r8a7793-lvds", .data = &rcar_lvds_gen2_info },
993 { .compatible = "renesas,r8a7795-lvds", .data = &rcar_lvds_gen3_info },
994 { .compatible = "renesas,r8a7796-lvds", .data = &rcar_lvds_gen3_info },
995 { .compatible = "renesas,r8a77965-lvds", .data = &rcar_lvds_gen3_info },
996 { .compatible = "renesas,r8a77970-lvds", .data = &rcar_lvds_r8a77970_info },
997 { .compatible = "renesas,r8a77980-lvds", .data = &rcar_lvds_gen3_info },
998 { .compatible = "renesas,r8a77990-lvds", .data = &rcar_lvds_r8a77990_info },
999 { .compatible = "renesas,r8a77995-lvds", .data = &rcar_lvds_r8a77995_info },
1000 { }
1001};
1002
1003MODULE_DEVICE_TABLE(of, rcar_lvds_of_table);
1004
1005static struct platform_driver rcar_lvds_platform_driver = {
1006 .probe = rcar_lvds_probe,
1007 .remove = rcar_lvds_remove,
1008 .driver = {
1009 .name = "rcar-lvds",
1010 .of_match_table = rcar_lvds_of_table,
1011 },
1012};
1013
1014module_platform_driver(rcar_lvds_platform_driver);
1015
1016MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>");
1017MODULE_DESCRIPTION("Renesas R-Car LVDS Encoder Driver");
1018MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * rcar_lvds.c -- R-Car LVDS Encoder
4 *
5 * Copyright (C) 2013-2018 Renesas Electronics Corporation
6 *
7 * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
8 */
9
10#include <linux/clk.h>
11#include <linux/delay.h>
12#include <linux/io.h>
13#include <linux/of.h>
14#include <linux/of_device.h>
15#include <linux/of_graph.h>
16#include <linux/platform_device.h>
17#include <linux/slab.h>
18
19#include <drm/drm_atomic.h>
20#include <drm/drm_atomic_helper.h>
21#include <drm/drm_bridge.h>
22#include <drm/drm_crtc_helper.h>
23#include <drm/drm_panel.h>
24
25#include "rcar_lvds_regs.h"
26
27/* Keep in sync with the LVDCR0.LVMD hardware register values. */
28enum rcar_lvds_mode {
29 RCAR_LVDS_MODE_JEIDA = 0,
30 RCAR_LVDS_MODE_MIRROR = 1,
31 RCAR_LVDS_MODE_VESA = 4,
32};
33
34#define RCAR_LVDS_QUIRK_LANES (1 << 0) /* LVDS lanes 1 and 3 inverted */
35#define RCAR_LVDS_QUIRK_GEN2_PLLCR (1 << 1) /* LVDPLLCR has gen2 layout */
36#define RCAR_LVDS_QUIRK_GEN3_LVEN (1 << 2) /* LVEN bit needs to be set */
37 /* on R8A77970/R8A7799x */
38
39struct rcar_lvds_device_info {
40 unsigned int gen;
41 unsigned int quirks;
42};
43
44struct rcar_lvds {
45 struct device *dev;
46 const struct rcar_lvds_device_info *info;
47
48 struct drm_bridge bridge;
49
50 struct drm_bridge *next_bridge;
51 struct drm_connector connector;
52 struct drm_panel *panel;
53
54 void __iomem *mmio;
55 struct clk *clock;
56 bool enabled;
57
58 struct drm_display_mode display_mode;
59 enum rcar_lvds_mode mode;
60};
61
62#define bridge_to_rcar_lvds(bridge) \
63 container_of(bridge, struct rcar_lvds, bridge)
64
65#define connector_to_rcar_lvds(connector) \
66 container_of(connector, struct rcar_lvds, connector)
67
68static void rcar_lvds_write(struct rcar_lvds *lvds, u32 reg, u32 data)
69{
70 iowrite32(data, lvds->mmio + reg);
71}
72
73/* -----------------------------------------------------------------------------
74 * Connector & Panel
75 */
76
77static int rcar_lvds_connector_get_modes(struct drm_connector *connector)
78{
79 struct rcar_lvds *lvds = connector_to_rcar_lvds(connector);
80
81 return drm_panel_get_modes(lvds->panel);
82}
83
84static int rcar_lvds_connector_atomic_check(struct drm_connector *connector,
85 struct drm_connector_state *state)
86{
87 struct rcar_lvds *lvds = connector_to_rcar_lvds(connector);
88 const struct drm_display_mode *panel_mode;
89 struct drm_crtc_state *crtc_state;
90
91 if (!state->crtc)
92 return 0;
93
94 if (list_empty(&connector->modes)) {
95 dev_dbg(lvds->dev, "connector: empty modes list\n");
96 return -EINVAL;
97 }
98
99 panel_mode = list_first_entry(&connector->modes,
100 struct drm_display_mode, head);
101
102 /* We're not allowed to modify the resolution. */
103 crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc);
104 if (IS_ERR(crtc_state))
105 return PTR_ERR(crtc_state);
106
107 if (crtc_state->mode.hdisplay != panel_mode->hdisplay ||
108 crtc_state->mode.vdisplay != panel_mode->vdisplay)
109 return -EINVAL;
110
111 /* The flat panel mode is fixed, just copy it to the adjusted mode. */
112 drm_mode_copy(&crtc_state->adjusted_mode, panel_mode);
113
114 return 0;
115}
116
117static const struct drm_connector_helper_funcs rcar_lvds_conn_helper_funcs = {
118 .get_modes = rcar_lvds_connector_get_modes,
119 .atomic_check = rcar_lvds_connector_atomic_check,
120};
121
122static const struct drm_connector_funcs rcar_lvds_conn_funcs = {
123 .reset = drm_atomic_helper_connector_reset,
124 .fill_modes = drm_helper_probe_single_connector_modes,
125 .destroy = drm_connector_cleanup,
126 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
127 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
128};
129
130/* -----------------------------------------------------------------------------
131 * Bridge
132 */
133
134static u32 rcar_lvds_lvdpllcr_gen2(unsigned int freq)
135{
136 if (freq < 39000)
137 return LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_38M;
138 else if (freq < 61000)
139 return LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_60M;
140 else if (freq < 121000)
141 return LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_121M;
142 else
143 return LVDPLLCR_PLLDLYCNT_150M;
144}
145
146static u32 rcar_lvds_lvdpllcr_gen3(unsigned int freq)
147{
148 if (freq < 42000)
149 return LVDPLLCR_PLLDIVCNT_42M;
150 else if (freq < 85000)
151 return LVDPLLCR_PLLDIVCNT_85M;
152 else if (freq < 128000)
153 return LVDPLLCR_PLLDIVCNT_128M;
154 else
155 return LVDPLLCR_PLLDIVCNT_148M;
156}
157
158static void rcar_lvds_enable(struct drm_bridge *bridge)
159{
160 struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
161 const struct drm_display_mode *mode = &lvds->display_mode;
162 /*
163 * FIXME: We should really retrieve the CRTC through the state, but how
164 * do we get a state pointer?
165 */
166 struct drm_crtc *crtc = lvds->bridge.encoder->crtc;
167 u32 lvdpllcr;
168 u32 lvdhcr;
169 u32 lvdcr0;
170 int ret;
171
172 WARN_ON(lvds->enabled);
173
174 ret = clk_prepare_enable(lvds->clock);
175 if (ret < 0)
176 return;
177
178 /*
179 * Hardcode the channels and control signals routing for now.
180 *
181 * HSYNC -> CTRL0
182 * VSYNC -> CTRL1
183 * DISP -> CTRL2
184 * 0 -> CTRL3
185 */
186 rcar_lvds_write(lvds, LVDCTRCR, LVDCTRCR_CTR3SEL_ZERO |
187 LVDCTRCR_CTR2SEL_DISP | LVDCTRCR_CTR1SEL_VSYNC |
188 LVDCTRCR_CTR0SEL_HSYNC);
189
190 if (lvds->info->quirks & RCAR_LVDS_QUIRK_LANES)
191 lvdhcr = LVDCHCR_CHSEL_CH(0, 0) | LVDCHCR_CHSEL_CH(1, 3)
192 | LVDCHCR_CHSEL_CH(2, 2) | LVDCHCR_CHSEL_CH(3, 1);
193 else
194 lvdhcr = LVDCHCR_CHSEL_CH(0, 0) | LVDCHCR_CHSEL_CH(1, 1)
195 | LVDCHCR_CHSEL_CH(2, 2) | LVDCHCR_CHSEL_CH(3, 3);
196
197 rcar_lvds_write(lvds, LVDCHCR, lvdhcr);
198
199 /* PLL clock configuration. */
200 if (lvds->info->quirks & RCAR_LVDS_QUIRK_GEN2_PLLCR)
201 lvdpllcr = rcar_lvds_lvdpllcr_gen2(mode->clock);
202 else
203 lvdpllcr = rcar_lvds_lvdpllcr_gen3(mode->clock);
204 rcar_lvds_write(lvds, LVDPLLCR, lvdpllcr);
205
206 /* Set the LVDS mode and select the input. */
207 lvdcr0 = lvds->mode << LVDCR0_LVMD_SHIFT;
208 if (drm_crtc_index(crtc) == 2)
209 lvdcr0 |= LVDCR0_DUSEL;
210 rcar_lvds_write(lvds, LVDCR0, lvdcr0);
211
212 /* Turn all the channels on. */
213 rcar_lvds_write(lvds, LVDCR1,
214 LVDCR1_CHSTBY(3) | LVDCR1_CHSTBY(2) |
215 LVDCR1_CHSTBY(1) | LVDCR1_CHSTBY(0) | LVDCR1_CLKSTBY);
216
217 if (lvds->info->gen < 3) {
218 /* Enable LVDS operation and turn the bias circuitry on. */
219 lvdcr0 |= LVDCR0_BEN | LVDCR0_LVEN;
220 rcar_lvds_write(lvds, LVDCR0, lvdcr0);
221 }
222
223 /* Turn the PLL on. */
224 lvdcr0 |= LVDCR0_PLLON;
225 rcar_lvds_write(lvds, LVDCR0, lvdcr0);
226
227 if (lvds->info->gen > 2) {
228 /* Set LVDS normal mode. */
229 lvdcr0 |= LVDCR0_PWD;
230 rcar_lvds_write(lvds, LVDCR0, lvdcr0);
231 }
232
233 if (lvds->info->quirks & RCAR_LVDS_QUIRK_GEN3_LVEN) {
234 /* Turn on the LVDS PHY. */
235 lvdcr0 |= LVDCR0_LVEN;
236 rcar_lvds_write(lvds, LVDCR0, lvdcr0);
237 }
238
239 /* Wait for the startup delay. */
240 usleep_range(100, 150);
241
242 /* Turn the output on. */
243 lvdcr0 |= LVDCR0_LVRES;
244 rcar_lvds_write(lvds, LVDCR0, lvdcr0);
245
246 if (lvds->panel) {
247 drm_panel_prepare(lvds->panel);
248 drm_panel_enable(lvds->panel);
249 }
250
251 lvds->enabled = true;
252}
253
254static void rcar_lvds_disable(struct drm_bridge *bridge)
255{
256 struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
257
258 WARN_ON(!lvds->enabled);
259
260 if (lvds->panel) {
261 drm_panel_disable(lvds->panel);
262 drm_panel_unprepare(lvds->panel);
263 }
264
265 rcar_lvds_write(lvds, LVDCR0, 0);
266 rcar_lvds_write(lvds, LVDCR1, 0);
267
268 clk_disable_unprepare(lvds->clock);
269
270 lvds->enabled = false;
271}
272
273static bool rcar_lvds_mode_fixup(struct drm_bridge *bridge,
274 const struct drm_display_mode *mode,
275 struct drm_display_mode *adjusted_mode)
276{
277 /*
278 * The internal LVDS encoder has a restricted clock frequency operating
279 * range (31MHz to 148.5MHz). Clamp the clock accordingly.
280 */
281 adjusted_mode->clock = clamp(adjusted_mode->clock, 31000, 148500);
282
283 return true;
284}
285
286static void rcar_lvds_get_lvds_mode(struct rcar_lvds *lvds)
287{
288 struct drm_display_info *info = &lvds->connector.display_info;
289 enum rcar_lvds_mode mode;
290
291 /*
292 * There is no API yet to retrieve LVDS mode from a bridge, only panels
293 * are supported.
294 */
295 if (!lvds->panel)
296 return;
297
298 if (!info->num_bus_formats || !info->bus_formats) {
299 dev_err(lvds->dev, "no LVDS bus format reported\n");
300 return;
301 }
302
303 switch (info->bus_formats[0]) {
304 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
305 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
306 mode = RCAR_LVDS_MODE_JEIDA;
307 break;
308 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
309 mode = RCAR_LVDS_MODE_VESA;
310 break;
311 default:
312 dev_err(lvds->dev, "unsupported LVDS bus format 0x%04x\n",
313 info->bus_formats[0]);
314 return;
315 }
316
317 if (info->bus_flags & DRM_BUS_FLAG_DATA_LSB_TO_MSB)
318 mode |= RCAR_LVDS_MODE_MIRROR;
319
320 lvds->mode = mode;
321}
322
323static void rcar_lvds_mode_set(struct drm_bridge *bridge,
324 struct drm_display_mode *mode,
325 struct drm_display_mode *adjusted_mode)
326{
327 struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
328
329 WARN_ON(lvds->enabled);
330
331 lvds->display_mode = *adjusted_mode;
332
333 rcar_lvds_get_lvds_mode(lvds);
334}
335
336static int rcar_lvds_attach(struct drm_bridge *bridge)
337{
338 struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
339 struct drm_connector *connector = &lvds->connector;
340 struct drm_encoder *encoder = bridge->encoder;
341 int ret;
342
343 /* If we have a next bridge just attach it. */
344 if (lvds->next_bridge)
345 return drm_bridge_attach(bridge->encoder, lvds->next_bridge,
346 bridge);
347
348 /* Otherwise we have a panel, create a connector. */
349 ret = drm_connector_init(bridge->dev, connector, &rcar_lvds_conn_funcs,
350 DRM_MODE_CONNECTOR_LVDS);
351 if (ret < 0)
352 return ret;
353
354 drm_connector_helper_add(connector, &rcar_lvds_conn_helper_funcs);
355
356 ret = drm_mode_connector_attach_encoder(connector, encoder);
357 if (ret < 0)
358 return ret;
359
360 return drm_panel_attach(lvds->panel, connector);
361}
362
363static void rcar_lvds_detach(struct drm_bridge *bridge)
364{
365 struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
366
367 if (lvds->panel)
368 drm_panel_detach(lvds->panel);
369}
370
371static const struct drm_bridge_funcs rcar_lvds_bridge_ops = {
372 .attach = rcar_lvds_attach,
373 .detach = rcar_lvds_detach,
374 .enable = rcar_lvds_enable,
375 .disable = rcar_lvds_disable,
376 .mode_fixup = rcar_lvds_mode_fixup,
377 .mode_set = rcar_lvds_mode_set,
378};
379
380/* -----------------------------------------------------------------------------
381 * Probe & Remove
382 */
383
384static int rcar_lvds_parse_dt(struct rcar_lvds *lvds)
385{
386 struct device_node *local_output = NULL;
387 struct device_node *remote_input = NULL;
388 struct device_node *remote = NULL;
389 struct device_node *node;
390 bool is_bridge = false;
391 int ret = 0;
392
393 local_output = of_graph_get_endpoint_by_regs(lvds->dev->of_node, 1, 0);
394 if (!local_output) {
395 dev_dbg(lvds->dev, "unconnected port@1\n");
396 return -ENODEV;
397 }
398
399 /*
400 * Locate the connected entity and infer its type from the number of
401 * endpoints.
402 */
403 remote = of_graph_get_remote_port_parent(local_output);
404 if (!remote) {
405 dev_dbg(lvds->dev, "unconnected endpoint %pOF\n", local_output);
406 ret = -ENODEV;
407 goto done;
408 }
409
410 if (!of_device_is_available(remote)) {
411 dev_dbg(lvds->dev, "connected entity %pOF is disabled\n",
412 remote);
413 ret = -ENODEV;
414 goto done;
415 }
416
417 remote_input = of_graph_get_remote_endpoint(local_output);
418
419 for_each_endpoint_of_node(remote, node) {
420 if (node != remote_input) {
421 /*
422 * We've found one endpoint other than the input, this
423 * must be a bridge.
424 */
425 is_bridge = true;
426 of_node_put(node);
427 break;
428 }
429 }
430
431 if (is_bridge) {
432 lvds->next_bridge = of_drm_find_bridge(remote);
433 if (!lvds->next_bridge)
434 ret = -EPROBE_DEFER;
435 } else {
436 lvds->panel = of_drm_find_panel(remote);
437 if (!lvds->panel)
438 ret = -EPROBE_DEFER;
439 }
440
441done:
442 of_node_put(local_output);
443 of_node_put(remote_input);
444 of_node_put(remote);
445
446 return ret;
447}
448
449static int rcar_lvds_probe(struct platform_device *pdev)
450{
451 struct rcar_lvds *lvds;
452 struct resource *mem;
453 int ret;
454
455 lvds = devm_kzalloc(&pdev->dev, sizeof(*lvds), GFP_KERNEL);
456 if (lvds == NULL)
457 return -ENOMEM;
458
459 platform_set_drvdata(pdev, lvds);
460
461 lvds->dev = &pdev->dev;
462 lvds->info = of_device_get_match_data(&pdev->dev);
463 lvds->enabled = false;
464
465 ret = rcar_lvds_parse_dt(lvds);
466 if (ret < 0)
467 return ret;
468
469 lvds->bridge.driver_private = lvds;
470 lvds->bridge.funcs = &rcar_lvds_bridge_ops;
471 lvds->bridge.of_node = pdev->dev.of_node;
472
473 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
474 lvds->mmio = devm_ioremap_resource(&pdev->dev, mem);
475 if (IS_ERR(lvds->mmio))
476 return PTR_ERR(lvds->mmio);
477
478 lvds->clock = devm_clk_get(&pdev->dev, NULL);
479 if (IS_ERR(lvds->clock)) {
480 dev_err(&pdev->dev, "failed to get clock\n");
481 return PTR_ERR(lvds->clock);
482 }
483
484 drm_bridge_add(&lvds->bridge);
485
486 return 0;
487}
488
489static int rcar_lvds_remove(struct platform_device *pdev)
490{
491 struct rcar_lvds *lvds = platform_get_drvdata(pdev);
492
493 drm_bridge_remove(&lvds->bridge);
494
495 return 0;
496}
497
498static const struct rcar_lvds_device_info rcar_lvds_gen2_info = {
499 .gen = 2,
500 .quirks = RCAR_LVDS_QUIRK_GEN2_PLLCR,
501};
502
503static const struct rcar_lvds_device_info rcar_lvds_r8a7790_info = {
504 .gen = 2,
505 .quirks = RCAR_LVDS_QUIRK_GEN2_PLLCR | RCAR_LVDS_QUIRK_LANES,
506};
507
508static const struct rcar_lvds_device_info rcar_lvds_gen3_info = {
509 .gen = 3,
510};
511
512static const struct rcar_lvds_device_info rcar_lvds_r8a77970_info = {
513 .gen = 3,
514 .quirks = RCAR_LVDS_QUIRK_GEN2_PLLCR | RCAR_LVDS_QUIRK_GEN3_LVEN,
515};
516
517static const struct of_device_id rcar_lvds_of_table[] = {
518 { .compatible = "renesas,r8a7743-lvds", .data = &rcar_lvds_gen2_info },
519 { .compatible = "renesas,r8a7790-lvds", .data = &rcar_lvds_r8a7790_info },
520 { .compatible = "renesas,r8a7791-lvds", .data = &rcar_lvds_gen2_info },
521 { .compatible = "renesas,r8a7793-lvds", .data = &rcar_lvds_gen2_info },
522 { .compatible = "renesas,r8a7795-lvds", .data = &rcar_lvds_gen3_info },
523 { .compatible = "renesas,r8a7796-lvds", .data = &rcar_lvds_gen3_info },
524 { .compatible = "renesas,r8a77970-lvds", .data = &rcar_lvds_r8a77970_info },
525 { }
526};
527
528MODULE_DEVICE_TABLE(of, rcar_lvds_of_table);
529
530static struct platform_driver rcar_lvds_platform_driver = {
531 .probe = rcar_lvds_probe,
532 .remove = rcar_lvds_remove,
533 .driver = {
534 .name = "rcar-lvds",
535 .of_match_table = rcar_lvds_of_table,
536 },
537};
538
539module_platform_driver(rcar_lvds_platform_driver);
540
541MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>");
542MODULE_DESCRIPTION("Renesas R-Car LVDS Encoder Driver");
543MODULE_LICENSE("GPL");