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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * tc358767 eDP bridge driver
4 *
5 * Copyright (C) 2016 CogentEmbedded Inc
6 * Author: Andrey Gusakov <andrey.gusakov@cogentembedded.com>
7 *
8 * Copyright (C) 2016 Pengutronix, Philipp Zabel <p.zabel@pengutronix.de>
9 *
10 * Copyright (C) 2016 Zodiac Inflight Innovations
11 *
12 * Initially based on: drivers/gpu/drm/i2c/tda998x_drv.c
13 *
14 * Copyright (C) 2012 Texas Instruments
15 * Author: Rob Clark <robdclark@gmail.com>
16 */
17
18#include <linux/bitfield.h>
19#include <linux/clk.h>
20#include <linux/device.h>
21#include <linux/gpio/consumer.h>
22#include <linux/i2c.h>
23#include <linux/kernel.h>
24#include <linux/module.h>
25#include <linux/regmap.h>
26#include <linux/slab.h>
27
28#include <drm/drm_atomic_helper.h>
29#include <drm/drm_bridge.h>
30#include <drm/drm_dp_helper.h>
31#include <drm/drm_edid.h>
32#include <drm/drm_of.h>
33#include <drm/drm_panel.h>
34#include <drm/drm_print.h>
35#include <drm/drm_probe_helper.h>
36
37/* Registers */
38
39/* Display Parallel Interface */
40#define DPIPXLFMT 0x0440
41#define VS_POL_ACTIVE_LOW (1 << 10)
42#define HS_POL_ACTIVE_LOW (1 << 9)
43#define DE_POL_ACTIVE_HIGH (0 << 8)
44#define SUB_CFG_TYPE_CONFIG1 (0 << 2) /* LSB aligned */
45#define SUB_CFG_TYPE_CONFIG2 (1 << 2) /* Loosely Packed */
46#define SUB_CFG_TYPE_CONFIG3 (2 << 2) /* LSB aligned 8-bit */
47#define DPI_BPP_RGB888 (0 << 0)
48#define DPI_BPP_RGB666 (1 << 0)
49#define DPI_BPP_RGB565 (2 << 0)
50
51/* Video Path */
52#define VPCTRL0 0x0450
53#define VSDELAY GENMASK(31, 20)
54#define OPXLFMT_RGB666 (0 << 8)
55#define OPXLFMT_RGB888 (1 << 8)
56#define FRMSYNC_DISABLED (0 << 4) /* Video Timing Gen Disabled */
57#define FRMSYNC_ENABLED (1 << 4) /* Video Timing Gen Enabled */
58#define MSF_DISABLED (0 << 0) /* Magic Square FRC disabled */
59#define MSF_ENABLED (1 << 0) /* Magic Square FRC enabled */
60#define HTIM01 0x0454
61#define HPW GENMASK(8, 0)
62#define HBPR GENMASK(24, 16)
63#define HTIM02 0x0458
64#define HDISPR GENMASK(10, 0)
65#define HFPR GENMASK(24, 16)
66#define VTIM01 0x045c
67#define VSPR GENMASK(7, 0)
68#define VBPR GENMASK(23, 16)
69#define VTIM02 0x0460
70#define VFPR GENMASK(23, 16)
71#define VDISPR GENMASK(10, 0)
72#define VFUEN0 0x0464
73#define VFUEN BIT(0) /* Video Frame Timing Upload */
74
75/* System */
76#define TC_IDREG 0x0500
77#define SYSSTAT 0x0508
78#define SYSCTRL 0x0510
79#define DP0_AUDSRC_NO_INPUT (0 << 3)
80#define DP0_AUDSRC_I2S_RX (1 << 3)
81#define DP0_VIDSRC_NO_INPUT (0 << 0)
82#define DP0_VIDSRC_DSI_RX (1 << 0)
83#define DP0_VIDSRC_DPI_RX (2 << 0)
84#define DP0_VIDSRC_COLOR_BAR (3 << 0)
85#define SYSRSTENB 0x050c
86#define ENBI2C (1 << 0)
87#define ENBLCD0 (1 << 2)
88#define ENBBM (1 << 3)
89#define ENBDSIRX (1 << 4)
90#define ENBREG (1 << 5)
91#define ENBHDCP (1 << 8)
92#define GPIOM 0x0540
93#define GPIOC 0x0544
94#define GPIOO 0x0548
95#define GPIOI 0x054c
96#define INTCTL_G 0x0560
97#define INTSTS_G 0x0564
98
99#define INT_SYSERR BIT(16)
100#define INT_GPIO_H(x) (1 << (x == 0 ? 2 : 10))
101#define INT_GPIO_LC(x) (1 << (x == 0 ? 3 : 11))
102
103#define INT_GP0_LCNT 0x0584
104#define INT_GP1_LCNT 0x0588
105
106/* Control */
107#define DP0CTL 0x0600
108#define VID_MN_GEN BIT(6) /* Auto-generate M/N values */
109#define EF_EN BIT(5) /* Enable Enhanced Framing */
110#define VID_EN BIT(1) /* Video transmission enable */
111#define DP_EN BIT(0) /* Enable DPTX function */
112
113/* Clocks */
114#define DP0_VIDMNGEN0 0x0610
115#define DP0_VIDMNGEN1 0x0614
116#define DP0_VMNGENSTATUS 0x0618
117
118/* Main Channel */
119#define DP0_SECSAMPLE 0x0640
120#define DP0_VIDSYNCDELAY 0x0644
121#define VID_SYNC_DLY GENMASK(15, 0)
122#define THRESH_DLY GENMASK(31, 16)
123
124#define DP0_TOTALVAL 0x0648
125#define H_TOTAL GENMASK(15, 0)
126#define V_TOTAL GENMASK(31, 16)
127#define DP0_STARTVAL 0x064c
128#define H_START GENMASK(15, 0)
129#define V_START GENMASK(31, 16)
130#define DP0_ACTIVEVAL 0x0650
131#define H_ACT GENMASK(15, 0)
132#define V_ACT GENMASK(31, 16)
133
134#define DP0_SYNCVAL 0x0654
135#define VS_WIDTH GENMASK(30, 16)
136#define HS_WIDTH GENMASK(14, 0)
137#define SYNCVAL_HS_POL_ACTIVE_LOW (1 << 15)
138#define SYNCVAL_VS_POL_ACTIVE_LOW (1 << 31)
139#define DP0_MISC 0x0658
140#define TU_SIZE_RECOMMENDED (63) /* LSCLK cycles per TU */
141#define MAX_TU_SYMBOL GENMASK(28, 23)
142#define TU_SIZE GENMASK(21, 16)
143#define BPC_6 (0 << 5)
144#define BPC_8 (1 << 5)
145
146/* AUX channel */
147#define DP0_AUXCFG0 0x0660
148#define DP0_AUXCFG0_BSIZE GENMASK(11, 8)
149#define DP0_AUXCFG0_ADDR_ONLY BIT(4)
150#define DP0_AUXCFG1 0x0664
151#define AUX_RX_FILTER_EN BIT(16)
152
153#define DP0_AUXADDR 0x0668
154#define DP0_AUXWDATA(i) (0x066c + (i) * 4)
155#define DP0_AUXRDATA(i) (0x067c + (i) * 4)
156#define DP0_AUXSTATUS 0x068c
157#define AUX_BYTES GENMASK(15, 8)
158#define AUX_STATUS GENMASK(7, 4)
159#define AUX_TIMEOUT BIT(1)
160#define AUX_BUSY BIT(0)
161#define DP0_AUXI2CADR 0x0698
162
163/* Link Training */
164#define DP0_SRCCTRL 0x06a0
165#define DP0_SRCCTRL_SCRMBLDIS BIT(13)
166#define DP0_SRCCTRL_EN810B BIT(12)
167#define DP0_SRCCTRL_NOTP (0 << 8)
168#define DP0_SRCCTRL_TP1 (1 << 8)
169#define DP0_SRCCTRL_TP2 (2 << 8)
170#define DP0_SRCCTRL_LANESKEW BIT(7)
171#define DP0_SRCCTRL_SSCG BIT(3)
172#define DP0_SRCCTRL_LANES_1 (0 << 2)
173#define DP0_SRCCTRL_LANES_2 (1 << 2)
174#define DP0_SRCCTRL_BW27 (1 << 1)
175#define DP0_SRCCTRL_BW162 (0 << 1)
176#define DP0_SRCCTRL_AUTOCORRECT BIT(0)
177#define DP0_LTSTAT 0x06d0
178#define LT_LOOPDONE BIT(13)
179#define LT_STATUS_MASK (0x1f << 8)
180#define LT_CHANNEL1_EQ_BITS (DP_CHANNEL_EQ_BITS << 4)
181#define LT_INTERLANE_ALIGN_DONE BIT(3)
182#define LT_CHANNEL0_EQ_BITS (DP_CHANNEL_EQ_BITS)
183#define DP0_SNKLTCHGREQ 0x06d4
184#define DP0_LTLOOPCTRL 0x06d8
185#define DP0_SNKLTCTRL 0x06e4
186
187#define DP1_SRCCTRL 0x07a0
188
189/* PHY */
190#define DP_PHY_CTRL 0x0800
191#define DP_PHY_RST BIT(28) /* DP PHY Global Soft Reset */
192#define BGREN BIT(25) /* AUX PHY BGR Enable */
193#define PWR_SW_EN BIT(24) /* PHY Power Switch Enable */
194#define PHY_M1_RST BIT(12) /* Reset PHY1 Main Channel */
195#define PHY_RDY BIT(16) /* PHY Main Channels Ready */
196#define PHY_M0_RST BIT(8) /* Reset PHY0 Main Channel */
197#define PHY_2LANE BIT(2) /* PHY Enable 2 lanes */
198#define PHY_A0_EN BIT(1) /* PHY Aux Channel0 Enable */
199#define PHY_M0_EN BIT(0) /* PHY Main Channel0 Enable */
200
201/* PLL */
202#define DP0_PLLCTRL 0x0900
203#define DP1_PLLCTRL 0x0904 /* not defined in DS */
204#define PXL_PLLCTRL 0x0908
205#define PLLUPDATE BIT(2)
206#define PLLBYP BIT(1)
207#define PLLEN BIT(0)
208#define PXL_PLLPARAM 0x0914
209#define IN_SEL_REFCLK (0 << 14)
210#define SYS_PLLPARAM 0x0918
211#define REF_FREQ_38M4 (0 << 8) /* 38.4 MHz */
212#define REF_FREQ_19M2 (1 << 8) /* 19.2 MHz */
213#define REF_FREQ_26M (2 << 8) /* 26 MHz */
214#define REF_FREQ_13M (3 << 8) /* 13 MHz */
215#define SYSCLK_SEL_LSCLK (0 << 4)
216#define LSCLK_DIV_1 (0 << 0)
217#define LSCLK_DIV_2 (1 << 0)
218
219/* Test & Debug */
220#define TSTCTL 0x0a00
221#define COLOR_R GENMASK(31, 24)
222#define COLOR_G GENMASK(23, 16)
223#define COLOR_B GENMASK(15, 8)
224#define ENI2CFILTER BIT(4)
225#define COLOR_BAR_MODE GENMASK(1, 0)
226#define COLOR_BAR_MODE_BARS 2
227#define PLL_DBG 0x0a04
228
229static bool tc_test_pattern;
230module_param_named(test, tc_test_pattern, bool, 0644);
231
232struct tc_edp_link {
233 u8 dpcd[DP_RECEIVER_CAP_SIZE];
234 unsigned int rate;
235 u8 num_lanes;
236 u8 assr;
237 bool scrambler_dis;
238 bool spread;
239};
240
241struct tc_data {
242 struct device *dev;
243 struct regmap *regmap;
244 struct drm_dp_aux aux;
245
246 struct drm_bridge bridge;
247 struct drm_connector connector;
248 struct drm_panel *panel;
249
250 /* link settings */
251 struct tc_edp_link link;
252
253 /* display edid */
254 struct edid *edid;
255 /* current mode */
256 struct drm_display_mode mode;
257
258 u32 rev;
259 u8 assr;
260
261 struct gpio_desc *sd_gpio;
262 struct gpio_desc *reset_gpio;
263 struct clk *refclk;
264
265 /* do we have IRQ */
266 bool have_irq;
267
268 /* HPD pin number (0 or 1) or -ENODEV */
269 int hpd_pin;
270};
271
272static inline struct tc_data *aux_to_tc(struct drm_dp_aux *a)
273{
274 return container_of(a, struct tc_data, aux);
275}
276
277static inline struct tc_data *bridge_to_tc(struct drm_bridge *b)
278{
279 return container_of(b, struct tc_data, bridge);
280}
281
282static inline struct tc_data *connector_to_tc(struct drm_connector *c)
283{
284 return container_of(c, struct tc_data, connector);
285}
286
287static inline int tc_poll_timeout(struct tc_data *tc, unsigned int addr,
288 unsigned int cond_mask,
289 unsigned int cond_value,
290 unsigned long sleep_us, u64 timeout_us)
291{
292 unsigned int val;
293
294 return regmap_read_poll_timeout(tc->regmap, addr, val,
295 (val & cond_mask) == cond_value,
296 sleep_us, timeout_us);
297}
298
299static int tc_aux_wait_busy(struct tc_data *tc)
300{
301 return tc_poll_timeout(tc, DP0_AUXSTATUS, AUX_BUSY, 0, 100, 100000);
302}
303
304static int tc_aux_write_data(struct tc_data *tc, const void *data,
305 size_t size)
306{
307 u32 auxwdata[DP_AUX_MAX_PAYLOAD_BYTES / sizeof(u32)] = { 0 };
308 int ret, count = ALIGN(size, sizeof(u32));
309
310 memcpy(auxwdata, data, size);
311
312 ret = regmap_raw_write(tc->regmap, DP0_AUXWDATA(0), auxwdata, count);
313 if (ret)
314 return ret;
315
316 return size;
317}
318
319static int tc_aux_read_data(struct tc_data *tc, void *data, size_t size)
320{
321 u32 auxrdata[DP_AUX_MAX_PAYLOAD_BYTES / sizeof(u32)];
322 int ret, count = ALIGN(size, sizeof(u32));
323
324 ret = regmap_raw_read(tc->regmap, DP0_AUXRDATA(0), auxrdata, count);
325 if (ret)
326 return ret;
327
328 memcpy(data, auxrdata, size);
329
330 return size;
331}
332
333static u32 tc_auxcfg0(struct drm_dp_aux_msg *msg, size_t size)
334{
335 u32 auxcfg0 = msg->request;
336
337 if (size)
338 auxcfg0 |= FIELD_PREP(DP0_AUXCFG0_BSIZE, size - 1);
339 else
340 auxcfg0 |= DP0_AUXCFG0_ADDR_ONLY;
341
342 return auxcfg0;
343}
344
345static ssize_t tc_aux_transfer(struct drm_dp_aux *aux,
346 struct drm_dp_aux_msg *msg)
347{
348 struct tc_data *tc = aux_to_tc(aux);
349 size_t size = min_t(size_t, DP_AUX_MAX_PAYLOAD_BYTES - 1, msg->size);
350 u8 request = msg->request & ~DP_AUX_I2C_MOT;
351 u32 auxstatus;
352 int ret;
353
354 ret = tc_aux_wait_busy(tc);
355 if (ret)
356 return ret;
357
358 switch (request) {
359 case DP_AUX_NATIVE_READ:
360 case DP_AUX_I2C_READ:
361 break;
362 case DP_AUX_NATIVE_WRITE:
363 case DP_AUX_I2C_WRITE:
364 if (size) {
365 ret = tc_aux_write_data(tc, msg->buffer, size);
366 if (ret < 0)
367 return ret;
368 }
369 break;
370 default:
371 return -EINVAL;
372 }
373
374 /* Store address */
375 ret = regmap_write(tc->regmap, DP0_AUXADDR, msg->address);
376 if (ret)
377 return ret;
378 /* Start transfer */
379 ret = regmap_write(tc->regmap, DP0_AUXCFG0, tc_auxcfg0(msg, size));
380 if (ret)
381 return ret;
382
383 ret = tc_aux_wait_busy(tc);
384 if (ret)
385 return ret;
386
387 ret = regmap_read(tc->regmap, DP0_AUXSTATUS, &auxstatus);
388 if (ret)
389 return ret;
390
391 if (auxstatus & AUX_TIMEOUT)
392 return -ETIMEDOUT;
393 /*
394 * For some reason address-only DP_AUX_I2C_WRITE (MOT), still
395 * reports 1 byte transferred in its status. To deal we that
396 * we ignore aux_bytes field if we know that this was an
397 * address-only transfer
398 */
399 if (size)
400 size = FIELD_GET(AUX_BYTES, auxstatus);
401 msg->reply = FIELD_GET(AUX_STATUS, auxstatus);
402
403 switch (request) {
404 case DP_AUX_NATIVE_READ:
405 case DP_AUX_I2C_READ:
406 if (size)
407 return tc_aux_read_data(tc, msg->buffer, size);
408 break;
409 }
410
411 return size;
412}
413
414static const char * const training_pattern1_errors[] = {
415 "No errors",
416 "Aux write error",
417 "Aux read error",
418 "Max voltage reached error",
419 "Loop counter expired error",
420 "res", "res", "res"
421};
422
423static const char * const training_pattern2_errors[] = {
424 "No errors",
425 "Aux write error",
426 "Aux read error",
427 "Clock recovery failed error",
428 "Loop counter expired error",
429 "res", "res", "res"
430};
431
432static u32 tc_srcctrl(struct tc_data *tc)
433{
434 /*
435 * No training pattern, skew lane 1 data by two LSCLK cycles with
436 * respect to lane 0 data, AutoCorrect Mode = 0
437 */
438 u32 reg = DP0_SRCCTRL_NOTP | DP0_SRCCTRL_LANESKEW | DP0_SRCCTRL_EN810B;
439
440 if (tc->link.scrambler_dis)
441 reg |= DP0_SRCCTRL_SCRMBLDIS; /* Scrambler Disabled */
442 if (tc->link.spread)
443 reg |= DP0_SRCCTRL_SSCG; /* Spread Spectrum Enable */
444 if (tc->link.num_lanes == 2)
445 reg |= DP0_SRCCTRL_LANES_2; /* Two Main Channel Lanes */
446 if (tc->link.rate != 162000)
447 reg |= DP0_SRCCTRL_BW27; /* 2.7 Gbps link */
448 return reg;
449}
450
451static int tc_pllupdate(struct tc_data *tc, unsigned int pllctrl)
452{
453 int ret;
454
455 ret = regmap_write(tc->regmap, pllctrl, PLLUPDATE | PLLEN);
456 if (ret)
457 return ret;
458
459 /* Wait for PLL to lock: up to 2.09 ms, depending on refclk */
460 usleep_range(3000, 6000);
461
462 return 0;
463}
464
465static int tc_pxl_pll_en(struct tc_data *tc, u32 refclk, u32 pixelclock)
466{
467 int ret;
468 int i_pre, best_pre = 1;
469 int i_post, best_post = 1;
470 int div, best_div = 1;
471 int mul, best_mul = 1;
472 int delta, best_delta;
473 int ext_div[] = {1, 2, 3, 5, 7};
474 int best_pixelclock = 0;
475 int vco_hi = 0;
476 u32 pxl_pllparam;
477
478 dev_dbg(tc->dev, "PLL: requested %d pixelclock, ref %d\n", pixelclock,
479 refclk);
480 best_delta = pixelclock;
481 /* Loop over all possible ext_divs, skipping invalid configurations */
482 for (i_pre = 0; i_pre < ARRAY_SIZE(ext_div); i_pre++) {
483 /*
484 * refclk / ext_pre_div should be in the 1 to 200 MHz range.
485 * We don't allow any refclk > 200 MHz, only check lower bounds.
486 */
487 if (refclk / ext_div[i_pre] < 1000000)
488 continue;
489 for (i_post = 0; i_post < ARRAY_SIZE(ext_div); i_post++) {
490 for (div = 1; div <= 16; div++) {
491 u32 clk;
492 u64 tmp;
493
494 tmp = pixelclock * ext_div[i_pre] *
495 ext_div[i_post] * div;
496 do_div(tmp, refclk);
497 mul = tmp;
498
499 /* Check limits */
500 if ((mul < 1) || (mul > 128))
501 continue;
502
503 clk = (refclk / ext_div[i_pre] / div) * mul;
504 /*
505 * refclk * mul / (ext_pre_div * pre_div)
506 * should be in the 150 to 650 MHz range
507 */
508 if ((clk > 650000000) || (clk < 150000000))
509 continue;
510
511 clk = clk / ext_div[i_post];
512 delta = clk - pixelclock;
513
514 if (abs(delta) < abs(best_delta)) {
515 best_pre = i_pre;
516 best_post = i_post;
517 best_div = div;
518 best_mul = mul;
519 best_delta = delta;
520 best_pixelclock = clk;
521 }
522 }
523 }
524 }
525 if (best_pixelclock == 0) {
526 dev_err(tc->dev, "Failed to calc clock for %d pixelclock\n",
527 pixelclock);
528 return -EINVAL;
529 }
530
531 dev_dbg(tc->dev, "PLL: got %d, delta %d\n", best_pixelclock,
532 best_delta);
533 dev_dbg(tc->dev, "PLL: %d / %d / %d * %d / %d\n", refclk,
534 ext_div[best_pre], best_div, best_mul, ext_div[best_post]);
535
536 /* if VCO >= 300 MHz */
537 if (refclk / ext_div[best_pre] / best_div * best_mul >= 300000000)
538 vco_hi = 1;
539 /* see DS */
540 if (best_div == 16)
541 best_div = 0;
542 if (best_mul == 128)
543 best_mul = 0;
544
545 /* Power up PLL and switch to bypass */
546 ret = regmap_write(tc->regmap, PXL_PLLCTRL, PLLBYP | PLLEN);
547 if (ret)
548 return ret;
549
550 pxl_pllparam = vco_hi << 24; /* For PLL VCO >= 300 MHz = 1 */
551 pxl_pllparam |= ext_div[best_pre] << 20; /* External Pre-divider */
552 pxl_pllparam |= ext_div[best_post] << 16; /* External Post-divider */
553 pxl_pllparam |= IN_SEL_REFCLK; /* Use RefClk as PLL input */
554 pxl_pllparam |= best_div << 8; /* Divider for PLL RefClk */
555 pxl_pllparam |= best_mul; /* Multiplier for PLL */
556
557 ret = regmap_write(tc->regmap, PXL_PLLPARAM, pxl_pllparam);
558 if (ret)
559 return ret;
560
561 /* Force PLL parameter update and disable bypass */
562 return tc_pllupdate(tc, PXL_PLLCTRL);
563}
564
565static int tc_pxl_pll_dis(struct tc_data *tc)
566{
567 /* Enable PLL bypass, power down PLL */
568 return regmap_write(tc->regmap, PXL_PLLCTRL, PLLBYP);
569}
570
571static int tc_stream_clock_calc(struct tc_data *tc)
572{
573 /*
574 * If the Stream clock and Link Symbol clock are
575 * asynchronous with each other, the value of M changes over
576 * time. This way of generating link clock and stream
577 * clock is called Asynchronous Clock mode. The value M
578 * must change while the value N stays constant. The
579 * value of N in this Asynchronous Clock mode must be set
580 * to 2^15 or 32,768.
581 *
582 * LSCLK = 1/10 of high speed link clock
583 *
584 * f_STRMCLK = M/N * f_LSCLK
585 * M/N = f_STRMCLK / f_LSCLK
586 *
587 */
588 return regmap_write(tc->regmap, DP0_VIDMNGEN1, 32768);
589}
590
591static int tc_set_syspllparam(struct tc_data *tc)
592{
593 unsigned long rate;
594 u32 pllparam = SYSCLK_SEL_LSCLK | LSCLK_DIV_2;
595
596 rate = clk_get_rate(tc->refclk);
597 switch (rate) {
598 case 38400000:
599 pllparam |= REF_FREQ_38M4;
600 break;
601 case 26000000:
602 pllparam |= REF_FREQ_26M;
603 break;
604 case 19200000:
605 pllparam |= REF_FREQ_19M2;
606 break;
607 case 13000000:
608 pllparam |= REF_FREQ_13M;
609 break;
610 default:
611 dev_err(tc->dev, "Invalid refclk rate: %lu Hz\n", rate);
612 return -EINVAL;
613 }
614
615 return regmap_write(tc->regmap, SYS_PLLPARAM, pllparam);
616}
617
618static int tc_aux_link_setup(struct tc_data *tc)
619{
620 int ret;
621 u32 dp0_auxcfg1;
622
623 /* Setup DP-PHY / PLL */
624 ret = tc_set_syspllparam(tc);
625 if (ret)
626 goto err;
627
628 ret = regmap_write(tc->regmap, DP_PHY_CTRL,
629 BGREN | PWR_SW_EN | PHY_A0_EN);
630 if (ret)
631 goto err;
632 /*
633 * Initially PLLs are in bypass. Force PLL parameter update,
634 * disable PLL bypass, enable PLL
635 */
636 ret = tc_pllupdate(tc, DP0_PLLCTRL);
637 if (ret)
638 goto err;
639
640 ret = tc_pllupdate(tc, DP1_PLLCTRL);
641 if (ret)
642 goto err;
643
644 ret = tc_poll_timeout(tc, DP_PHY_CTRL, PHY_RDY, PHY_RDY, 100, 100000);
645 if (ret == -ETIMEDOUT) {
646 dev_err(tc->dev, "Timeout waiting for PHY to become ready");
647 return ret;
648 } else if (ret) {
649 goto err;
650 }
651
652 /* Setup AUX link */
653 dp0_auxcfg1 = AUX_RX_FILTER_EN;
654 dp0_auxcfg1 |= 0x06 << 8; /* Aux Bit Period Calculator Threshold */
655 dp0_auxcfg1 |= 0x3f << 0; /* Aux Response Timeout Timer */
656
657 ret = regmap_write(tc->regmap, DP0_AUXCFG1, dp0_auxcfg1);
658 if (ret)
659 goto err;
660
661 return 0;
662err:
663 dev_err(tc->dev, "tc_aux_link_setup failed: %d\n", ret);
664 return ret;
665}
666
667static int tc_get_display_props(struct tc_data *tc)
668{
669 u8 revision, num_lanes;
670 unsigned int rate;
671 int ret;
672 u8 reg;
673
674 /* Read DP Rx Link Capability */
675 ret = drm_dp_dpcd_read(&tc->aux, DP_DPCD_REV, tc->link.dpcd,
676 DP_RECEIVER_CAP_SIZE);
677 if (ret < 0)
678 goto err_dpcd_read;
679
680 revision = tc->link.dpcd[DP_DPCD_REV];
681 rate = drm_dp_max_link_rate(tc->link.dpcd);
682 num_lanes = drm_dp_max_lane_count(tc->link.dpcd);
683
684 if (rate != 162000 && rate != 270000) {
685 dev_dbg(tc->dev, "Falling to 2.7 Gbps rate\n");
686 rate = 270000;
687 }
688
689 tc->link.rate = rate;
690
691 if (num_lanes > 2) {
692 dev_dbg(tc->dev, "Falling to 2 lanes\n");
693 num_lanes = 2;
694 }
695
696 tc->link.num_lanes = num_lanes;
697
698 ret = drm_dp_dpcd_readb(&tc->aux, DP_MAX_DOWNSPREAD, ®);
699 if (ret < 0)
700 goto err_dpcd_read;
701 tc->link.spread = reg & DP_MAX_DOWNSPREAD_0_5;
702
703 ret = drm_dp_dpcd_readb(&tc->aux, DP_MAIN_LINK_CHANNEL_CODING, ®);
704 if (ret < 0)
705 goto err_dpcd_read;
706
707 tc->link.scrambler_dis = false;
708 /* read assr */
709 ret = drm_dp_dpcd_readb(&tc->aux, DP_EDP_CONFIGURATION_SET, ®);
710 if (ret < 0)
711 goto err_dpcd_read;
712 tc->link.assr = reg & DP_ALTERNATE_SCRAMBLER_RESET_ENABLE;
713
714 dev_dbg(tc->dev, "DPCD rev: %d.%d, rate: %s, lanes: %d, framing: %s\n",
715 revision >> 4, revision & 0x0f,
716 (tc->link.rate == 162000) ? "1.62Gbps" : "2.7Gbps",
717 tc->link.num_lanes,
718 drm_dp_enhanced_frame_cap(tc->link.dpcd) ?
719 "enhanced" : "default");
720 dev_dbg(tc->dev, "Downspread: %s, scrambler: %s\n",
721 tc->link.spread ? "0.5%" : "0.0%",
722 tc->link.scrambler_dis ? "disabled" : "enabled");
723 dev_dbg(tc->dev, "Display ASSR: %d, TC358767 ASSR: %d\n",
724 tc->link.assr, tc->assr);
725
726 return 0;
727
728err_dpcd_read:
729 dev_err(tc->dev, "failed to read DPCD: %d\n", ret);
730 return ret;
731}
732
733static int tc_set_video_mode(struct tc_data *tc,
734 const struct drm_display_mode *mode)
735{
736 int ret;
737 int vid_sync_dly;
738 int max_tu_symbol;
739
740 int left_margin = mode->htotal - mode->hsync_end;
741 int right_margin = mode->hsync_start - mode->hdisplay;
742 int hsync_len = mode->hsync_end - mode->hsync_start;
743 int upper_margin = mode->vtotal - mode->vsync_end;
744 int lower_margin = mode->vsync_start - mode->vdisplay;
745 int vsync_len = mode->vsync_end - mode->vsync_start;
746 u32 dp0_syncval;
747 u32 bits_per_pixel = 24;
748 u32 in_bw, out_bw;
749
750 /*
751 * Recommended maximum number of symbols transferred in a transfer unit:
752 * DIV_ROUND_UP((input active video bandwidth in bytes) * tu_size,
753 * (output active video bandwidth in bytes))
754 * Must be less than tu_size.
755 */
756
757 in_bw = mode->clock * bits_per_pixel / 8;
758 out_bw = tc->link.num_lanes * tc->link.rate;
759 max_tu_symbol = DIV_ROUND_UP(in_bw * TU_SIZE_RECOMMENDED, out_bw);
760
761 dev_dbg(tc->dev, "set mode %dx%d\n",
762 mode->hdisplay, mode->vdisplay);
763 dev_dbg(tc->dev, "H margin %d,%d sync %d\n",
764 left_margin, right_margin, hsync_len);
765 dev_dbg(tc->dev, "V margin %d,%d sync %d\n",
766 upper_margin, lower_margin, vsync_len);
767 dev_dbg(tc->dev, "total: %dx%d\n", mode->htotal, mode->vtotal);
768
769
770 /*
771 * LCD Ctl Frame Size
772 * datasheet is not clear of vsdelay in case of DPI
773 * assume we do not need any delay when DPI is a source of
774 * sync signals
775 */
776 ret = regmap_write(tc->regmap, VPCTRL0,
777 FIELD_PREP(VSDELAY, 0) |
778 OPXLFMT_RGB888 | FRMSYNC_DISABLED | MSF_DISABLED);
779 if (ret)
780 return ret;
781
782 ret = regmap_write(tc->regmap, HTIM01,
783 FIELD_PREP(HBPR, ALIGN(left_margin, 2)) |
784 FIELD_PREP(HPW, ALIGN(hsync_len, 2)));
785 if (ret)
786 return ret;
787
788 ret = regmap_write(tc->regmap, HTIM02,
789 FIELD_PREP(HDISPR, ALIGN(mode->hdisplay, 2)) |
790 FIELD_PREP(HFPR, ALIGN(right_margin, 2)));
791 if (ret)
792 return ret;
793
794 ret = regmap_write(tc->regmap, VTIM01,
795 FIELD_PREP(VBPR, upper_margin) |
796 FIELD_PREP(VSPR, vsync_len));
797 if (ret)
798 return ret;
799
800 ret = regmap_write(tc->regmap, VTIM02,
801 FIELD_PREP(VFPR, lower_margin) |
802 FIELD_PREP(VDISPR, mode->vdisplay));
803 if (ret)
804 return ret;
805
806 ret = regmap_write(tc->regmap, VFUEN0, VFUEN); /* update settings */
807 if (ret)
808 return ret;
809
810 /* Test pattern settings */
811 ret = regmap_write(tc->regmap, TSTCTL,
812 FIELD_PREP(COLOR_R, 120) |
813 FIELD_PREP(COLOR_G, 20) |
814 FIELD_PREP(COLOR_B, 99) |
815 ENI2CFILTER |
816 FIELD_PREP(COLOR_BAR_MODE, COLOR_BAR_MODE_BARS));
817 if (ret)
818 return ret;
819
820 /* DP Main Stream Attributes */
821 vid_sync_dly = hsync_len + left_margin + mode->hdisplay;
822 ret = regmap_write(tc->regmap, DP0_VIDSYNCDELAY,
823 FIELD_PREP(THRESH_DLY, max_tu_symbol) |
824 FIELD_PREP(VID_SYNC_DLY, vid_sync_dly));
825
826 ret = regmap_write(tc->regmap, DP0_TOTALVAL,
827 FIELD_PREP(H_TOTAL, mode->htotal) |
828 FIELD_PREP(V_TOTAL, mode->vtotal));
829 if (ret)
830 return ret;
831
832 ret = regmap_write(tc->regmap, DP0_STARTVAL,
833 FIELD_PREP(H_START, left_margin + hsync_len) |
834 FIELD_PREP(V_START, upper_margin + vsync_len));
835 if (ret)
836 return ret;
837
838 ret = regmap_write(tc->regmap, DP0_ACTIVEVAL,
839 FIELD_PREP(V_ACT, mode->vdisplay) |
840 FIELD_PREP(H_ACT, mode->hdisplay));
841 if (ret)
842 return ret;
843
844 dp0_syncval = FIELD_PREP(VS_WIDTH, vsync_len) |
845 FIELD_PREP(HS_WIDTH, hsync_len);
846
847 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
848 dp0_syncval |= SYNCVAL_VS_POL_ACTIVE_LOW;
849
850 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
851 dp0_syncval |= SYNCVAL_HS_POL_ACTIVE_LOW;
852
853 ret = regmap_write(tc->regmap, DP0_SYNCVAL, dp0_syncval);
854 if (ret)
855 return ret;
856
857 ret = regmap_write(tc->regmap, DPIPXLFMT,
858 VS_POL_ACTIVE_LOW | HS_POL_ACTIVE_LOW |
859 DE_POL_ACTIVE_HIGH | SUB_CFG_TYPE_CONFIG1 |
860 DPI_BPP_RGB888);
861 if (ret)
862 return ret;
863
864 ret = regmap_write(tc->regmap, DP0_MISC,
865 FIELD_PREP(MAX_TU_SYMBOL, max_tu_symbol) |
866 FIELD_PREP(TU_SIZE, TU_SIZE_RECOMMENDED) |
867 BPC_8);
868 if (ret)
869 return ret;
870
871 return 0;
872}
873
874static int tc_wait_link_training(struct tc_data *tc)
875{
876 u32 value;
877 int ret;
878
879 ret = tc_poll_timeout(tc, DP0_LTSTAT, LT_LOOPDONE,
880 LT_LOOPDONE, 500, 100000);
881 if (ret) {
882 dev_err(tc->dev, "Link training timeout waiting for LT_LOOPDONE!\n");
883 return ret;
884 }
885
886 ret = regmap_read(tc->regmap, DP0_LTSTAT, &value);
887 if (ret)
888 return ret;
889
890 return (value >> 8) & 0x7;
891}
892
893static int tc_main_link_enable(struct tc_data *tc)
894{
895 struct drm_dp_aux *aux = &tc->aux;
896 struct device *dev = tc->dev;
897 u32 dp_phy_ctrl;
898 u32 value;
899 int ret;
900 u8 tmp[DP_LINK_STATUS_SIZE];
901
902 dev_dbg(tc->dev, "link enable\n");
903
904 ret = regmap_read(tc->regmap, DP0CTL, &value);
905 if (ret)
906 return ret;
907
908 if (WARN_ON(value & DP_EN)) {
909 ret = regmap_write(tc->regmap, DP0CTL, 0);
910 if (ret)
911 return ret;
912 }
913
914 ret = regmap_write(tc->regmap, DP0_SRCCTRL, tc_srcctrl(tc));
915 if (ret)
916 return ret;
917 /* SSCG and BW27 on DP1 must be set to the same as on DP0 */
918 ret = regmap_write(tc->regmap, DP1_SRCCTRL,
919 (tc->link.spread ? DP0_SRCCTRL_SSCG : 0) |
920 ((tc->link.rate != 162000) ? DP0_SRCCTRL_BW27 : 0));
921 if (ret)
922 return ret;
923
924 ret = tc_set_syspllparam(tc);
925 if (ret)
926 return ret;
927
928 /* Setup Main Link */
929 dp_phy_ctrl = BGREN | PWR_SW_EN | PHY_A0_EN | PHY_M0_EN;
930 if (tc->link.num_lanes == 2)
931 dp_phy_ctrl |= PHY_2LANE;
932
933 ret = regmap_write(tc->regmap, DP_PHY_CTRL, dp_phy_ctrl);
934 if (ret)
935 return ret;
936
937 /* PLL setup */
938 ret = tc_pllupdate(tc, DP0_PLLCTRL);
939 if (ret)
940 return ret;
941
942 ret = tc_pllupdate(tc, DP1_PLLCTRL);
943 if (ret)
944 return ret;
945
946 /* Reset/Enable Main Links */
947 dp_phy_ctrl |= DP_PHY_RST | PHY_M1_RST | PHY_M0_RST;
948 ret = regmap_write(tc->regmap, DP_PHY_CTRL, dp_phy_ctrl);
949 usleep_range(100, 200);
950 dp_phy_ctrl &= ~(DP_PHY_RST | PHY_M1_RST | PHY_M0_RST);
951 ret = regmap_write(tc->regmap, DP_PHY_CTRL, dp_phy_ctrl);
952
953 ret = tc_poll_timeout(tc, DP_PHY_CTRL, PHY_RDY, PHY_RDY, 500, 100000);
954 if (ret) {
955 dev_err(dev, "timeout waiting for phy become ready");
956 return ret;
957 }
958
959 /* Set misc: 8 bits per color */
960 ret = regmap_update_bits(tc->regmap, DP0_MISC, BPC_8, BPC_8);
961 if (ret)
962 return ret;
963
964 /*
965 * ASSR mode
966 * on TC358767 side ASSR configured through strap pin
967 * seems there is no way to change this setting from SW
968 *
969 * check is tc configured for same mode
970 */
971 if (tc->assr != tc->link.assr) {
972 dev_dbg(dev, "Trying to set display to ASSR: %d\n",
973 tc->assr);
974 /* try to set ASSR on display side */
975 tmp[0] = tc->assr;
976 ret = drm_dp_dpcd_writeb(aux, DP_EDP_CONFIGURATION_SET, tmp[0]);
977 if (ret < 0)
978 goto err_dpcd_read;
979 /* read back */
980 ret = drm_dp_dpcd_readb(aux, DP_EDP_CONFIGURATION_SET, tmp);
981 if (ret < 0)
982 goto err_dpcd_read;
983
984 if (tmp[0] != tc->assr) {
985 dev_dbg(dev, "Failed to switch display ASSR to %d, falling back to unscrambled mode\n",
986 tc->assr);
987 /* trying with disabled scrambler */
988 tc->link.scrambler_dis = true;
989 }
990 }
991
992 /* Setup Link & DPRx Config for Training */
993 tmp[0] = drm_dp_link_rate_to_bw_code(tc->link.rate);
994 tmp[1] = tc->link.num_lanes;
995
996 if (drm_dp_enhanced_frame_cap(tc->link.dpcd))
997 tmp[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
998
999 ret = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, tmp, 2);
1000 if (ret < 0)
1001 goto err_dpcd_write;
1002
1003 /* DOWNSPREAD_CTRL */
1004 tmp[0] = tc->link.spread ? DP_SPREAD_AMP_0_5 : 0x00;
1005 /* MAIN_LINK_CHANNEL_CODING_SET */
1006 tmp[1] = DP_SET_ANSI_8B10B;
1007 ret = drm_dp_dpcd_write(aux, DP_DOWNSPREAD_CTRL, tmp, 2);
1008 if (ret < 0)
1009 goto err_dpcd_write;
1010
1011 /* Reset voltage-swing & pre-emphasis */
1012 tmp[0] = tmp[1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 |
1013 DP_TRAIN_PRE_EMPH_LEVEL_0;
1014 ret = drm_dp_dpcd_write(aux, DP_TRAINING_LANE0_SET, tmp, 2);
1015 if (ret < 0)
1016 goto err_dpcd_write;
1017
1018 /* Clock-Recovery */
1019
1020 /* Set DPCD 0x102 for Training Pattern 1 */
1021 ret = regmap_write(tc->regmap, DP0_SNKLTCTRL,
1022 DP_LINK_SCRAMBLING_DISABLE |
1023 DP_TRAINING_PATTERN_1);
1024 if (ret)
1025 return ret;
1026
1027 ret = regmap_write(tc->regmap, DP0_LTLOOPCTRL,
1028 (15 << 28) | /* Defer Iteration Count */
1029 (15 << 24) | /* Loop Iteration Count */
1030 (0xd << 0)); /* Loop Timer Delay */
1031 if (ret)
1032 return ret;
1033
1034 ret = regmap_write(tc->regmap, DP0_SRCCTRL,
1035 tc_srcctrl(tc) | DP0_SRCCTRL_SCRMBLDIS |
1036 DP0_SRCCTRL_AUTOCORRECT |
1037 DP0_SRCCTRL_TP1);
1038 if (ret)
1039 return ret;
1040
1041 /* Enable DP0 to start Link Training */
1042 ret = regmap_write(tc->regmap, DP0CTL,
1043 (drm_dp_enhanced_frame_cap(tc->link.dpcd) ?
1044 EF_EN : 0) | DP_EN);
1045 if (ret)
1046 return ret;
1047
1048 /* wait */
1049
1050 ret = tc_wait_link_training(tc);
1051 if (ret < 0)
1052 return ret;
1053
1054 if (ret) {
1055 dev_err(tc->dev, "Link training phase 1 failed: %s\n",
1056 training_pattern1_errors[ret]);
1057 return -ENODEV;
1058 }
1059
1060 /* Channel Equalization */
1061
1062 /* Set DPCD 0x102 for Training Pattern 2 */
1063 ret = regmap_write(tc->regmap, DP0_SNKLTCTRL,
1064 DP_LINK_SCRAMBLING_DISABLE |
1065 DP_TRAINING_PATTERN_2);
1066 if (ret)
1067 return ret;
1068
1069 ret = regmap_write(tc->regmap, DP0_SRCCTRL,
1070 tc_srcctrl(tc) | DP0_SRCCTRL_SCRMBLDIS |
1071 DP0_SRCCTRL_AUTOCORRECT |
1072 DP0_SRCCTRL_TP2);
1073 if (ret)
1074 return ret;
1075
1076 /* wait */
1077 ret = tc_wait_link_training(tc);
1078 if (ret < 0)
1079 return ret;
1080
1081 if (ret) {
1082 dev_err(tc->dev, "Link training phase 2 failed: %s\n",
1083 training_pattern2_errors[ret]);
1084 return -ENODEV;
1085 }
1086
1087 /*
1088 * Toshiba's documentation suggests to first clear DPCD 0x102, then
1089 * clear the training pattern bit in DP0_SRCCTRL. Testing shows
1090 * that the link sometimes drops if those steps are done in that order,
1091 * but if the steps are done in reverse order, the link stays up.
1092 *
1093 * So we do the steps differently than documented here.
1094 */
1095
1096 /* Clear Training Pattern, set AutoCorrect Mode = 1 */
1097 ret = regmap_write(tc->regmap, DP0_SRCCTRL, tc_srcctrl(tc) |
1098 DP0_SRCCTRL_AUTOCORRECT);
1099 if (ret)
1100 return ret;
1101
1102 /* Clear DPCD 0x102 */
1103 /* Note: Can Not use DP0_SNKLTCTRL (0x06E4) short cut */
1104 tmp[0] = tc->link.scrambler_dis ? DP_LINK_SCRAMBLING_DISABLE : 0x00;
1105 ret = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET, tmp[0]);
1106 if (ret < 0)
1107 goto err_dpcd_write;
1108
1109 /* Check link status */
1110 ret = drm_dp_dpcd_read_link_status(aux, tmp);
1111 if (ret < 0)
1112 goto err_dpcd_read;
1113
1114 ret = 0;
1115
1116 value = tmp[0] & DP_CHANNEL_EQ_BITS;
1117
1118 if (value != DP_CHANNEL_EQ_BITS) {
1119 dev_err(tc->dev, "Lane 0 failed: %x\n", value);
1120 ret = -ENODEV;
1121 }
1122
1123 if (tc->link.num_lanes == 2) {
1124 value = (tmp[0] >> 4) & DP_CHANNEL_EQ_BITS;
1125
1126 if (value != DP_CHANNEL_EQ_BITS) {
1127 dev_err(tc->dev, "Lane 1 failed: %x\n", value);
1128 ret = -ENODEV;
1129 }
1130
1131 if (!(tmp[2] & DP_INTERLANE_ALIGN_DONE)) {
1132 dev_err(tc->dev, "Interlane align failed\n");
1133 ret = -ENODEV;
1134 }
1135 }
1136
1137 if (ret) {
1138 dev_err(dev, "0x0202 LANE0_1_STATUS: 0x%02x\n", tmp[0]);
1139 dev_err(dev, "0x0203 LANE2_3_STATUS 0x%02x\n", tmp[1]);
1140 dev_err(dev, "0x0204 LANE_ALIGN_STATUS_UPDATED: 0x%02x\n", tmp[2]);
1141 dev_err(dev, "0x0205 SINK_STATUS: 0x%02x\n", tmp[3]);
1142 dev_err(dev, "0x0206 ADJUST_REQUEST_LANE0_1: 0x%02x\n", tmp[4]);
1143 dev_err(dev, "0x0207 ADJUST_REQUEST_LANE2_3: 0x%02x\n", tmp[5]);
1144 return ret;
1145 }
1146
1147 return 0;
1148err_dpcd_read:
1149 dev_err(tc->dev, "Failed to read DPCD: %d\n", ret);
1150 return ret;
1151err_dpcd_write:
1152 dev_err(tc->dev, "Failed to write DPCD: %d\n", ret);
1153 return ret;
1154}
1155
1156static int tc_main_link_disable(struct tc_data *tc)
1157{
1158 int ret;
1159
1160 dev_dbg(tc->dev, "link disable\n");
1161
1162 ret = regmap_write(tc->regmap, DP0_SRCCTRL, 0);
1163 if (ret)
1164 return ret;
1165
1166 return regmap_write(tc->regmap, DP0CTL, 0);
1167}
1168
1169static int tc_stream_enable(struct tc_data *tc)
1170{
1171 int ret;
1172 u32 value;
1173
1174 dev_dbg(tc->dev, "enable video stream\n");
1175
1176 /* PXL PLL setup */
1177 if (tc_test_pattern) {
1178 ret = tc_pxl_pll_en(tc, clk_get_rate(tc->refclk),
1179 1000 * tc->mode.clock);
1180 if (ret)
1181 return ret;
1182 }
1183
1184 ret = tc_set_video_mode(tc, &tc->mode);
1185 if (ret)
1186 return ret;
1187
1188 /* Set M/N */
1189 ret = tc_stream_clock_calc(tc);
1190 if (ret)
1191 return ret;
1192
1193 value = VID_MN_GEN | DP_EN;
1194 if (drm_dp_enhanced_frame_cap(tc->link.dpcd))
1195 value |= EF_EN;
1196 ret = regmap_write(tc->regmap, DP0CTL, value);
1197 if (ret)
1198 return ret;
1199 /*
1200 * VID_EN assertion should be delayed by at least N * LSCLK
1201 * cycles from the time VID_MN_GEN is enabled in order to
1202 * generate stable values for VID_M. LSCLK is 270 MHz or
1203 * 162 MHz, VID_N is set to 32768 in tc_stream_clock_calc(),
1204 * so a delay of at least 203 us should suffice.
1205 */
1206 usleep_range(500, 1000);
1207 value |= VID_EN;
1208 ret = regmap_write(tc->regmap, DP0CTL, value);
1209 if (ret)
1210 return ret;
1211 /* Set input interface */
1212 value = DP0_AUDSRC_NO_INPUT;
1213 if (tc_test_pattern)
1214 value |= DP0_VIDSRC_COLOR_BAR;
1215 else
1216 value |= DP0_VIDSRC_DPI_RX;
1217 ret = regmap_write(tc->regmap, SYSCTRL, value);
1218 if (ret)
1219 return ret;
1220
1221 return 0;
1222}
1223
1224static int tc_stream_disable(struct tc_data *tc)
1225{
1226 int ret;
1227
1228 dev_dbg(tc->dev, "disable video stream\n");
1229
1230 ret = regmap_update_bits(tc->regmap, DP0CTL, VID_EN, 0);
1231 if (ret)
1232 return ret;
1233
1234 tc_pxl_pll_dis(tc);
1235
1236 return 0;
1237}
1238
1239static void tc_bridge_pre_enable(struct drm_bridge *bridge)
1240{
1241 struct tc_data *tc = bridge_to_tc(bridge);
1242
1243 drm_panel_prepare(tc->panel);
1244}
1245
1246static void tc_bridge_enable(struct drm_bridge *bridge)
1247{
1248 struct tc_data *tc = bridge_to_tc(bridge);
1249 int ret;
1250
1251 ret = tc_get_display_props(tc);
1252 if (ret < 0) {
1253 dev_err(tc->dev, "failed to read display props: %d\n", ret);
1254 return;
1255 }
1256
1257 ret = tc_main_link_enable(tc);
1258 if (ret < 0) {
1259 dev_err(tc->dev, "main link enable error: %d\n", ret);
1260 return;
1261 }
1262
1263 ret = tc_stream_enable(tc);
1264 if (ret < 0) {
1265 dev_err(tc->dev, "main link stream start error: %d\n", ret);
1266 tc_main_link_disable(tc);
1267 return;
1268 }
1269
1270 drm_panel_enable(tc->panel);
1271}
1272
1273static void tc_bridge_disable(struct drm_bridge *bridge)
1274{
1275 struct tc_data *tc = bridge_to_tc(bridge);
1276 int ret;
1277
1278 drm_panel_disable(tc->panel);
1279
1280 ret = tc_stream_disable(tc);
1281 if (ret < 0)
1282 dev_err(tc->dev, "main link stream stop error: %d\n", ret);
1283
1284 ret = tc_main_link_disable(tc);
1285 if (ret < 0)
1286 dev_err(tc->dev, "main link disable error: %d\n", ret);
1287}
1288
1289static void tc_bridge_post_disable(struct drm_bridge *bridge)
1290{
1291 struct tc_data *tc = bridge_to_tc(bridge);
1292
1293 drm_panel_unprepare(tc->panel);
1294}
1295
1296static bool tc_bridge_mode_fixup(struct drm_bridge *bridge,
1297 const struct drm_display_mode *mode,
1298 struct drm_display_mode *adj)
1299{
1300 /* Fixup sync polarities, both hsync and vsync are active low */
1301 adj->flags = mode->flags;
1302 adj->flags |= (DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
1303 adj->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
1304
1305 return true;
1306}
1307
1308static enum drm_mode_status tc_mode_valid(struct drm_bridge *bridge,
1309 const struct drm_display_info *info,
1310 const struct drm_display_mode *mode)
1311{
1312 struct tc_data *tc = bridge_to_tc(bridge);
1313 u32 req, avail;
1314 u32 bits_per_pixel = 24;
1315
1316 /* DPI interface clock limitation: upto 154 MHz */
1317 if (mode->clock > 154000)
1318 return MODE_CLOCK_HIGH;
1319
1320 req = mode->clock * bits_per_pixel / 8;
1321 avail = tc->link.num_lanes * tc->link.rate;
1322
1323 if (req > avail)
1324 return MODE_BAD;
1325
1326 return MODE_OK;
1327}
1328
1329static void tc_bridge_mode_set(struct drm_bridge *bridge,
1330 const struct drm_display_mode *mode,
1331 const struct drm_display_mode *adj)
1332{
1333 struct tc_data *tc = bridge_to_tc(bridge);
1334
1335 tc->mode = *mode;
1336}
1337
1338static int tc_connector_get_modes(struct drm_connector *connector)
1339{
1340 struct tc_data *tc = connector_to_tc(connector);
1341 struct edid *edid;
1342 int count;
1343 int ret;
1344
1345 ret = tc_get_display_props(tc);
1346 if (ret < 0) {
1347 dev_err(tc->dev, "failed to read display props: %d\n", ret);
1348 return 0;
1349 }
1350
1351 count = drm_panel_get_modes(tc->panel, connector);
1352 if (count > 0)
1353 return count;
1354
1355 edid = drm_get_edid(connector, &tc->aux.ddc);
1356
1357 kfree(tc->edid);
1358 tc->edid = edid;
1359 if (!edid)
1360 return 0;
1361
1362 drm_connector_update_edid_property(connector, edid);
1363 count = drm_add_edid_modes(connector, edid);
1364
1365 return count;
1366}
1367
1368static const struct drm_connector_helper_funcs tc_connector_helper_funcs = {
1369 .get_modes = tc_connector_get_modes,
1370};
1371
1372static enum drm_connector_status tc_connector_detect(struct drm_connector *connector,
1373 bool force)
1374{
1375 struct tc_data *tc = connector_to_tc(connector);
1376 bool conn;
1377 u32 val;
1378 int ret;
1379
1380 if (tc->hpd_pin < 0) {
1381 if (tc->panel)
1382 return connector_status_connected;
1383 else
1384 return connector_status_unknown;
1385 }
1386
1387 ret = regmap_read(tc->regmap, GPIOI, &val);
1388 if (ret)
1389 return connector_status_unknown;
1390
1391 conn = val & BIT(tc->hpd_pin);
1392
1393 if (conn)
1394 return connector_status_connected;
1395 else
1396 return connector_status_disconnected;
1397}
1398
1399static const struct drm_connector_funcs tc_connector_funcs = {
1400 .detect = tc_connector_detect,
1401 .fill_modes = drm_helper_probe_single_connector_modes,
1402 .destroy = drm_connector_cleanup,
1403 .reset = drm_atomic_helper_connector_reset,
1404 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1405 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1406};
1407
1408static int tc_bridge_attach(struct drm_bridge *bridge,
1409 enum drm_bridge_attach_flags flags)
1410{
1411 u32 bus_format = MEDIA_BUS_FMT_RGB888_1X24;
1412 struct tc_data *tc = bridge_to_tc(bridge);
1413 struct drm_device *drm = bridge->dev;
1414 int ret;
1415
1416 if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) {
1417 DRM_ERROR("Fix bridge driver to make connector optional!");
1418 return -EINVAL;
1419 }
1420
1421 /* Create DP/eDP connector */
1422 drm_connector_helper_add(&tc->connector, &tc_connector_helper_funcs);
1423 ret = drm_connector_init(drm, &tc->connector, &tc_connector_funcs,
1424 tc->panel ? DRM_MODE_CONNECTOR_eDP :
1425 DRM_MODE_CONNECTOR_DisplayPort);
1426 if (ret)
1427 return ret;
1428
1429 /* Don't poll if don't have HPD connected */
1430 if (tc->hpd_pin >= 0) {
1431 if (tc->have_irq)
1432 tc->connector.polled = DRM_CONNECTOR_POLL_HPD;
1433 else
1434 tc->connector.polled = DRM_CONNECTOR_POLL_CONNECT |
1435 DRM_CONNECTOR_POLL_DISCONNECT;
1436 }
1437
1438 if (tc->panel)
1439 drm_panel_attach(tc->panel, &tc->connector);
1440
1441 drm_display_info_set_bus_formats(&tc->connector.display_info,
1442 &bus_format, 1);
1443 tc->connector.display_info.bus_flags =
1444 DRM_BUS_FLAG_DE_HIGH |
1445 DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE |
1446 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE;
1447 drm_connector_attach_encoder(&tc->connector, tc->bridge.encoder);
1448
1449 return 0;
1450}
1451
1452static const struct drm_bridge_funcs tc_bridge_funcs = {
1453 .attach = tc_bridge_attach,
1454 .mode_valid = tc_mode_valid,
1455 .mode_set = tc_bridge_mode_set,
1456 .pre_enable = tc_bridge_pre_enable,
1457 .enable = tc_bridge_enable,
1458 .disable = tc_bridge_disable,
1459 .post_disable = tc_bridge_post_disable,
1460 .mode_fixup = tc_bridge_mode_fixup,
1461};
1462
1463static bool tc_readable_reg(struct device *dev, unsigned int reg)
1464{
1465 return reg != SYSCTRL;
1466}
1467
1468static const struct regmap_range tc_volatile_ranges[] = {
1469 regmap_reg_range(DP0_AUXWDATA(0), DP0_AUXSTATUS),
1470 regmap_reg_range(DP0_LTSTAT, DP0_SNKLTCHGREQ),
1471 regmap_reg_range(DP_PHY_CTRL, DP_PHY_CTRL),
1472 regmap_reg_range(DP0_PLLCTRL, PXL_PLLCTRL),
1473 regmap_reg_range(VFUEN0, VFUEN0),
1474 regmap_reg_range(INTSTS_G, INTSTS_G),
1475 regmap_reg_range(GPIOI, GPIOI),
1476};
1477
1478static const struct regmap_access_table tc_volatile_table = {
1479 .yes_ranges = tc_volatile_ranges,
1480 .n_yes_ranges = ARRAY_SIZE(tc_volatile_ranges),
1481};
1482
1483static bool tc_writeable_reg(struct device *dev, unsigned int reg)
1484{
1485 return (reg != TC_IDREG) &&
1486 (reg != DP0_LTSTAT) &&
1487 (reg != DP0_SNKLTCHGREQ);
1488}
1489
1490static const struct regmap_config tc_regmap_config = {
1491 .name = "tc358767",
1492 .reg_bits = 16,
1493 .val_bits = 32,
1494 .reg_stride = 4,
1495 .max_register = PLL_DBG,
1496 .cache_type = REGCACHE_RBTREE,
1497 .readable_reg = tc_readable_reg,
1498 .volatile_table = &tc_volatile_table,
1499 .writeable_reg = tc_writeable_reg,
1500 .reg_format_endian = REGMAP_ENDIAN_BIG,
1501 .val_format_endian = REGMAP_ENDIAN_LITTLE,
1502};
1503
1504static irqreturn_t tc_irq_handler(int irq, void *arg)
1505{
1506 struct tc_data *tc = arg;
1507 u32 val;
1508 int r;
1509
1510 r = regmap_read(tc->regmap, INTSTS_G, &val);
1511 if (r)
1512 return IRQ_NONE;
1513
1514 if (!val)
1515 return IRQ_NONE;
1516
1517 if (val & INT_SYSERR) {
1518 u32 stat = 0;
1519
1520 regmap_read(tc->regmap, SYSSTAT, &stat);
1521
1522 dev_err(tc->dev, "syserr %x\n", stat);
1523 }
1524
1525 if (tc->hpd_pin >= 0 && tc->bridge.dev) {
1526 /*
1527 * H is triggered when the GPIO goes high.
1528 *
1529 * LC is triggered when the GPIO goes low and stays low for
1530 * the duration of LCNT
1531 */
1532 bool h = val & INT_GPIO_H(tc->hpd_pin);
1533 bool lc = val & INT_GPIO_LC(tc->hpd_pin);
1534
1535 dev_dbg(tc->dev, "GPIO%d: %s %s\n", tc->hpd_pin,
1536 h ? "H" : "", lc ? "LC" : "");
1537
1538 if (h || lc)
1539 drm_kms_helper_hotplug_event(tc->bridge.dev);
1540 }
1541
1542 regmap_write(tc->regmap, INTSTS_G, val);
1543
1544 return IRQ_HANDLED;
1545}
1546
1547static int tc_probe(struct i2c_client *client, const struct i2c_device_id *id)
1548{
1549 struct device *dev = &client->dev;
1550 struct tc_data *tc;
1551 int ret;
1552
1553 tc = devm_kzalloc(dev, sizeof(*tc), GFP_KERNEL);
1554 if (!tc)
1555 return -ENOMEM;
1556
1557 tc->dev = dev;
1558
1559 /* port@2 is the output port */
1560 ret = drm_of_find_panel_or_bridge(dev->of_node, 2, 0, &tc->panel, NULL);
1561 if (ret && ret != -ENODEV)
1562 return ret;
1563
1564 /* Shut down GPIO is optional */
1565 tc->sd_gpio = devm_gpiod_get_optional(dev, "shutdown", GPIOD_OUT_HIGH);
1566 if (IS_ERR(tc->sd_gpio))
1567 return PTR_ERR(tc->sd_gpio);
1568
1569 if (tc->sd_gpio) {
1570 gpiod_set_value_cansleep(tc->sd_gpio, 0);
1571 usleep_range(5000, 10000);
1572 }
1573
1574 /* Reset GPIO is optional */
1575 tc->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
1576 if (IS_ERR(tc->reset_gpio))
1577 return PTR_ERR(tc->reset_gpio);
1578
1579 if (tc->reset_gpio) {
1580 gpiod_set_value_cansleep(tc->reset_gpio, 1);
1581 usleep_range(5000, 10000);
1582 }
1583
1584 tc->refclk = devm_clk_get(dev, "ref");
1585 if (IS_ERR(tc->refclk)) {
1586 ret = PTR_ERR(tc->refclk);
1587 dev_err(dev, "Failed to get refclk: %d\n", ret);
1588 return ret;
1589 }
1590
1591 tc->regmap = devm_regmap_init_i2c(client, &tc_regmap_config);
1592 if (IS_ERR(tc->regmap)) {
1593 ret = PTR_ERR(tc->regmap);
1594 dev_err(dev, "Failed to initialize regmap: %d\n", ret);
1595 return ret;
1596 }
1597
1598 ret = of_property_read_u32(dev->of_node, "toshiba,hpd-pin",
1599 &tc->hpd_pin);
1600 if (ret) {
1601 tc->hpd_pin = -ENODEV;
1602 } else {
1603 if (tc->hpd_pin < 0 || tc->hpd_pin > 1) {
1604 dev_err(dev, "failed to parse HPD number\n");
1605 return ret;
1606 }
1607 }
1608
1609 if (client->irq > 0) {
1610 /* enable SysErr */
1611 regmap_write(tc->regmap, INTCTL_G, INT_SYSERR);
1612
1613 ret = devm_request_threaded_irq(dev, client->irq,
1614 NULL, tc_irq_handler,
1615 IRQF_ONESHOT,
1616 "tc358767-irq", tc);
1617 if (ret) {
1618 dev_err(dev, "failed to register dp interrupt\n");
1619 return ret;
1620 }
1621
1622 tc->have_irq = true;
1623 }
1624
1625 ret = regmap_read(tc->regmap, TC_IDREG, &tc->rev);
1626 if (ret) {
1627 dev_err(tc->dev, "can not read device ID: %d\n", ret);
1628 return ret;
1629 }
1630
1631 if ((tc->rev != 0x6601) && (tc->rev != 0x6603)) {
1632 dev_err(tc->dev, "invalid device ID: 0x%08x\n", tc->rev);
1633 return -EINVAL;
1634 }
1635
1636 tc->assr = (tc->rev == 0x6601); /* Enable ASSR for eDP panels */
1637
1638 if (!tc->reset_gpio) {
1639 /*
1640 * If the reset pin isn't present, do a software reset. It isn't
1641 * as thorough as the hardware reset, as we can't reset the I2C
1642 * communication block for obvious reasons, but it's getting the
1643 * chip into a defined state.
1644 */
1645 regmap_update_bits(tc->regmap, SYSRSTENB,
1646 ENBLCD0 | ENBBM | ENBDSIRX | ENBREG | ENBHDCP,
1647 0);
1648 regmap_update_bits(tc->regmap, SYSRSTENB,
1649 ENBLCD0 | ENBBM | ENBDSIRX | ENBREG | ENBHDCP,
1650 ENBLCD0 | ENBBM | ENBDSIRX | ENBREG | ENBHDCP);
1651 usleep_range(5000, 10000);
1652 }
1653
1654 if (tc->hpd_pin >= 0) {
1655 u32 lcnt_reg = tc->hpd_pin == 0 ? INT_GP0_LCNT : INT_GP1_LCNT;
1656 u32 h_lc = INT_GPIO_H(tc->hpd_pin) | INT_GPIO_LC(tc->hpd_pin);
1657
1658 /* Set LCNT to 2ms */
1659 regmap_write(tc->regmap, lcnt_reg,
1660 clk_get_rate(tc->refclk) * 2 / 1000);
1661 /* We need the "alternate" mode for HPD */
1662 regmap_write(tc->regmap, GPIOM, BIT(tc->hpd_pin));
1663
1664 if (tc->have_irq) {
1665 /* enable H & LC */
1666 regmap_update_bits(tc->regmap, INTCTL_G, h_lc, h_lc);
1667 }
1668 }
1669
1670 ret = tc_aux_link_setup(tc);
1671 if (ret)
1672 return ret;
1673
1674 /* Register DP AUX channel */
1675 tc->aux.name = "TC358767 AUX i2c adapter";
1676 tc->aux.dev = tc->dev;
1677 tc->aux.transfer = tc_aux_transfer;
1678 ret = drm_dp_aux_register(&tc->aux);
1679 if (ret)
1680 return ret;
1681
1682 tc->bridge.funcs = &tc_bridge_funcs;
1683 tc->bridge.of_node = dev->of_node;
1684 drm_bridge_add(&tc->bridge);
1685
1686 i2c_set_clientdata(client, tc);
1687
1688 return 0;
1689}
1690
1691static int tc_remove(struct i2c_client *client)
1692{
1693 struct tc_data *tc = i2c_get_clientdata(client);
1694
1695 drm_bridge_remove(&tc->bridge);
1696 drm_dp_aux_unregister(&tc->aux);
1697
1698 return 0;
1699}
1700
1701static const struct i2c_device_id tc358767_i2c_ids[] = {
1702 { "tc358767", 0 },
1703 { }
1704};
1705MODULE_DEVICE_TABLE(i2c, tc358767_i2c_ids);
1706
1707static const struct of_device_id tc358767_of_ids[] = {
1708 { .compatible = "toshiba,tc358767", },
1709 { }
1710};
1711MODULE_DEVICE_TABLE(of, tc358767_of_ids);
1712
1713static struct i2c_driver tc358767_driver = {
1714 .driver = {
1715 .name = "tc358767",
1716 .of_match_table = tc358767_of_ids,
1717 },
1718 .id_table = tc358767_i2c_ids,
1719 .probe = tc_probe,
1720 .remove = tc_remove,
1721};
1722module_i2c_driver(tc358767_driver);
1723
1724MODULE_AUTHOR("Andrey Gusakov <andrey.gusakov@cogentembedded.com>");
1725MODULE_DESCRIPTION("tc358767 eDP encoder driver");
1726MODULE_LICENSE("GPL");
1/*
2 * tc358767 eDP bridge driver
3 *
4 * Copyright (C) 2016 CogentEmbedded Inc
5 * Author: Andrey Gusakov <andrey.gusakov@cogentembedded.com>
6 *
7 * Copyright (C) 2016 Pengutronix, Philipp Zabel <p.zabel@pengutronix.de>
8 *
9 * Copyright (C) 2016 Zodiac Inflight Innovations
10 *
11 * Initially based on: drivers/gpu/drm/i2c/tda998x_drv.c
12 *
13 * Copyright (C) 2012 Texas Instruments
14 * Author: Rob Clark <robdclark@gmail.com>
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 */
26
27#include <linux/clk.h>
28#include <linux/device.h>
29#include <linux/gpio/consumer.h>
30#include <linux/i2c.h>
31#include <linux/kernel.h>
32#include <linux/module.h>
33#include <linux/regmap.h>
34#include <linux/slab.h>
35
36#include <drm/drm_atomic_helper.h>
37#include <drm/drm_crtc_helper.h>
38#include <drm/drm_dp_helper.h>
39#include <drm/drm_edid.h>
40#include <drm/drm_of.h>
41#include <drm/drm_panel.h>
42
43/* Registers */
44
45/* Display Parallel Interface */
46#define DPIPXLFMT 0x0440
47#define VS_POL_ACTIVE_LOW (1 << 10)
48#define HS_POL_ACTIVE_LOW (1 << 9)
49#define DE_POL_ACTIVE_HIGH (0 << 8)
50#define SUB_CFG_TYPE_CONFIG1 (0 << 2) /* LSB aligned */
51#define SUB_CFG_TYPE_CONFIG2 (1 << 2) /* Loosely Packed */
52#define SUB_CFG_TYPE_CONFIG3 (2 << 2) /* LSB aligned 8-bit */
53#define DPI_BPP_RGB888 (0 << 0)
54#define DPI_BPP_RGB666 (1 << 0)
55#define DPI_BPP_RGB565 (2 << 0)
56
57/* Video Path */
58#define VPCTRL0 0x0450
59#define OPXLFMT_RGB666 (0 << 8)
60#define OPXLFMT_RGB888 (1 << 8)
61#define FRMSYNC_DISABLED (0 << 4) /* Video Timing Gen Disabled */
62#define FRMSYNC_ENABLED (1 << 4) /* Video Timing Gen Enabled */
63#define MSF_DISABLED (0 << 0) /* Magic Square FRC disabled */
64#define MSF_ENABLED (1 << 0) /* Magic Square FRC enabled */
65#define HTIM01 0x0454
66#define HTIM02 0x0458
67#define VTIM01 0x045c
68#define VTIM02 0x0460
69#define VFUEN0 0x0464
70#define VFUEN BIT(0) /* Video Frame Timing Upload */
71
72/* System */
73#define TC_IDREG 0x0500
74#define SYSCTRL 0x0510
75#define DP0_AUDSRC_NO_INPUT (0 << 3)
76#define DP0_AUDSRC_I2S_RX (1 << 3)
77#define DP0_VIDSRC_NO_INPUT (0 << 0)
78#define DP0_VIDSRC_DSI_RX (1 << 0)
79#define DP0_VIDSRC_DPI_RX (2 << 0)
80#define DP0_VIDSRC_COLOR_BAR (3 << 0)
81
82/* Control */
83#define DP0CTL 0x0600
84#define VID_MN_GEN BIT(6) /* Auto-generate M/N values */
85#define EF_EN BIT(5) /* Enable Enhanced Framing */
86#define VID_EN BIT(1) /* Video transmission enable */
87#define DP_EN BIT(0) /* Enable DPTX function */
88
89/* Clocks */
90#define DP0_VIDMNGEN0 0x0610
91#define DP0_VIDMNGEN1 0x0614
92#define DP0_VMNGENSTATUS 0x0618
93
94/* Main Channel */
95#define DP0_SECSAMPLE 0x0640
96#define DP0_VIDSYNCDELAY 0x0644
97#define DP0_TOTALVAL 0x0648
98#define DP0_STARTVAL 0x064c
99#define DP0_ACTIVEVAL 0x0650
100#define DP0_SYNCVAL 0x0654
101#define DP0_MISC 0x0658
102#define TU_SIZE_RECOMMENDED (63) /* LSCLK cycles per TU */
103#define BPC_6 (0 << 5)
104#define BPC_8 (1 << 5)
105
106/* AUX channel */
107#define DP0_AUXCFG0 0x0660
108#define DP0_AUXCFG1 0x0664
109#define AUX_RX_FILTER_EN BIT(16)
110
111#define DP0_AUXADDR 0x0668
112#define DP0_AUXWDATA(i) (0x066c + (i) * 4)
113#define DP0_AUXRDATA(i) (0x067c + (i) * 4)
114#define DP0_AUXSTATUS 0x068c
115#define AUX_STATUS_MASK 0xf0
116#define AUX_STATUS_SHIFT 4
117#define AUX_TIMEOUT BIT(1)
118#define AUX_BUSY BIT(0)
119#define DP0_AUXI2CADR 0x0698
120
121/* Link Training */
122#define DP0_SRCCTRL 0x06a0
123#define DP0_SRCCTRL_SCRMBLDIS BIT(13)
124#define DP0_SRCCTRL_EN810B BIT(12)
125#define DP0_SRCCTRL_NOTP (0 << 8)
126#define DP0_SRCCTRL_TP1 (1 << 8)
127#define DP0_SRCCTRL_TP2 (2 << 8)
128#define DP0_SRCCTRL_LANESKEW BIT(7)
129#define DP0_SRCCTRL_SSCG BIT(3)
130#define DP0_SRCCTRL_LANES_1 (0 << 2)
131#define DP0_SRCCTRL_LANES_2 (1 << 2)
132#define DP0_SRCCTRL_BW27 (1 << 1)
133#define DP0_SRCCTRL_BW162 (0 << 1)
134#define DP0_SRCCTRL_AUTOCORRECT BIT(0)
135#define DP0_LTSTAT 0x06d0
136#define LT_LOOPDONE BIT(13)
137#define LT_STATUS_MASK (0x1f << 8)
138#define LT_CHANNEL1_EQ_BITS (DP_CHANNEL_EQ_BITS << 4)
139#define LT_INTERLANE_ALIGN_DONE BIT(3)
140#define LT_CHANNEL0_EQ_BITS (DP_CHANNEL_EQ_BITS)
141#define DP0_SNKLTCHGREQ 0x06d4
142#define DP0_LTLOOPCTRL 0x06d8
143#define DP0_SNKLTCTRL 0x06e4
144
145/* PHY */
146#define DP_PHY_CTRL 0x0800
147#define DP_PHY_RST BIT(28) /* DP PHY Global Soft Reset */
148#define BGREN BIT(25) /* AUX PHY BGR Enable */
149#define PWR_SW_EN BIT(24) /* PHY Power Switch Enable */
150#define PHY_M1_RST BIT(12) /* Reset PHY1 Main Channel */
151#define PHY_RDY BIT(16) /* PHY Main Channels Ready */
152#define PHY_M0_RST BIT(8) /* Reset PHY0 Main Channel */
153#define PHY_A0_EN BIT(1) /* PHY Aux Channel0 Enable */
154#define PHY_M0_EN BIT(0) /* PHY Main Channel0 Enable */
155
156/* PLL */
157#define DP0_PLLCTRL 0x0900
158#define DP1_PLLCTRL 0x0904 /* not defined in DS */
159#define PXL_PLLCTRL 0x0908
160#define PLLUPDATE BIT(2)
161#define PLLBYP BIT(1)
162#define PLLEN BIT(0)
163#define PXL_PLLPARAM 0x0914
164#define IN_SEL_REFCLK (0 << 14)
165#define SYS_PLLPARAM 0x0918
166#define REF_FREQ_38M4 (0 << 8) /* 38.4 MHz */
167#define REF_FREQ_19M2 (1 << 8) /* 19.2 MHz */
168#define REF_FREQ_26M (2 << 8) /* 26 MHz */
169#define REF_FREQ_13M (3 << 8) /* 13 MHz */
170#define SYSCLK_SEL_LSCLK (0 << 4)
171#define LSCLK_DIV_1 (0 << 0)
172#define LSCLK_DIV_2 (1 << 0)
173
174/* Test & Debug */
175#define TSTCTL 0x0a00
176#define PLL_DBG 0x0a04
177
178static bool tc_test_pattern;
179module_param_named(test, tc_test_pattern, bool, 0644);
180
181struct tc_edp_link {
182 struct drm_dp_link base;
183 u8 assr;
184 int scrambler_dis;
185 int spread;
186 int coding8b10b;
187 u8 swing;
188 u8 preemp;
189};
190
191struct tc_data {
192 struct device *dev;
193 struct regmap *regmap;
194 struct drm_dp_aux aux;
195
196 struct drm_bridge bridge;
197 struct drm_connector connector;
198 struct drm_panel *panel;
199
200 /* link settings */
201 struct tc_edp_link link;
202
203 /* display edid */
204 struct edid *edid;
205 /* current mode */
206 struct drm_display_mode *mode;
207
208 u32 rev;
209 u8 assr;
210
211 struct gpio_desc *sd_gpio;
212 struct gpio_desc *reset_gpio;
213 struct clk *refclk;
214};
215
216static inline struct tc_data *aux_to_tc(struct drm_dp_aux *a)
217{
218 return container_of(a, struct tc_data, aux);
219}
220
221static inline struct tc_data *bridge_to_tc(struct drm_bridge *b)
222{
223 return container_of(b, struct tc_data, bridge);
224}
225
226static inline struct tc_data *connector_to_tc(struct drm_connector *c)
227{
228 return container_of(c, struct tc_data, connector);
229}
230
231/* Simple macros to avoid repeated error checks */
232#define tc_write(reg, var) \
233 do { \
234 ret = regmap_write(tc->regmap, reg, var); \
235 if (ret) \
236 goto err; \
237 } while (0)
238#define tc_read(reg, var) \
239 do { \
240 ret = regmap_read(tc->regmap, reg, var); \
241 if (ret) \
242 goto err; \
243 } while (0)
244
245static inline int tc_poll_timeout(struct regmap *map, unsigned int addr,
246 unsigned int cond_mask,
247 unsigned int cond_value,
248 unsigned long sleep_us, u64 timeout_us)
249{
250 ktime_t timeout = ktime_add_us(ktime_get(), timeout_us);
251 unsigned int val;
252 int ret;
253
254 for (;;) {
255 ret = regmap_read(map, addr, &val);
256 if (ret)
257 break;
258 if ((val & cond_mask) == cond_value)
259 break;
260 if (timeout_us && ktime_compare(ktime_get(), timeout) > 0) {
261 ret = regmap_read(map, addr, &val);
262 break;
263 }
264 if (sleep_us)
265 usleep_range((sleep_us >> 2) + 1, sleep_us);
266 }
267 return ret ?: (((val & cond_mask) == cond_value) ? 0 : -ETIMEDOUT);
268}
269
270static int tc_aux_wait_busy(struct tc_data *tc, unsigned int timeout_ms)
271{
272 return tc_poll_timeout(tc->regmap, DP0_AUXSTATUS, AUX_BUSY, 0,
273 1000, 1000 * timeout_ms);
274}
275
276static int tc_aux_get_status(struct tc_data *tc, u8 *reply)
277{
278 int ret;
279 u32 value;
280
281 ret = regmap_read(tc->regmap, DP0_AUXSTATUS, &value);
282 if (ret < 0)
283 return ret;
284 if (value & AUX_BUSY) {
285 if (value & AUX_TIMEOUT) {
286 dev_err(tc->dev, "i2c access timeout!\n");
287 return -ETIMEDOUT;
288 }
289 return -EBUSY;
290 }
291
292 *reply = (value & AUX_STATUS_MASK) >> AUX_STATUS_SHIFT;
293 return 0;
294}
295
296static ssize_t tc_aux_transfer(struct drm_dp_aux *aux,
297 struct drm_dp_aux_msg *msg)
298{
299 struct tc_data *tc = aux_to_tc(aux);
300 size_t size = min_t(size_t, 8, msg->size);
301 u8 request = msg->request & ~DP_AUX_I2C_MOT;
302 u8 *buf = msg->buffer;
303 u32 tmp = 0;
304 int i = 0;
305 int ret;
306
307 if (size == 0)
308 return 0;
309
310 ret = tc_aux_wait_busy(tc, 100);
311 if (ret)
312 goto err;
313
314 if (request == DP_AUX_I2C_WRITE || request == DP_AUX_NATIVE_WRITE) {
315 /* Store data */
316 while (i < size) {
317 if (request == DP_AUX_NATIVE_WRITE)
318 tmp = tmp | (buf[i] << (8 * (i & 0x3)));
319 else
320 tmp = (tmp << 8) | buf[i];
321 i++;
322 if (((i % 4) == 0) || (i == size)) {
323 tc_write(DP0_AUXWDATA((i - 1) >> 2), tmp);
324 tmp = 0;
325 }
326 }
327 } else if (request != DP_AUX_I2C_READ &&
328 request != DP_AUX_NATIVE_READ) {
329 return -EINVAL;
330 }
331
332 /* Store address */
333 tc_write(DP0_AUXADDR, msg->address);
334 /* Start transfer */
335 tc_write(DP0_AUXCFG0, ((size - 1) << 8) | request);
336
337 ret = tc_aux_wait_busy(tc, 100);
338 if (ret)
339 goto err;
340
341 ret = tc_aux_get_status(tc, &msg->reply);
342 if (ret)
343 goto err;
344
345 if (request == DP_AUX_I2C_READ || request == DP_AUX_NATIVE_READ) {
346 /* Read data */
347 while (i < size) {
348 if ((i % 4) == 0)
349 tc_read(DP0_AUXRDATA(i >> 2), &tmp);
350 buf[i] = tmp & 0xff;
351 tmp = tmp >> 8;
352 i++;
353 }
354 }
355
356 return size;
357err:
358 return ret;
359}
360
361static const char * const training_pattern1_errors[] = {
362 "No errors",
363 "Aux write error",
364 "Aux read error",
365 "Max voltage reached error",
366 "Loop counter expired error",
367 "res", "res", "res"
368};
369
370static const char * const training_pattern2_errors[] = {
371 "No errors",
372 "Aux write error",
373 "Aux read error",
374 "Clock recovery failed error",
375 "Loop counter expired error",
376 "res", "res", "res"
377};
378
379static u32 tc_srcctrl(struct tc_data *tc)
380{
381 /*
382 * No training pattern, skew lane 1 data by two LSCLK cycles with
383 * respect to lane 0 data, AutoCorrect Mode = 0
384 */
385 u32 reg = DP0_SRCCTRL_NOTP | DP0_SRCCTRL_LANESKEW;
386
387 if (tc->link.scrambler_dis)
388 reg |= DP0_SRCCTRL_SCRMBLDIS; /* Scrambler Disabled */
389 if (tc->link.coding8b10b)
390 /* Enable 8/10B Encoder (TxData[19:16] not used) */
391 reg |= DP0_SRCCTRL_EN810B;
392 if (tc->link.spread)
393 reg |= DP0_SRCCTRL_SSCG; /* Spread Spectrum Enable */
394 if (tc->link.base.num_lanes == 2)
395 reg |= DP0_SRCCTRL_LANES_2; /* Two Main Channel Lanes */
396 if (tc->link.base.rate != 162000)
397 reg |= DP0_SRCCTRL_BW27; /* 2.7 Gbps link */
398 return reg;
399}
400
401static void tc_wait_pll_lock(struct tc_data *tc)
402{
403 /* Wait for PLL to lock: up to 2.09 ms, depending on refclk */
404 usleep_range(3000, 6000);
405}
406
407static int tc_pxl_pll_en(struct tc_data *tc, u32 refclk, u32 pixelclock)
408{
409 int ret;
410 int i_pre, best_pre = 1;
411 int i_post, best_post = 1;
412 int div, best_div = 1;
413 int mul, best_mul = 1;
414 int delta, best_delta;
415 int ext_div[] = {1, 2, 3, 5, 7};
416 int best_pixelclock = 0;
417 int vco_hi = 0;
418
419 dev_dbg(tc->dev, "PLL: requested %d pixelclock, ref %d\n", pixelclock,
420 refclk);
421 best_delta = pixelclock;
422 /* Loop over all possible ext_divs, skipping invalid configurations */
423 for (i_pre = 0; i_pre < ARRAY_SIZE(ext_div); i_pre++) {
424 /*
425 * refclk / ext_pre_div should be in the 1 to 200 MHz range.
426 * We don't allow any refclk > 200 MHz, only check lower bounds.
427 */
428 if (refclk / ext_div[i_pre] < 1000000)
429 continue;
430 for (i_post = 0; i_post < ARRAY_SIZE(ext_div); i_post++) {
431 for (div = 1; div <= 16; div++) {
432 u32 clk;
433 u64 tmp;
434
435 tmp = pixelclock * ext_div[i_pre] *
436 ext_div[i_post] * div;
437 do_div(tmp, refclk);
438 mul = tmp;
439
440 /* Check limits */
441 if ((mul < 1) || (mul > 128))
442 continue;
443
444 clk = (refclk / ext_div[i_pre] / div) * mul;
445 /*
446 * refclk * mul / (ext_pre_div * pre_div)
447 * should be in the 150 to 650 MHz range
448 */
449 if ((clk > 650000000) || (clk < 150000000))
450 continue;
451
452 clk = clk / ext_div[i_post];
453 delta = clk - pixelclock;
454
455 if (abs(delta) < abs(best_delta)) {
456 best_pre = i_pre;
457 best_post = i_post;
458 best_div = div;
459 best_mul = mul;
460 best_delta = delta;
461 best_pixelclock = clk;
462 }
463 }
464 }
465 }
466 if (best_pixelclock == 0) {
467 dev_err(tc->dev, "Failed to calc clock for %d pixelclock\n",
468 pixelclock);
469 return -EINVAL;
470 }
471
472 dev_dbg(tc->dev, "PLL: got %d, delta %d\n", best_pixelclock,
473 best_delta);
474 dev_dbg(tc->dev, "PLL: %d / %d / %d * %d / %d\n", refclk,
475 ext_div[best_pre], best_div, best_mul, ext_div[best_post]);
476
477 /* if VCO >= 300 MHz */
478 if (refclk / ext_div[best_pre] / best_div * best_mul >= 300000000)
479 vco_hi = 1;
480 /* see DS */
481 if (best_div == 16)
482 best_div = 0;
483 if (best_mul == 128)
484 best_mul = 0;
485
486 /* Power up PLL and switch to bypass */
487 tc_write(PXL_PLLCTRL, PLLBYP | PLLEN);
488
489 tc_write(PXL_PLLPARAM,
490 (vco_hi << 24) | /* For PLL VCO >= 300 MHz = 1 */
491 (ext_div[best_pre] << 20) | /* External Pre-divider */
492 (ext_div[best_post] << 16) | /* External Post-divider */
493 IN_SEL_REFCLK | /* Use RefClk as PLL input */
494 (best_div << 8) | /* Divider for PLL RefClk */
495 (best_mul << 0)); /* Multiplier for PLL */
496
497 /* Force PLL parameter update and disable bypass */
498 tc_write(PXL_PLLCTRL, PLLUPDATE | PLLEN);
499
500 tc_wait_pll_lock(tc);
501
502 return 0;
503err:
504 return ret;
505}
506
507static int tc_pxl_pll_dis(struct tc_data *tc)
508{
509 /* Enable PLL bypass, power down PLL */
510 return regmap_write(tc->regmap, PXL_PLLCTRL, PLLBYP);
511}
512
513static int tc_stream_clock_calc(struct tc_data *tc)
514{
515 int ret;
516 /*
517 * If the Stream clock and Link Symbol clock are
518 * asynchronous with each other, the value of M changes over
519 * time. This way of generating link clock and stream
520 * clock is called Asynchronous Clock mode. The value M
521 * must change while the value N stays constant. The
522 * value of N in this Asynchronous Clock mode must be set
523 * to 2^15 or 32,768.
524 *
525 * LSCLK = 1/10 of high speed link clock
526 *
527 * f_STRMCLK = M/N * f_LSCLK
528 * M/N = f_STRMCLK / f_LSCLK
529 *
530 */
531 tc_write(DP0_VIDMNGEN1, 32768);
532
533 return 0;
534err:
535 return ret;
536}
537
538static int tc_aux_link_setup(struct tc_data *tc)
539{
540 unsigned long rate;
541 u32 value;
542 int ret;
543
544 rate = clk_get_rate(tc->refclk);
545 switch (rate) {
546 case 38400000:
547 value = REF_FREQ_38M4;
548 break;
549 case 26000000:
550 value = REF_FREQ_26M;
551 break;
552 case 19200000:
553 value = REF_FREQ_19M2;
554 break;
555 case 13000000:
556 value = REF_FREQ_13M;
557 break;
558 default:
559 dev_err(tc->dev, "Invalid refclk rate: %lu Hz\n", rate);
560 return -EINVAL;
561 }
562
563 /* Setup DP-PHY / PLL */
564 value |= SYSCLK_SEL_LSCLK | LSCLK_DIV_2;
565 tc_write(SYS_PLLPARAM, value);
566
567 tc_write(DP_PHY_CTRL, BGREN | PWR_SW_EN | BIT(2) | PHY_A0_EN);
568
569 /*
570 * Initially PLLs are in bypass. Force PLL parameter update,
571 * disable PLL bypass, enable PLL
572 */
573 tc_write(DP0_PLLCTRL, PLLUPDATE | PLLEN);
574 tc_wait_pll_lock(tc);
575
576 tc_write(DP1_PLLCTRL, PLLUPDATE | PLLEN);
577 tc_wait_pll_lock(tc);
578
579 ret = tc_poll_timeout(tc->regmap, DP_PHY_CTRL, PHY_RDY, PHY_RDY, 1,
580 1000);
581 if (ret == -ETIMEDOUT) {
582 dev_err(tc->dev, "Timeout waiting for PHY to become ready");
583 return ret;
584 } else if (ret)
585 goto err;
586
587 /* Setup AUX link */
588 tc_write(DP0_AUXCFG1, AUX_RX_FILTER_EN |
589 (0x06 << 8) | /* Aux Bit Period Calculator Threshold */
590 (0x3f << 0)); /* Aux Response Timeout Timer */
591
592 return 0;
593err:
594 dev_err(tc->dev, "tc_aux_link_setup failed: %d\n", ret);
595 return ret;
596}
597
598static int tc_get_display_props(struct tc_data *tc)
599{
600 int ret;
601 /* temp buffer */
602 u8 tmp[8];
603
604 /* Read DP Rx Link Capability */
605 ret = drm_dp_link_probe(&tc->aux, &tc->link.base);
606 if (ret < 0)
607 goto err_dpcd_read;
608 if (tc->link.base.rate != 162000 && tc->link.base.rate != 270000) {
609 dev_dbg(tc->dev, "Falling to 2.7 Gbps rate\n");
610 tc->link.base.rate = 270000;
611 }
612
613 if (tc->link.base.num_lanes > 2) {
614 dev_dbg(tc->dev, "Falling to 2 lanes\n");
615 tc->link.base.num_lanes = 2;
616 }
617
618 ret = drm_dp_dpcd_readb(&tc->aux, DP_MAX_DOWNSPREAD, tmp);
619 if (ret < 0)
620 goto err_dpcd_read;
621 tc->link.spread = tmp[0] & BIT(0); /* 0.5% down spread */
622
623 ret = drm_dp_dpcd_readb(&tc->aux, DP_MAIN_LINK_CHANNEL_CODING, tmp);
624 if (ret < 0)
625 goto err_dpcd_read;
626 tc->link.coding8b10b = tmp[0] & BIT(0);
627 tc->link.scrambler_dis = 0;
628 /* read assr */
629 ret = drm_dp_dpcd_readb(&tc->aux, DP_EDP_CONFIGURATION_SET, tmp);
630 if (ret < 0)
631 goto err_dpcd_read;
632 tc->link.assr = tmp[0] & DP_ALTERNATE_SCRAMBLER_RESET_ENABLE;
633
634 dev_dbg(tc->dev, "DPCD rev: %d.%d, rate: %s, lanes: %d, framing: %s\n",
635 tc->link.base.revision >> 4, tc->link.base.revision & 0x0f,
636 (tc->link.base.rate == 162000) ? "1.62Gbps" : "2.7Gbps",
637 tc->link.base.num_lanes,
638 (tc->link.base.capabilities & DP_LINK_CAP_ENHANCED_FRAMING) ?
639 "enhanced" : "non-enhanced");
640 dev_dbg(tc->dev, "ANSI 8B/10B: %d\n", tc->link.coding8b10b);
641 dev_dbg(tc->dev, "Display ASSR: %d, TC358767 ASSR: %d\n",
642 tc->link.assr, tc->assr);
643
644 return 0;
645
646err_dpcd_read:
647 dev_err(tc->dev, "failed to read DPCD: %d\n", ret);
648 return ret;
649}
650
651static int tc_set_video_mode(struct tc_data *tc, struct drm_display_mode *mode)
652{
653 int ret;
654 int vid_sync_dly;
655 int max_tu_symbol;
656
657 int left_margin = mode->htotal - mode->hsync_end;
658 int right_margin = mode->hsync_start - mode->hdisplay;
659 int hsync_len = mode->hsync_end - mode->hsync_start;
660 int upper_margin = mode->vtotal - mode->vsync_end;
661 int lower_margin = mode->vsync_start - mode->vdisplay;
662 int vsync_len = mode->vsync_end - mode->vsync_start;
663
664 /*
665 * Recommended maximum number of symbols transferred in a transfer unit:
666 * DIV_ROUND_UP((input active video bandwidth in bytes) * tu_size,
667 * (output active video bandwidth in bytes))
668 * Must be less than tu_size.
669 */
670 max_tu_symbol = TU_SIZE_RECOMMENDED - 1;
671
672 dev_dbg(tc->dev, "set mode %dx%d\n",
673 mode->hdisplay, mode->vdisplay);
674 dev_dbg(tc->dev, "H margin %d,%d sync %d\n",
675 left_margin, right_margin, hsync_len);
676 dev_dbg(tc->dev, "V margin %d,%d sync %d\n",
677 upper_margin, lower_margin, vsync_len);
678 dev_dbg(tc->dev, "total: %dx%d\n", mode->htotal, mode->vtotal);
679
680
681 /*
682 * LCD Ctl Frame Size
683 * datasheet is not clear of vsdelay in case of DPI
684 * assume we do not need any delay when DPI is a source of
685 * sync signals
686 */
687 tc_write(VPCTRL0, (0 << 20) /* VSDELAY */ |
688 OPXLFMT_RGB888 | FRMSYNC_DISABLED | MSF_DISABLED);
689 tc_write(HTIM01, (ALIGN(left_margin, 2) << 16) | /* H back porch */
690 (ALIGN(hsync_len, 2) << 0)); /* Hsync */
691 tc_write(HTIM02, (ALIGN(right_margin, 2) << 16) | /* H front porch */
692 (ALIGN(mode->hdisplay, 2) << 0)); /* width */
693 tc_write(VTIM01, (upper_margin << 16) | /* V back porch */
694 (vsync_len << 0)); /* Vsync */
695 tc_write(VTIM02, (lower_margin << 16) | /* V front porch */
696 (mode->vdisplay << 0)); /* height */
697 tc_write(VFUEN0, VFUEN); /* update settings */
698
699 /* Test pattern settings */
700 tc_write(TSTCTL,
701 (120 << 24) | /* Red Color component value */
702 (20 << 16) | /* Green Color component value */
703 (99 << 8) | /* Blue Color component value */
704 (1 << 4) | /* Enable I2C Filter */
705 (2 << 0) | /* Color bar Mode */
706 0);
707
708 /* DP Main Stream Attributes */
709 vid_sync_dly = hsync_len + left_margin + mode->hdisplay;
710 tc_write(DP0_VIDSYNCDELAY,
711 (max_tu_symbol << 16) | /* thresh_dly */
712 (vid_sync_dly << 0));
713
714 tc_write(DP0_TOTALVAL, (mode->vtotal << 16) | (mode->htotal));
715
716 tc_write(DP0_STARTVAL,
717 ((upper_margin + vsync_len) << 16) |
718 ((left_margin + hsync_len) << 0));
719
720 tc_write(DP0_ACTIVEVAL, (mode->vdisplay << 16) | (mode->hdisplay));
721
722 tc_write(DP0_SYNCVAL, (vsync_len << 16) | (hsync_len << 0));
723
724 tc_write(DPIPXLFMT, VS_POL_ACTIVE_LOW | HS_POL_ACTIVE_LOW |
725 DE_POL_ACTIVE_HIGH | SUB_CFG_TYPE_CONFIG1 | DPI_BPP_RGB888);
726
727 tc_write(DP0_MISC, (max_tu_symbol << 23) | (TU_SIZE_RECOMMENDED << 16) |
728 BPC_8);
729
730 return 0;
731err:
732 return ret;
733}
734
735static int tc_link_training(struct tc_data *tc, int pattern)
736{
737 const char * const *errors;
738 u32 srcctrl = tc_srcctrl(tc) | DP0_SRCCTRL_SCRMBLDIS |
739 DP0_SRCCTRL_AUTOCORRECT;
740 int timeout;
741 int retry;
742 u32 value;
743 int ret;
744
745 if (pattern == DP_TRAINING_PATTERN_1) {
746 srcctrl |= DP0_SRCCTRL_TP1;
747 errors = training_pattern1_errors;
748 } else {
749 srcctrl |= DP0_SRCCTRL_TP2;
750 errors = training_pattern2_errors;
751 }
752
753 /* Set DPCD 0x102 for Training Part 1 or 2 */
754 tc_write(DP0_SNKLTCTRL, DP_LINK_SCRAMBLING_DISABLE | pattern);
755
756 tc_write(DP0_LTLOOPCTRL,
757 (0x0f << 28) | /* Defer Iteration Count */
758 (0x0f << 24) | /* Loop Iteration Count */
759 (0x0d << 0)); /* Loop Timer Delay */
760
761 retry = 5;
762 do {
763 /* Set DP0 Training Pattern */
764 tc_write(DP0_SRCCTRL, srcctrl);
765
766 /* Enable DP0 to start Link Training */
767 tc_write(DP0CTL, DP_EN);
768
769 /* wait */
770 timeout = 1000;
771 do {
772 tc_read(DP0_LTSTAT, &value);
773 udelay(1);
774 } while ((!(value & LT_LOOPDONE)) && (--timeout));
775 if (timeout == 0) {
776 dev_err(tc->dev, "Link training timeout!\n");
777 } else {
778 int pattern = (value >> 11) & 0x3;
779 int error = (value >> 8) & 0x7;
780
781 dev_dbg(tc->dev,
782 "Link training phase %d done after %d uS: %s\n",
783 pattern, 1000 - timeout, errors[error]);
784 if (pattern == DP_TRAINING_PATTERN_1 && error == 0)
785 break;
786 if (pattern == DP_TRAINING_PATTERN_2) {
787 value &= LT_CHANNEL1_EQ_BITS |
788 LT_INTERLANE_ALIGN_DONE |
789 LT_CHANNEL0_EQ_BITS;
790 /* in case of two lanes */
791 if ((tc->link.base.num_lanes == 2) &&
792 (value == (LT_CHANNEL1_EQ_BITS |
793 LT_INTERLANE_ALIGN_DONE |
794 LT_CHANNEL0_EQ_BITS)))
795 break;
796 /* in case of one line */
797 if ((tc->link.base.num_lanes == 1) &&
798 (value == (LT_INTERLANE_ALIGN_DONE |
799 LT_CHANNEL0_EQ_BITS)))
800 break;
801 }
802 }
803 /* restart */
804 tc_write(DP0CTL, 0);
805 usleep_range(10, 20);
806 } while (--retry);
807 if (retry == 0) {
808 dev_err(tc->dev, "Failed to finish training phase %d\n",
809 pattern);
810 }
811
812 return 0;
813err:
814 return ret;
815}
816
817static int tc_main_link_setup(struct tc_data *tc)
818{
819 struct drm_dp_aux *aux = &tc->aux;
820 struct device *dev = tc->dev;
821 unsigned int rate;
822 u32 dp_phy_ctrl;
823 int timeout;
824 u32 value;
825 int ret;
826 u8 tmp[8];
827
828 /* display mode should be set at this point */
829 if (!tc->mode)
830 return -EINVAL;
831
832 /* from excel file - DP0_SrcCtrl */
833 tc_write(DP0_SRCCTRL, DP0_SRCCTRL_SCRMBLDIS | DP0_SRCCTRL_EN810B |
834 DP0_SRCCTRL_LANESKEW | DP0_SRCCTRL_LANES_2 |
835 DP0_SRCCTRL_BW27 | DP0_SRCCTRL_AUTOCORRECT);
836 /* from excel file - DP1_SrcCtrl */
837 tc_write(0x07a0, 0x00003083);
838
839 rate = clk_get_rate(tc->refclk);
840 switch (rate) {
841 case 38400000:
842 value = REF_FREQ_38M4;
843 break;
844 case 26000000:
845 value = REF_FREQ_26M;
846 break;
847 case 19200000:
848 value = REF_FREQ_19M2;
849 break;
850 case 13000000:
851 value = REF_FREQ_13M;
852 break;
853 default:
854 return -EINVAL;
855 }
856 value |= SYSCLK_SEL_LSCLK | LSCLK_DIV_2;
857 tc_write(SYS_PLLPARAM, value);
858 /* Setup Main Link */
859 dp_phy_ctrl = BGREN | PWR_SW_EN | BIT(2) | PHY_A0_EN | PHY_M0_EN;
860 tc_write(DP_PHY_CTRL, dp_phy_ctrl);
861 msleep(100);
862
863 /* PLL setup */
864 tc_write(DP0_PLLCTRL, PLLUPDATE | PLLEN);
865 tc_wait_pll_lock(tc);
866
867 tc_write(DP1_PLLCTRL, PLLUPDATE | PLLEN);
868 tc_wait_pll_lock(tc);
869
870 /* PXL PLL setup */
871 if (tc_test_pattern) {
872 ret = tc_pxl_pll_en(tc, clk_get_rate(tc->refclk),
873 1000 * tc->mode->clock);
874 if (ret)
875 goto err;
876 }
877
878 /* Reset/Enable Main Links */
879 dp_phy_ctrl |= DP_PHY_RST | PHY_M1_RST | PHY_M0_RST;
880 tc_write(DP_PHY_CTRL, dp_phy_ctrl);
881 usleep_range(100, 200);
882 dp_phy_ctrl &= ~(DP_PHY_RST | PHY_M1_RST | PHY_M0_RST);
883 tc_write(DP_PHY_CTRL, dp_phy_ctrl);
884
885 timeout = 1000;
886 do {
887 tc_read(DP_PHY_CTRL, &value);
888 udelay(1);
889 } while ((!(value & PHY_RDY)) && (--timeout));
890
891 if (timeout == 0) {
892 dev_err(dev, "timeout waiting for phy become ready");
893 return -ETIMEDOUT;
894 }
895
896 /* Set misc: 8 bits per color */
897 ret = regmap_update_bits(tc->regmap, DP0_MISC, BPC_8, BPC_8);
898 if (ret)
899 goto err;
900
901 /*
902 * ASSR mode
903 * on TC358767 side ASSR configured through strap pin
904 * seems there is no way to change this setting from SW
905 *
906 * check is tc configured for same mode
907 */
908 if (tc->assr != tc->link.assr) {
909 dev_dbg(dev, "Trying to set display to ASSR: %d\n",
910 tc->assr);
911 /* try to set ASSR on display side */
912 tmp[0] = tc->assr;
913 ret = drm_dp_dpcd_writeb(aux, DP_EDP_CONFIGURATION_SET, tmp[0]);
914 if (ret < 0)
915 goto err_dpcd_read;
916 /* read back */
917 ret = drm_dp_dpcd_readb(aux, DP_EDP_CONFIGURATION_SET, tmp);
918 if (ret < 0)
919 goto err_dpcd_read;
920
921 if (tmp[0] != tc->assr) {
922 dev_dbg(dev, "Failed to switch display ASSR to %d, falling back to unscrambled mode\n",
923 tc->assr);
924 /* trying with disabled scrambler */
925 tc->link.scrambler_dis = 1;
926 }
927 }
928
929 /* Setup Link & DPRx Config for Training */
930 ret = drm_dp_link_configure(aux, &tc->link.base);
931 if (ret < 0)
932 goto err_dpcd_write;
933
934 /* DOWNSPREAD_CTRL */
935 tmp[0] = tc->link.spread ? DP_SPREAD_AMP_0_5 : 0x00;
936 /* MAIN_LINK_CHANNEL_CODING_SET */
937 tmp[1] = tc->link.coding8b10b ? DP_SET_ANSI_8B10B : 0x00;
938 ret = drm_dp_dpcd_write(aux, DP_DOWNSPREAD_CTRL, tmp, 2);
939 if (ret < 0)
940 goto err_dpcd_write;
941
942 ret = tc_link_training(tc, DP_TRAINING_PATTERN_1);
943 if (ret)
944 goto err;
945
946 ret = tc_link_training(tc, DP_TRAINING_PATTERN_2);
947 if (ret)
948 goto err;
949
950 /* Clear DPCD 0x102 */
951 /* Note: Can Not use DP0_SNKLTCTRL (0x06E4) short cut */
952 tmp[0] = tc->link.scrambler_dis ? DP_LINK_SCRAMBLING_DISABLE : 0x00;
953 ret = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET, tmp[0]);
954 if (ret < 0)
955 goto err_dpcd_write;
956
957 /* Clear Training Pattern, set AutoCorrect Mode = 1 */
958 tc_write(DP0_SRCCTRL, tc_srcctrl(tc) | DP0_SRCCTRL_AUTOCORRECT);
959
960 /* Wait */
961 timeout = 100;
962 do {
963 udelay(1);
964 /* Read DPCD 0x202-0x207 */
965 ret = drm_dp_dpcd_read_link_status(aux, tmp + 2);
966 if (ret < 0)
967 goto err_dpcd_read;
968 } while ((--timeout) &&
969 !(drm_dp_channel_eq_ok(tmp + 2, tc->link.base.num_lanes)));
970
971 if (timeout == 0) {
972 /* Read DPCD 0x200-0x201 */
973 ret = drm_dp_dpcd_read(aux, DP_SINK_COUNT, tmp, 2);
974 if (ret < 0)
975 goto err_dpcd_read;
976 dev_err(dev, "channel(s) EQ not ok\n");
977 dev_info(dev, "0x0200 SINK_COUNT: 0x%02x\n", tmp[0]);
978 dev_info(dev, "0x0201 DEVICE_SERVICE_IRQ_VECTOR: 0x%02x\n",
979 tmp[1]);
980 dev_info(dev, "0x0202 LANE0_1_STATUS: 0x%02x\n", tmp[2]);
981 dev_info(dev, "0x0204 LANE_ALIGN_STATUS_UPDATED: 0x%02x\n",
982 tmp[4]);
983 dev_info(dev, "0x0205 SINK_STATUS: 0x%02x\n", tmp[5]);
984 dev_info(dev, "0x0206 ADJUST_REQUEST_LANE0_1: 0x%02x\n",
985 tmp[6]);
986
987 return -EAGAIN;
988 }
989
990 ret = tc_set_video_mode(tc, tc->mode);
991 if (ret)
992 goto err;
993
994 /* Set M/N */
995 ret = tc_stream_clock_calc(tc);
996 if (ret)
997 goto err;
998
999 return 0;
1000err_dpcd_read:
1001 dev_err(tc->dev, "Failed to read DPCD: %d\n", ret);
1002 return ret;
1003err_dpcd_write:
1004 dev_err(tc->dev, "Failed to write DPCD: %d\n", ret);
1005err:
1006 return ret;
1007}
1008
1009static int tc_main_link_stream(struct tc_data *tc, int state)
1010{
1011 int ret;
1012 u32 value;
1013
1014 dev_dbg(tc->dev, "stream: %d\n", state);
1015
1016 if (state) {
1017 value = VID_MN_GEN | DP_EN;
1018 if (tc->link.base.capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
1019 value |= EF_EN;
1020 tc_write(DP0CTL, value);
1021 /*
1022 * VID_EN assertion should be delayed by at least N * LSCLK
1023 * cycles from the time VID_MN_GEN is enabled in order to
1024 * generate stable values for VID_M. LSCLK is 270 MHz or
1025 * 162 MHz, VID_N is set to 32768 in tc_stream_clock_calc(),
1026 * so a delay of at least 203 us should suffice.
1027 */
1028 usleep_range(500, 1000);
1029 value |= VID_EN;
1030 tc_write(DP0CTL, value);
1031 /* Set input interface */
1032 value = DP0_AUDSRC_NO_INPUT;
1033 if (tc_test_pattern)
1034 value |= DP0_VIDSRC_COLOR_BAR;
1035 else
1036 value |= DP0_VIDSRC_DPI_RX;
1037 tc_write(SYSCTRL, value);
1038 } else {
1039 tc_write(DP0CTL, 0);
1040 }
1041
1042 return 0;
1043err:
1044 return ret;
1045}
1046
1047static void tc_bridge_pre_enable(struct drm_bridge *bridge)
1048{
1049 struct tc_data *tc = bridge_to_tc(bridge);
1050
1051 drm_panel_prepare(tc->panel);
1052}
1053
1054static void tc_bridge_enable(struct drm_bridge *bridge)
1055{
1056 struct tc_data *tc = bridge_to_tc(bridge);
1057 int ret;
1058
1059 ret = tc_main_link_setup(tc);
1060 if (ret < 0) {
1061 dev_err(tc->dev, "main link setup error: %d\n", ret);
1062 return;
1063 }
1064
1065 ret = tc_main_link_stream(tc, 1);
1066 if (ret < 0) {
1067 dev_err(tc->dev, "main link stream start error: %d\n", ret);
1068 return;
1069 }
1070
1071 drm_panel_enable(tc->panel);
1072}
1073
1074static void tc_bridge_disable(struct drm_bridge *bridge)
1075{
1076 struct tc_data *tc = bridge_to_tc(bridge);
1077 int ret;
1078
1079 drm_panel_disable(tc->panel);
1080
1081 ret = tc_main_link_stream(tc, 0);
1082 if (ret < 0)
1083 dev_err(tc->dev, "main link stream stop error: %d\n", ret);
1084}
1085
1086static void tc_bridge_post_disable(struct drm_bridge *bridge)
1087{
1088 struct tc_data *tc = bridge_to_tc(bridge);
1089
1090 drm_panel_unprepare(tc->panel);
1091}
1092
1093static bool tc_bridge_mode_fixup(struct drm_bridge *bridge,
1094 const struct drm_display_mode *mode,
1095 struct drm_display_mode *adj)
1096{
1097 /* Fixup sync polarities, both hsync and vsync are active low */
1098 adj->flags = mode->flags;
1099 adj->flags |= (DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
1100 adj->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
1101
1102 return true;
1103}
1104
1105static int tc_connector_mode_valid(struct drm_connector *connector,
1106 struct drm_display_mode *mode)
1107{
1108 /* DPI interface clock limitation: upto 154 MHz */
1109 if (mode->clock > 154000)
1110 return MODE_CLOCK_HIGH;
1111
1112 return MODE_OK;
1113}
1114
1115static void tc_bridge_mode_set(struct drm_bridge *bridge,
1116 struct drm_display_mode *mode,
1117 struct drm_display_mode *adj)
1118{
1119 struct tc_data *tc = bridge_to_tc(bridge);
1120
1121 tc->mode = mode;
1122}
1123
1124static int tc_connector_get_modes(struct drm_connector *connector)
1125{
1126 struct tc_data *tc = connector_to_tc(connector);
1127 struct edid *edid;
1128 unsigned int count;
1129
1130 if (tc->panel && tc->panel->funcs && tc->panel->funcs->get_modes) {
1131 count = tc->panel->funcs->get_modes(tc->panel);
1132 if (count > 0)
1133 return count;
1134 }
1135
1136 edid = drm_get_edid(connector, &tc->aux.ddc);
1137
1138 kfree(tc->edid);
1139 tc->edid = edid;
1140 if (!edid)
1141 return 0;
1142
1143 drm_mode_connector_update_edid_property(connector, edid);
1144 count = drm_add_edid_modes(connector, edid);
1145
1146 return count;
1147}
1148
1149static void tc_connector_set_polling(struct tc_data *tc,
1150 struct drm_connector *connector)
1151{
1152 /* TODO: add support for HPD */
1153 connector->polled = DRM_CONNECTOR_POLL_CONNECT |
1154 DRM_CONNECTOR_POLL_DISCONNECT;
1155}
1156
1157static struct drm_encoder *
1158tc_connector_best_encoder(struct drm_connector *connector)
1159{
1160 struct tc_data *tc = connector_to_tc(connector);
1161
1162 return tc->bridge.encoder;
1163}
1164
1165static const struct drm_connector_helper_funcs tc_connector_helper_funcs = {
1166 .get_modes = tc_connector_get_modes,
1167 .mode_valid = tc_connector_mode_valid,
1168 .best_encoder = tc_connector_best_encoder,
1169};
1170
1171static const struct drm_connector_funcs tc_connector_funcs = {
1172 .fill_modes = drm_helper_probe_single_connector_modes,
1173 .destroy = drm_connector_cleanup,
1174 .reset = drm_atomic_helper_connector_reset,
1175 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1176 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1177};
1178
1179static int tc_bridge_attach(struct drm_bridge *bridge)
1180{
1181 u32 bus_format = MEDIA_BUS_FMT_RGB888_1X24;
1182 struct tc_data *tc = bridge_to_tc(bridge);
1183 struct drm_device *drm = bridge->dev;
1184 int ret;
1185
1186 /* Create eDP connector */
1187 drm_connector_helper_add(&tc->connector, &tc_connector_helper_funcs);
1188 ret = drm_connector_init(drm, &tc->connector, &tc_connector_funcs,
1189 DRM_MODE_CONNECTOR_eDP);
1190 if (ret)
1191 return ret;
1192
1193 if (tc->panel)
1194 drm_panel_attach(tc->panel, &tc->connector);
1195
1196 drm_display_info_set_bus_formats(&tc->connector.display_info,
1197 &bus_format, 1);
1198 drm_mode_connector_attach_encoder(&tc->connector, tc->bridge.encoder);
1199
1200 return 0;
1201}
1202
1203static const struct drm_bridge_funcs tc_bridge_funcs = {
1204 .attach = tc_bridge_attach,
1205 .mode_set = tc_bridge_mode_set,
1206 .pre_enable = tc_bridge_pre_enable,
1207 .enable = tc_bridge_enable,
1208 .disable = tc_bridge_disable,
1209 .post_disable = tc_bridge_post_disable,
1210 .mode_fixup = tc_bridge_mode_fixup,
1211};
1212
1213static bool tc_readable_reg(struct device *dev, unsigned int reg)
1214{
1215 return reg != SYSCTRL;
1216}
1217
1218static const struct regmap_range tc_volatile_ranges[] = {
1219 regmap_reg_range(DP0_AUXWDATA(0), DP0_AUXSTATUS),
1220 regmap_reg_range(DP0_LTSTAT, DP0_SNKLTCHGREQ),
1221 regmap_reg_range(DP_PHY_CTRL, DP_PHY_CTRL),
1222 regmap_reg_range(DP0_PLLCTRL, PXL_PLLCTRL),
1223 regmap_reg_range(VFUEN0, VFUEN0),
1224};
1225
1226static const struct regmap_access_table tc_volatile_table = {
1227 .yes_ranges = tc_volatile_ranges,
1228 .n_yes_ranges = ARRAY_SIZE(tc_volatile_ranges),
1229};
1230
1231static bool tc_writeable_reg(struct device *dev, unsigned int reg)
1232{
1233 return (reg != TC_IDREG) &&
1234 (reg != DP0_LTSTAT) &&
1235 (reg != DP0_SNKLTCHGREQ);
1236}
1237
1238static const struct regmap_config tc_regmap_config = {
1239 .name = "tc358767",
1240 .reg_bits = 16,
1241 .val_bits = 32,
1242 .reg_stride = 4,
1243 .max_register = PLL_DBG,
1244 .cache_type = REGCACHE_RBTREE,
1245 .readable_reg = tc_readable_reg,
1246 .volatile_table = &tc_volatile_table,
1247 .writeable_reg = tc_writeable_reg,
1248 .reg_format_endian = REGMAP_ENDIAN_BIG,
1249 .val_format_endian = REGMAP_ENDIAN_LITTLE,
1250};
1251
1252static int tc_probe(struct i2c_client *client, const struct i2c_device_id *id)
1253{
1254 struct device *dev = &client->dev;
1255 struct tc_data *tc;
1256 int ret;
1257
1258 tc = devm_kzalloc(dev, sizeof(*tc), GFP_KERNEL);
1259 if (!tc)
1260 return -ENOMEM;
1261
1262 tc->dev = dev;
1263
1264 /* port@2 is the output port */
1265 ret = drm_of_find_panel_or_bridge(dev->of_node, 2, 0, &tc->panel, NULL);
1266 if (ret && ret != -ENODEV)
1267 return ret;
1268
1269 /* Shut down GPIO is optional */
1270 tc->sd_gpio = devm_gpiod_get_optional(dev, "shutdown", GPIOD_OUT_HIGH);
1271 if (IS_ERR(tc->sd_gpio))
1272 return PTR_ERR(tc->sd_gpio);
1273
1274 if (tc->sd_gpio) {
1275 gpiod_set_value_cansleep(tc->sd_gpio, 0);
1276 usleep_range(5000, 10000);
1277 }
1278
1279 /* Reset GPIO is optional */
1280 tc->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
1281 if (IS_ERR(tc->reset_gpio))
1282 return PTR_ERR(tc->reset_gpio);
1283
1284 if (tc->reset_gpio) {
1285 gpiod_set_value_cansleep(tc->reset_gpio, 1);
1286 usleep_range(5000, 10000);
1287 }
1288
1289 tc->refclk = devm_clk_get(dev, "ref");
1290 if (IS_ERR(tc->refclk)) {
1291 ret = PTR_ERR(tc->refclk);
1292 dev_err(dev, "Failed to get refclk: %d\n", ret);
1293 return ret;
1294 }
1295
1296 tc->regmap = devm_regmap_init_i2c(client, &tc_regmap_config);
1297 if (IS_ERR(tc->regmap)) {
1298 ret = PTR_ERR(tc->regmap);
1299 dev_err(dev, "Failed to initialize regmap: %d\n", ret);
1300 return ret;
1301 }
1302
1303 ret = regmap_read(tc->regmap, TC_IDREG, &tc->rev);
1304 if (ret) {
1305 dev_err(tc->dev, "can not read device ID: %d\n", ret);
1306 return ret;
1307 }
1308
1309 if ((tc->rev != 0x6601) && (tc->rev != 0x6603)) {
1310 dev_err(tc->dev, "invalid device ID: 0x%08x\n", tc->rev);
1311 return -EINVAL;
1312 }
1313
1314 tc->assr = (tc->rev == 0x6601); /* Enable ASSR for eDP panels */
1315
1316 ret = tc_aux_link_setup(tc);
1317 if (ret)
1318 return ret;
1319
1320 /* Register DP AUX channel */
1321 tc->aux.name = "TC358767 AUX i2c adapter";
1322 tc->aux.dev = tc->dev;
1323 tc->aux.transfer = tc_aux_transfer;
1324 ret = drm_dp_aux_register(&tc->aux);
1325 if (ret)
1326 return ret;
1327
1328 ret = tc_get_display_props(tc);
1329 if (ret)
1330 goto err_unregister_aux;
1331
1332 tc_connector_set_polling(tc, &tc->connector);
1333
1334 tc->bridge.funcs = &tc_bridge_funcs;
1335 tc->bridge.of_node = dev->of_node;
1336 drm_bridge_add(&tc->bridge);
1337
1338 i2c_set_clientdata(client, tc);
1339
1340 return 0;
1341err_unregister_aux:
1342 drm_dp_aux_unregister(&tc->aux);
1343 return ret;
1344}
1345
1346static int tc_remove(struct i2c_client *client)
1347{
1348 struct tc_data *tc = i2c_get_clientdata(client);
1349
1350 drm_bridge_remove(&tc->bridge);
1351 drm_dp_aux_unregister(&tc->aux);
1352
1353 tc_pxl_pll_dis(tc);
1354
1355 return 0;
1356}
1357
1358static const struct i2c_device_id tc358767_i2c_ids[] = {
1359 { "tc358767", 0 },
1360 { }
1361};
1362MODULE_DEVICE_TABLE(i2c, tc358767_i2c_ids);
1363
1364static const struct of_device_id tc358767_of_ids[] = {
1365 { .compatible = "toshiba,tc358767", },
1366 { }
1367};
1368MODULE_DEVICE_TABLE(of, tc358767_of_ids);
1369
1370static struct i2c_driver tc358767_driver = {
1371 .driver = {
1372 .name = "tc358767",
1373 .of_match_table = tc358767_of_ids,
1374 },
1375 .id_table = tc358767_i2c_ids,
1376 .probe = tc_probe,
1377 .remove = tc_remove,
1378};
1379module_i2c_driver(tc358767_driver);
1380
1381MODULE_AUTHOR("Andrey Gusakov <andrey.gusakov@cogentembedded.com>");
1382MODULE_DESCRIPTION("tc358767 eDP encoder driver");
1383MODULE_LICENSE("GPL");