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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Xilinx ZynqMP DPDMA Engine driver
4 *
5 * Copyright (C) 2015 - 2020 Xilinx, Inc.
6 *
7 * Author: Hyun Woo Kwon <hyun.kwon@xilinx.com>
8 */
9
10#include <linux/bitfield.h>
11#include <linux/bits.h>
12#include <linux/clk.h>
13#include <linux/delay.h>
14#include <linux/dmaengine.h>
15#include <linux/dmapool.h>
16#include <linux/interrupt.h>
17#include <linux/module.h>
18#include <linux/of.h>
19#include <linux/of_dma.h>
20#include <linux/platform_device.h>
21#include <linux/sched.h>
22#include <linux/slab.h>
23#include <linux/spinlock.h>
24#include <linux/wait.h>
25
26#include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
27
28#include "../dmaengine.h"
29#include "../virt-dma.h"
30
31/* DPDMA registers */
32#define XILINX_DPDMA_ERR_CTRL 0x000
33#define XILINX_DPDMA_ISR 0x004
34#define XILINX_DPDMA_IMR 0x008
35#define XILINX_DPDMA_IEN 0x00c
36#define XILINX_DPDMA_IDS 0x010
37#define XILINX_DPDMA_INTR_DESC_DONE(n) BIT((n) + 0)
38#define XILINX_DPDMA_INTR_DESC_DONE_MASK GENMASK(5, 0)
39#define XILINX_DPDMA_INTR_NO_OSTAND(n) BIT((n) + 6)
40#define XILINX_DPDMA_INTR_NO_OSTAND_MASK GENMASK(11, 6)
41#define XILINX_DPDMA_INTR_AXI_ERR(n) BIT((n) + 12)
42#define XILINX_DPDMA_INTR_AXI_ERR_MASK GENMASK(17, 12)
43#define XILINX_DPDMA_INTR_DESC_ERR(n) BIT((n) + 16)
44#define XILINX_DPDMA_INTR_DESC_ERR_MASK GENMASK(23, 18)
45#define XILINX_DPDMA_INTR_WR_CMD_FIFO_FULL BIT(24)
46#define XILINX_DPDMA_INTR_WR_DATA_FIFO_FULL BIT(25)
47#define XILINX_DPDMA_INTR_AXI_4K_CROSS BIT(26)
48#define XILINX_DPDMA_INTR_VSYNC BIT(27)
49#define XILINX_DPDMA_INTR_CHAN_ERR_MASK 0x00041000
50#define XILINX_DPDMA_INTR_CHAN_ERR 0x00fff000
51#define XILINX_DPDMA_INTR_GLOBAL_ERR 0x07000000
52#define XILINX_DPDMA_INTR_ERR_ALL 0x07fff000
53#define XILINX_DPDMA_INTR_CHAN_MASK 0x00041041
54#define XILINX_DPDMA_INTR_GLOBAL_MASK 0x0f000000
55#define XILINX_DPDMA_INTR_ALL 0x0fffffff
56#define XILINX_DPDMA_EISR 0x014
57#define XILINX_DPDMA_EIMR 0x018
58#define XILINX_DPDMA_EIEN 0x01c
59#define XILINX_DPDMA_EIDS 0x020
60#define XILINX_DPDMA_EINTR_INV_APB BIT(0)
61#define XILINX_DPDMA_EINTR_RD_AXI_ERR(n) BIT((n) + 1)
62#define XILINX_DPDMA_EINTR_RD_AXI_ERR_MASK GENMASK(6, 1)
63#define XILINX_DPDMA_EINTR_PRE_ERR(n) BIT((n) + 7)
64#define XILINX_DPDMA_EINTR_PRE_ERR_MASK GENMASK(12, 7)
65#define XILINX_DPDMA_EINTR_CRC_ERR(n) BIT((n) + 13)
66#define XILINX_DPDMA_EINTR_CRC_ERR_MASK GENMASK(18, 13)
67#define XILINX_DPDMA_EINTR_WR_AXI_ERR(n) BIT((n) + 19)
68#define XILINX_DPDMA_EINTR_WR_AXI_ERR_MASK GENMASK(24, 19)
69#define XILINX_DPDMA_EINTR_DESC_DONE_ERR(n) BIT((n) + 25)
70#define XILINX_DPDMA_EINTR_DESC_DONE_ERR_MASK GENMASK(30, 25)
71#define XILINX_DPDMA_EINTR_RD_CMD_FIFO_FULL BIT(32)
72#define XILINX_DPDMA_EINTR_CHAN_ERR_MASK 0x02082082
73#define XILINX_DPDMA_EINTR_CHAN_ERR 0x7ffffffe
74#define XILINX_DPDMA_EINTR_GLOBAL_ERR 0x80000001
75#define XILINX_DPDMA_EINTR_ALL 0xffffffff
76#define XILINX_DPDMA_CNTL 0x100
77#define XILINX_DPDMA_GBL 0x104
78#define XILINX_DPDMA_GBL_TRIG_MASK(n) ((n) << 0)
79#define XILINX_DPDMA_GBL_RETRIG_MASK(n) ((n) << 6)
80#define XILINX_DPDMA_ALC0_CNTL 0x108
81#define XILINX_DPDMA_ALC0_STATUS 0x10c
82#define XILINX_DPDMA_ALC0_MAX 0x110
83#define XILINX_DPDMA_ALC0_MIN 0x114
84#define XILINX_DPDMA_ALC0_ACC 0x118
85#define XILINX_DPDMA_ALC0_ACC_TRAN 0x11c
86#define XILINX_DPDMA_ALC1_CNTL 0x120
87#define XILINX_DPDMA_ALC1_STATUS 0x124
88#define XILINX_DPDMA_ALC1_MAX 0x128
89#define XILINX_DPDMA_ALC1_MIN 0x12c
90#define XILINX_DPDMA_ALC1_ACC 0x130
91#define XILINX_DPDMA_ALC1_ACC_TRAN 0x134
92
93/* Channel register */
94#define XILINX_DPDMA_CH_BASE 0x200
95#define XILINX_DPDMA_CH_OFFSET 0x100
96#define XILINX_DPDMA_CH_DESC_START_ADDRE 0x000
97#define XILINX_DPDMA_CH_DESC_START_ADDRE_MASK GENMASK(15, 0)
98#define XILINX_DPDMA_CH_DESC_START_ADDR 0x004
99#define XILINX_DPDMA_CH_DESC_NEXT_ADDRE 0x008
100#define XILINX_DPDMA_CH_DESC_NEXT_ADDR 0x00c
101#define XILINX_DPDMA_CH_PYLD_CUR_ADDRE 0x010
102#define XILINX_DPDMA_CH_PYLD_CUR_ADDR 0x014
103#define XILINX_DPDMA_CH_CNTL 0x018
104#define XILINX_DPDMA_CH_CNTL_ENABLE BIT(0)
105#define XILINX_DPDMA_CH_CNTL_PAUSE BIT(1)
106#define XILINX_DPDMA_CH_CNTL_QOS_DSCR_WR_MASK GENMASK(5, 2)
107#define XILINX_DPDMA_CH_CNTL_QOS_DSCR_RD_MASK GENMASK(9, 6)
108#define XILINX_DPDMA_CH_CNTL_QOS_DATA_RD_MASK GENMASK(13, 10)
109#define XILINX_DPDMA_CH_CNTL_QOS_VID_CLASS 11
110#define XILINX_DPDMA_CH_STATUS 0x01c
111#define XILINX_DPDMA_CH_STATUS_OTRAN_CNT_MASK GENMASK(24, 21)
112#define XILINX_DPDMA_CH_VDO 0x020
113#define XILINX_DPDMA_CH_PYLD_SZ 0x024
114#define XILINX_DPDMA_CH_DESC_ID 0x028
115
116/* DPDMA descriptor fields */
117#define XILINX_DPDMA_DESC_CONTROL_PREEMBLE 0xa5
118#define XILINX_DPDMA_DESC_CONTROL_COMPLETE_INTR BIT(8)
119#define XILINX_DPDMA_DESC_CONTROL_DESC_UPDATE BIT(9)
120#define XILINX_DPDMA_DESC_CONTROL_IGNORE_DONE BIT(10)
121#define XILINX_DPDMA_DESC_CONTROL_FRAG_MODE BIT(18)
122#define XILINX_DPDMA_DESC_CONTROL_LAST BIT(19)
123#define XILINX_DPDMA_DESC_CONTROL_ENABLE_CRC BIT(20)
124#define XILINX_DPDMA_DESC_CONTROL_LAST_OF_FRAME BIT(21)
125#define XILINX_DPDMA_DESC_ID_MASK GENMASK(15, 0)
126#define XILINX_DPDMA_DESC_HSIZE_STRIDE_HSIZE_MASK GENMASK(17, 0)
127#define XILINX_DPDMA_DESC_HSIZE_STRIDE_STRIDE_MASK GENMASK(31, 18)
128#define XILINX_DPDMA_DESC_ADDR_EXT_NEXT_ADDR_MASK GENMASK(15, 0)
129#define XILINX_DPDMA_DESC_ADDR_EXT_SRC_ADDR_MASK GENMASK(31, 16)
130
131#define XILINX_DPDMA_ALIGN_BYTES 256
132#define XILINX_DPDMA_LINESIZE_ALIGN_BITS 128
133
134#define XILINX_DPDMA_NUM_CHAN 6
135
136struct xilinx_dpdma_chan;
137
138/**
139 * struct xilinx_dpdma_hw_desc - DPDMA hardware descriptor
140 * @control: control configuration field
141 * @desc_id: descriptor ID
142 * @xfer_size: transfer size
143 * @hsize_stride: horizontal size and stride
144 * @timestamp_lsb: LSB of time stamp
145 * @timestamp_msb: MSB of time stamp
146 * @addr_ext: upper 16 bit of 48 bit address (next_desc and src_addr)
147 * @next_desc: next descriptor 32 bit address
148 * @src_addr: payload source address (1st page, 32 LSB)
149 * @addr_ext_23: payload source address (3nd and 3rd pages, 16 LSBs)
150 * @addr_ext_45: payload source address (4th and 5th pages, 16 LSBs)
151 * @src_addr2: payload source address (2nd page, 32 LSB)
152 * @src_addr3: payload source address (3rd page, 32 LSB)
153 * @src_addr4: payload source address (4th page, 32 LSB)
154 * @src_addr5: payload source address (5th page, 32 LSB)
155 * @crc: descriptor CRC
156 */
157struct xilinx_dpdma_hw_desc {
158 u32 control;
159 u32 desc_id;
160 u32 xfer_size;
161 u32 hsize_stride;
162 u32 timestamp_lsb;
163 u32 timestamp_msb;
164 u32 addr_ext;
165 u32 next_desc;
166 u32 src_addr;
167 u32 addr_ext_23;
168 u32 addr_ext_45;
169 u32 src_addr2;
170 u32 src_addr3;
171 u32 src_addr4;
172 u32 src_addr5;
173 u32 crc;
174} __aligned(XILINX_DPDMA_ALIGN_BYTES);
175
176/**
177 * struct xilinx_dpdma_sw_desc - DPDMA software descriptor
178 * @hw: DPDMA hardware descriptor
179 * @node: list node for software descriptors
180 * @dma_addr: DMA address of the software descriptor
181 */
182struct xilinx_dpdma_sw_desc {
183 struct xilinx_dpdma_hw_desc hw;
184 struct list_head node;
185 dma_addr_t dma_addr;
186};
187
188/**
189 * struct xilinx_dpdma_tx_desc - DPDMA transaction descriptor
190 * @vdesc: virtual DMA descriptor
191 * @chan: DMA channel
192 * @descriptors: list of software descriptors
193 * @error: an error has been detected with this descriptor
194 */
195struct xilinx_dpdma_tx_desc {
196 struct virt_dma_desc vdesc;
197 struct xilinx_dpdma_chan *chan;
198 struct list_head descriptors;
199 bool error;
200};
201
202#define to_dpdma_tx_desc(_desc) \
203 container_of(_desc, struct xilinx_dpdma_tx_desc, vdesc)
204
205/**
206 * struct xilinx_dpdma_chan - DPDMA channel
207 * @vchan: virtual DMA channel
208 * @reg: register base address
209 * @id: channel ID
210 * @wait_to_stop: queue to wait for outstanding transacitons before stopping
211 * @running: true if the channel is running
212 * @first_frame: flag for the first frame of stream
213 * @video_group: flag if multi-channel operation is needed for video channels
214 * @lock: lock to access struct xilinx_dpdma_chan
215 * @desc_pool: descriptor allocation pool
216 * @err_task: error IRQ bottom half handler
217 * @desc: References to descriptors being processed
218 * @desc.pending: Descriptor schedule to the hardware, pending execution
219 * @desc.active: Descriptor being executed by the hardware
220 * @xdev: DPDMA device
221 */
222struct xilinx_dpdma_chan {
223 struct virt_dma_chan vchan;
224 void __iomem *reg;
225 unsigned int id;
226
227 wait_queue_head_t wait_to_stop;
228 bool running;
229 bool first_frame;
230 bool video_group;
231
232 spinlock_t lock; /* lock to access struct xilinx_dpdma_chan */
233 struct dma_pool *desc_pool;
234 struct tasklet_struct err_task;
235
236 struct {
237 struct xilinx_dpdma_tx_desc *pending;
238 struct xilinx_dpdma_tx_desc *active;
239 } desc;
240
241 struct xilinx_dpdma_device *xdev;
242};
243
244#define to_xilinx_chan(_chan) \
245 container_of(_chan, struct xilinx_dpdma_chan, vchan.chan)
246
247/**
248 * struct xilinx_dpdma_device - DPDMA device
249 * @common: generic dma device structure
250 * @reg: register base address
251 * @dev: generic device structure
252 * @irq: the interrupt number
253 * @axi_clk: axi clock
254 * @chan: DPDMA channels
255 * @ext_addr: flag for 64 bit system (48 bit addressing)
256 */
257struct xilinx_dpdma_device {
258 struct dma_device common;
259 void __iomem *reg;
260 struct device *dev;
261 int irq;
262
263 struct clk *axi_clk;
264 struct xilinx_dpdma_chan *chan[XILINX_DPDMA_NUM_CHAN];
265
266 bool ext_addr;
267};
268
269/* -----------------------------------------------------------------------------
270 * I/O Accessors
271 */
272
273static inline u32 dpdma_read(void __iomem *base, u32 offset)
274{
275 return ioread32(base + offset);
276}
277
278static inline void dpdma_write(void __iomem *base, u32 offset, u32 val)
279{
280 iowrite32(val, base + offset);
281}
282
283static inline void dpdma_clr(void __iomem *base, u32 offset, u32 clr)
284{
285 dpdma_write(base, offset, dpdma_read(base, offset) & ~clr);
286}
287
288static inline void dpdma_set(void __iomem *base, u32 offset, u32 set)
289{
290 dpdma_write(base, offset, dpdma_read(base, offset) | set);
291}
292
293/* -----------------------------------------------------------------------------
294 * Descriptor Operations
295 */
296
297/**
298 * xilinx_dpdma_sw_desc_set_dma_addrs - Set DMA addresses in the descriptor
299 * @xdev: DPDMA device
300 * @sw_desc: The software descriptor in which to set DMA addresses
301 * @prev: The previous descriptor
302 * @dma_addr: array of dma addresses
303 * @num_src_addr: number of addresses in @dma_addr
304 *
305 * Set all the DMA addresses in the hardware descriptor corresponding to @dev
306 * from @dma_addr. If a previous descriptor is specified in @prev, its next
307 * descriptor DMA address is set to the DMA address of @sw_desc. @prev may be
308 * identical to @sw_desc for cyclic transfers.
309 */
310static void xilinx_dpdma_sw_desc_set_dma_addrs(struct xilinx_dpdma_device *xdev,
311 struct xilinx_dpdma_sw_desc *sw_desc,
312 struct xilinx_dpdma_sw_desc *prev,
313 dma_addr_t dma_addr[],
314 unsigned int num_src_addr)
315{
316 struct xilinx_dpdma_hw_desc *hw_desc = &sw_desc->hw;
317 unsigned int i;
318
319 hw_desc->src_addr = lower_32_bits(dma_addr[0]);
320 if (xdev->ext_addr)
321 hw_desc->addr_ext |=
322 FIELD_PREP(XILINX_DPDMA_DESC_ADDR_EXT_SRC_ADDR_MASK,
323 upper_32_bits(dma_addr[0]));
324
325 for (i = 1; i < num_src_addr; i++) {
326 u32 *addr = &hw_desc->src_addr2;
327
328 addr[i-1] = lower_32_bits(dma_addr[i]);
329
330 if (xdev->ext_addr) {
331 u32 *addr_ext = &hw_desc->addr_ext_23;
332 u32 addr_msb;
333
334 addr_msb = upper_32_bits(dma_addr[i]) & GENMASK(15, 0);
335 addr_msb <<= 16 * ((i - 1) % 2);
336 addr_ext[(i - 1) / 2] |= addr_msb;
337 }
338 }
339
340 if (!prev)
341 return;
342
343 prev->hw.next_desc = lower_32_bits(sw_desc->dma_addr);
344 if (xdev->ext_addr)
345 prev->hw.addr_ext |=
346 FIELD_PREP(XILINX_DPDMA_DESC_ADDR_EXT_NEXT_ADDR_MASK,
347 upper_32_bits(sw_desc->dma_addr));
348}
349
350/**
351 * xilinx_dpdma_chan_alloc_sw_desc - Allocate a software descriptor
352 * @chan: DPDMA channel
353 *
354 * Allocate a software descriptor from the channel's descriptor pool.
355 *
356 * Return: a software descriptor or NULL.
357 */
358static struct xilinx_dpdma_sw_desc *
359xilinx_dpdma_chan_alloc_sw_desc(struct xilinx_dpdma_chan *chan)
360{
361 struct xilinx_dpdma_sw_desc *sw_desc;
362 dma_addr_t dma_addr;
363
364 sw_desc = dma_pool_zalloc(chan->desc_pool, GFP_ATOMIC, &dma_addr);
365 if (!sw_desc)
366 return NULL;
367
368 sw_desc->dma_addr = dma_addr;
369
370 return sw_desc;
371}
372
373/**
374 * xilinx_dpdma_chan_free_sw_desc - Free a software descriptor
375 * @chan: DPDMA channel
376 * @sw_desc: software descriptor to free
377 *
378 * Free a software descriptor from the channel's descriptor pool.
379 */
380static void
381xilinx_dpdma_chan_free_sw_desc(struct xilinx_dpdma_chan *chan,
382 struct xilinx_dpdma_sw_desc *sw_desc)
383{
384 dma_pool_free(chan->desc_pool, sw_desc, sw_desc->dma_addr);
385}
386
387/**
388 * xilinx_dpdma_chan_dump_tx_desc - Dump a tx descriptor
389 * @chan: DPDMA channel
390 * @tx_desc: tx descriptor to dump
391 *
392 * Dump contents of a tx descriptor
393 */
394static void xilinx_dpdma_chan_dump_tx_desc(struct xilinx_dpdma_chan *chan,
395 struct xilinx_dpdma_tx_desc *tx_desc)
396{
397 struct xilinx_dpdma_sw_desc *sw_desc;
398 struct device *dev = chan->xdev->dev;
399 unsigned int i = 0;
400
401 dev_dbg(dev, "------- TX descriptor dump start -------\n");
402 dev_dbg(dev, "------- channel ID = %d -------\n", chan->id);
403
404 list_for_each_entry(sw_desc, &tx_desc->descriptors, node) {
405 struct xilinx_dpdma_hw_desc *hw_desc = &sw_desc->hw;
406
407 dev_dbg(dev, "------- HW descriptor %d -------\n", i++);
408 dev_dbg(dev, "descriptor DMA addr: %pad\n", &sw_desc->dma_addr);
409 dev_dbg(dev, "control: 0x%08x\n", hw_desc->control);
410 dev_dbg(dev, "desc_id: 0x%08x\n", hw_desc->desc_id);
411 dev_dbg(dev, "xfer_size: 0x%08x\n", hw_desc->xfer_size);
412 dev_dbg(dev, "hsize_stride: 0x%08x\n", hw_desc->hsize_stride);
413 dev_dbg(dev, "timestamp_lsb: 0x%08x\n", hw_desc->timestamp_lsb);
414 dev_dbg(dev, "timestamp_msb: 0x%08x\n", hw_desc->timestamp_msb);
415 dev_dbg(dev, "addr_ext: 0x%08x\n", hw_desc->addr_ext);
416 dev_dbg(dev, "next_desc: 0x%08x\n", hw_desc->next_desc);
417 dev_dbg(dev, "src_addr: 0x%08x\n", hw_desc->src_addr);
418 dev_dbg(dev, "addr_ext_23: 0x%08x\n", hw_desc->addr_ext_23);
419 dev_dbg(dev, "addr_ext_45: 0x%08x\n", hw_desc->addr_ext_45);
420 dev_dbg(dev, "src_addr2: 0x%08x\n", hw_desc->src_addr2);
421 dev_dbg(dev, "src_addr3: 0x%08x\n", hw_desc->src_addr3);
422 dev_dbg(dev, "src_addr4: 0x%08x\n", hw_desc->src_addr4);
423 dev_dbg(dev, "src_addr5: 0x%08x\n", hw_desc->src_addr5);
424 dev_dbg(dev, "crc: 0x%08x\n", hw_desc->crc);
425 }
426
427 dev_dbg(dev, "------- TX descriptor dump end -------\n");
428}
429
430/**
431 * xilinx_dpdma_chan_alloc_tx_desc - Allocate a transaction descriptor
432 * @chan: DPDMA channel
433 *
434 * Allocate a tx descriptor.
435 *
436 * Return: a tx descriptor or NULL.
437 */
438static struct xilinx_dpdma_tx_desc *
439xilinx_dpdma_chan_alloc_tx_desc(struct xilinx_dpdma_chan *chan)
440{
441 struct xilinx_dpdma_tx_desc *tx_desc;
442
443 tx_desc = kzalloc(sizeof(*tx_desc), GFP_NOWAIT);
444 if (!tx_desc)
445 return NULL;
446
447 INIT_LIST_HEAD(&tx_desc->descriptors);
448 tx_desc->chan = chan;
449 tx_desc->error = false;
450
451 return tx_desc;
452}
453
454/**
455 * xilinx_dpdma_chan_free_tx_desc - Free a virtual DMA descriptor
456 * @vdesc: virtual DMA descriptor
457 *
458 * Free the virtual DMA descriptor @vdesc including its software descriptors.
459 */
460static void xilinx_dpdma_chan_free_tx_desc(struct virt_dma_desc *vdesc)
461{
462 struct xilinx_dpdma_sw_desc *sw_desc, *next;
463 struct xilinx_dpdma_tx_desc *desc;
464
465 if (!vdesc)
466 return;
467
468 desc = to_dpdma_tx_desc(vdesc);
469
470 list_for_each_entry_safe(sw_desc, next, &desc->descriptors, node) {
471 list_del(&sw_desc->node);
472 xilinx_dpdma_chan_free_sw_desc(desc->chan, sw_desc);
473 }
474
475 kfree(desc);
476}
477
478/**
479 * xilinx_dpdma_chan_prep_interleaved_dma - Prepare an interleaved dma
480 * descriptor
481 * @chan: DPDMA channel
482 * @xt: dma interleaved template
483 *
484 * Prepare a tx descriptor including internal software/hardware descriptors
485 * based on @xt.
486 *
487 * Return: A DPDMA TX descriptor on success, or NULL.
488 */
489static struct xilinx_dpdma_tx_desc *
490xilinx_dpdma_chan_prep_interleaved_dma(struct xilinx_dpdma_chan *chan,
491 struct dma_interleaved_template *xt)
492{
493 struct xilinx_dpdma_tx_desc *tx_desc;
494 struct xilinx_dpdma_sw_desc *sw_desc;
495 struct xilinx_dpdma_hw_desc *hw_desc;
496 size_t hsize = xt->sgl[0].size;
497 size_t stride = hsize + xt->sgl[0].icg;
498
499 if (!IS_ALIGNED(xt->src_start, XILINX_DPDMA_ALIGN_BYTES)) {
500 dev_err(chan->xdev->dev, "buffer should be aligned at %d B\n",
501 XILINX_DPDMA_ALIGN_BYTES);
502 return NULL;
503 }
504
505 tx_desc = xilinx_dpdma_chan_alloc_tx_desc(chan);
506 if (!tx_desc)
507 return NULL;
508
509 sw_desc = xilinx_dpdma_chan_alloc_sw_desc(chan);
510 if (!sw_desc) {
511 xilinx_dpdma_chan_free_tx_desc(&tx_desc->vdesc);
512 return NULL;
513 }
514
515 xilinx_dpdma_sw_desc_set_dma_addrs(chan->xdev, sw_desc, sw_desc,
516 &xt->src_start, 1);
517
518 hw_desc = &sw_desc->hw;
519 hsize = ALIGN(hsize, XILINX_DPDMA_LINESIZE_ALIGN_BITS / 8);
520 hw_desc->xfer_size = hsize * xt->numf;
521 hw_desc->hsize_stride =
522 FIELD_PREP(XILINX_DPDMA_DESC_HSIZE_STRIDE_HSIZE_MASK, hsize) |
523 FIELD_PREP(XILINX_DPDMA_DESC_HSIZE_STRIDE_STRIDE_MASK,
524 stride / 16);
525 hw_desc->control |= XILINX_DPDMA_DESC_CONTROL_PREEMBLE;
526 hw_desc->control |= XILINX_DPDMA_DESC_CONTROL_COMPLETE_INTR;
527 hw_desc->control |= XILINX_DPDMA_DESC_CONTROL_IGNORE_DONE;
528 hw_desc->control |= XILINX_DPDMA_DESC_CONTROL_LAST_OF_FRAME;
529
530 list_add_tail(&sw_desc->node, &tx_desc->descriptors);
531
532 return tx_desc;
533}
534
535/* -----------------------------------------------------------------------------
536 * DPDMA Channel Operations
537 */
538
539/**
540 * xilinx_dpdma_chan_enable - Enable the channel
541 * @chan: DPDMA channel
542 *
543 * Enable the channel and its interrupts. Set the QoS values for video class.
544 */
545static void xilinx_dpdma_chan_enable(struct xilinx_dpdma_chan *chan)
546{
547 u32 reg;
548
549 reg = (XILINX_DPDMA_INTR_CHAN_MASK << chan->id)
550 | XILINX_DPDMA_INTR_GLOBAL_MASK;
551 dpdma_write(chan->xdev->reg, XILINX_DPDMA_IEN, reg);
552 reg = (XILINX_DPDMA_EINTR_CHAN_ERR_MASK << chan->id)
553 | XILINX_DPDMA_INTR_GLOBAL_ERR;
554 dpdma_write(chan->xdev->reg, XILINX_DPDMA_EIEN, reg);
555
556 reg = XILINX_DPDMA_CH_CNTL_ENABLE
557 | FIELD_PREP(XILINX_DPDMA_CH_CNTL_QOS_DSCR_WR_MASK,
558 XILINX_DPDMA_CH_CNTL_QOS_VID_CLASS)
559 | FIELD_PREP(XILINX_DPDMA_CH_CNTL_QOS_DSCR_RD_MASK,
560 XILINX_DPDMA_CH_CNTL_QOS_VID_CLASS)
561 | FIELD_PREP(XILINX_DPDMA_CH_CNTL_QOS_DATA_RD_MASK,
562 XILINX_DPDMA_CH_CNTL_QOS_VID_CLASS);
563 dpdma_set(chan->reg, XILINX_DPDMA_CH_CNTL, reg);
564}
565
566/**
567 * xilinx_dpdma_chan_disable - Disable the channel
568 * @chan: DPDMA channel
569 *
570 * Disable the channel and its interrupts.
571 */
572static void xilinx_dpdma_chan_disable(struct xilinx_dpdma_chan *chan)
573{
574 u32 reg;
575
576 reg = XILINX_DPDMA_INTR_CHAN_MASK << chan->id;
577 dpdma_write(chan->xdev->reg, XILINX_DPDMA_IEN, reg);
578 reg = XILINX_DPDMA_EINTR_CHAN_ERR_MASK << chan->id;
579 dpdma_write(chan->xdev->reg, XILINX_DPDMA_EIEN, reg);
580
581 dpdma_clr(chan->reg, XILINX_DPDMA_CH_CNTL, XILINX_DPDMA_CH_CNTL_ENABLE);
582}
583
584/**
585 * xilinx_dpdma_chan_pause - Pause the channel
586 * @chan: DPDMA channel
587 *
588 * Pause the channel.
589 */
590static void xilinx_dpdma_chan_pause(struct xilinx_dpdma_chan *chan)
591{
592 dpdma_set(chan->reg, XILINX_DPDMA_CH_CNTL, XILINX_DPDMA_CH_CNTL_PAUSE);
593}
594
595/**
596 * xilinx_dpdma_chan_unpause - Unpause the channel
597 * @chan: DPDMA channel
598 *
599 * Unpause the channel.
600 */
601static void xilinx_dpdma_chan_unpause(struct xilinx_dpdma_chan *chan)
602{
603 dpdma_clr(chan->reg, XILINX_DPDMA_CH_CNTL, XILINX_DPDMA_CH_CNTL_PAUSE);
604}
605
606static u32 xilinx_dpdma_chan_video_group_ready(struct xilinx_dpdma_chan *chan)
607{
608 struct xilinx_dpdma_device *xdev = chan->xdev;
609 u32 channels = 0;
610 unsigned int i;
611
612 for (i = ZYNQMP_DPDMA_VIDEO0; i <= ZYNQMP_DPDMA_VIDEO2; i++) {
613 if (xdev->chan[i]->video_group && !xdev->chan[i]->running)
614 return 0;
615
616 if (xdev->chan[i]->video_group)
617 channels |= BIT(i);
618 }
619
620 return channels;
621}
622
623/**
624 * xilinx_dpdma_chan_queue_transfer - Queue the next transfer
625 * @chan: DPDMA channel
626 *
627 * Queue the next descriptor, if any, to the hardware. If the channel is
628 * stopped, start it first. Otherwise retrigger it with the next descriptor.
629 */
630static void xilinx_dpdma_chan_queue_transfer(struct xilinx_dpdma_chan *chan)
631{
632 struct xilinx_dpdma_device *xdev = chan->xdev;
633 struct xilinx_dpdma_sw_desc *sw_desc;
634 struct xilinx_dpdma_tx_desc *desc;
635 struct virt_dma_desc *vdesc;
636 u32 reg, channels;
637
638 lockdep_assert_held(&chan->lock);
639
640 if (chan->desc.pending)
641 return;
642
643 if (!chan->running) {
644 xilinx_dpdma_chan_unpause(chan);
645 xilinx_dpdma_chan_enable(chan);
646 chan->first_frame = true;
647 chan->running = true;
648 }
649
650 if (chan->video_group)
651 channels = xilinx_dpdma_chan_video_group_ready(chan);
652 else
653 channels = BIT(chan->id);
654
655 if (!channels)
656 return;
657
658 vdesc = vchan_next_desc(&chan->vchan);
659 if (!vdesc)
660 return;
661
662 desc = to_dpdma_tx_desc(vdesc);
663 chan->desc.pending = desc;
664 list_del(&desc->vdesc.node);
665
666 /*
667 * Assign the cookie to descriptors in this transaction. Only 16 bit
668 * will be used, but it should be enough.
669 */
670 list_for_each_entry(sw_desc, &desc->descriptors, node)
671 sw_desc->hw.desc_id = desc->vdesc.tx.cookie;
672
673 sw_desc = list_first_entry(&desc->descriptors,
674 struct xilinx_dpdma_sw_desc, node);
675 dpdma_write(chan->reg, XILINX_DPDMA_CH_DESC_START_ADDR,
676 lower_32_bits(sw_desc->dma_addr));
677 if (xdev->ext_addr)
678 dpdma_write(chan->reg, XILINX_DPDMA_CH_DESC_START_ADDRE,
679 FIELD_PREP(XILINX_DPDMA_CH_DESC_START_ADDRE_MASK,
680 upper_32_bits(sw_desc->dma_addr)));
681
682 if (chan->first_frame)
683 reg = XILINX_DPDMA_GBL_TRIG_MASK(channels);
684 else
685 reg = XILINX_DPDMA_GBL_RETRIG_MASK(channels);
686
687 chan->first_frame = false;
688
689 dpdma_write(xdev->reg, XILINX_DPDMA_GBL, reg);
690}
691
692/**
693 * xilinx_dpdma_chan_ostand - Number of outstanding transactions
694 * @chan: DPDMA channel
695 *
696 * Read and return the number of outstanding transactions from register.
697 *
698 * Return: Number of outstanding transactions from the status register.
699 */
700static u32 xilinx_dpdma_chan_ostand(struct xilinx_dpdma_chan *chan)
701{
702 return FIELD_GET(XILINX_DPDMA_CH_STATUS_OTRAN_CNT_MASK,
703 dpdma_read(chan->reg, XILINX_DPDMA_CH_STATUS));
704}
705
706/**
707 * xilinx_dpdma_chan_no_ostand - Notify no outstanding transaction event
708 * @chan: DPDMA channel
709 *
710 * Notify waiters for no outstanding event, so waiters can stop the channel
711 * safely. This function is supposed to be called when 'no outstanding'
712 * interrupt is generated. The 'no outstanding' interrupt is disabled and
713 * should be re-enabled when this event is handled. If the channel status
714 * register still shows some number of outstanding transactions, the interrupt
715 * remains enabled.
716 *
717 * Return: 0 on success. On failure, -EWOULDBLOCK if there's still outstanding
718 * transaction(s).
719 */
720static int xilinx_dpdma_chan_notify_no_ostand(struct xilinx_dpdma_chan *chan)
721{
722 u32 cnt;
723
724 cnt = xilinx_dpdma_chan_ostand(chan);
725 if (cnt) {
726 dev_dbg(chan->xdev->dev, "%d outstanding transactions\n", cnt);
727 return -EWOULDBLOCK;
728 }
729
730 /* Disable 'no outstanding' interrupt */
731 dpdma_write(chan->xdev->reg, XILINX_DPDMA_IDS,
732 XILINX_DPDMA_INTR_NO_OSTAND(chan->id));
733 wake_up(&chan->wait_to_stop);
734
735 return 0;
736}
737
738/**
739 * xilinx_dpdma_chan_wait_no_ostand - Wait for the no outstanding irq
740 * @chan: DPDMA channel
741 *
742 * Wait for the no outstanding transaction interrupt. This functions can sleep
743 * for 50ms.
744 *
745 * Return: 0 on success. On failure, -ETIMEOUT for time out, or the error code
746 * from wait_event_interruptible_timeout().
747 */
748static int xilinx_dpdma_chan_wait_no_ostand(struct xilinx_dpdma_chan *chan)
749{
750 int ret;
751
752 /* Wait for a no outstanding transaction interrupt upto 50msec */
753 ret = wait_event_interruptible_timeout(chan->wait_to_stop,
754 !xilinx_dpdma_chan_ostand(chan),
755 msecs_to_jiffies(50));
756 if (ret > 0) {
757 dpdma_write(chan->xdev->reg, XILINX_DPDMA_IEN,
758 XILINX_DPDMA_INTR_NO_OSTAND(chan->id));
759 return 0;
760 }
761
762 dev_err(chan->xdev->dev, "not ready to stop: %d trans\n",
763 xilinx_dpdma_chan_ostand(chan));
764
765 if (ret == 0)
766 return -ETIMEDOUT;
767
768 return ret;
769}
770
771/**
772 * xilinx_dpdma_chan_poll_no_ostand - Poll the outstanding transaction status
773 * @chan: DPDMA channel
774 *
775 * Poll the outstanding transaction status, and return when there's no
776 * outstanding transaction. This functions can be used in the interrupt context
777 * or where the atomicity is required. Calling thread may wait more than 50ms.
778 *
779 * Return: 0 on success, or -ETIMEDOUT.
780 */
781static int xilinx_dpdma_chan_poll_no_ostand(struct xilinx_dpdma_chan *chan)
782{
783 u32 cnt, loop = 50000;
784
785 /* Poll at least for 50ms (20 fps). */
786 do {
787 cnt = xilinx_dpdma_chan_ostand(chan);
788 udelay(1);
789 } while (loop-- > 0 && cnt);
790
791 if (loop) {
792 dpdma_write(chan->xdev->reg, XILINX_DPDMA_IEN,
793 XILINX_DPDMA_INTR_NO_OSTAND(chan->id));
794 return 0;
795 }
796
797 dev_err(chan->xdev->dev, "not ready to stop: %d trans\n",
798 xilinx_dpdma_chan_ostand(chan));
799
800 return -ETIMEDOUT;
801}
802
803/**
804 * xilinx_dpdma_chan_stop - Stop the channel
805 * @chan: DPDMA channel
806 *
807 * Stop a previously paused channel by first waiting for completion of all
808 * outstanding transaction and then disabling the channel.
809 *
810 * Return: 0 on success, or -ETIMEDOUT if the channel failed to stop.
811 */
812static int xilinx_dpdma_chan_stop(struct xilinx_dpdma_chan *chan)
813{
814 unsigned long flags;
815 int ret;
816
817 ret = xilinx_dpdma_chan_wait_no_ostand(chan);
818 if (ret)
819 return ret;
820
821 spin_lock_irqsave(&chan->lock, flags);
822 xilinx_dpdma_chan_disable(chan);
823 chan->running = false;
824 spin_unlock_irqrestore(&chan->lock, flags);
825
826 return 0;
827}
828
829/**
830 * xilinx_dpdma_chan_done_irq - Handle hardware descriptor completion
831 * @chan: DPDMA channel
832 *
833 * Handle completion of the currently active descriptor (@chan->desc.active). As
834 * we currently support cyclic transfers only, this just invokes the cyclic
835 * callback. The descriptor will be completed at the VSYNC interrupt when a new
836 * descriptor replaces it.
837 */
838static void xilinx_dpdma_chan_done_irq(struct xilinx_dpdma_chan *chan)
839{
840 struct xilinx_dpdma_tx_desc *active = chan->desc.active;
841 unsigned long flags;
842
843 spin_lock_irqsave(&chan->lock, flags);
844
845 if (active)
846 vchan_cyclic_callback(&active->vdesc);
847 else
848 dev_warn(chan->xdev->dev,
849 "DONE IRQ with no active descriptor!\n");
850
851 spin_unlock_irqrestore(&chan->lock, flags);
852}
853
854/**
855 * xilinx_dpdma_chan_vsync_irq - Handle hardware descriptor scheduling
856 * @chan: DPDMA channel
857 *
858 * At VSYNC the active descriptor may have been replaced by the pending
859 * descriptor. Detect this through the DESC_ID and perform appropriate
860 * bookkeeping.
861 */
862static void xilinx_dpdma_chan_vsync_irq(struct xilinx_dpdma_chan *chan)
863{
864 struct xilinx_dpdma_tx_desc *pending;
865 struct xilinx_dpdma_sw_desc *sw_desc;
866 unsigned long flags;
867 u32 desc_id;
868
869 spin_lock_irqsave(&chan->lock, flags);
870
871 pending = chan->desc.pending;
872 if (!chan->running || !pending)
873 goto out;
874
875 desc_id = dpdma_read(chan->reg, XILINX_DPDMA_CH_DESC_ID);
876
877 /* If the retrigger raced with vsync, retry at the next frame. */
878 sw_desc = list_first_entry(&pending->descriptors,
879 struct xilinx_dpdma_sw_desc, node);
880 if (sw_desc->hw.desc_id != desc_id)
881 goto out;
882
883 /*
884 * Complete the active descriptor, if any, promote the pending
885 * descriptor to active, and queue the next transfer, if any.
886 */
887 if (chan->desc.active)
888 vchan_cookie_complete(&chan->desc.active->vdesc);
889 chan->desc.active = pending;
890 chan->desc.pending = NULL;
891
892 xilinx_dpdma_chan_queue_transfer(chan);
893
894out:
895 spin_unlock_irqrestore(&chan->lock, flags);
896}
897
898/**
899 * xilinx_dpdma_chan_err - Detect any channel error
900 * @chan: DPDMA channel
901 * @isr: masked Interrupt Status Register
902 * @eisr: Error Interrupt Status Register
903 *
904 * Return: true if any channel error occurs, or false otherwise.
905 */
906static bool
907xilinx_dpdma_chan_err(struct xilinx_dpdma_chan *chan, u32 isr, u32 eisr)
908{
909 if (!chan)
910 return false;
911
912 if (chan->running &&
913 ((isr & (XILINX_DPDMA_INTR_CHAN_ERR_MASK << chan->id)) ||
914 (eisr & (XILINX_DPDMA_EINTR_CHAN_ERR_MASK << chan->id))))
915 return true;
916
917 return false;
918}
919
920/**
921 * xilinx_dpdma_chan_handle_err - DPDMA channel error handling
922 * @chan: DPDMA channel
923 *
924 * This function is called when any channel error or any global error occurs.
925 * The function disables the paused channel by errors and determines
926 * if the current active descriptor can be rescheduled depending on
927 * the descriptor status.
928 */
929static void xilinx_dpdma_chan_handle_err(struct xilinx_dpdma_chan *chan)
930{
931 struct xilinx_dpdma_device *xdev = chan->xdev;
932 struct xilinx_dpdma_tx_desc *active;
933 unsigned long flags;
934
935 spin_lock_irqsave(&chan->lock, flags);
936
937 dev_dbg(xdev->dev, "cur desc addr = 0x%04x%08x\n",
938 dpdma_read(chan->reg, XILINX_DPDMA_CH_DESC_START_ADDRE),
939 dpdma_read(chan->reg, XILINX_DPDMA_CH_DESC_START_ADDR));
940 dev_dbg(xdev->dev, "cur payload addr = 0x%04x%08x\n",
941 dpdma_read(chan->reg, XILINX_DPDMA_CH_PYLD_CUR_ADDRE),
942 dpdma_read(chan->reg, XILINX_DPDMA_CH_PYLD_CUR_ADDR));
943
944 xilinx_dpdma_chan_disable(chan);
945 chan->running = false;
946
947 if (!chan->desc.active)
948 goto out_unlock;
949
950 active = chan->desc.active;
951 chan->desc.active = NULL;
952
953 xilinx_dpdma_chan_dump_tx_desc(chan, active);
954
955 if (active->error)
956 dev_dbg(xdev->dev, "repeated error on desc\n");
957
958 /* Reschedule if there's no new descriptor */
959 if (!chan->desc.pending &&
960 list_empty(&chan->vchan.desc_issued)) {
961 active->error = true;
962 list_add_tail(&active->vdesc.node,
963 &chan->vchan.desc_issued);
964 } else {
965 xilinx_dpdma_chan_free_tx_desc(&active->vdesc);
966 }
967
968out_unlock:
969 spin_unlock_irqrestore(&chan->lock, flags);
970}
971
972/* -----------------------------------------------------------------------------
973 * DMA Engine Operations
974 */
975
976static struct dma_async_tx_descriptor *
977xilinx_dpdma_prep_interleaved_dma(struct dma_chan *dchan,
978 struct dma_interleaved_template *xt,
979 unsigned long flags)
980{
981 struct xilinx_dpdma_chan *chan = to_xilinx_chan(dchan);
982 struct xilinx_dpdma_tx_desc *desc;
983
984 if (xt->dir != DMA_MEM_TO_DEV)
985 return NULL;
986
987 if (!xt->numf || !xt->sgl[0].size)
988 return NULL;
989
990 if (!(flags & DMA_PREP_REPEAT) || !(flags & DMA_PREP_LOAD_EOT))
991 return NULL;
992
993 desc = xilinx_dpdma_chan_prep_interleaved_dma(chan, xt);
994 if (!desc)
995 return NULL;
996
997 vchan_tx_prep(&chan->vchan, &desc->vdesc, flags | DMA_CTRL_ACK);
998
999 return &desc->vdesc.tx;
1000}
1001
1002/**
1003 * xilinx_dpdma_alloc_chan_resources - Allocate resources for the channel
1004 * @dchan: DMA channel
1005 *
1006 * Allocate a descriptor pool for the channel.
1007 *
1008 * Return: 0 on success, or -ENOMEM if failed to allocate a pool.
1009 */
1010static int xilinx_dpdma_alloc_chan_resources(struct dma_chan *dchan)
1011{
1012 struct xilinx_dpdma_chan *chan = to_xilinx_chan(dchan);
1013 size_t align = __alignof__(struct xilinx_dpdma_sw_desc);
1014
1015 chan->desc_pool = dma_pool_create(dev_name(chan->xdev->dev),
1016 chan->xdev->dev,
1017 sizeof(struct xilinx_dpdma_sw_desc),
1018 align, 0);
1019 if (!chan->desc_pool) {
1020 dev_err(chan->xdev->dev,
1021 "failed to allocate a descriptor pool\n");
1022 return -ENOMEM;
1023 }
1024
1025 return 0;
1026}
1027
1028/**
1029 * xilinx_dpdma_free_chan_resources - Free all resources for the channel
1030 * @dchan: DMA channel
1031 *
1032 * Free resources associated with the virtual DMA channel, and destroy the
1033 * descriptor pool.
1034 */
1035static void xilinx_dpdma_free_chan_resources(struct dma_chan *dchan)
1036{
1037 struct xilinx_dpdma_chan *chan = to_xilinx_chan(dchan);
1038
1039 vchan_free_chan_resources(&chan->vchan);
1040
1041 dma_pool_destroy(chan->desc_pool);
1042 chan->desc_pool = NULL;
1043}
1044
1045static void xilinx_dpdma_issue_pending(struct dma_chan *dchan)
1046{
1047 struct xilinx_dpdma_chan *chan = to_xilinx_chan(dchan);
1048 unsigned long flags;
1049
1050 spin_lock_irqsave(&chan->vchan.lock, flags);
1051 if (vchan_issue_pending(&chan->vchan))
1052 xilinx_dpdma_chan_queue_transfer(chan);
1053 spin_unlock_irqrestore(&chan->vchan.lock, flags);
1054}
1055
1056static int xilinx_dpdma_config(struct dma_chan *dchan,
1057 struct dma_slave_config *config)
1058{
1059 struct xilinx_dpdma_chan *chan = to_xilinx_chan(dchan);
1060 unsigned long flags;
1061
1062 /*
1063 * The destination address doesn't need to be specified as the DPDMA is
1064 * hardwired to the destination (the DP controller). The transfer
1065 * width, burst size and port window size are thus meaningless, they're
1066 * fixed both on the DPDMA side and on the DP controller side.
1067 */
1068
1069 spin_lock_irqsave(&chan->lock, flags);
1070
1071 /*
1072 * Abuse the slave_id to indicate that the channel is part of a video
1073 * group.
1074 */
1075 if (chan->id <= ZYNQMP_DPDMA_VIDEO2)
1076 chan->video_group = config->slave_id != 0;
1077
1078 spin_unlock_irqrestore(&chan->lock, flags);
1079
1080 return 0;
1081}
1082
1083static int xilinx_dpdma_pause(struct dma_chan *dchan)
1084{
1085 xilinx_dpdma_chan_pause(to_xilinx_chan(dchan));
1086
1087 return 0;
1088}
1089
1090static int xilinx_dpdma_resume(struct dma_chan *dchan)
1091{
1092 xilinx_dpdma_chan_unpause(to_xilinx_chan(dchan));
1093
1094 return 0;
1095}
1096
1097/**
1098 * xilinx_dpdma_terminate_all - Terminate the channel and descriptors
1099 * @dchan: DMA channel
1100 *
1101 * Pause the channel without waiting for ongoing transfers to complete. Waiting
1102 * for completion is performed by xilinx_dpdma_synchronize() that will disable
1103 * the channel to complete the stop.
1104 *
1105 * All the descriptors associated with the channel that are guaranteed not to
1106 * be touched by the hardware. The pending and active descriptor are not
1107 * touched, and will be freed either upon completion, or by
1108 * xilinx_dpdma_synchronize().
1109 *
1110 * Return: 0 on success, or -ETIMEDOUT if the channel failed to stop.
1111 */
1112static int xilinx_dpdma_terminate_all(struct dma_chan *dchan)
1113{
1114 struct xilinx_dpdma_chan *chan = to_xilinx_chan(dchan);
1115 struct xilinx_dpdma_device *xdev = chan->xdev;
1116 LIST_HEAD(descriptors);
1117 unsigned long flags;
1118 unsigned int i;
1119
1120 /* Pause the channel (including the whole video group if applicable). */
1121 if (chan->video_group) {
1122 for (i = ZYNQMP_DPDMA_VIDEO0; i <= ZYNQMP_DPDMA_VIDEO2; i++) {
1123 if (xdev->chan[i]->video_group &&
1124 xdev->chan[i]->running) {
1125 xilinx_dpdma_chan_pause(xdev->chan[i]);
1126 xdev->chan[i]->video_group = false;
1127 }
1128 }
1129 } else {
1130 xilinx_dpdma_chan_pause(chan);
1131 }
1132
1133 /* Gather all the descriptors we can free and free them. */
1134 spin_lock_irqsave(&chan->vchan.lock, flags);
1135 vchan_get_all_descriptors(&chan->vchan, &descriptors);
1136 spin_unlock_irqrestore(&chan->vchan.lock, flags);
1137
1138 vchan_dma_desc_free_list(&chan->vchan, &descriptors);
1139
1140 return 0;
1141}
1142
1143/**
1144 * xilinx_dpdma_synchronize - Synchronize callback execution
1145 * @dchan: DMA channel
1146 *
1147 * Synchronizing callback execution ensures that all previously issued
1148 * transfers have completed and all associated callbacks have been called and
1149 * have returned.
1150 *
1151 * This function waits for the DMA channel to stop. It assumes it has been
1152 * paused by a previous call to dmaengine_terminate_async(), and that no new
1153 * pending descriptors have been issued with dma_async_issue_pending(). The
1154 * behaviour is undefined otherwise.
1155 */
1156static void xilinx_dpdma_synchronize(struct dma_chan *dchan)
1157{
1158 struct xilinx_dpdma_chan *chan = to_xilinx_chan(dchan);
1159 unsigned long flags;
1160
1161 xilinx_dpdma_chan_stop(chan);
1162
1163 spin_lock_irqsave(&chan->vchan.lock, flags);
1164 if (chan->desc.pending) {
1165 vchan_terminate_vdesc(&chan->desc.pending->vdesc);
1166 chan->desc.pending = NULL;
1167 }
1168 if (chan->desc.active) {
1169 vchan_terminate_vdesc(&chan->desc.active->vdesc);
1170 chan->desc.active = NULL;
1171 }
1172 spin_unlock_irqrestore(&chan->vchan.lock, flags);
1173
1174 vchan_synchronize(&chan->vchan);
1175}
1176
1177/* -----------------------------------------------------------------------------
1178 * Interrupt and Tasklet Handling
1179 */
1180
1181/**
1182 * xilinx_dpdma_err - Detect any global error
1183 * @isr: Interrupt Status Register
1184 * @eisr: Error Interrupt Status Register
1185 *
1186 * Return: True if any global error occurs, or false otherwise.
1187 */
1188static bool xilinx_dpdma_err(u32 isr, u32 eisr)
1189{
1190 if (isr & XILINX_DPDMA_INTR_GLOBAL_ERR ||
1191 eisr & XILINX_DPDMA_EINTR_GLOBAL_ERR)
1192 return true;
1193
1194 return false;
1195}
1196
1197/**
1198 * xilinx_dpdma_handle_err_irq - Handle DPDMA error interrupt
1199 * @xdev: DPDMA device
1200 * @isr: masked Interrupt Status Register
1201 * @eisr: Error Interrupt Status Register
1202 *
1203 * Handle if any error occurs based on @isr and @eisr. This function disables
1204 * corresponding error interrupts, and those should be re-enabled once handling
1205 * is done.
1206 */
1207static void xilinx_dpdma_handle_err_irq(struct xilinx_dpdma_device *xdev,
1208 u32 isr, u32 eisr)
1209{
1210 bool err = xilinx_dpdma_err(isr, eisr);
1211 unsigned int i;
1212
1213 dev_dbg_ratelimited(xdev->dev,
1214 "error irq: isr = 0x%08x, eisr = 0x%08x\n",
1215 isr, eisr);
1216
1217 /* Disable channel error interrupts until errors are handled. */
1218 dpdma_write(xdev->reg, XILINX_DPDMA_IDS,
1219 isr & ~XILINX_DPDMA_INTR_GLOBAL_ERR);
1220 dpdma_write(xdev->reg, XILINX_DPDMA_EIDS,
1221 eisr & ~XILINX_DPDMA_EINTR_GLOBAL_ERR);
1222
1223 for (i = 0; i < ARRAY_SIZE(xdev->chan); i++)
1224 if (err || xilinx_dpdma_chan_err(xdev->chan[i], isr, eisr))
1225 tasklet_schedule(&xdev->chan[i]->err_task);
1226}
1227
1228/**
1229 * xilinx_dpdma_enable_irq - Enable interrupts
1230 * @xdev: DPDMA device
1231 *
1232 * Enable interrupts.
1233 */
1234static void xilinx_dpdma_enable_irq(struct xilinx_dpdma_device *xdev)
1235{
1236 dpdma_write(xdev->reg, XILINX_DPDMA_IEN, XILINX_DPDMA_INTR_ALL);
1237 dpdma_write(xdev->reg, XILINX_DPDMA_EIEN, XILINX_DPDMA_EINTR_ALL);
1238}
1239
1240/**
1241 * xilinx_dpdma_disable_irq - Disable interrupts
1242 * @xdev: DPDMA device
1243 *
1244 * Disable interrupts.
1245 */
1246static void xilinx_dpdma_disable_irq(struct xilinx_dpdma_device *xdev)
1247{
1248 dpdma_write(xdev->reg, XILINX_DPDMA_IDS, XILINX_DPDMA_INTR_ERR_ALL);
1249 dpdma_write(xdev->reg, XILINX_DPDMA_EIDS, XILINX_DPDMA_EINTR_ALL);
1250}
1251
1252/**
1253 * xilinx_dpdma_chan_err_task - Per channel tasklet for error handling
1254 * @data: tasklet data to be casted to DPDMA channel structure
1255 *
1256 * Per channel error handling tasklet. This function waits for the outstanding
1257 * transaction to complete and triggers error handling. After error handling,
1258 * re-enable channel error interrupts, and restart the channel if needed.
1259 */
1260static void xilinx_dpdma_chan_err_task(unsigned long data)
1261{
1262 struct xilinx_dpdma_chan *chan = (struct xilinx_dpdma_chan *)data;
1263 struct xilinx_dpdma_device *xdev = chan->xdev;
1264 unsigned long flags;
1265
1266 /* Proceed error handling even when polling fails. */
1267 xilinx_dpdma_chan_poll_no_ostand(chan);
1268
1269 xilinx_dpdma_chan_handle_err(chan);
1270
1271 dpdma_write(xdev->reg, XILINX_DPDMA_IEN,
1272 XILINX_DPDMA_INTR_CHAN_ERR_MASK << chan->id);
1273 dpdma_write(xdev->reg, XILINX_DPDMA_EIEN,
1274 XILINX_DPDMA_EINTR_CHAN_ERR_MASK << chan->id);
1275
1276 spin_lock_irqsave(&chan->lock, flags);
1277 xilinx_dpdma_chan_queue_transfer(chan);
1278 spin_unlock_irqrestore(&chan->lock, flags);
1279}
1280
1281static irqreturn_t xilinx_dpdma_irq_handler(int irq, void *data)
1282{
1283 struct xilinx_dpdma_device *xdev = data;
1284 unsigned long mask;
1285 unsigned int i;
1286 u32 status;
1287 u32 error;
1288
1289 status = dpdma_read(xdev->reg, XILINX_DPDMA_ISR);
1290 error = dpdma_read(xdev->reg, XILINX_DPDMA_EISR);
1291 if (!status && !error)
1292 return IRQ_NONE;
1293
1294 dpdma_write(xdev->reg, XILINX_DPDMA_ISR, status);
1295 dpdma_write(xdev->reg, XILINX_DPDMA_EISR, error);
1296
1297 if (status & XILINX_DPDMA_INTR_VSYNC) {
1298 /*
1299 * There's a single VSYNC interrupt that needs to be processed
1300 * by each running channel to update the active descriptor.
1301 */
1302 for (i = 0; i < ARRAY_SIZE(xdev->chan); i++) {
1303 struct xilinx_dpdma_chan *chan = xdev->chan[i];
1304
1305 if (chan)
1306 xilinx_dpdma_chan_vsync_irq(chan);
1307 }
1308 }
1309
1310 mask = FIELD_GET(XILINX_DPDMA_INTR_DESC_DONE_MASK, status);
1311 if (mask) {
1312 for_each_set_bit(i, &mask, ARRAY_SIZE(xdev->chan))
1313 xilinx_dpdma_chan_done_irq(xdev->chan[i]);
1314 }
1315
1316 mask = FIELD_GET(XILINX_DPDMA_INTR_NO_OSTAND_MASK, status);
1317 if (mask) {
1318 for_each_set_bit(i, &mask, ARRAY_SIZE(xdev->chan))
1319 xilinx_dpdma_chan_notify_no_ostand(xdev->chan[i]);
1320 }
1321
1322 mask = status & XILINX_DPDMA_INTR_ERR_ALL;
1323 if (mask || error)
1324 xilinx_dpdma_handle_err_irq(xdev, mask, error);
1325
1326 return IRQ_HANDLED;
1327}
1328
1329/* -----------------------------------------------------------------------------
1330 * Initialization & Cleanup
1331 */
1332
1333static int xilinx_dpdma_chan_init(struct xilinx_dpdma_device *xdev,
1334 unsigned int chan_id)
1335{
1336 struct xilinx_dpdma_chan *chan;
1337
1338 chan = devm_kzalloc(xdev->dev, sizeof(*chan), GFP_KERNEL);
1339 if (!chan)
1340 return -ENOMEM;
1341
1342 chan->id = chan_id;
1343 chan->reg = xdev->reg + XILINX_DPDMA_CH_BASE
1344 + XILINX_DPDMA_CH_OFFSET * chan->id;
1345 chan->running = false;
1346 chan->xdev = xdev;
1347
1348 spin_lock_init(&chan->lock);
1349 init_waitqueue_head(&chan->wait_to_stop);
1350
1351 tasklet_init(&chan->err_task, xilinx_dpdma_chan_err_task,
1352 (unsigned long)chan);
1353
1354 chan->vchan.desc_free = xilinx_dpdma_chan_free_tx_desc;
1355 vchan_init(&chan->vchan, &xdev->common);
1356
1357 xdev->chan[chan->id] = chan;
1358
1359 return 0;
1360}
1361
1362static void xilinx_dpdma_chan_remove(struct xilinx_dpdma_chan *chan)
1363{
1364 if (!chan)
1365 return;
1366
1367 tasklet_kill(&chan->err_task);
1368 list_del(&chan->vchan.chan.device_node);
1369}
1370
1371static struct dma_chan *of_dma_xilinx_xlate(struct of_phandle_args *dma_spec,
1372 struct of_dma *ofdma)
1373{
1374 struct xilinx_dpdma_device *xdev = ofdma->of_dma_data;
1375 uint32_t chan_id = dma_spec->args[0];
1376
1377 if (chan_id >= ARRAY_SIZE(xdev->chan))
1378 return NULL;
1379
1380 if (!xdev->chan[chan_id])
1381 return NULL;
1382
1383 return dma_get_slave_channel(&xdev->chan[chan_id]->vchan.chan);
1384}
1385
1386static int xilinx_dpdma_probe(struct platform_device *pdev)
1387{
1388 struct xilinx_dpdma_device *xdev;
1389 struct dma_device *ddev;
1390 unsigned int i;
1391 int ret;
1392
1393 xdev = devm_kzalloc(&pdev->dev, sizeof(*xdev), GFP_KERNEL);
1394 if (!xdev)
1395 return -ENOMEM;
1396
1397 xdev->dev = &pdev->dev;
1398 xdev->ext_addr = sizeof(dma_addr_t) > 4;
1399
1400 INIT_LIST_HEAD(&xdev->common.channels);
1401
1402 platform_set_drvdata(pdev, xdev);
1403
1404 xdev->axi_clk = devm_clk_get(xdev->dev, "axi_clk");
1405 if (IS_ERR(xdev->axi_clk))
1406 return PTR_ERR(xdev->axi_clk);
1407
1408 xdev->reg = devm_platform_ioremap_resource(pdev, 0);
1409 if (IS_ERR(xdev->reg))
1410 return PTR_ERR(xdev->reg);
1411
1412 xdev->irq = platform_get_irq(pdev, 0);
1413 if (xdev->irq < 0) {
1414 dev_err(xdev->dev, "failed to get platform irq\n");
1415 return xdev->irq;
1416 }
1417
1418 ret = request_irq(xdev->irq, xilinx_dpdma_irq_handler, IRQF_SHARED,
1419 dev_name(xdev->dev), xdev);
1420 if (ret) {
1421 dev_err(xdev->dev, "failed to request IRQ\n");
1422 return ret;
1423 }
1424
1425 ddev = &xdev->common;
1426 ddev->dev = &pdev->dev;
1427
1428 dma_cap_set(DMA_SLAVE, ddev->cap_mask);
1429 dma_cap_set(DMA_PRIVATE, ddev->cap_mask);
1430 dma_cap_set(DMA_INTERLEAVE, ddev->cap_mask);
1431 dma_cap_set(DMA_REPEAT, ddev->cap_mask);
1432 dma_cap_set(DMA_LOAD_EOT, ddev->cap_mask);
1433 ddev->copy_align = fls(XILINX_DPDMA_ALIGN_BYTES - 1);
1434
1435 ddev->device_alloc_chan_resources = xilinx_dpdma_alloc_chan_resources;
1436 ddev->device_free_chan_resources = xilinx_dpdma_free_chan_resources;
1437 ddev->device_prep_interleaved_dma = xilinx_dpdma_prep_interleaved_dma;
1438 /* TODO: Can we achieve better granularity ? */
1439 ddev->device_tx_status = dma_cookie_status;
1440 ddev->device_issue_pending = xilinx_dpdma_issue_pending;
1441 ddev->device_config = xilinx_dpdma_config;
1442 ddev->device_pause = xilinx_dpdma_pause;
1443 ddev->device_resume = xilinx_dpdma_resume;
1444 ddev->device_terminate_all = xilinx_dpdma_terminate_all;
1445 ddev->device_synchronize = xilinx_dpdma_synchronize;
1446 ddev->src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED);
1447 ddev->directions = BIT(DMA_MEM_TO_DEV);
1448 ddev->residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR;
1449
1450 for (i = 0; i < ARRAY_SIZE(xdev->chan); ++i) {
1451 ret = xilinx_dpdma_chan_init(xdev, i);
1452 if (ret < 0) {
1453 dev_err(xdev->dev, "failed to initialize channel %u\n",
1454 i);
1455 goto error;
1456 }
1457 }
1458
1459 ret = clk_prepare_enable(xdev->axi_clk);
1460 if (ret) {
1461 dev_err(xdev->dev, "failed to enable the axi clock\n");
1462 goto error;
1463 }
1464
1465 ret = dma_async_device_register(ddev);
1466 if (ret) {
1467 dev_err(xdev->dev, "failed to register the dma device\n");
1468 goto error_dma_async;
1469 }
1470
1471 ret = of_dma_controller_register(xdev->dev->of_node,
1472 of_dma_xilinx_xlate, ddev);
1473 if (ret) {
1474 dev_err(xdev->dev, "failed to register DMA to DT DMA helper\n");
1475 goto error_of_dma;
1476 }
1477
1478 xilinx_dpdma_enable_irq(xdev);
1479
1480 dev_info(&pdev->dev, "Xilinx DPDMA engine is probed\n");
1481
1482 return 0;
1483
1484error_of_dma:
1485 dma_async_device_unregister(ddev);
1486error_dma_async:
1487 clk_disable_unprepare(xdev->axi_clk);
1488error:
1489 for (i = 0; i < ARRAY_SIZE(xdev->chan); i++)
1490 xilinx_dpdma_chan_remove(xdev->chan[i]);
1491
1492 free_irq(xdev->irq, xdev);
1493
1494 return ret;
1495}
1496
1497static int xilinx_dpdma_remove(struct platform_device *pdev)
1498{
1499 struct xilinx_dpdma_device *xdev = platform_get_drvdata(pdev);
1500 unsigned int i;
1501
1502 /* Start by disabling the IRQ to avoid races during cleanup. */
1503 free_irq(xdev->irq, xdev);
1504
1505 xilinx_dpdma_disable_irq(xdev);
1506 of_dma_controller_free(pdev->dev.of_node);
1507 dma_async_device_unregister(&xdev->common);
1508 clk_disable_unprepare(xdev->axi_clk);
1509
1510 for (i = 0; i < ARRAY_SIZE(xdev->chan); i++)
1511 xilinx_dpdma_chan_remove(xdev->chan[i]);
1512
1513 return 0;
1514}
1515
1516static const struct of_device_id xilinx_dpdma_of_match[] = {
1517 { .compatible = "xlnx,zynqmp-dpdma",},
1518 { /* end of table */ },
1519};
1520MODULE_DEVICE_TABLE(of, xilinx_dpdma_of_match);
1521
1522static struct platform_driver xilinx_dpdma_driver = {
1523 .probe = xilinx_dpdma_probe,
1524 .remove = xilinx_dpdma_remove,
1525 .driver = {
1526 .name = "xilinx-zynqmp-dpdma",
1527 .of_match_table = xilinx_dpdma_of_match,
1528 },
1529};
1530
1531module_platform_driver(xilinx_dpdma_driver);
1532
1533MODULE_AUTHOR("Xilinx, Inc.");
1534MODULE_DESCRIPTION("Xilinx ZynqMP DPDMA driver");
1535MODULE_LICENSE("GPL v2");