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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation
4 *
5 * Rewrite, cleanup, new allocation schemes, virtual merging:
6 * Copyright (C) 2004 Olof Johansson, IBM Corporation
7 * and Ben. Herrenschmidt, IBM Corporation
8 *
9 * Dynamic DMA mapping support, bus-independent parts.
10 */
11
12
13#include <linux/init.h>
14#include <linux/types.h>
15#include <linux/slab.h>
16#include <linux/mm.h>
17#include <linux/spinlock.h>
18#include <linux/string.h>
19#include <linux/dma-mapping.h>
20#include <linux/bitmap.h>
21#include <linux/iommu-helper.h>
22#include <linux/crash_dump.h>
23#include <linux/hash.h>
24#include <linux/fault-inject.h>
25#include <linux/pci.h>
26#include <linux/iommu.h>
27#include <linux/sched.h>
28#include <asm/io.h>
29#include <asm/prom.h>
30#include <asm/iommu.h>
31#include <asm/pci-bridge.h>
32#include <asm/machdep.h>
33#include <asm/kdump.h>
34#include <asm/fadump.h>
35#include <asm/vio.h>
36#include <asm/tce.h>
37#include <asm/mmu_context.h>
38
39#define DBG(...)
40
41static int novmerge;
42
43static void __iommu_free(struct iommu_table *, dma_addr_t, unsigned int);
44
45static int __init setup_iommu(char *str)
46{
47 if (!strcmp(str, "novmerge"))
48 novmerge = 1;
49 else if (!strcmp(str, "vmerge"))
50 novmerge = 0;
51 return 1;
52}
53
54__setup("iommu=", setup_iommu);
55
56static DEFINE_PER_CPU(unsigned int, iommu_pool_hash);
57
58/*
59 * We precalculate the hash to avoid doing it on every allocation.
60 *
61 * The hash is important to spread CPUs across all the pools. For example,
62 * on a POWER7 with 4 way SMT we want interrupts on the primary threads and
63 * with 4 pools all primary threads would map to the same pool.
64 */
65static int __init setup_iommu_pool_hash(void)
66{
67 unsigned int i;
68
69 for_each_possible_cpu(i)
70 per_cpu(iommu_pool_hash, i) = hash_32(i, IOMMU_POOL_HASHBITS);
71
72 return 0;
73}
74subsys_initcall(setup_iommu_pool_hash);
75
76#ifdef CONFIG_FAIL_IOMMU
77
78static DECLARE_FAULT_ATTR(fail_iommu);
79
80static int __init setup_fail_iommu(char *str)
81{
82 return setup_fault_attr(&fail_iommu, str);
83}
84__setup("fail_iommu=", setup_fail_iommu);
85
86static bool should_fail_iommu(struct device *dev)
87{
88 return dev->archdata.fail_iommu && should_fail(&fail_iommu, 1);
89}
90
91static int __init fail_iommu_debugfs(void)
92{
93 struct dentry *dir = fault_create_debugfs_attr("fail_iommu",
94 NULL, &fail_iommu);
95
96 return PTR_ERR_OR_ZERO(dir);
97}
98late_initcall(fail_iommu_debugfs);
99
100static ssize_t fail_iommu_show(struct device *dev,
101 struct device_attribute *attr, char *buf)
102{
103 return sprintf(buf, "%d\n", dev->archdata.fail_iommu);
104}
105
106static ssize_t fail_iommu_store(struct device *dev,
107 struct device_attribute *attr, const char *buf,
108 size_t count)
109{
110 int i;
111
112 if (count > 0 && sscanf(buf, "%d", &i) > 0)
113 dev->archdata.fail_iommu = (i == 0) ? 0 : 1;
114
115 return count;
116}
117
118static DEVICE_ATTR_RW(fail_iommu);
119
120static int fail_iommu_bus_notify(struct notifier_block *nb,
121 unsigned long action, void *data)
122{
123 struct device *dev = data;
124
125 if (action == BUS_NOTIFY_ADD_DEVICE) {
126 if (device_create_file(dev, &dev_attr_fail_iommu))
127 pr_warn("Unable to create IOMMU fault injection sysfs "
128 "entries\n");
129 } else if (action == BUS_NOTIFY_DEL_DEVICE) {
130 device_remove_file(dev, &dev_attr_fail_iommu);
131 }
132
133 return 0;
134}
135
136static struct notifier_block fail_iommu_bus_notifier = {
137 .notifier_call = fail_iommu_bus_notify
138};
139
140static int __init fail_iommu_setup(void)
141{
142#ifdef CONFIG_PCI
143 bus_register_notifier(&pci_bus_type, &fail_iommu_bus_notifier);
144#endif
145#ifdef CONFIG_IBMVIO
146 bus_register_notifier(&vio_bus_type, &fail_iommu_bus_notifier);
147#endif
148
149 return 0;
150}
151/*
152 * Must execute after PCI and VIO subsystem have initialised but before
153 * devices are probed.
154 */
155arch_initcall(fail_iommu_setup);
156#else
157static inline bool should_fail_iommu(struct device *dev)
158{
159 return false;
160}
161#endif
162
163static unsigned long iommu_range_alloc(struct device *dev,
164 struct iommu_table *tbl,
165 unsigned long npages,
166 unsigned long *handle,
167 unsigned long mask,
168 unsigned int align_order)
169{
170 unsigned long n, end, start;
171 unsigned long limit;
172 int largealloc = npages > 15;
173 int pass = 0;
174 unsigned long align_mask;
175 unsigned long boundary_size;
176 unsigned long flags;
177 unsigned int pool_nr;
178 struct iommu_pool *pool;
179
180 align_mask = (1ull << align_order) - 1;
181
182 /* This allocator was derived from x86_64's bit string search */
183
184 /* Sanity check */
185 if (unlikely(npages == 0)) {
186 if (printk_ratelimit())
187 WARN_ON(1);
188 return DMA_MAPPING_ERROR;
189 }
190
191 if (should_fail_iommu(dev))
192 return DMA_MAPPING_ERROR;
193
194 /*
195 * We don't need to disable preemption here because any CPU can
196 * safely use any IOMMU pool.
197 */
198 pool_nr = raw_cpu_read(iommu_pool_hash) & (tbl->nr_pools - 1);
199
200 if (largealloc)
201 pool = &(tbl->large_pool);
202 else
203 pool = &(tbl->pools[pool_nr]);
204
205 spin_lock_irqsave(&(pool->lock), flags);
206
207again:
208 if ((pass == 0) && handle && *handle &&
209 (*handle >= pool->start) && (*handle < pool->end))
210 start = *handle;
211 else
212 start = pool->hint;
213
214 limit = pool->end;
215
216 /* The case below can happen if we have a small segment appended
217 * to a large, or when the previous alloc was at the very end of
218 * the available space. If so, go back to the initial start.
219 */
220 if (start >= limit)
221 start = pool->start;
222
223 if (limit + tbl->it_offset > mask) {
224 limit = mask - tbl->it_offset + 1;
225 /* If we're constrained on address range, first try
226 * at the masked hint to avoid O(n) search complexity,
227 * but on second pass, start at 0 in pool 0.
228 */
229 if ((start & mask) >= limit || pass > 0) {
230 spin_unlock(&(pool->lock));
231 pool = &(tbl->pools[0]);
232 spin_lock(&(pool->lock));
233 start = pool->start;
234 } else {
235 start &= mask;
236 }
237 }
238
239 if (dev)
240 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
241 1 << tbl->it_page_shift);
242 else
243 boundary_size = ALIGN(1UL << 32, 1 << tbl->it_page_shift);
244 /* 4GB boundary for iseries_hv_alloc and iseries_hv_map */
245
246 n = iommu_area_alloc(tbl->it_map, limit, start, npages, tbl->it_offset,
247 boundary_size >> tbl->it_page_shift, align_mask);
248 if (n == -1) {
249 if (likely(pass == 0)) {
250 /* First try the pool from the start */
251 pool->hint = pool->start;
252 pass++;
253 goto again;
254
255 } else if (pass <= tbl->nr_pools) {
256 /* Now try scanning all the other pools */
257 spin_unlock(&(pool->lock));
258 pool_nr = (pool_nr + 1) & (tbl->nr_pools - 1);
259 pool = &tbl->pools[pool_nr];
260 spin_lock(&(pool->lock));
261 pool->hint = pool->start;
262 pass++;
263 goto again;
264
265 } else {
266 /* Give up */
267 spin_unlock_irqrestore(&(pool->lock), flags);
268 return DMA_MAPPING_ERROR;
269 }
270 }
271
272 end = n + npages;
273
274 /* Bump the hint to a new block for small allocs. */
275 if (largealloc) {
276 /* Don't bump to new block to avoid fragmentation */
277 pool->hint = end;
278 } else {
279 /* Overflow will be taken care of at the next allocation */
280 pool->hint = (end + tbl->it_blocksize - 1) &
281 ~(tbl->it_blocksize - 1);
282 }
283
284 /* Update handle for SG allocations */
285 if (handle)
286 *handle = end;
287
288 spin_unlock_irqrestore(&(pool->lock), flags);
289
290 return n;
291}
292
293static dma_addr_t iommu_alloc(struct device *dev, struct iommu_table *tbl,
294 void *page, unsigned int npages,
295 enum dma_data_direction direction,
296 unsigned long mask, unsigned int align_order,
297 unsigned long attrs)
298{
299 unsigned long entry;
300 dma_addr_t ret = DMA_MAPPING_ERROR;
301 int build_fail;
302
303 entry = iommu_range_alloc(dev, tbl, npages, NULL, mask, align_order);
304
305 if (unlikely(entry == DMA_MAPPING_ERROR))
306 return DMA_MAPPING_ERROR;
307
308 entry += tbl->it_offset; /* Offset into real TCE table */
309 ret = entry << tbl->it_page_shift; /* Set the return dma address */
310
311 /* Put the TCEs in the HW table */
312 build_fail = tbl->it_ops->set(tbl, entry, npages,
313 (unsigned long)page &
314 IOMMU_PAGE_MASK(tbl), direction, attrs);
315
316 /* tbl->it_ops->set() only returns non-zero for transient errors.
317 * Clean up the table bitmap in this case and return
318 * DMA_MAPPING_ERROR. For all other errors the functionality is
319 * not altered.
320 */
321 if (unlikely(build_fail)) {
322 __iommu_free(tbl, ret, npages);
323 return DMA_MAPPING_ERROR;
324 }
325
326 /* Flush/invalidate TLB caches if necessary */
327 if (tbl->it_ops->flush)
328 tbl->it_ops->flush(tbl);
329
330 /* Make sure updates are seen by hardware */
331 mb();
332
333 return ret;
334}
335
336static bool iommu_free_check(struct iommu_table *tbl, dma_addr_t dma_addr,
337 unsigned int npages)
338{
339 unsigned long entry, free_entry;
340
341 entry = dma_addr >> tbl->it_page_shift;
342 free_entry = entry - tbl->it_offset;
343
344 if (((free_entry + npages) > tbl->it_size) ||
345 (entry < tbl->it_offset)) {
346 if (printk_ratelimit()) {
347 printk(KERN_INFO "iommu_free: invalid entry\n");
348 printk(KERN_INFO "\tentry = 0x%lx\n", entry);
349 printk(KERN_INFO "\tdma_addr = 0x%llx\n", (u64)dma_addr);
350 printk(KERN_INFO "\tTable = 0x%llx\n", (u64)tbl);
351 printk(KERN_INFO "\tbus# = 0x%llx\n", (u64)tbl->it_busno);
352 printk(KERN_INFO "\tsize = 0x%llx\n", (u64)tbl->it_size);
353 printk(KERN_INFO "\tstartOff = 0x%llx\n", (u64)tbl->it_offset);
354 printk(KERN_INFO "\tindex = 0x%llx\n", (u64)tbl->it_index);
355 WARN_ON(1);
356 }
357
358 return false;
359 }
360
361 return true;
362}
363
364static struct iommu_pool *get_pool(struct iommu_table *tbl,
365 unsigned long entry)
366{
367 struct iommu_pool *p;
368 unsigned long largepool_start = tbl->large_pool.start;
369
370 /* The large pool is the last pool at the top of the table */
371 if (entry >= largepool_start) {
372 p = &tbl->large_pool;
373 } else {
374 unsigned int pool_nr = entry / tbl->poolsize;
375
376 BUG_ON(pool_nr > tbl->nr_pools);
377 p = &tbl->pools[pool_nr];
378 }
379
380 return p;
381}
382
383static void __iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
384 unsigned int npages)
385{
386 unsigned long entry, free_entry;
387 unsigned long flags;
388 struct iommu_pool *pool;
389
390 entry = dma_addr >> tbl->it_page_shift;
391 free_entry = entry - tbl->it_offset;
392
393 pool = get_pool(tbl, free_entry);
394
395 if (!iommu_free_check(tbl, dma_addr, npages))
396 return;
397
398 tbl->it_ops->clear(tbl, entry, npages);
399
400 spin_lock_irqsave(&(pool->lock), flags);
401 bitmap_clear(tbl->it_map, free_entry, npages);
402 spin_unlock_irqrestore(&(pool->lock), flags);
403}
404
405static void iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
406 unsigned int npages)
407{
408 __iommu_free(tbl, dma_addr, npages);
409
410 /* Make sure TLB cache is flushed if the HW needs it. We do
411 * not do an mb() here on purpose, it is not needed on any of
412 * the current platforms.
413 */
414 if (tbl->it_ops->flush)
415 tbl->it_ops->flush(tbl);
416}
417
418int ppc_iommu_map_sg(struct device *dev, struct iommu_table *tbl,
419 struct scatterlist *sglist, int nelems,
420 unsigned long mask, enum dma_data_direction direction,
421 unsigned long attrs)
422{
423 dma_addr_t dma_next = 0, dma_addr;
424 struct scatterlist *s, *outs, *segstart;
425 int outcount, incount, i, build_fail = 0;
426 unsigned int align;
427 unsigned long handle;
428 unsigned int max_seg_size;
429
430 BUG_ON(direction == DMA_NONE);
431
432 if ((nelems == 0) || !tbl)
433 return 0;
434
435 outs = s = segstart = &sglist[0];
436 outcount = 1;
437 incount = nelems;
438 handle = 0;
439
440 /* Init first segment length for backout at failure */
441 outs->dma_length = 0;
442
443 DBG("sg mapping %d elements:\n", nelems);
444
445 max_seg_size = dma_get_max_seg_size(dev);
446 for_each_sg(sglist, s, nelems, i) {
447 unsigned long vaddr, npages, entry, slen;
448
449 slen = s->length;
450 /* Sanity check */
451 if (slen == 0) {
452 dma_next = 0;
453 continue;
454 }
455 /* Allocate iommu entries for that segment */
456 vaddr = (unsigned long) sg_virt(s);
457 npages = iommu_num_pages(vaddr, slen, IOMMU_PAGE_SIZE(tbl));
458 align = 0;
459 if (tbl->it_page_shift < PAGE_SHIFT && slen >= PAGE_SIZE &&
460 (vaddr & ~PAGE_MASK) == 0)
461 align = PAGE_SHIFT - tbl->it_page_shift;
462 entry = iommu_range_alloc(dev, tbl, npages, &handle,
463 mask >> tbl->it_page_shift, align);
464
465 DBG(" - vaddr: %lx, size: %lx\n", vaddr, slen);
466
467 /* Handle failure */
468 if (unlikely(entry == DMA_MAPPING_ERROR)) {
469 if (!(attrs & DMA_ATTR_NO_WARN) &&
470 printk_ratelimit())
471 dev_info(dev, "iommu_alloc failed, tbl %p "
472 "vaddr %lx npages %lu\n", tbl, vaddr,
473 npages);
474 goto failure;
475 }
476
477 /* Convert entry to a dma_addr_t */
478 entry += tbl->it_offset;
479 dma_addr = entry << tbl->it_page_shift;
480 dma_addr |= (s->offset & ~IOMMU_PAGE_MASK(tbl));
481
482 DBG(" - %lu pages, entry: %lx, dma_addr: %lx\n",
483 npages, entry, dma_addr);
484
485 /* Insert into HW table */
486 build_fail = tbl->it_ops->set(tbl, entry, npages,
487 vaddr & IOMMU_PAGE_MASK(tbl),
488 direction, attrs);
489 if(unlikely(build_fail))
490 goto failure;
491
492 /* If we are in an open segment, try merging */
493 if (segstart != s) {
494 DBG(" - trying merge...\n");
495 /* We cannot merge if:
496 * - allocated dma_addr isn't contiguous to previous allocation
497 */
498 if (novmerge || (dma_addr != dma_next) ||
499 (outs->dma_length + s->length > max_seg_size)) {
500 /* Can't merge: create a new segment */
501 segstart = s;
502 outcount++;
503 outs = sg_next(outs);
504 DBG(" can't merge, new segment.\n");
505 } else {
506 outs->dma_length += s->length;
507 DBG(" merged, new len: %ux\n", outs->dma_length);
508 }
509 }
510
511 if (segstart == s) {
512 /* This is a new segment, fill entries */
513 DBG(" - filling new segment.\n");
514 outs->dma_address = dma_addr;
515 outs->dma_length = slen;
516 }
517
518 /* Calculate next page pointer for contiguous check */
519 dma_next = dma_addr + slen;
520
521 DBG(" - dma next is: %lx\n", dma_next);
522 }
523
524 /* Flush/invalidate TLB caches if necessary */
525 if (tbl->it_ops->flush)
526 tbl->it_ops->flush(tbl);
527
528 DBG("mapped %d elements:\n", outcount);
529
530 /* For the sake of ppc_iommu_unmap_sg, we clear out the length in the
531 * next entry of the sglist if we didn't fill the list completely
532 */
533 if (outcount < incount) {
534 outs = sg_next(outs);
535 outs->dma_address = DMA_MAPPING_ERROR;
536 outs->dma_length = 0;
537 }
538
539 /* Make sure updates are seen by hardware */
540 mb();
541
542 return outcount;
543
544 failure:
545 for_each_sg(sglist, s, nelems, i) {
546 if (s->dma_length != 0) {
547 unsigned long vaddr, npages;
548
549 vaddr = s->dma_address & IOMMU_PAGE_MASK(tbl);
550 npages = iommu_num_pages(s->dma_address, s->dma_length,
551 IOMMU_PAGE_SIZE(tbl));
552 __iommu_free(tbl, vaddr, npages);
553 s->dma_address = DMA_MAPPING_ERROR;
554 s->dma_length = 0;
555 }
556 if (s == outs)
557 break;
558 }
559 return 0;
560}
561
562
563void ppc_iommu_unmap_sg(struct iommu_table *tbl, struct scatterlist *sglist,
564 int nelems, enum dma_data_direction direction,
565 unsigned long attrs)
566{
567 struct scatterlist *sg;
568
569 BUG_ON(direction == DMA_NONE);
570
571 if (!tbl)
572 return;
573
574 sg = sglist;
575 while (nelems--) {
576 unsigned int npages;
577 dma_addr_t dma_handle = sg->dma_address;
578
579 if (sg->dma_length == 0)
580 break;
581 npages = iommu_num_pages(dma_handle, sg->dma_length,
582 IOMMU_PAGE_SIZE(tbl));
583 __iommu_free(tbl, dma_handle, npages);
584 sg = sg_next(sg);
585 }
586
587 /* Flush/invalidate TLBs if necessary. As for iommu_free(), we
588 * do not do an mb() here, the affected platforms do not need it
589 * when freeing.
590 */
591 if (tbl->it_ops->flush)
592 tbl->it_ops->flush(tbl);
593}
594
595static void iommu_table_clear(struct iommu_table *tbl)
596{
597 /*
598 * In case of firmware assisted dump system goes through clean
599 * reboot process at the time of system crash. Hence it's safe to
600 * clear the TCE entries if firmware assisted dump is active.
601 */
602 if (!is_kdump_kernel() || is_fadump_active()) {
603 /* Clear the table in case firmware left allocations in it */
604 tbl->it_ops->clear(tbl, tbl->it_offset, tbl->it_size);
605 return;
606 }
607
608#ifdef CONFIG_CRASH_DUMP
609 if (tbl->it_ops->get) {
610 unsigned long index, tceval, tcecount = 0;
611
612 /* Reserve the existing mappings left by the first kernel. */
613 for (index = 0; index < tbl->it_size; index++) {
614 tceval = tbl->it_ops->get(tbl, index + tbl->it_offset);
615 /*
616 * Freed TCE entry contains 0x7fffffffffffffff on JS20
617 */
618 if (tceval && (tceval != 0x7fffffffffffffffUL)) {
619 __set_bit(index, tbl->it_map);
620 tcecount++;
621 }
622 }
623
624 if ((tbl->it_size - tcecount) < KDUMP_MIN_TCE_ENTRIES) {
625 printk(KERN_WARNING "TCE table is full; freeing ");
626 printk(KERN_WARNING "%d entries for the kdump boot\n",
627 KDUMP_MIN_TCE_ENTRIES);
628 for (index = tbl->it_size - KDUMP_MIN_TCE_ENTRIES;
629 index < tbl->it_size; index++)
630 __clear_bit(index, tbl->it_map);
631 }
632 }
633#endif
634}
635
636static void iommu_table_reserve_pages(struct iommu_table *tbl,
637 unsigned long res_start, unsigned long res_end)
638{
639 int i;
640
641 WARN_ON_ONCE(res_end < res_start);
642 /*
643 * Reserve page 0 so it will not be used for any mappings.
644 * This avoids buggy drivers that consider page 0 to be invalid
645 * to crash the machine or even lose data.
646 */
647 if (tbl->it_offset == 0)
648 set_bit(0, tbl->it_map);
649
650 tbl->it_reserved_start = res_start;
651 tbl->it_reserved_end = res_end;
652
653 /* Check if res_start..res_end isn't empty and overlaps the table */
654 if (res_start && res_end &&
655 (tbl->it_offset + tbl->it_size < res_start ||
656 res_end < tbl->it_offset))
657 return;
658
659 for (i = tbl->it_reserved_start; i < tbl->it_reserved_end; ++i)
660 set_bit(i - tbl->it_offset, tbl->it_map);
661}
662
663static void iommu_table_release_pages(struct iommu_table *tbl)
664{
665 int i;
666
667 /*
668 * In case we have reserved the first bit, we should not emit
669 * the warning below.
670 */
671 if (tbl->it_offset == 0)
672 clear_bit(0, tbl->it_map);
673
674 for (i = tbl->it_reserved_start; i < tbl->it_reserved_end; ++i)
675 clear_bit(i - tbl->it_offset, tbl->it_map);
676}
677
678/*
679 * Build a iommu_table structure. This contains a bit map which
680 * is used to manage allocation of the tce space.
681 */
682struct iommu_table *iommu_init_table(struct iommu_table *tbl, int nid,
683 unsigned long res_start, unsigned long res_end)
684{
685 unsigned long sz;
686 static int welcomed = 0;
687 struct page *page;
688 unsigned int i;
689 struct iommu_pool *p;
690
691 BUG_ON(!tbl->it_ops);
692
693 /* number of bytes needed for the bitmap */
694 sz = BITS_TO_LONGS(tbl->it_size) * sizeof(unsigned long);
695
696 page = alloc_pages_node(nid, GFP_KERNEL, get_order(sz));
697 if (!page)
698 panic("iommu_init_table: Can't allocate %ld bytes\n", sz);
699 tbl->it_map = page_address(page);
700 memset(tbl->it_map, 0, sz);
701
702 iommu_table_reserve_pages(tbl, res_start, res_end);
703
704 /* We only split the IOMMU table if we have 1GB or more of space */
705 if ((tbl->it_size << tbl->it_page_shift) >= (1UL * 1024 * 1024 * 1024))
706 tbl->nr_pools = IOMMU_NR_POOLS;
707 else
708 tbl->nr_pools = 1;
709
710 /* We reserve the top 1/4 of the table for large allocations */
711 tbl->poolsize = (tbl->it_size * 3 / 4) / tbl->nr_pools;
712
713 for (i = 0; i < tbl->nr_pools; i++) {
714 p = &tbl->pools[i];
715 spin_lock_init(&(p->lock));
716 p->start = tbl->poolsize * i;
717 p->hint = p->start;
718 p->end = p->start + tbl->poolsize;
719 }
720
721 p = &tbl->large_pool;
722 spin_lock_init(&(p->lock));
723 p->start = tbl->poolsize * i;
724 p->hint = p->start;
725 p->end = tbl->it_size;
726
727 iommu_table_clear(tbl);
728
729 if (!welcomed) {
730 printk(KERN_INFO "IOMMU table initialized, virtual merging %s\n",
731 novmerge ? "disabled" : "enabled");
732 welcomed = 1;
733 }
734
735 return tbl;
736}
737
738static void iommu_table_free(struct kref *kref)
739{
740 unsigned long bitmap_sz;
741 unsigned int order;
742 struct iommu_table *tbl;
743
744 tbl = container_of(kref, struct iommu_table, it_kref);
745
746 if (tbl->it_ops->free)
747 tbl->it_ops->free(tbl);
748
749 if (!tbl->it_map) {
750 kfree(tbl);
751 return;
752 }
753
754 iommu_table_release_pages(tbl);
755
756 /* verify that table contains no entries */
757 if (!bitmap_empty(tbl->it_map, tbl->it_size))
758 pr_warn("%s: Unexpected TCEs\n", __func__);
759
760 /* calculate bitmap size in bytes */
761 bitmap_sz = BITS_TO_LONGS(tbl->it_size) * sizeof(unsigned long);
762
763 /* free bitmap */
764 order = get_order(bitmap_sz);
765 free_pages((unsigned long) tbl->it_map, order);
766
767 /* free table */
768 kfree(tbl);
769}
770
771struct iommu_table *iommu_tce_table_get(struct iommu_table *tbl)
772{
773 if (kref_get_unless_zero(&tbl->it_kref))
774 return tbl;
775
776 return NULL;
777}
778EXPORT_SYMBOL_GPL(iommu_tce_table_get);
779
780int iommu_tce_table_put(struct iommu_table *tbl)
781{
782 if (WARN_ON(!tbl))
783 return 0;
784
785 return kref_put(&tbl->it_kref, iommu_table_free);
786}
787EXPORT_SYMBOL_GPL(iommu_tce_table_put);
788
789/* Creates TCEs for a user provided buffer. The user buffer must be
790 * contiguous real kernel storage (not vmalloc). The address passed here
791 * comprises a page address and offset into that page. The dma_addr_t
792 * returned will point to the same byte within the page as was passed in.
793 */
794dma_addr_t iommu_map_page(struct device *dev, struct iommu_table *tbl,
795 struct page *page, unsigned long offset, size_t size,
796 unsigned long mask, enum dma_data_direction direction,
797 unsigned long attrs)
798{
799 dma_addr_t dma_handle = DMA_MAPPING_ERROR;
800 void *vaddr;
801 unsigned long uaddr;
802 unsigned int npages, align;
803
804 BUG_ON(direction == DMA_NONE);
805
806 vaddr = page_address(page) + offset;
807 uaddr = (unsigned long)vaddr;
808
809 if (tbl) {
810 npages = iommu_num_pages(uaddr, size, IOMMU_PAGE_SIZE(tbl));
811 align = 0;
812 if (tbl->it_page_shift < PAGE_SHIFT && size >= PAGE_SIZE &&
813 ((unsigned long)vaddr & ~PAGE_MASK) == 0)
814 align = PAGE_SHIFT - tbl->it_page_shift;
815
816 dma_handle = iommu_alloc(dev, tbl, vaddr, npages, direction,
817 mask >> tbl->it_page_shift, align,
818 attrs);
819 if (dma_handle == DMA_MAPPING_ERROR) {
820 if (!(attrs & DMA_ATTR_NO_WARN) &&
821 printk_ratelimit()) {
822 dev_info(dev, "iommu_alloc failed, tbl %p "
823 "vaddr %p npages %d\n", tbl, vaddr,
824 npages);
825 }
826 } else
827 dma_handle |= (uaddr & ~IOMMU_PAGE_MASK(tbl));
828 }
829
830 return dma_handle;
831}
832
833void iommu_unmap_page(struct iommu_table *tbl, dma_addr_t dma_handle,
834 size_t size, enum dma_data_direction direction,
835 unsigned long attrs)
836{
837 unsigned int npages;
838
839 BUG_ON(direction == DMA_NONE);
840
841 if (tbl) {
842 npages = iommu_num_pages(dma_handle, size,
843 IOMMU_PAGE_SIZE(tbl));
844 iommu_free(tbl, dma_handle, npages);
845 }
846}
847
848/* Allocates a contiguous real buffer and creates mappings over it.
849 * Returns the virtual address of the buffer and sets dma_handle
850 * to the dma address (mapping) of the first page.
851 */
852void *iommu_alloc_coherent(struct device *dev, struct iommu_table *tbl,
853 size_t size, dma_addr_t *dma_handle,
854 unsigned long mask, gfp_t flag, int node)
855{
856 void *ret = NULL;
857 dma_addr_t mapping;
858 unsigned int order;
859 unsigned int nio_pages, io_order;
860 struct page *page;
861
862 size = PAGE_ALIGN(size);
863 order = get_order(size);
864
865 /*
866 * Client asked for way too much space. This is checked later
867 * anyway. It is easier to debug here for the drivers than in
868 * the tce tables.
869 */
870 if (order >= IOMAP_MAX_ORDER) {
871 dev_info(dev, "iommu_alloc_consistent size too large: 0x%lx\n",
872 size);
873 return NULL;
874 }
875
876 if (!tbl)
877 return NULL;
878
879 /* Alloc enough pages (and possibly more) */
880 page = alloc_pages_node(node, flag, order);
881 if (!page)
882 return NULL;
883 ret = page_address(page);
884 memset(ret, 0, size);
885
886 /* Set up tces to cover the allocated range */
887 nio_pages = size >> tbl->it_page_shift;
888 io_order = get_iommu_order(size, tbl);
889 mapping = iommu_alloc(dev, tbl, ret, nio_pages, DMA_BIDIRECTIONAL,
890 mask >> tbl->it_page_shift, io_order, 0);
891 if (mapping == DMA_MAPPING_ERROR) {
892 free_pages((unsigned long)ret, order);
893 return NULL;
894 }
895 *dma_handle = mapping;
896 return ret;
897}
898
899void iommu_free_coherent(struct iommu_table *tbl, size_t size,
900 void *vaddr, dma_addr_t dma_handle)
901{
902 if (tbl) {
903 unsigned int nio_pages;
904
905 size = PAGE_ALIGN(size);
906 nio_pages = size >> tbl->it_page_shift;
907 iommu_free(tbl, dma_handle, nio_pages);
908 size = PAGE_ALIGN(size);
909 free_pages((unsigned long)vaddr, get_order(size));
910 }
911}
912
913unsigned long iommu_direction_to_tce_perm(enum dma_data_direction dir)
914{
915 switch (dir) {
916 case DMA_BIDIRECTIONAL:
917 return TCE_PCI_READ | TCE_PCI_WRITE;
918 case DMA_FROM_DEVICE:
919 return TCE_PCI_WRITE;
920 case DMA_TO_DEVICE:
921 return TCE_PCI_READ;
922 default:
923 return 0;
924 }
925}
926EXPORT_SYMBOL_GPL(iommu_direction_to_tce_perm);
927
928#ifdef CONFIG_IOMMU_API
929/*
930 * SPAPR TCE API
931 */
932static void group_release(void *iommu_data)
933{
934 struct iommu_table_group *table_group = iommu_data;
935
936 table_group->group = NULL;
937}
938
939void iommu_register_group(struct iommu_table_group *table_group,
940 int pci_domain_number, unsigned long pe_num)
941{
942 struct iommu_group *grp;
943 char *name;
944
945 grp = iommu_group_alloc();
946 if (IS_ERR(grp)) {
947 pr_warn("powerpc iommu api: cannot create new group, err=%ld\n",
948 PTR_ERR(grp));
949 return;
950 }
951 table_group->group = grp;
952 iommu_group_set_iommudata(grp, table_group, group_release);
953 name = kasprintf(GFP_KERNEL, "domain%d-pe%lx",
954 pci_domain_number, pe_num);
955 if (!name)
956 return;
957 iommu_group_set_name(grp, name);
958 kfree(name);
959}
960
961enum dma_data_direction iommu_tce_direction(unsigned long tce)
962{
963 if ((tce & TCE_PCI_READ) && (tce & TCE_PCI_WRITE))
964 return DMA_BIDIRECTIONAL;
965 else if (tce & TCE_PCI_READ)
966 return DMA_TO_DEVICE;
967 else if (tce & TCE_PCI_WRITE)
968 return DMA_FROM_DEVICE;
969 else
970 return DMA_NONE;
971}
972EXPORT_SYMBOL_GPL(iommu_tce_direction);
973
974void iommu_flush_tce(struct iommu_table *tbl)
975{
976 /* Flush/invalidate TLB caches if necessary */
977 if (tbl->it_ops->flush)
978 tbl->it_ops->flush(tbl);
979
980 /* Make sure updates are seen by hardware */
981 mb();
982}
983EXPORT_SYMBOL_GPL(iommu_flush_tce);
984
985int iommu_tce_check_ioba(unsigned long page_shift,
986 unsigned long offset, unsigned long size,
987 unsigned long ioba, unsigned long npages)
988{
989 unsigned long mask = (1UL << page_shift) - 1;
990
991 if (ioba & mask)
992 return -EINVAL;
993
994 ioba >>= page_shift;
995 if (ioba < offset)
996 return -EINVAL;
997
998 if ((ioba + 1) > (offset + size))
999 return -EINVAL;
1000
1001 return 0;
1002}
1003EXPORT_SYMBOL_GPL(iommu_tce_check_ioba);
1004
1005int iommu_tce_check_gpa(unsigned long page_shift, unsigned long gpa)
1006{
1007 unsigned long mask = (1UL << page_shift) - 1;
1008
1009 if (gpa & mask)
1010 return -EINVAL;
1011
1012 return 0;
1013}
1014EXPORT_SYMBOL_GPL(iommu_tce_check_gpa);
1015
1016extern long iommu_tce_xchg_no_kill(struct mm_struct *mm,
1017 struct iommu_table *tbl,
1018 unsigned long entry, unsigned long *hpa,
1019 enum dma_data_direction *direction)
1020{
1021 long ret;
1022 unsigned long size = 0;
1023
1024 ret = tbl->it_ops->xchg_no_kill(tbl, entry, hpa, direction, false);
1025 if (!ret && ((*direction == DMA_FROM_DEVICE) ||
1026 (*direction == DMA_BIDIRECTIONAL)) &&
1027 !mm_iommu_is_devmem(mm, *hpa, tbl->it_page_shift,
1028 &size))
1029 SetPageDirty(pfn_to_page(*hpa >> PAGE_SHIFT));
1030
1031 return ret;
1032}
1033EXPORT_SYMBOL_GPL(iommu_tce_xchg_no_kill);
1034
1035void iommu_tce_kill(struct iommu_table *tbl,
1036 unsigned long entry, unsigned long pages)
1037{
1038 if (tbl->it_ops->tce_kill)
1039 tbl->it_ops->tce_kill(tbl, entry, pages, false);
1040}
1041EXPORT_SYMBOL_GPL(iommu_tce_kill);
1042
1043int iommu_take_ownership(struct iommu_table *tbl)
1044{
1045 unsigned long flags, i, sz = (tbl->it_size + 7) >> 3;
1046 int ret = 0;
1047
1048 /*
1049 * VFIO does not control TCE entries allocation and the guest
1050 * can write new TCEs on top of existing ones so iommu_tce_build()
1051 * must be able to release old pages. This functionality
1052 * requires exchange() callback defined so if it is not
1053 * implemented, we disallow taking ownership over the table.
1054 */
1055 if (!tbl->it_ops->xchg_no_kill)
1056 return -EINVAL;
1057
1058 spin_lock_irqsave(&tbl->large_pool.lock, flags);
1059 for (i = 0; i < tbl->nr_pools; i++)
1060 spin_lock(&tbl->pools[i].lock);
1061
1062 iommu_table_release_pages(tbl);
1063
1064 if (!bitmap_empty(tbl->it_map, tbl->it_size)) {
1065 pr_err("iommu_tce: it_map is not empty");
1066 ret = -EBUSY;
1067 /* Undo iommu_table_release_pages, i.e. restore bit#0, etc */
1068 iommu_table_reserve_pages(tbl, tbl->it_reserved_start,
1069 tbl->it_reserved_end);
1070 } else {
1071 memset(tbl->it_map, 0xff, sz);
1072 }
1073
1074 for (i = 0; i < tbl->nr_pools; i++)
1075 spin_unlock(&tbl->pools[i].lock);
1076 spin_unlock_irqrestore(&tbl->large_pool.lock, flags);
1077
1078 return ret;
1079}
1080EXPORT_SYMBOL_GPL(iommu_take_ownership);
1081
1082void iommu_release_ownership(struct iommu_table *tbl)
1083{
1084 unsigned long flags, i, sz = (tbl->it_size + 7) >> 3;
1085
1086 spin_lock_irqsave(&tbl->large_pool.lock, flags);
1087 for (i = 0; i < tbl->nr_pools; i++)
1088 spin_lock(&tbl->pools[i].lock);
1089
1090 memset(tbl->it_map, 0, sz);
1091
1092 iommu_table_reserve_pages(tbl, tbl->it_reserved_start,
1093 tbl->it_reserved_end);
1094
1095 for (i = 0; i < tbl->nr_pools; i++)
1096 spin_unlock(&tbl->pools[i].lock);
1097 spin_unlock_irqrestore(&tbl->large_pool.lock, flags);
1098}
1099EXPORT_SYMBOL_GPL(iommu_release_ownership);
1100
1101int iommu_add_device(struct iommu_table_group *table_group, struct device *dev)
1102{
1103 /*
1104 * The sysfs entries should be populated before
1105 * binding IOMMU group. If sysfs entries isn't
1106 * ready, we simply bail.
1107 */
1108 if (!device_is_registered(dev))
1109 return -ENOENT;
1110
1111 if (device_iommu_mapped(dev)) {
1112 pr_debug("%s: Skipping device %s with iommu group %d\n",
1113 __func__, dev_name(dev),
1114 iommu_group_id(dev->iommu_group));
1115 return -EBUSY;
1116 }
1117
1118 pr_debug("%s: Adding %s to iommu group %d\n",
1119 __func__, dev_name(dev), iommu_group_id(table_group->group));
1120
1121 return iommu_group_add_device(table_group->group, dev);
1122}
1123EXPORT_SYMBOL_GPL(iommu_add_device);
1124
1125void iommu_del_device(struct device *dev)
1126{
1127 /*
1128 * Some devices might not have IOMMU table and group
1129 * and we needn't detach them from the associated
1130 * IOMMU groups
1131 */
1132 if (!device_iommu_mapped(dev)) {
1133 pr_debug("iommu_tce: skipping device %s with no tbl\n",
1134 dev_name(dev));
1135 return;
1136 }
1137
1138 iommu_group_remove_device(dev);
1139}
1140EXPORT_SYMBOL_GPL(iommu_del_device);
1141#endif /* CONFIG_IOMMU_API */
1/*
2 * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation
3 *
4 * Rewrite, cleanup, new allocation schemes, virtual merging:
5 * Copyright (C) 2004 Olof Johansson, IBM Corporation
6 * and Ben. Herrenschmidt, IBM Corporation
7 *
8 * Dynamic DMA mapping support, bus-independent parts.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 */
24
25
26#include <linux/init.h>
27#include <linux/types.h>
28#include <linux/slab.h>
29#include <linux/mm.h>
30#include <linux/spinlock.h>
31#include <linux/string.h>
32#include <linux/dma-mapping.h>
33#include <linux/bitmap.h>
34#include <linux/iommu-helper.h>
35#include <linux/crash_dump.h>
36#include <linux/hash.h>
37#include <linux/fault-inject.h>
38#include <linux/pci.h>
39#include <linux/iommu.h>
40#include <linux/sched.h>
41#include <asm/io.h>
42#include <asm/prom.h>
43#include <asm/iommu.h>
44#include <asm/pci-bridge.h>
45#include <asm/machdep.h>
46#include <asm/kdump.h>
47#include <asm/fadump.h>
48#include <asm/vio.h>
49#include <asm/tce.h>
50
51#define DBG(...)
52
53static int novmerge;
54
55static void __iommu_free(struct iommu_table *, dma_addr_t, unsigned int);
56
57static int __init setup_iommu(char *str)
58{
59 if (!strcmp(str, "novmerge"))
60 novmerge = 1;
61 else if (!strcmp(str, "vmerge"))
62 novmerge = 0;
63 return 1;
64}
65
66__setup("iommu=", setup_iommu);
67
68static DEFINE_PER_CPU(unsigned int, iommu_pool_hash);
69
70/*
71 * We precalculate the hash to avoid doing it on every allocation.
72 *
73 * The hash is important to spread CPUs across all the pools. For example,
74 * on a POWER7 with 4 way SMT we want interrupts on the primary threads and
75 * with 4 pools all primary threads would map to the same pool.
76 */
77static int __init setup_iommu_pool_hash(void)
78{
79 unsigned int i;
80
81 for_each_possible_cpu(i)
82 per_cpu(iommu_pool_hash, i) = hash_32(i, IOMMU_POOL_HASHBITS);
83
84 return 0;
85}
86subsys_initcall(setup_iommu_pool_hash);
87
88#ifdef CONFIG_FAIL_IOMMU
89
90static DECLARE_FAULT_ATTR(fail_iommu);
91
92static int __init setup_fail_iommu(char *str)
93{
94 return setup_fault_attr(&fail_iommu, str);
95}
96__setup("fail_iommu=", setup_fail_iommu);
97
98static bool should_fail_iommu(struct device *dev)
99{
100 return dev->archdata.fail_iommu && should_fail(&fail_iommu, 1);
101}
102
103static int __init fail_iommu_debugfs(void)
104{
105 struct dentry *dir = fault_create_debugfs_attr("fail_iommu",
106 NULL, &fail_iommu);
107
108 return PTR_ERR_OR_ZERO(dir);
109}
110late_initcall(fail_iommu_debugfs);
111
112static ssize_t fail_iommu_show(struct device *dev,
113 struct device_attribute *attr, char *buf)
114{
115 return sprintf(buf, "%d\n", dev->archdata.fail_iommu);
116}
117
118static ssize_t fail_iommu_store(struct device *dev,
119 struct device_attribute *attr, const char *buf,
120 size_t count)
121{
122 int i;
123
124 if (count > 0 && sscanf(buf, "%d", &i) > 0)
125 dev->archdata.fail_iommu = (i == 0) ? 0 : 1;
126
127 return count;
128}
129
130static DEVICE_ATTR_RW(fail_iommu);
131
132static int fail_iommu_bus_notify(struct notifier_block *nb,
133 unsigned long action, void *data)
134{
135 struct device *dev = data;
136
137 if (action == BUS_NOTIFY_ADD_DEVICE) {
138 if (device_create_file(dev, &dev_attr_fail_iommu))
139 pr_warn("Unable to create IOMMU fault injection sysfs "
140 "entries\n");
141 } else if (action == BUS_NOTIFY_DEL_DEVICE) {
142 device_remove_file(dev, &dev_attr_fail_iommu);
143 }
144
145 return 0;
146}
147
148static struct notifier_block fail_iommu_bus_notifier = {
149 .notifier_call = fail_iommu_bus_notify
150};
151
152static int __init fail_iommu_setup(void)
153{
154#ifdef CONFIG_PCI
155 bus_register_notifier(&pci_bus_type, &fail_iommu_bus_notifier);
156#endif
157#ifdef CONFIG_IBMVIO
158 bus_register_notifier(&vio_bus_type, &fail_iommu_bus_notifier);
159#endif
160
161 return 0;
162}
163/*
164 * Must execute after PCI and VIO subsystem have initialised but before
165 * devices are probed.
166 */
167arch_initcall(fail_iommu_setup);
168#else
169static inline bool should_fail_iommu(struct device *dev)
170{
171 return false;
172}
173#endif
174
175static unsigned long iommu_range_alloc(struct device *dev,
176 struct iommu_table *tbl,
177 unsigned long npages,
178 unsigned long *handle,
179 unsigned long mask,
180 unsigned int align_order)
181{
182 unsigned long n, end, start;
183 unsigned long limit;
184 int largealloc = npages > 15;
185 int pass = 0;
186 unsigned long align_mask;
187 unsigned long boundary_size;
188 unsigned long flags;
189 unsigned int pool_nr;
190 struct iommu_pool *pool;
191
192 align_mask = (1ull << align_order) - 1;
193
194 /* This allocator was derived from x86_64's bit string search */
195
196 /* Sanity check */
197 if (unlikely(npages == 0)) {
198 if (printk_ratelimit())
199 WARN_ON(1);
200 return IOMMU_MAPPING_ERROR;
201 }
202
203 if (should_fail_iommu(dev))
204 return IOMMU_MAPPING_ERROR;
205
206 /*
207 * We don't need to disable preemption here because any CPU can
208 * safely use any IOMMU pool.
209 */
210 pool_nr = raw_cpu_read(iommu_pool_hash) & (tbl->nr_pools - 1);
211
212 if (largealloc)
213 pool = &(tbl->large_pool);
214 else
215 pool = &(tbl->pools[pool_nr]);
216
217 spin_lock_irqsave(&(pool->lock), flags);
218
219again:
220 if ((pass == 0) && handle && *handle &&
221 (*handle >= pool->start) && (*handle < pool->end))
222 start = *handle;
223 else
224 start = pool->hint;
225
226 limit = pool->end;
227
228 /* The case below can happen if we have a small segment appended
229 * to a large, or when the previous alloc was at the very end of
230 * the available space. If so, go back to the initial start.
231 */
232 if (start >= limit)
233 start = pool->start;
234
235 if (limit + tbl->it_offset > mask) {
236 limit = mask - tbl->it_offset + 1;
237 /* If we're constrained on address range, first try
238 * at the masked hint to avoid O(n) search complexity,
239 * but on second pass, start at 0 in pool 0.
240 */
241 if ((start & mask) >= limit || pass > 0) {
242 spin_unlock(&(pool->lock));
243 pool = &(tbl->pools[0]);
244 spin_lock(&(pool->lock));
245 start = pool->start;
246 } else {
247 start &= mask;
248 }
249 }
250
251 if (dev)
252 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
253 1 << tbl->it_page_shift);
254 else
255 boundary_size = ALIGN(1UL << 32, 1 << tbl->it_page_shift);
256 /* 4GB boundary for iseries_hv_alloc and iseries_hv_map */
257
258 n = iommu_area_alloc(tbl->it_map, limit, start, npages, tbl->it_offset,
259 boundary_size >> tbl->it_page_shift, align_mask);
260 if (n == -1) {
261 if (likely(pass == 0)) {
262 /* First try the pool from the start */
263 pool->hint = pool->start;
264 pass++;
265 goto again;
266
267 } else if (pass <= tbl->nr_pools) {
268 /* Now try scanning all the other pools */
269 spin_unlock(&(pool->lock));
270 pool_nr = (pool_nr + 1) & (tbl->nr_pools - 1);
271 pool = &tbl->pools[pool_nr];
272 spin_lock(&(pool->lock));
273 pool->hint = pool->start;
274 pass++;
275 goto again;
276
277 } else {
278 /* Give up */
279 spin_unlock_irqrestore(&(pool->lock), flags);
280 return IOMMU_MAPPING_ERROR;
281 }
282 }
283
284 end = n + npages;
285
286 /* Bump the hint to a new block for small allocs. */
287 if (largealloc) {
288 /* Don't bump to new block to avoid fragmentation */
289 pool->hint = end;
290 } else {
291 /* Overflow will be taken care of at the next allocation */
292 pool->hint = (end + tbl->it_blocksize - 1) &
293 ~(tbl->it_blocksize - 1);
294 }
295
296 /* Update handle for SG allocations */
297 if (handle)
298 *handle = end;
299
300 spin_unlock_irqrestore(&(pool->lock), flags);
301
302 return n;
303}
304
305static dma_addr_t iommu_alloc(struct device *dev, struct iommu_table *tbl,
306 void *page, unsigned int npages,
307 enum dma_data_direction direction,
308 unsigned long mask, unsigned int align_order,
309 unsigned long attrs)
310{
311 unsigned long entry;
312 dma_addr_t ret = IOMMU_MAPPING_ERROR;
313 int build_fail;
314
315 entry = iommu_range_alloc(dev, tbl, npages, NULL, mask, align_order);
316
317 if (unlikely(entry == IOMMU_MAPPING_ERROR))
318 return IOMMU_MAPPING_ERROR;
319
320 entry += tbl->it_offset; /* Offset into real TCE table */
321 ret = entry << tbl->it_page_shift; /* Set the return dma address */
322
323 /* Put the TCEs in the HW table */
324 build_fail = tbl->it_ops->set(tbl, entry, npages,
325 (unsigned long)page &
326 IOMMU_PAGE_MASK(tbl), direction, attrs);
327
328 /* tbl->it_ops->set() only returns non-zero for transient errors.
329 * Clean up the table bitmap in this case and return
330 * IOMMU_MAPPING_ERROR. For all other errors the functionality is
331 * not altered.
332 */
333 if (unlikely(build_fail)) {
334 __iommu_free(tbl, ret, npages);
335 return IOMMU_MAPPING_ERROR;
336 }
337
338 /* Flush/invalidate TLB caches if necessary */
339 if (tbl->it_ops->flush)
340 tbl->it_ops->flush(tbl);
341
342 /* Make sure updates are seen by hardware */
343 mb();
344
345 return ret;
346}
347
348static bool iommu_free_check(struct iommu_table *tbl, dma_addr_t dma_addr,
349 unsigned int npages)
350{
351 unsigned long entry, free_entry;
352
353 entry = dma_addr >> tbl->it_page_shift;
354 free_entry = entry - tbl->it_offset;
355
356 if (((free_entry + npages) > tbl->it_size) ||
357 (entry < tbl->it_offset)) {
358 if (printk_ratelimit()) {
359 printk(KERN_INFO "iommu_free: invalid entry\n");
360 printk(KERN_INFO "\tentry = 0x%lx\n", entry);
361 printk(KERN_INFO "\tdma_addr = 0x%llx\n", (u64)dma_addr);
362 printk(KERN_INFO "\tTable = 0x%llx\n", (u64)tbl);
363 printk(KERN_INFO "\tbus# = 0x%llx\n", (u64)tbl->it_busno);
364 printk(KERN_INFO "\tsize = 0x%llx\n", (u64)tbl->it_size);
365 printk(KERN_INFO "\tstartOff = 0x%llx\n", (u64)tbl->it_offset);
366 printk(KERN_INFO "\tindex = 0x%llx\n", (u64)tbl->it_index);
367 WARN_ON(1);
368 }
369
370 return false;
371 }
372
373 return true;
374}
375
376static struct iommu_pool *get_pool(struct iommu_table *tbl,
377 unsigned long entry)
378{
379 struct iommu_pool *p;
380 unsigned long largepool_start = tbl->large_pool.start;
381
382 /* The large pool is the last pool at the top of the table */
383 if (entry >= largepool_start) {
384 p = &tbl->large_pool;
385 } else {
386 unsigned int pool_nr = entry / tbl->poolsize;
387
388 BUG_ON(pool_nr > tbl->nr_pools);
389 p = &tbl->pools[pool_nr];
390 }
391
392 return p;
393}
394
395static void __iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
396 unsigned int npages)
397{
398 unsigned long entry, free_entry;
399 unsigned long flags;
400 struct iommu_pool *pool;
401
402 entry = dma_addr >> tbl->it_page_shift;
403 free_entry = entry - tbl->it_offset;
404
405 pool = get_pool(tbl, free_entry);
406
407 if (!iommu_free_check(tbl, dma_addr, npages))
408 return;
409
410 tbl->it_ops->clear(tbl, entry, npages);
411
412 spin_lock_irqsave(&(pool->lock), flags);
413 bitmap_clear(tbl->it_map, free_entry, npages);
414 spin_unlock_irqrestore(&(pool->lock), flags);
415}
416
417static void iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
418 unsigned int npages)
419{
420 __iommu_free(tbl, dma_addr, npages);
421
422 /* Make sure TLB cache is flushed if the HW needs it. We do
423 * not do an mb() here on purpose, it is not needed on any of
424 * the current platforms.
425 */
426 if (tbl->it_ops->flush)
427 tbl->it_ops->flush(tbl);
428}
429
430int ppc_iommu_map_sg(struct device *dev, struct iommu_table *tbl,
431 struct scatterlist *sglist, int nelems,
432 unsigned long mask, enum dma_data_direction direction,
433 unsigned long attrs)
434{
435 dma_addr_t dma_next = 0, dma_addr;
436 struct scatterlist *s, *outs, *segstart;
437 int outcount, incount, i, build_fail = 0;
438 unsigned int align;
439 unsigned long handle;
440 unsigned int max_seg_size;
441
442 BUG_ON(direction == DMA_NONE);
443
444 if ((nelems == 0) || !tbl)
445 return 0;
446
447 outs = s = segstart = &sglist[0];
448 outcount = 1;
449 incount = nelems;
450 handle = 0;
451
452 /* Init first segment length for backout at failure */
453 outs->dma_length = 0;
454
455 DBG("sg mapping %d elements:\n", nelems);
456
457 max_seg_size = dma_get_max_seg_size(dev);
458 for_each_sg(sglist, s, nelems, i) {
459 unsigned long vaddr, npages, entry, slen;
460
461 slen = s->length;
462 /* Sanity check */
463 if (slen == 0) {
464 dma_next = 0;
465 continue;
466 }
467 /* Allocate iommu entries for that segment */
468 vaddr = (unsigned long) sg_virt(s);
469 npages = iommu_num_pages(vaddr, slen, IOMMU_PAGE_SIZE(tbl));
470 align = 0;
471 if (tbl->it_page_shift < PAGE_SHIFT && slen >= PAGE_SIZE &&
472 (vaddr & ~PAGE_MASK) == 0)
473 align = PAGE_SHIFT - tbl->it_page_shift;
474 entry = iommu_range_alloc(dev, tbl, npages, &handle,
475 mask >> tbl->it_page_shift, align);
476
477 DBG(" - vaddr: %lx, size: %lx\n", vaddr, slen);
478
479 /* Handle failure */
480 if (unlikely(entry == IOMMU_MAPPING_ERROR)) {
481 if (!(attrs & DMA_ATTR_NO_WARN) &&
482 printk_ratelimit())
483 dev_info(dev, "iommu_alloc failed, tbl %p "
484 "vaddr %lx npages %lu\n", tbl, vaddr,
485 npages);
486 goto failure;
487 }
488
489 /* Convert entry to a dma_addr_t */
490 entry += tbl->it_offset;
491 dma_addr = entry << tbl->it_page_shift;
492 dma_addr |= (s->offset & ~IOMMU_PAGE_MASK(tbl));
493
494 DBG(" - %lu pages, entry: %lx, dma_addr: %lx\n",
495 npages, entry, dma_addr);
496
497 /* Insert into HW table */
498 build_fail = tbl->it_ops->set(tbl, entry, npages,
499 vaddr & IOMMU_PAGE_MASK(tbl),
500 direction, attrs);
501 if(unlikely(build_fail))
502 goto failure;
503
504 /* If we are in an open segment, try merging */
505 if (segstart != s) {
506 DBG(" - trying merge...\n");
507 /* We cannot merge if:
508 * - allocated dma_addr isn't contiguous to previous allocation
509 */
510 if (novmerge || (dma_addr != dma_next) ||
511 (outs->dma_length + s->length > max_seg_size)) {
512 /* Can't merge: create a new segment */
513 segstart = s;
514 outcount++;
515 outs = sg_next(outs);
516 DBG(" can't merge, new segment.\n");
517 } else {
518 outs->dma_length += s->length;
519 DBG(" merged, new len: %ux\n", outs->dma_length);
520 }
521 }
522
523 if (segstart == s) {
524 /* This is a new segment, fill entries */
525 DBG(" - filling new segment.\n");
526 outs->dma_address = dma_addr;
527 outs->dma_length = slen;
528 }
529
530 /* Calculate next page pointer for contiguous check */
531 dma_next = dma_addr + slen;
532
533 DBG(" - dma next is: %lx\n", dma_next);
534 }
535
536 /* Flush/invalidate TLB caches if necessary */
537 if (tbl->it_ops->flush)
538 tbl->it_ops->flush(tbl);
539
540 DBG("mapped %d elements:\n", outcount);
541
542 /* For the sake of ppc_iommu_unmap_sg, we clear out the length in the
543 * next entry of the sglist if we didn't fill the list completely
544 */
545 if (outcount < incount) {
546 outs = sg_next(outs);
547 outs->dma_address = IOMMU_MAPPING_ERROR;
548 outs->dma_length = 0;
549 }
550
551 /* Make sure updates are seen by hardware */
552 mb();
553
554 return outcount;
555
556 failure:
557 for_each_sg(sglist, s, nelems, i) {
558 if (s->dma_length != 0) {
559 unsigned long vaddr, npages;
560
561 vaddr = s->dma_address & IOMMU_PAGE_MASK(tbl);
562 npages = iommu_num_pages(s->dma_address, s->dma_length,
563 IOMMU_PAGE_SIZE(tbl));
564 __iommu_free(tbl, vaddr, npages);
565 s->dma_address = IOMMU_MAPPING_ERROR;
566 s->dma_length = 0;
567 }
568 if (s == outs)
569 break;
570 }
571 return 0;
572}
573
574
575void ppc_iommu_unmap_sg(struct iommu_table *tbl, struct scatterlist *sglist,
576 int nelems, enum dma_data_direction direction,
577 unsigned long attrs)
578{
579 struct scatterlist *sg;
580
581 BUG_ON(direction == DMA_NONE);
582
583 if (!tbl)
584 return;
585
586 sg = sglist;
587 while (nelems--) {
588 unsigned int npages;
589 dma_addr_t dma_handle = sg->dma_address;
590
591 if (sg->dma_length == 0)
592 break;
593 npages = iommu_num_pages(dma_handle, sg->dma_length,
594 IOMMU_PAGE_SIZE(tbl));
595 __iommu_free(tbl, dma_handle, npages);
596 sg = sg_next(sg);
597 }
598
599 /* Flush/invalidate TLBs if necessary. As for iommu_free(), we
600 * do not do an mb() here, the affected platforms do not need it
601 * when freeing.
602 */
603 if (tbl->it_ops->flush)
604 tbl->it_ops->flush(tbl);
605}
606
607static void iommu_table_clear(struct iommu_table *tbl)
608{
609 /*
610 * In case of firmware assisted dump system goes through clean
611 * reboot process at the time of system crash. Hence it's safe to
612 * clear the TCE entries if firmware assisted dump is active.
613 */
614 if (!is_kdump_kernel() || is_fadump_active()) {
615 /* Clear the table in case firmware left allocations in it */
616 tbl->it_ops->clear(tbl, tbl->it_offset, tbl->it_size);
617 return;
618 }
619
620#ifdef CONFIG_CRASH_DUMP
621 if (tbl->it_ops->get) {
622 unsigned long index, tceval, tcecount = 0;
623
624 /* Reserve the existing mappings left by the first kernel. */
625 for (index = 0; index < tbl->it_size; index++) {
626 tceval = tbl->it_ops->get(tbl, index + tbl->it_offset);
627 /*
628 * Freed TCE entry contains 0x7fffffffffffffff on JS20
629 */
630 if (tceval && (tceval != 0x7fffffffffffffffUL)) {
631 __set_bit(index, tbl->it_map);
632 tcecount++;
633 }
634 }
635
636 if ((tbl->it_size - tcecount) < KDUMP_MIN_TCE_ENTRIES) {
637 printk(KERN_WARNING "TCE table is full; freeing ");
638 printk(KERN_WARNING "%d entries for the kdump boot\n",
639 KDUMP_MIN_TCE_ENTRIES);
640 for (index = tbl->it_size - KDUMP_MIN_TCE_ENTRIES;
641 index < tbl->it_size; index++)
642 __clear_bit(index, tbl->it_map);
643 }
644 }
645#endif
646}
647
648/*
649 * Build a iommu_table structure. This contains a bit map which
650 * is used to manage allocation of the tce space.
651 */
652struct iommu_table *iommu_init_table(struct iommu_table *tbl, int nid)
653{
654 unsigned long sz;
655 static int welcomed = 0;
656 struct page *page;
657 unsigned int i;
658 struct iommu_pool *p;
659
660 BUG_ON(!tbl->it_ops);
661
662 /* number of bytes needed for the bitmap */
663 sz = BITS_TO_LONGS(tbl->it_size) * sizeof(unsigned long);
664
665 page = alloc_pages_node(nid, GFP_KERNEL, get_order(sz));
666 if (!page)
667 panic("iommu_init_table: Can't allocate %ld bytes\n", sz);
668 tbl->it_map = page_address(page);
669 memset(tbl->it_map, 0, sz);
670
671 /*
672 * Reserve page 0 so it will not be used for any mappings.
673 * This avoids buggy drivers that consider page 0 to be invalid
674 * to crash the machine or even lose data.
675 */
676 if (tbl->it_offset == 0)
677 set_bit(0, tbl->it_map);
678
679 /* We only split the IOMMU table if we have 1GB or more of space */
680 if ((tbl->it_size << tbl->it_page_shift) >= (1UL * 1024 * 1024 * 1024))
681 tbl->nr_pools = IOMMU_NR_POOLS;
682 else
683 tbl->nr_pools = 1;
684
685 /* We reserve the top 1/4 of the table for large allocations */
686 tbl->poolsize = (tbl->it_size * 3 / 4) / tbl->nr_pools;
687
688 for (i = 0; i < tbl->nr_pools; i++) {
689 p = &tbl->pools[i];
690 spin_lock_init(&(p->lock));
691 p->start = tbl->poolsize * i;
692 p->hint = p->start;
693 p->end = p->start + tbl->poolsize;
694 }
695
696 p = &tbl->large_pool;
697 spin_lock_init(&(p->lock));
698 p->start = tbl->poolsize * i;
699 p->hint = p->start;
700 p->end = tbl->it_size;
701
702 iommu_table_clear(tbl);
703
704 if (!welcomed) {
705 printk(KERN_INFO "IOMMU table initialized, virtual merging %s\n",
706 novmerge ? "disabled" : "enabled");
707 welcomed = 1;
708 }
709
710 return tbl;
711}
712
713static void iommu_table_free(struct kref *kref)
714{
715 unsigned long bitmap_sz;
716 unsigned int order;
717 struct iommu_table *tbl;
718
719 tbl = container_of(kref, struct iommu_table, it_kref);
720
721 if (tbl->it_ops->free)
722 tbl->it_ops->free(tbl);
723
724 if (!tbl->it_map) {
725 kfree(tbl);
726 return;
727 }
728
729 /*
730 * In case we have reserved the first bit, we should not emit
731 * the warning below.
732 */
733 if (tbl->it_offset == 0)
734 clear_bit(0, tbl->it_map);
735
736 /* verify that table contains no entries */
737 if (!bitmap_empty(tbl->it_map, tbl->it_size))
738 pr_warn("%s: Unexpected TCEs\n", __func__);
739
740 /* calculate bitmap size in bytes */
741 bitmap_sz = BITS_TO_LONGS(tbl->it_size) * sizeof(unsigned long);
742
743 /* free bitmap */
744 order = get_order(bitmap_sz);
745 free_pages((unsigned long) tbl->it_map, order);
746
747 /* free table */
748 kfree(tbl);
749}
750
751struct iommu_table *iommu_tce_table_get(struct iommu_table *tbl)
752{
753 if (kref_get_unless_zero(&tbl->it_kref))
754 return tbl;
755
756 return NULL;
757}
758EXPORT_SYMBOL_GPL(iommu_tce_table_get);
759
760int iommu_tce_table_put(struct iommu_table *tbl)
761{
762 if (WARN_ON(!tbl))
763 return 0;
764
765 return kref_put(&tbl->it_kref, iommu_table_free);
766}
767EXPORT_SYMBOL_GPL(iommu_tce_table_put);
768
769/* Creates TCEs for a user provided buffer. The user buffer must be
770 * contiguous real kernel storage (not vmalloc). The address passed here
771 * comprises a page address and offset into that page. The dma_addr_t
772 * returned will point to the same byte within the page as was passed in.
773 */
774dma_addr_t iommu_map_page(struct device *dev, struct iommu_table *tbl,
775 struct page *page, unsigned long offset, size_t size,
776 unsigned long mask, enum dma_data_direction direction,
777 unsigned long attrs)
778{
779 dma_addr_t dma_handle = IOMMU_MAPPING_ERROR;
780 void *vaddr;
781 unsigned long uaddr;
782 unsigned int npages, align;
783
784 BUG_ON(direction == DMA_NONE);
785
786 vaddr = page_address(page) + offset;
787 uaddr = (unsigned long)vaddr;
788 npages = iommu_num_pages(uaddr, size, IOMMU_PAGE_SIZE(tbl));
789
790 if (tbl) {
791 align = 0;
792 if (tbl->it_page_shift < PAGE_SHIFT && size >= PAGE_SIZE &&
793 ((unsigned long)vaddr & ~PAGE_MASK) == 0)
794 align = PAGE_SHIFT - tbl->it_page_shift;
795
796 dma_handle = iommu_alloc(dev, tbl, vaddr, npages, direction,
797 mask >> tbl->it_page_shift, align,
798 attrs);
799 if (dma_handle == IOMMU_MAPPING_ERROR) {
800 if (!(attrs & DMA_ATTR_NO_WARN) &&
801 printk_ratelimit()) {
802 dev_info(dev, "iommu_alloc failed, tbl %p "
803 "vaddr %p npages %d\n", tbl, vaddr,
804 npages);
805 }
806 } else
807 dma_handle |= (uaddr & ~IOMMU_PAGE_MASK(tbl));
808 }
809
810 return dma_handle;
811}
812
813void iommu_unmap_page(struct iommu_table *tbl, dma_addr_t dma_handle,
814 size_t size, enum dma_data_direction direction,
815 unsigned long attrs)
816{
817 unsigned int npages;
818
819 BUG_ON(direction == DMA_NONE);
820
821 if (tbl) {
822 npages = iommu_num_pages(dma_handle, size,
823 IOMMU_PAGE_SIZE(tbl));
824 iommu_free(tbl, dma_handle, npages);
825 }
826}
827
828/* Allocates a contiguous real buffer and creates mappings over it.
829 * Returns the virtual address of the buffer and sets dma_handle
830 * to the dma address (mapping) of the first page.
831 */
832void *iommu_alloc_coherent(struct device *dev, struct iommu_table *tbl,
833 size_t size, dma_addr_t *dma_handle,
834 unsigned long mask, gfp_t flag, int node)
835{
836 void *ret = NULL;
837 dma_addr_t mapping;
838 unsigned int order;
839 unsigned int nio_pages, io_order;
840 struct page *page;
841
842 size = PAGE_ALIGN(size);
843 order = get_order(size);
844
845 /*
846 * Client asked for way too much space. This is checked later
847 * anyway. It is easier to debug here for the drivers than in
848 * the tce tables.
849 */
850 if (order >= IOMAP_MAX_ORDER) {
851 dev_info(dev, "iommu_alloc_consistent size too large: 0x%lx\n",
852 size);
853 return NULL;
854 }
855
856 if (!tbl)
857 return NULL;
858
859 /* Alloc enough pages (and possibly more) */
860 page = alloc_pages_node(node, flag, order);
861 if (!page)
862 return NULL;
863 ret = page_address(page);
864 memset(ret, 0, size);
865
866 /* Set up tces to cover the allocated range */
867 nio_pages = size >> tbl->it_page_shift;
868 io_order = get_iommu_order(size, tbl);
869 mapping = iommu_alloc(dev, tbl, ret, nio_pages, DMA_BIDIRECTIONAL,
870 mask >> tbl->it_page_shift, io_order, 0);
871 if (mapping == IOMMU_MAPPING_ERROR) {
872 free_pages((unsigned long)ret, order);
873 return NULL;
874 }
875 *dma_handle = mapping;
876 return ret;
877}
878
879void iommu_free_coherent(struct iommu_table *tbl, size_t size,
880 void *vaddr, dma_addr_t dma_handle)
881{
882 if (tbl) {
883 unsigned int nio_pages;
884
885 size = PAGE_ALIGN(size);
886 nio_pages = size >> tbl->it_page_shift;
887 iommu_free(tbl, dma_handle, nio_pages);
888 size = PAGE_ALIGN(size);
889 free_pages((unsigned long)vaddr, get_order(size));
890 }
891}
892
893unsigned long iommu_direction_to_tce_perm(enum dma_data_direction dir)
894{
895 switch (dir) {
896 case DMA_BIDIRECTIONAL:
897 return TCE_PCI_READ | TCE_PCI_WRITE;
898 case DMA_FROM_DEVICE:
899 return TCE_PCI_WRITE;
900 case DMA_TO_DEVICE:
901 return TCE_PCI_READ;
902 default:
903 return 0;
904 }
905}
906EXPORT_SYMBOL_GPL(iommu_direction_to_tce_perm);
907
908#ifdef CONFIG_IOMMU_API
909/*
910 * SPAPR TCE API
911 */
912static void group_release(void *iommu_data)
913{
914 struct iommu_table_group *table_group = iommu_data;
915
916 table_group->group = NULL;
917}
918
919void iommu_register_group(struct iommu_table_group *table_group,
920 int pci_domain_number, unsigned long pe_num)
921{
922 struct iommu_group *grp;
923 char *name;
924
925 grp = iommu_group_alloc();
926 if (IS_ERR(grp)) {
927 pr_warn("powerpc iommu api: cannot create new group, err=%ld\n",
928 PTR_ERR(grp));
929 return;
930 }
931 table_group->group = grp;
932 iommu_group_set_iommudata(grp, table_group, group_release);
933 name = kasprintf(GFP_KERNEL, "domain%d-pe%lx",
934 pci_domain_number, pe_num);
935 if (!name)
936 return;
937 iommu_group_set_name(grp, name);
938 kfree(name);
939}
940
941enum dma_data_direction iommu_tce_direction(unsigned long tce)
942{
943 if ((tce & TCE_PCI_READ) && (tce & TCE_PCI_WRITE))
944 return DMA_BIDIRECTIONAL;
945 else if (tce & TCE_PCI_READ)
946 return DMA_TO_DEVICE;
947 else if (tce & TCE_PCI_WRITE)
948 return DMA_FROM_DEVICE;
949 else
950 return DMA_NONE;
951}
952EXPORT_SYMBOL_GPL(iommu_tce_direction);
953
954void iommu_flush_tce(struct iommu_table *tbl)
955{
956 /* Flush/invalidate TLB caches if necessary */
957 if (tbl->it_ops->flush)
958 tbl->it_ops->flush(tbl);
959
960 /* Make sure updates are seen by hardware */
961 mb();
962}
963EXPORT_SYMBOL_GPL(iommu_flush_tce);
964
965int iommu_tce_check_ioba(unsigned long page_shift,
966 unsigned long offset, unsigned long size,
967 unsigned long ioba, unsigned long npages)
968{
969 unsigned long mask = (1UL << page_shift) - 1;
970
971 if (ioba & mask)
972 return -EINVAL;
973
974 ioba >>= page_shift;
975 if (ioba < offset)
976 return -EINVAL;
977
978 if ((ioba + 1) > (offset + size))
979 return -EINVAL;
980
981 return 0;
982}
983EXPORT_SYMBOL_GPL(iommu_tce_check_ioba);
984
985int iommu_tce_check_gpa(unsigned long page_shift, unsigned long gpa)
986{
987 unsigned long mask = (1UL << page_shift) - 1;
988
989 if (gpa & mask)
990 return -EINVAL;
991
992 return 0;
993}
994EXPORT_SYMBOL_GPL(iommu_tce_check_gpa);
995
996long iommu_tce_xchg(struct iommu_table *tbl, unsigned long entry,
997 unsigned long *hpa, enum dma_data_direction *direction)
998{
999 long ret;
1000
1001 ret = tbl->it_ops->exchange(tbl, entry, hpa, direction);
1002
1003 if (!ret && ((*direction == DMA_FROM_DEVICE) ||
1004 (*direction == DMA_BIDIRECTIONAL)))
1005 SetPageDirty(pfn_to_page(*hpa >> PAGE_SHIFT));
1006
1007 /* if (unlikely(ret))
1008 pr_err("iommu_tce: %s failed on hwaddr=%lx ioba=%lx kva=%lx ret=%d\n",
1009 __func__, hwaddr, entry << tbl->it_page_shift,
1010 hwaddr, ret); */
1011
1012 return ret;
1013}
1014EXPORT_SYMBOL_GPL(iommu_tce_xchg);
1015
1016#ifdef CONFIG_PPC_BOOK3S_64
1017long iommu_tce_xchg_rm(struct iommu_table *tbl, unsigned long entry,
1018 unsigned long *hpa, enum dma_data_direction *direction)
1019{
1020 long ret;
1021
1022 ret = tbl->it_ops->exchange_rm(tbl, entry, hpa, direction);
1023
1024 if (!ret && ((*direction == DMA_FROM_DEVICE) ||
1025 (*direction == DMA_BIDIRECTIONAL))) {
1026 struct page *pg = realmode_pfn_to_page(*hpa >> PAGE_SHIFT);
1027
1028 if (likely(pg)) {
1029 SetPageDirty(pg);
1030 } else {
1031 tbl->it_ops->exchange_rm(tbl, entry, hpa, direction);
1032 ret = -EFAULT;
1033 }
1034 }
1035
1036 return ret;
1037}
1038EXPORT_SYMBOL_GPL(iommu_tce_xchg_rm);
1039#endif
1040
1041int iommu_take_ownership(struct iommu_table *tbl)
1042{
1043 unsigned long flags, i, sz = (tbl->it_size + 7) >> 3;
1044 int ret = 0;
1045
1046 /*
1047 * VFIO does not control TCE entries allocation and the guest
1048 * can write new TCEs on top of existing ones so iommu_tce_build()
1049 * must be able to release old pages. This functionality
1050 * requires exchange() callback defined so if it is not
1051 * implemented, we disallow taking ownership over the table.
1052 */
1053 if (!tbl->it_ops->exchange)
1054 return -EINVAL;
1055
1056 spin_lock_irqsave(&tbl->large_pool.lock, flags);
1057 for (i = 0; i < tbl->nr_pools; i++)
1058 spin_lock(&tbl->pools[i].lock);
1059
1060 if (tbl->it_offset == 0)
1061 clear_bit(0, tbl->it_map);
1062
1063 if (!bitmap_empty(tbl->it_map, tbl->it_size)) {
1064 pr_err("iommu_tce: it_map is not empty");
1065 ret = -EBUSY;
1066 /* Restore bit#0 set by iommu_init_table() */
1067 if (tbl->it_offset == 0)
1068 set_bit(0, tbl->it_map);
1069 } else {
1070 memset(tbl->it_map, 0xff, sz);
1071 }
1072
1073 for (i = 0; i < tbl->nr_pools; i++)
1074 spin_unlock(&tbl->pools[i].lock);
1075 spin_unlock_irqrestore(&tbl->large_pool.lock, flags);
1076
1077 return ret;
1078}
1079EXPORT_SYMBOL_GPL(iommu_take_ownership);
1080
1081void iommu_release_ownership(struct iommu_table *tbl)
1082{
1083 unsigned long flags, i, sz = (tbl->it_size + 7) >> 3;
1084
1085 spin_lock_irqsave(&tbl->large_pool.lock, flags);
1086 for (i = 0; i < tbl->nr_pools; i++)
1087 spin_lock(&tbl->pools[i].lock);
1088
1089 memset(tbl->it_map, 0, sz);
1090
1091 /* Restore bit#0 set by iommu_init_table() */
1092 if (tbl->it_offset == 0)
1093 set_bit(0, tbl->it_map);
1094
1095 for (i = 0; i < tbl->nr_pools; i++)
1096 spin_unlock(&tbl->pools[i].lock);
1097 spin_unlock_irqrestore(&tbl->large_pool.lock, flags);
1098}
1099EXPORT_SYMBOL_GPL(iommu_release_ownership);
1100
1101int iommu_add_device(struct device *dev)
1102{
1103 struct iommu_table *tbl;
1104 struct iommu_table_group_link *tgl;
1105
1106 /*
1107 * The sysfs entries should be populated before
1108 * binding IOMMU group. If sysfs entries isn't
1109 * ready, we simply bail.
1110 */
1111 if (!device_is_registered(dev))
1112 return -ENOENT;
1113
1114 if (dev->iommu_group) {
1115 pr_debug("%s: Skipping device %s with iommu group %d\n",
1116 __func__, dev_name(dev),
1117 iommu_group_id(dev->iommu_group));
1118 return -EBUSY;
1119 }
1120
1121 tbl = get_iommu_table_base(dev);
1122 if (!tbl) {
1123 pr_debug("%s: Skipping device %s with no tbl\n",
1124 __func__, dev_name(dev));
1125 return 0;
1126 }
1127
1128 tgl = list_first_entry_or_null(&tbl->it_group_list,
1129 struct iommu_table_group_link, next);
1130 if (!tgl) {
1131 pr_debug("%s: Skipping device %s with no group\n",
1132 __func__, dev_name(dev));
1133 return 0;
1134 }
1135 pr_debug("%s: Adding %s to iommu group %d\n",
1136 __func__, dev_name(dev),
1137 iommu_group_id(tgl->table_group->group));
1138
1139 if (PAGE_SIZE < IOMMU_PAGE_SIZE(tbl)) {
1140 pr_err("%s: Invalid IOMMU page size %lx (%lx) on %s\n",
1141 __func__, IOMMU_PAGE_SIZE(tbl),
1142 PAGE_SIZE, dev_name(dev));
1143 return -EINVAL;
1144 }
1145
1146 return iommu_group_add_device(tgl->table_group->group, dev);
1147}
1148EXPORT_SYMBOL_GPL(iommu_add_device);
1149
1150void iommu_del_device(struct device *dev)
1151{
1152 /*
1153 * Some devices might not have IOMMU table and group
1154 * and we needn't detach them from the associated
1155 * IOMMU groups
1156 */
1157 if (!dev->iommu_group) {
1158 pr_debug("iommu_tce: skipping device %s with no tbl\n",
1159 dev_name(dev));
1160 return;
1161 }
1162
1163 iommu_group_remove_device(dev);
1164}
1165EXPORT_SYMBOL_GPL(iommu_del_device);
1166
1167static int tce_iommu_bus_notifier(struct notifier_block *nb,
1168 unsigned long action, void *data)
1169{
1170 struct device *dev = data;
1171
1172 switch (action) {
1173 case BUS_NOTIFY_ADD_DEVICE:
1174 return iommu_add_device(dev);
1175 case BUS_NOTIFY_DEL_DEVICE:
1176 if (dev->iommu_group)
1177 iommu_del_device(dev);
1178 return 0;
1179 default:
1180 return 0;
1181 }
1182}
1183
1184static struct notifier_block tce_iommu_bus_nb = {
1185 .notifier_call = tce_iommu_bus_notifier,
1186};
1187
1188int __init tce_iommu_bus_notifier_init(void)
1189{
1190 bus_register_notifier(&pci_bus_type, &tce_iommu_bus_nb);
1191 return 0;
1192}
1193#endif /* CONFIG_IOMMU_API */