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1/*
2 * Copyright (C) 2006 Benjamin Herrenschmidt, IBM Corporation
3 *
4 * Provide default implementations of the DMA mapping callbacks for
5 * directly mapped busses.
6 */
7
8#include <linux/device.h>
9#include <linux/dma-mapping.h>
10#include <linux/dma-debug.h>
11#include <linux/gfp.h>
12#include <linux/memblock.h>
13#include <linux/export.h>
14#include <linux/pci.h>
15#include <asm/vio.h>
16#include <asm/bug.h>
17#include <asm/machdep.h>
18#include <asm/swiotlb.h>
19#include <asm/iommu.h>
20
21/*
22 * Generic direct DMA implementation
23 *
24 * This implementation supports a per-device offset that can be applied if
25 * the address at which memory is visible to devices is not 0. Platform code
26 * can set archdata.dma_data to an unsigned long holding the offset. By
27 * default the offset is PCI_DRAM_OFFSET.
28 */
29
30static u64 __maybe_unused get_pfn_limit(struct device *dev)
31{
32 u64 pfn = (dev->coherent_dma_mask >> PAGE_SHIFT) + 1;
33 struct dev_archdata __maybe_unused *sd = &dev->archdata;
34
35#ifdef CONFIG_SWIOTLB
36 if (sd->max_direct_dma_addr && dev->dma_ops == &powerpc_swiotlb_dma_ops)
37 pfn = min_t(u64, pfn, sd->max_direct_dma_addr >> PAGE_SHIFT);
38#endif
39
40 return pfn;
41}
42
43static int dma_nommu_dma_supported(struct device *dev, u64 mask)
44{
45#ifdef CONFIG_PPC64
46 u64 limit = get_dma_offset(dev) + (memblock_end_of_DRAM() - 1);
47
48 /* Limit fits in the mask, we are good */
49 if (mask >= limit)
50 return 1;
51
52#ifdef CONFIG_FSL_SOC
53 /* Freescale gets another chance via ZONE_DMA/ZONE_DMA32, however
54 * that will have to be refined if/when they support iommus
55 */
56 return 1;
57#endif
58 /* Sorry ... */
59 return 0;
60#else
61 return 1;
62#endif
63}
64
65void *__dma_nommu_alloc_coherent(struct device *dev, size_t size,
66 dma_addr_t *dma_handle, gfp_t flag,
67 unsigned long attrs)
68{
69 void *ret;
70#ifdef CONFIG_NOT_COHERENT_CACHE
71 ret = __dma_alloc_coherent(dev, size, dma_handle, flag);
72 if (ret == NULL)
73 return NULL;
74 *dma_handle += get_dma_offset(dev);
75 return ret;
76#else
77 struct page *page;
78 int node = dev_to_node(dev);
79#ifdef CONFIG_FSL_SOC
80 u64 pfn = get_pfn_limit(dev);
81 int zone;
82
83 /*
84 * This code should be OK on other platforms, but we have drivers that
85 * don't set coherent_dma_mask. As a workaround we just ifdef it. This
86 * whole routine needs some serious cleanup.
87 */
88
89 zone = dma_pfn_limit_to_zone(pfn);
90 if (zone < 0) {
91 dev_err(dev, "%s: No suitable zone for pfn %#llx\n",
92 __func__, pfn);
93 return NULL;
94 }
95
96 switch (zone) {
97 case ZONE_DMA:
98 flag |= GFP_DMA;
99 break;
100#ifdef CONFIG_ZONE_DMA32
101 case ZONE_DMA32:
102 flag |= GFP_DMA32;
103 break;
104#endif
105 };
106#endif /* CONFIG_FSL_SOC */
107
108 page = alloc_pages_node(node, flag, get_order(size));
109 if (page == NULL)
110 return NULL;
111 ret = page_address(page);
112 memset(ret, 0, size);
113 *dma_handle = __pa(ret) + get_dma_offset(dev);
114
115 return ret;
116#endif
117}
118
119void __dma_nommu_free_coherent(struct device *dev, size_t size,
120 void *vaddr, dma_addr_t dma_handle,
121 unsigned long attrs)
122{
123#ifdef CONFIG_NOT_COHERENT_CACHE
124 __dma_free_coherent(size, vaddr);
125#else
126 free_pages((unsigned long)vaddr, get_order(size));
127#endif
128}
129
130static void *dma_nommu_alloc_coherent(struct device *dev, size_t size,
131 dma_addr_t *dma_handle, gfp_t flag,
132 unsigned long attrs)
133{
134 struct iommu_table *iommu;
135
136 /* The coherent mask may be smaller than the real mask, check if
137 * we can really use the direct ops
138 */
139 if (dma_nommu_dma_supported(dev, dev->coherent_dma_mask))
140 return __dma_nommu_alloc_coherent(dev, size, dma_handle,
141 flag, attrs);
142
143 /* Ok we can't ... do we have an iommu ? If not, fail */
144 iommu = get_iommu_table_base(dev);
145 if (!iommu)
146 return NULL;
147
148 /* Try to use the iommu */
149 return iommu_alloc_coherent(dev, iommu, size, dma_handle,
150 dev->coherent_dma_mask, flag,
151 dev_to_node(dev));
152}
153
154static void dma_nommu_free_coherent(struct device *dev, size_t size,
155 void *vaddr, dma_addr_t dma_handle,
156 unsigned long attrs)
157{
158 struct iommu_table *iommu;
159
160 /* See comments in dma_nommu_alloc_coherent() */
161 if (dma_nommu_dma_supported(dev, dev->coherent_dma_mask))
162 return __dma_nommu_free_coherent(dev, size, vaddr, dma_handle,
163 attrs);
164 /* Maybe we used an iommu ... */
165 iommu = get_iommu_table_base(dev);
166
167 /* If we hit that we should have never allocated in the first
168 * place so how come we are freeing ?
169 */
170 if (WARN_ON(!iommu))
171 return;
172 iommu_free_coherent(iommu, size, vaddr, dma_handle);
173}
174
175int dma_nommu_mmap_coherent(struct device *dev, struct vm_area_struct *vma,
176 void *cpu_addr, dma_addr_t handle, size_t size,
177 unsigned long attrs)
178{
179 unsigned long pfn;
180
181#ifdef CONFIG_NOT_COHERENT_CACHE
182 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
183 pfn = __dma_get_coherent_pfn((unsigned long)cpu_addr);
184#else
185 pfn = page_to_pfn(virt_to_page(cpu_addr));
186#endif
187 return remap_pfn_range(vma, vma->vm_start,
188 pfn + vma->vm_pgoff,
189 vma->vm_end - vma->vm_start,
190 vma->vm_page_prot);
191}
192
193static int dma_nommu_map_sg(struct device *dev, struct scatterlist *sgl,
194 int nents, enum dma_data_direction direction,
195 unsigned long attrs)
196{
197 struct scatterlist *sg;
198 int i;
199
200 for_each_sg(sgl, sg, nents, i) {
201 sg->dma_address = sg_phys(sg) + get_dma_offset(dev);
202 sg->dma_length = sg->length;
203
204 if (attrs & DMA_ATTR_SKIP_CPU_SYNC)
205 continue;
206
207 __dma_sync_page(sg_page(sg), sg->offset, sg->length, direction);
208 }
209
210 return nents;
211}
212
213static void dma_nommu_unmap_sg(struct device *dev, struct scatterlist *sg,
214 int nents, enum dma_data_direction direction,
215 unsigned long attrs)
216{
217}
218
219static u64 dma_nommu_get_required_mask(struct device *dev)
220{
221 u64 end, mask;
222
223 end = memblock_end_of_DRAM() + get_dma_offset(dev);
224
225 mask = 1ULL << (fls64(end) - 1);
226 mask += mask - 1;
227
228 return mask;
229}
230
231static inline dma_addr_t dma_nommu_map_page(struct device *dev,
232 struct page *page,
233 unsigned long offset,
234 size_t size,
235 enum dma_data_direction dir,
236 unsigned long attrs)
237{
238 BUG_ON(dir == DMA_NONE);
239
240 if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC))
241 __dma_sync_page(page, offset, size, dir);
242
243 return page_to_phys(page) + offset + get_dma_offset(dev);
244}
245
246static inline void dma_nommu_unmap_page(struct device *dev,
247 dma_addr_t dma_address,
248 size_t size,
249 enum dma_data_direction direction,
250 unsigned long attrs)
251{
252}
253
254#ifdef CONFIG_NOT_COHERENT_CACHE
255static inline void dma_nommu_sync_sg(struct device *dev,
256 struct scatterlist *sgl, int nents,
257 enum dma_data_direction direction)
258{
259 struct scatterlist *sg;
260 int i;
261
262 for_each_sg(sgl, sg, nents, i)
263 __dma_sync_page(sg_page(sg), sg->offset, sg->length, direction);
264}
265
266static inline void dma_nommu_sync_single(struct device *dev,
267 dma_addr_t dma_handle, size_t size,
268 enum dma_data_direction direction)
269{
270 __dma_sync(bus_to_virt(dma_handle), size, direction);
271}
272#endif
273
274const struct dma_map_ops dma_nommu_ops = {
275 .alloc = dma_nommu_alloc_coherent,
276 .free = dma_nommu_free_coherent,
277 .mmap = dma_nommu_mmap_coherent,
278 .map_sg = dma_nommu_map_sg,
279 .unmap_sg = dma_nommu_unmap_sg,
280 .dma_supported = dma_nommu_dma_supported,
281 .map_page = dma_nommu_map_page,
282 .unmap_page = dma_nommu_unmap_page,
283 .get_required_mask = dma_nommu_get_required_mask,
284#ifdef CONFIG_NOT_COHERENT_CACHE
285 .sync_single_for_cpu = dma_nommu_sync_single,
286 .sync_single_for_device = dma_nommu_sync_single,
287 .sync_sg_for_cpu = dma_nommu_sync_sg,
288 .sync_sg_for_device = dma_nommu_sync_sg,
289#endif
290};
291EXPORT_SYMBOL(dma_nommu_ops);
292
293int dma_set_coherent_mask(struct device *dev, u64 mask)
294{
295 if (!dma_supported(dev, mask)) {
296 /*
297 * We need to special case the direct DMA ops which can
298 * support a fallback for coherent allocations. There
299 * is no dma_op->set_coherent_mask() so we have to do
300 * things the hard way:
301 */
302 if (get_dma_ops(dev) != &dma_nommu_ops ||
303 get_iommu_table_base(dev) == NULL ||
304 !dma_iommu_dma_supported(dev, mask))
305 return -EIO;
306 }
307 dev->coherent_dma_mask = mask;
308 return 0;
309}
310EXPORT_SYMBOL(dma_set_coherent_mask);
311
312#define PREALLOC_DMA_DEBUG_ENTRIES (1 << 16)
313
314int dma_set_mask(struct device *dev, u64 dma_mask)
315{
316 if (ppc_md.dma_set_mask)
317 return ppc_md.dma_set_mask(dev, dma_mask);
318
319 if (dev_is_pci(dev)) {
320 struct pci_dev *pdev = to_pci_dev(dev);
321 struct pci_controller *phb = pci_bus_to_host(pdev->bus);
322 if (phb->controller_ops.dma_set_mask)
323 return phb->controller_ops.dma_set_mask(pdev, dma_mask);
324 }
325
326 if (!dev->dma_mask || !dma_supported(dev, dma_mask))
327 return -EIO;
328 *dev->dma_mask = dma_mask;
329 return 0;
330}
331EXPORT_SYMBOL(dma_set_mask);
332
333u64 __dma_get_required_mask(struct device *dev)
334{
335 const struct dma_map_ops *dma_ops = get_dma_ops(dev);
336
337 if (unlikely(dma_ops == NULL))
338 return 0;
339
340 if (dma_ops->get_required_mask)
341 return dma_ops->get_required_mask(dev);
342
343 return DMA_BIT_MASK(8 * sizeof(dma_addr_t));
344}
345
346u64 dma_get_required_mask(struct device *dev)
347{
348 if (ppc_md.dma_get_required_mask)
349 return ppc_md.dma_get_required_mask(dev);
350
351 if (dev_is_pci(dev)) {
352 struct pci_dev *pdev = to_pci_dev(dev);
353 struct pci_controller *phb = pci_bus_to_host(pdev->bus);
354 if (phb->controller_ops.dma_get_required_mask)
355 return phb->controller_ops.dma_get_required_mask(pdev);
356 }
357
358 return __dma_get_required_mask(dev);
359}
360EXPORT_SYMBOL_GPL(dma_get_required_mask);
361
362static int __init dma_init(void)
363{
364 dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES);
365#ifdef CONFIG_PCI
366 dma_debug_add_bus(&pci_bus_type);
367#endif
368#ifdef CONFIG_IBMVIO
369 dma_debug_add_bus(&vio_bus_type);
370#endif
371
372 return 0;
373}
374fs_initcall(dma_init);
375