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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * TI QSPI driver
4 *
5 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com
6 * Author: Sourav Poddar <sourav.poddar@ti.com>
7 */
8
9#include <linux/kernel.h>
10#include <linux/init.h>
11#include <linux/interrupt.h>
12#include <linux/module.h>
13#include <linux/device.h>
14#include <linux/delay.h>
15#include <linux/dma-mapping.h>
16#include <linux/dmaengine.h>
17#include <linux/omap-dma.h>
18#include <linux/platform_device.h>
19#include <linux/err.h>
20#include <linux/clk.h>
21#include <linux/io.h>
22#include <linux/slab.h>
23#include <linux/pm_runtime.h>
24#include <linux/of.h>
25#include <linux/of_device.h>
26#include <linux/pinctrl/consumer.h>
27#include <linux/mfd/syscon.h>
28#include <linux/regmap.h>
29#include <linux/sizes.h>
30
31#include <linux/spi/spi.h>
32#include <linux/spi/spi-mem.h>
33
34struct ti_qspi_regs {
35 u32 clkctrl;
36};
37
38struct ti_qspi {
39 struct completion transfer_complete;
40
41 /* list synchronization */
42 struct mutex list_lock;
43
44 struct spi_master *master;
45 void __iomem *base;
46 void __iomem *mmap_base;
47 size_t mmap_size;
48 struct regmap *ctrl_base;
49 unsigned int ctrl_reg;
50 struct clk *fclk;
51 struct device *dev;
52
53 struct ti_qspi_regs ctx_reg;
54
55 dma_addr_t mmap_phys_base;
56 dma_addr_t rx_bb_dma_addr;
57 void *rx_bb_addr;
58 struct dma_chan *rx_chan;
59
60 u32 spi_max_frequency;
61 u32 cmd;
62 u32 dc;
63
64 bool mmap_enabled;
65 int current_cs;
66};
67
68#define QSPI_PID (0x0)
69#define QSPI_SYSCONFIG (0x10)
70#define QSPI_SPI_CLOCK_CNTRL_REG (0x40)
71#define QSPI_SPI_DC_REG (0x44)
72#define QSPI_SPI_CMD_REG (0x48)
73#define QSPI_SPI_STATUS_REG (0x4c)
74#define QSPI_SPI_DATA_REG (0x50)
75#define QSPI_SPI_SETUP_REG(n) ((0x54 + 4 * n))
76#define QSPI_SPI_SWITCH_REG (0x64)
77#define QSPI_SPI_DATA_REG_1 (0x68)
78#define QSPI_SPI_DATA_REG_2 (0x6c)
79#define QSPI_SPI_DATA_REG_3 (0x70)
80
81#define QSPI_COMPLETION_TIMEOUT msecs_to_jiffies(2000)
82
83/* Clock Control */
84#define QSPI_CLK_EN (1 << 31)
85#define QSPI_CLK_DIV_MAX 0xffff
86
87/* Command */
88#define QSPI_EN_CS(n) (n << 28)
89#define QSPI_WLEN(n) ((n - 1) << 19)
90#define QSPI_3_PIN (1 << 18)
91#define QSPI_RD_SNGL (1 << 16)
92#define QSPI_WR_SNGL (2 << 16)
93#define QSPI_RD_DUAL (3 << 16)
94#define QSPI_RD_QUAD (7 << 16)
95#define QSPI_INVAL (4 << 16)
96#define QSPI_FLEN(n) ((n - 1) << 0)
97#define QSPI_WLEN_MAX_BITS 128
98#define QSPI_WLEN_MAX_BYTES 16
99#define QSPI_WLEN_MASK QSPI_WLEN(QSPI_WLEN_MAX_BITS)
100
101/* STATUS REGISTER */
102#define BUSY 0x01
103#define WC 0x02
104
105/* Device Control */
106#define QSPI_DD(m, n) (m << (3 + n * 8))
107#define QSPI_CKPHA(n) (1 << (2 + n * 8))
108#define QSPI_CSPOL(n) (1 << (1 + n * 8))
109#define QSPI_CKPOL(n) (1 << (n * 8))
110
111#define QSPI_FRAME 4096
112
113#define QSPI_AUTOSUSPEND_TIMEOUT 2000
114
115#define MEM_CS_EN(n) ((n + 1) << 8)
116#define MEM_CS_MASK (7 << 8)
117
118#define MM_SWITCH 0x1
119
120#define QSPI_SETUP_RD_NORMAL (0x0 << 12)
121#define QSPI_SETUP_RD_DUAL (0x1 << 12)
122#define QSPI_SETUP_RD_QUAD (0x3 << 12)
123#define QSPI_SETUP_ADDR_SHIFT 8
124#define QSPI_SETUP_DUMMY_SHIFT 10
125
126#define QSPI_DMA_BUFFER_SIZE SZ_64K
127
128static inline unsigned long ti_qspi_read(struct ti_qspi *qspi,
129 unsigned long reg)
130{
131 return readl(qspi->base + reg);
132}
133
134static inline void ti_qspi_write(struct ti_qspi *qspi,
135 unsigned long val, unsigned long reg)
136{
137 writel(val, qspi->base + reg);
138}
139
140static int ti_qspi_setup(struct spi_device *spi)
141{
142 struct ti_qspi *qspi = spi_master_get_devdata(spi->master);
143 struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
144 int clk_div = 0, ret;
145 u32 clk_ctrl_reg, clk_rate, clk_mask;
146
147 if (spi->master->busy) {
148 dev_dbg(qspi->dev, "master busy doing other transfers\n");
149 return -EBUSY;
150 }
151
152 if (!qspi->spi_max_frequency) {
153 dev_err(qspi->dev, "spi max frequency not defined\n");
154 return -EINVAL;
155 }
156
157 clk_rate = clk_get_rate(qspi->fclk);
158
159 clk_div = DIV_ROUND_UP(clk_rate, qspi->spi_max_frequency) - 1;
160
161 if (clk_div < 0) {
162 dev_dbg(qspi->dev, "clock divider < 0, using /1 divider\n");
163 return -EINVAL;
164 }
165
166 if (clk_div > QSPI_CLK_DIV_MAX) {
167 dev_dbg(qspi->dev, "clock divider >%d , using /%d divider\n",
168 QSPI_CLK_DIV_MAX, QSPI_CLK_DIV_MAX + 1);
169 return -EINVAL;
170 }
171
172 dev_dbg(qspi->dev, "hz: %d, clock divider %d\n",
173 qspi->spi_max_frequency, clk_div);
174
175 ret = pm_runtime_get_sync(qspi->dev);
176 if (ret < 0) {
177 dev_err(qspi->dev, "pm_runtime_get_sync() failed\n");
178 return ret;
179 }
180
181 clk_ctrl_reg = ti_qspi_read(qspi, QSPI_SPI_CLOCK_CNTRL_REG);
182
183 clk_ctrl_reg &= ~QSPI_CLK_EN;
184
185 /* disable SCLK */
186 ti_qspi_write(qspi, clk_ctrl_reg, QSPI_SPI_CLOCK_CNTRL_REG);
187
188 /* enable SCLK */
189 clk_mask = QSPI_CLK_EN | clk_div;
190 ti_qspi_write(qspi, clk_mask, QSPI_SPI_CLOCK_CNTRL_REG);
191 ctx_reg->clkctrl = clk_mask;
192
193 pm_runtime_mark_last_busy(qspi->dev);
194 ret = pm_runtime_put_autosuspend(qspi->dev);
195 if (ret < 0) {
196 dev_err(qspi->dev, "pm_runtime_put_autosuspend() failed\n");
197 return ret;
198 }
199
200 return 0;
201}
202
203static void ti_qspi_restore_ctx(struct ti_qspi *qspi)
204{
205 struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
206
207 ti_qspi_write(qspi, ctx_reg->clkctrl, QSPI_SPI_CLOCK_CNTRL_REG);
208}
209
210static inline u32 qspi_is_busy(struct ti_qspi *qspi)
211{
212 u32 stat;
213 unsigned long timeout = jiffies + QSPI_COMPLETION_TIMEOUT;
214
215 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
216 while ((stat & BUSY) && time_after(timeout, jiffies)) {
217 cpu_relax();
218 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
219 }
220
221 WARN(stat & BUSY, "qspi busy\n");
222 return stat & BUSY;
223}
224
225static inline int ti_qspi_poll_wc(struct ti_qspi *qspi)
226{
227 u32 stat;
228 unsigned long timeout = jiffies + QSPI_COMPLETION_TIMEOUT;
229
230 do {
231 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
232 if (stat & WC)
233 return 0;
234 cpu_relax();
235 } while (time_after(timeout, jiffies));
236
237 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
238 if (stat & WC)
239 return 0;
240 return -ETIMEDOUT;
241}
242
243static int qspi_write_msg(struct ti_qspi *qspi, struct spi_transfer *t,
244 int count)
245{
246 int wlen, xfer_len;
247 unsigned int cmd;
248 const u8 *txbuf;
249 u32 data;
250
251 txbuf = t->tx_buf;
252 cmd = qspi->cmd | QSPI_WR_SNGL;
253 wlen = t->bits_per_word >> 3; /* in bytes */
254 xfer_len = wlen;
255
256 while (count) {
257 if (qspi_is_busy(qspi))
258 return -EBUSY;
259
260 switch (wlen) {
261 case 1:
262 dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %02x\n",
263 cmd, qspi->dc, *txbuf);
264 if (count >= QSPI_WLEN_MAX_BYTES) {
265 u32 *txp = (u32 *)txbuf;
266
267 data = cpu_to_be32(*txp++);
268 writel(data, qspi->base +
269 QSPI_SPI_DATA_REG_3);
270 data = cpu_to_be32(*txp++);
271 writel(data, qspi->base +
272 QSPI_SPI_DATA_REG_2);
273 data = cpu_to_be32(*txp++);
274 writel(data, qspi->base +
275 QSPI_SPI_DATA_REG_1);
276 data = cpu_to_be32(*txp++);
277 writel(data, qspi->base +
278 QSPI_SPI_DATA_REG);
279 xfer_len = QSPI_WLEN_MAX_BYTES;
280 cmd |= QSPI_WLEN(QSPI_WLEN_MAX_BITS);
281 } else {
282 writeb(*txbuf, qspi->base + QSPI_SPI_DATA_REG);
283 cmd = qspi->cmd | QSPI_WR_SNGL;
284 xfer_len = wlen;
285 cmd |= QSPI_WLEN(wlen);
286 }
287 break;
288 case 2:
289 dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %04x\n",
290 cmd, qspi->dc, *txbuf);
291 writew(*((u16 *)txbuf), qspi->base + QSPI_SPI_DATA_REG);
292 break;
293 case 4:
294 dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %08x\n",
295 cmd, qspi->dc, *txbuf);
296 writel(*((u32 *)txbuf), qspi->base + QSPI_SPI_DATA_REG);
297 break;
298 }
299
300 ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
301 if (ti_qspi_poll_wc(qspi)) {
302 dev_err(qspi->dev, "write timed out\n");
303 return -ETIMEDOUT;
304 }
305 txbuf += xfer_len;
306 count -= xfer_len;
307 }
308
309 return 0;
310}
311
312static int qspi_read_msg(struct ti_qspi *qspi, struct spi_transfer *t,
313 int count)
314{
315 int wlen;
316 unsigned int cmd;
317 u32 rx;
318 u8 rxlen, rx_wlen;
319 u8 *rxbuf;
320
321 rxbuf = t->rx_buf;
322 cmd = qspi->cmd;
323 switch (t->rx_nbits) {
324 case SPI_NBITS_DUAL:
325 cmd |= QSPI_RD_DUAL;
326 break;
327 case SPI_NBITS_QUAD:
328 cmd |= QSPI_RD_QUAD;
329 break;
330 default:
331 cmd |= QSPI_RD_SNGL;
332 break;
333 }
334 wlen = t->bits_per_word >> 3; /* in bytes */
335 rx_wlen = wlen;
336
337 while (count) {
338 dev_dbg(qspi->dev, "rx cmd %08x dc %08x\n", cmd, qspi->dc);
339 if (qspi_is_busy(qspi))
340 return -EBUSY;
341
342 switch (wlen) {
343 case 1:
344 /*
345 * Optimize the 8-bit words transfers, as used by
346 * the SPI flash devices.
347 */
348 if (count >= QSPI_WLEN_MAX_BYTES) {
349 rxlen = QSPI_WLEN_MAX_BYTES;
350 } else {
351 rxlen = min(count, 4);
352 }
353 rx_wlen = rxlen << 3;
354 cmd &= ~QSPI_WLEN_MASK;
355 cmd |= QSPI_WLEN(rx_wlen);
356 break;
357 default:
358 rxlen = wlen;
359 break;
360 }
361
362 ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
363 if (ti_qspi_poll_wc(qspi)) {
364 dev_err(qspi->dev, "read timed out\n");
365 return -ETIMEDOUT;
366 }
367
368 switch (wlen) {
369 case 1:
370 /*
371 * Optimize the 8-bit words transfers, as used by
372 * the SPI flash devices.
373 */
374 if (count >= QSPI_WLEN_MAX_BYTES) {
375 u32 *rxp = (u32 *) rxbuf;
376 rx = readl(qspi->base + QSPI_SPI_DATA_REG_3);
377 *rxp++ = be32_to_cpu(rx);
378 rx = readl(qspi->base + QSPI_SPI_DATA_REG_2);
379 *rxp++ = be32_to_cpu(rx);
380 rx = readl(qspi->base + QSPI_SPI_DATA_REG_1);
381 *rxp++ = be32_to_cpu(rx);
382 rx = readl(qspi->base + QSPI_SPI_DATA_REG);
383 *rxp++ = be32_to_cpu(rx);
384 } else {
385 u8 *rxp = rxbuf;
386 rx = readl(qspi->base + QSPI_SPI_DATA_REG);
387 if (rx_wlen >= 8)
388 *rxp++ = rx >> (rx_wlen - 8);
389 if (rx_wlen >= 16)
390 *rxp++ = rx >> (rx_wlen - 16);
391 if (rx_wlen >= 24)
392 *rxp++ = rx >> (rx_wlen - 24);
393 if (rx_wlen >= 32)
394 *rxp++ = rx;
395 }
396 break;
397 case 2:
398 *((u16 *)rxbuf) = readw(qspi->base + QSPI_SPI_DATA_REG);
399 break;
400 case 4:
401 *((u32 *)rxbuf) = readl(qspi->base + QSPI_SPI_DATA_REG);
402 break;
403 }
404 rxbuf += rxlen;
405 count -= rxlen;
406 }
407
408 return 0;
409}
410
411static int qspi_transfer_msg(struct ti_qspi *qspi, struct spi_transfer *t,
412 int count)
413{
414 int ret;
415
416 if (t->tx_buf) {
417 ret = qspi_write_msg(qspi, t, count);
418 if (ret) {
419 dev_dbg(qspi->dev, "Error while writing\n");
420 return ret;
421 }
422 }
423
424 if (t->rx_buf) {
425 ret = qspi_read_msg(qspi, t, count);
426 if (ret) {
427 dev_dbg(qspi->dev, "Error while reading\n");
428 return ret;
429 }
430 }
431
432 return 0;
433}
434
435static void ti_qspi_dma_callback(void *param)
436{
437 struct ti_qspi *qspi = param;
438
439 complete(&qspi->transfer_complete);
440}
441
442static int ti_qspi_dma_xfer(struct ti_qspi *qspi, dma_addr_t dma_dst,
443 dma_addr_t dma_src, size_t len)
444{
445 struct dma_chan *chan = qspi->rx_chan;
446 dma_cookie_t cookie;
447 enum dma_ctrl_flags flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
448 struct dma_async_tx_descriptor *tx;
449 int ret;
450
451 tx = dmaengine_prep_dma_memcpy(chan, dma_dst, dma_src, len, flags);
452 if (!tx) {
453 dev_err(qspi->dev, "device_prep_dma_memcpy error\n");
454 return -EIO;
455 }
456
457 tx->callback = ti_qspi_dma_callback;
458 tx->callback_param = qspi;
459 cookie = tx->tx_submit(tx);
460 reinit_completion(&qspi->transfer_complete);
461
462 ret = dma_submit_error(cookie);
463 if (ret) {
464 dev_err(qspi->dev, "dma_submit_error %d\n", cookie);
465 return -EIO;
466 }
467
468 dma_async_issue_pending(chan);
469 ret = wait_for_completion_timeout(&qspi->transfer_complete,
470 msecs_to_jiffies(len));
471 if (ret <= 0) {
472 dmaengine_terminate_sync(chan);
473 dev_err(qspi->dev, "DMA wait_for_completion_timeout\n");
474 return -ETIMEDOUT;
475 }
476
477 return 0;
478}
479
480static int ti_qspi_dma_bounce_buffer(struct ti_qspi *qspi, loff_t offs,
481 void *to, size_t readsize)
482{
483 dma_addr_t dma_src = qspi->mmap_phys_base + offs;
484 int ret = 0;
485
486 /*
487 * Use bounce buffer as FS like jffs2, ubifs may pass
488 * buffers that does not belong to kernel lowmem region.
489 */
490 while (readsize != 0) {
491 size_t xfer_len = min_t(size_t, QSPI_DMA_BUFFER_SIZE,
492 readsize);
493
494 ret = ti_qspi_dma_xfer(qspi, qspi->rx_bb_dma_addr,
495 dma_src, xfer_len);
496 if (ret != 0)
497 return ret;
498 memcpy(to, qspi->rx_bb_addr, xfer_len);
499 readsize -= xfer_len;
500 dma_src += xfer_len;
501 to += xfer_len;
502 }
503
504 return ret;
505}
506
507static int ti_qspi_dma_xfer_sg(struct ti_qspi *qspi, struct sg_table rx_sg,
508 loff_t from)
509{
510 struct scatterlist *sg;
511 dma_addr_t dma_src = qspi->mmap_phys_base + from;
512 dma_addr_t dma_dst;
513 int i, len, ret;
514
515 for_each_sg(rx_sg.sgl, sg, rx_sg.nents, i) {
516 dma_dst = sg_dma_address(sg);
517 len = sg_dma_len(sg);
518 ret = ti_qspi_dma_xfer(qspi, dma_dst, dma_src, len);
519 if (ret)
520 return ret;
521 dma_src += len;
522 }
523
524 return 0;
525}
526
527static void ti_qspi_enable_memory_map(struct spi_device *spi)
528{
529 struct ti_qspi *qspi = spi_master_get_devdata(spi->master);
530
531 ti_qspi_write(qspi, MM_SWITCH, QSPI_SPI_SWITCH_REG);
532 if (qspi->ctrl_base) {
533 regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg,
534 MEM_CS_MASK,
535 MEM_CS_EN(spi->chip_select));
536 }
537 qspi->mmap_enabled = true;
538 qspi->current_cs = spi->chip_select;
539}
540
541static void ti_qspi_disable_memory_map(struct spi_device *spi)
542{
543 struct ti_qspi *qspi = spi_master_get_devdata(spi->master);
544
545 ti_qspi_write(qspi, 0, QSPI_SPI_SWITCH_REG);
546 if (qspi->ctrl_base)
547 regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg,
548 MEM_CS_MASK, 0);
549 qspi->mmap_enabled = false;
550 qspi->current_cs = -1;
551}
552
553static void ti_qspi_setup_mmap_read(struct spi_device *spi, u8 opcode,
554 u8 data_nbits, u8 addr_width,
555 u8 dummy_bytes)
556{
557 struct ti_qspi *qspi = spi_master_get_devdata(spi->master);
558 u32 memval = opcode;
559
560 switch (data_nbits) {
561 case SPI_NBITS_QUAD:
562 memval |= QSPI_SETUP_RD_QUAD;
563 break;
564 case SPI_NBITS_DUAL:
565 memval |= QSPI_SETUP_RD_DUAL;
566 break;
567 default:
568 memval |= QSPI_SETUP_RD_NORMAL;
569 break;
570 }
571 memval |= ((addr_width - 1) << QSPI_SETUP_ADDR_SHIFT |
572 dummy_bytes << QSPI_SETUP_DUMMY_SHIFT);
573 ti_qspi_write(qspi, memval,
574 QSPI_SPI_SETUP_REG(spi->chip_select));
575}
576
577static int ti_qspi_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op)
578{
579 struct ti_qspi *qspi = spi_controller_get_devdata(mem->spi->master);
580 size_t max_len;
581
582 if (op->data.dir == SPI_MEM_DATA_IN) {
583 if (op->addr.val < qspi->mmap_size) {
584 /* Limit MMIO to the mmaped region */
585 if (op->addr.val + op->data.nbytes > qspi->mmap_size) {
586 max_len = qspi->mmap_size - op->addr.val;
587 op->data.nbytes = min((size_t) op->data.nbytes,
588 max_len);
589 }
590 } else {
591 /*
592 * Use fallback mode (SW generated transfers) above the
593 * mmaped region.
594 * Adjust size to comply with the QSPI max frame length.
595 */
596 max_len = QSPI_FRAME;
597 max_len -= 1 + op->addr.nbytes + op->dummy.nbytes;
598 op->data.nbytes = min((size_t) op->data.nbytes,
599 max_len);
600 }
601 }
602
603 return 0;
604}
605
606static int ti_qspi_exec_mem_op(struct spi_mem *mem,
607 const struct spi_mem_op *op)
608{
609 struct ti_qspi *qspi = spi_master_get_devdata(mem->spi->master);
610 u32 from = 0;
611 int ret = 0;
612
613 /* Only optimize read path. */
614 if (!op->data.nbytes || op->data.dir != SPI_MEM_DATA_IN ||
615 !op->addr.nbytes || op->addr.nbytes > 4)
616 return -ENOTSUPP;
617
618 /* Address exceeds MMIO window size, fall back to regular mode. */
619 from = op->addr.val;
620 if (from + op->data.nbytes > qspi->mmap_size)
621 return -ENOTSUPP;
622
623 mutex_lock(&qspi->list_lock);
624
625 if (!qspi->mmap_enabled || qspi->current_cs != mem->spi->chip_select)
626 ti_qspi_enable_memory_map(mem->spi);
627 ti_qspi_setup_mmap_read(mem->spi, op->cmd.opcode, op->data.buswidth,
628 op->addr.nbytes, op->dummy.nbytes);
629
630 if (qspi->rx_chan) {
631 struct sg_table sgt;
632
633 if (virt_addr_valid(op->data.buf.in) &&
634 !spi_controller_dma_map_mem_op_data(mem->spi->master, op,
635 &sgt)) {
636 ret = ti_qspi_dma_xfer_sg(qspi, sgt, from);
637 spi_controller_dma_unmap_mem_op_data(mem->spi->master,
638 op, &sgt);
639 } else {
640 ret = ti_qspi_dma_bounce_buffer(qspi, from,
641 op->data.buf.in,
642 op->data.nbytes);
643 }
644 } else {
645 memcpy_fromio(op->data.buf.in, qspi->mmap_base + from,
646 op->data.nbytes);
647 }
648
649 mutex_unlock(&qspi->list_lock);
650
651 return ret;
652}
653
654static const struct spi_controller_mem_ops ti_qspi_mem_ops = {
655 .exec_op = ti_qspi_exec_mem_op,
656 .adjust_op_size = ti_qspi_adjust_op_size,
657};
658
659static int ti_qspi_start_transfer_one(struct spi_master *master,
660 struct spi_message *m)
661{
662 struct ti_qspi *qspi = spi_master_get_devdata(master);
663 struct spi_device *spi = m->spi;
664 struct spi_transfer *t;
665 int status = 0, ret;
666 unsigned int frame_len_words, transfer_len_words;
667 int wlen;
668
669 /* setup device control reg */
670 qspi->dc = 0;
671
672 if (spi->mode & SPI_CPHA)
673 qspi->dc |= QSPI_CKPHA(spi->chip_select);
674 if (spi->mode & SPI_CPOL)
675 qspi->dc |= QSPI_CKPOL(spi->chip_select);
676 if (spi->mode & SPI_CS_HIGH)
677 qspi->dc |= QSPI_CSPOL(spi->chip_select);
678
679 frame_len_words = 0;
680 list_for_each_entry(t, &m->transfers, transfer_list)
681 frame_len_words += t->len / (t->bits_per_word >> 3);
682 frame_len_words = min_t(unsigned int, frame_len_words, QSPI_FRAME);
683
684 /* setup command reg */
685 qspi->cmd = 0;
686 qspi->cmd |= QSPI_EN_CS(spi->chip_select);
687 qspi->cmd |= QSPI_FLEN(frame_len_words);
688
689 ti_qspi_write(qspi, qspi->dc, QSPI_SPI_DC_REG);
690
691 mutex_lock(&qspi->list_lock);
692
693 if (qspi->mmap_enabled)
694 ti_qspi_disable_memory_map(spi);
695
696 list_for_each_entry(t, &m->transfers, transfer_list) {
697 qspi->cmd = ((qspi->cmd & ~QSPI_WLEN_MASK) |
698 QSPI_WLEN(t->bits_per_word));
699
700 wlen = t->bits_per_word >> 3;
701 transfer_len_words = min(t->len / wlen, frame_len_words);
702
703 ret = qspi_transfer_msg(qspi, t, transfer_len_words * wlen);
704 if (ret) {
705 dev_dbg(qspi->dev, "transfer message failed\n");
706 mutex_unlock(&qspi->list_lock);
707 return -EINVAL;
708 }
709
710 m->actual_length += transfer_len_words * wlen;
711 frame_len_words -= transfer_len_words;
712 if (frame_len_words == 0)
713 break;
714 }
715
716 mutex_unlock(&qspi->list_lock);
717
718 ti_qspi_write(qspi, qspi->cmd | QSPI_INVAL, QSPI_SPI_CMD_REG);
719 m->status = status;
720 spi_finalize_current_message(master);
721
722 return status;
723}
724
725static int ti_qspi_runtime_resume(struct device *dev)
726{
727 struct ti_qspi *qspi;
728
729 qspi = dev_get_drvdata(dev);
730 ti_qspi_restore_ctx(qspi);
731
732 return 0;
733}
734
735static const struct of_device_id ti_qspi_match[] = {
736 {.compatible = "ti,dra7xxx-qspi" },
737 {.compatible = "ti,am4372-qspi" },
738 {},
739};
740MODULE_DEVICE_TABLE(of, ti_qspi_match);
741
742static int ti_qspi_probe(struct platform_device *pdev)
743{
744 struct ti_qspi *qspi;
745 struct spi_master *master;
746 struct resource *r, *res_mmap;
747 struct device_node *np = pdev->dev.of_node;
748 u32 max_freq;
749 int ret = 0, num_cs, irq;
750 dma_cap_mask_t mask;
751
752 master = spi_alloc_master(&pdev->dev, sizeof(*qspi));
753 if (!master)
754 return -ENOMEM;
755
756 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD;
757
758 master->flags = SPI_MASTER_HALF_DUPLEX;
759 master->setup = ti_qspi_setup;
760 master->auto_runtime_pm = true;
761 master->transfer_one_message = ti_qspi_start_transfer_one;
762 master->dev.of_node = pdev->dev.of_node;
763 master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) |
764 SPI_BPW_MASK(8);
765 master->mem_ops = &ti_qspi_mem_ops;
766
767 if (!of_property_read_u32(np, "num-cs", &num_cs))
768 master->num_chipselect = num_cs;
769
770 qspi = spi_master_get_devdata(master);
771 qspi->master = master;
772 qspi->dev = &pdev->dev;
773 platform_set_drvdata(pdev, qspi);
774
775 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_base");
776 if (r == NULL) {
777 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
778 if (r == NULL) {
779 dev_err(&pdev->dev, "missing platform data\n");
780 ret = -ENODEV;
781 goto free_master;
782 }
783 }
784
785 res_mmap = platform_get_resource_byname(pdev,
786 IORESOURCE_MEM, "qspi_mmap");
787 if (res_mmap == NULL) {
788 res_mmap = platform_get_resource(pdev, IORESOURCE_MEM, 1);
789 if (res_mmap == NULL) {
790 dev_err(&pdev->dev,
791 "memory mapped resource not required\n");
792 }
793 }
794
795 if (res_mmap)
796 qspi->mmap_size = resource_size(res_mmap);
797
798 irq = platform_get_irq(pdev, 0);
799 if (irq < 0) {
800 ret = irq;
801 goto free_master;
802 }
803
804 mutex_init(&qspi->list_lock);
805
806 qspi->base = devm_ioremap_resource(&pdev->dev, r);
807 if (IS_ERR(qspi->base)) {
808 ret = PTR_ERR(qspi->base);
809 goto free_master;
810 }
811
812
813 if (of_property_read_bool(np, "syscon-chipselects")) {
814 qspi->ctrl_base =
815 syscon_regmap_lookup_by_phandle(np,
816 "syscon-chipselects");
817 if (IS_ERR(qspi->ctrl_base)) {
818 ret = PTR_ERR(qspi->ctrl_base);
819 goto free_master;
820 }
821 ret = of_property_read_u32_index(np,
822 "syscon-chipselects",
823 1, &qspi->ctrl_reg);
824 if (ret) {
825 dev_err(&pdev->dev,
826 "couldn't get ctrl_mod reg index\n");
827 goto free_master;
828 }
829 }
830
831 qspi->fclk = devm_clk_get(&pdev->dev, "fck");
832 if (IS_ERR(qspi->fclk)) {
833 ret = PTR_ERR(qspi->fclk);
834 dev_err(&pdev->dev, "could not get clk: %d\n", ret);
835 }
836
837 pm_runtime_use_autosuspend(&pdev->dev);
838 pm_runtime_set_autosuspend_delay(&pdev->dev, QSPI_AUTOSUSPEND_TIMEOUT);
839 pm_runtime_enable(&pdev->dev);
840
841 if (!of_property_read_u32(np, "spi-max-frequency", &max_freq))
842 qspi->spi_max_frequency = max_freq;
843
844 dma_cap_zero(mask);
845 dma_cap_set(DMA_MEMCPY, mask);
846
847 qspi->rx_chan = dma_request_chan_by_mask(&mask);
848 if (IS_ERR(qspi->rx_chan)) {
849 dev_err(qspi->dev,
850 "No Rx DMA available, trying mmap mode\n");
851 qspi->rx_chan = NULL;
852 ret = 0;
853 goto no_dma;
854 }
855 qspi->rx_bb_addr = dma_alloc_coherent(qspi->dev,
856 QSPI_DMA_BUFFER_SIZE,
857 &qspi->rx_bb_dma_addr,
858 GFP_KERNEL | GFP_DMA);
859 if (!qspi->rx_bb_addr) {
860 dev_err(qspi->dev,
861 "dma_alloc_coherent failed, using PIO mode\n");
862 dma_release_channel(qspi->rx_chan);
863 goto no_dma;
864 }
865 master->dma_rx = qspi->rx_chan;
866 init_completion(&qspi->transfer_complete);
867 if (res_mmap)
868 qspi->mmap_phys_base = (dma_addr_t)res_mmap->start;
869
870no_dma:
871 if (!qspi->rx_chan && res_mmap) {
872 qspi->mmap_base = devm_ioremap_resource(&pdev->dev, res_mmap);
873 if (IS_ERR(qspi->mmap_base)) {
874 dev_info(&pdev->dev,
875 "mmap failed with error %ld using PIO mode\n",
876 PTR_ERR(qspi->mmap_base));
877 qspi->mmap_base = NULL;
878 master->mem_ops = NULL;
879 }
880 }
881 qspi->mmap_enabled = false;
882 qspi->current_cs = -1;
883
884 ret = devm_spi_register_master(&pdev->dev, master);
885 if (!ret)
886 return 0;
887
888 pm_runtime_disable(&pdev->dev);
889free_master:
890 spi_master_put(master);
891 return ret;
892}
893
894static int ti_qspi_remove(struct platform_device *pdev)
895{
896 struct ti_qspi *qspi = platform_get_drvdata(pdev);
897 int rc;
898
899 rc = spi_master_suspend(qspi->master);
900 if (rc)
901 return rc;
902
903 pm_runtime_put_sync(&pdev->dev);
904 pm_runtime_disable(&pdev->dev);
905
906 if (qspi->rx_bb_addr)
907 dma_free_coherent(qspi->dev, QSPI_DMA_BUFFER_SIZE,
908 qspi->rx_bb_addr,
909 qspi->rx_bb_dma_addr);
910 if (qspi->rx_chan)
911 dma_release_channel(qspi->rx_chan);
912
913 return 0;
914}
915
916static const struct dev_pm_ops ti_qspi_pm_ops = {
917 .runtime_resume = ti_qspi_runtime_resume,
918};
919
920static struct platform_driver ti_qspi_driver = {
921 .probe = ti_qspi_probe,
922 .remove = ti_qspi_remove,
923 .driver = {
924 .name = "ti-qspi",
925 .pm = &ti_qspi_pm_ops,
926 .of_match_table = ti_qspi_match,
927 }
928};
929
930module_platform_driver(ti_qspi_driver);
931
932MODULE_AUTHOR("Sourav Poddar <sourav.poddar@ti.com>");
933MODULE_LICENSE("GPL v2");
934MODULE_DESCRIPTION("TI QSPI controller driver");
935MODULE_ALIAS("platform:ti-qspi");
1/*
2 * TI QSPI driver
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 * Author: Sourav Poddar <sourav.poddar@ti.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GPLv2.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/kernel.h>
17#include <linux/init.h>
18#include <linux/interrupt.h>
19#include <linux/module.h>
20#include <linux/device.h>
21#include <linux/delay.h>
22#include <linux/dma-mapping.h>
23#include <linux/dmaengine.h>
24#include <linux/omap-dma.h>
25#include <linux/platform_device.h>
26#include <linux/err.h>
27#include <linux/clk.h>
28#include <linux/io.h>
29#include <linux/slab.h>
30#include <linux/pm_runtime.h>
31#include <linux/of.h>
32#include <linux/of_device.h>
33#include <linux/pinctrl/consumer.h>
34#include <linux/mfd/syscon.h>
35#include <linux/regmap.h>
36#include <linux/sizes.h>
37
38#include <linux/spi/spi.h>
39
40struct ti_qspi_regs {
41 u32 clkctrl;
42};
43
44struct ti_qspi {
45 struct completion transfer_complete;
46
47 /* list synchronization */
48 struct mutex list_lock;
49
50 struct spi_master *master;
51 void __iomem *base;
52 void __iomem *mmap_base;
53 struct regmap *ctrl_base;
54 unsigned int ctrl_reg;
55 struct clk *fclk;
56 struct device *dev;
57
58 struct ti_qspi_regs ctx_reg;
59
60 dma_addr_t mmap_phys_base;
61 dma_addr_t rx_bb_dma_addr;
62 void *rx_bb_addr;
63 struct dma_chan *rx_chan;
64
65 u32 spi_max_frequency;
66 u32 cmd;
67 u32 dc;
68
69 bool mmap_enabled;
70};
71
72#define QSPI_PID (0x0)
73#define QSPI_SYSCONFIG (0x10)
74#define QSPI_SPI_CLOCK_CNTRL_REG (0x40)
75#define QSPI_SPI_DC_REG (0x44)
76#define QSPI_SPI_CMD_REG (0x48)
77#define QSPI_SPI_STATUS_REG (0x4c)
78#define QSPI_SPI_DATA_REG (0x50)
79#define QSPI_SPI_SETUP_REG(n) ((0x54 + 4 * n))
80#define QSPI_SPI_SWITCH_REG (0x64)
81#define QSPI_SPI_DATA_REG_1 (0x68)
82#define QSPI_SPI_DATA_REG_2 (0x6c)
83#define QSPI_SPI_DATA_REG_3 (0x70)
84
85#define QSPI_COMPLETION_TIMEOUT msecs_to_jiffies(2000)
86
87#define QSPI_FCLK 192000000
88
89/* Clock Control */
90#define QSPI_CLK_EN (1 << 31)
91#define QSPI_CLK_DIV_MAX 0xffff
92
93/* Command */
94#define QSPI_EN_CS(n) (n << 28)
95#define QSPI_WLEN(n) ((n - 1) << 19)
96#define QSPI_3_PIN (1 << 18)
97#define QSPI_RD_SNGL (1 << 16)
98#define QSPI_WR_SNGL (2 << 16)
99#define QSPI_RD_DUAL (3 << 16)
100#define QSPI_RD_QUAD (7 << 16)
101#define QSPI_INVAL (4 << 16)
102#define QSPI_FLEN(n) ((n - 1) << 0)
103#define QSPI_WLEN_MAX_BITS 128
104#define QSPI_WLEN_MAX_BYTES 16
105#define QSPI_WLEN_MASK QSPI_WLEN(QSPI_WLEN_MAX_BITS)
106
107/* STATUS REGISTER */
108#define BUSY 0x01
109#define WC 0x02
110
111/* Device Control */
112#define QSPI_DD(m, n) (m << (3 + n * 8))
113#define QSPI_CKPHA(n) (1 << (2 + n * 8))
114#define QSPI_CSPOL(n) (1 << (1 + n * 8))
115#define QSPI_CKPOL(n) (1 << (n * 8))
116
117#define QSPI_FRAME 4096
118
119#define QSPI_AUTOSUSPEND_TIMEOUT 2000
120
121#define MEM_CS_EN(n) ((n + 1) << 8)
122#define MEM_CS_MASK (7 << 8)
123
124#define MM_SWITCH 0x1
125
126#define QSPI_SETUP_RD_NORMAL (0x0 << 12)
127#define QSPI_SETUP_RD_DUAL (0x1 << 12)
128#define QSPI_SETUP_RD_QUAD (0x3 << 12)
129#define QSPI_SETUP_ADDR_SHIFT 8
130#define QSPI_SETUP_DUMMY_SHIFT 10
131
132#define QSPI_DMA_BUFFER_SIZE SZ_64K
133
134static inline unsigned long ti_qspi_read(struct ti_qspi *qspi,
135 unsigned long reg)
136{
137 return readl(qspi->base + reg);
138}
139
140static inline void ti_qspi_write(struct ti_qspi *qspi,
141 unsigned long val, unsigned long reg)
142{
143 writel(val, qspi->base + reg);
144}
145
146static int ti_qspi_setup(struct spi_device *spi)
147{
148 struct ti_qspi *qspi = spi_master_get_devdata(spi->master);
149 struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
150 int clk_div = 0, ret;
151 u32 clk_ctrl_reg, clk_rate, clk_mask;
152
153 if (spi->master->busy) {
154 dev_dbg(qspi->dev, "master busy doing other transfers\n");
155 return -EBUSY;
156 }
157
158 if (!qspi->spi_max_frequency) {
159 dev_err(qspi->dev, "spi max frequency not defined\n");
160 return -EINVAL;
161 }
162
163 clk_rate = clk_get_rate(qspi->fclk);
164
165 clk_div = DIV_ROUND_UP(clk_rate, qspi->spi_max_frequency) - 1;
166
167 if (clk_div < 0) {
168 dev_dbg(qspi->dev, "clock divider < 0, using /1 divider\n");
169 return -EINVAL;
170 }
171
172 if (clk_div > QSPI_CLK_DIV_MAX) {
173 dev_dbg(qspi->dev, "clock divider >%d , using /%d divider\n",
174 QSPI_CLK_DIV_MAX, QSPI_CLK_DIV_MAX + 1);
175 return -EINVAL;
176 }
177
178 dev_dbg(qspi->dev, "hz: %d, clock divider %d\n",
179 qspi->spi_max_frequency, clk_div);
180
181 ret = pm_runtime_get_sync(qspi->dev);
182 if (ret < 0) {
183 dev_err(qspi->dev, "pm_runtime_get_sync() failed\n");
184 return ret;
185 }
186
187 clk_ctrl_reg = ti_qspi_read(qspi, QSPI_SPI_CLOCK_CNTRL_REG);
188
189 clk_ctrl_reg &= ~QSPI_CLK_EN;
190
191 /* disable SCLK */
192 ti_qspi_write(qspi, clk_ctrl_reg, QSPI_SPI_CLOCK_CNTRL_REG);
193
194 /* enable SCLK */
195 clk_mask = QSPI_CLK_EN | clk_div;
196 ti_qspi_write(qspi, clk_mask, QSPI_SPI_CLOCK_CNTRL_REG);
197 ctx_reg->clkctrl = clk_mask;
198
199 pm_runtime_mark_last_busy(qspi->dev);
200 ret = pm_runtime_put_autosuspend(qspi->dev);
201 if (ret < 0) {
202 dev_err(qspi->dev, "pm_runtime_put_autosuspend() failed\n");
203 return ret;
204 }
205
206 return 0;
207}
208
209static void ti_qspi_restore_ctx(struct ti_qspi *qspi)
210{
211 struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
212
213 ti_qspi_write(qspi, ctx_reg->clkctrl, QSPI_SPI_CLOCK_CNTRL_REG);
214}
215
216static inline u32 qspi_is_busy(struct ti_qspi *qspi)
217{
218 u32 stat;
219 unsigned long timeout = jiffies + QSPI_COMPLETION_TIMEOUT;
220
221 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
222 while ((stat & BUSY) && time_after(timeout, jiffies)) {
223 cpu_relax();
224 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
225 }
226
227 WARN(stat & BUSY, "qspi busy\n");
228 return stat & BUSY;
229}
230
231static inline int ti_qspi_poll_wc(struct ti_qspi *qspi)
232{
233 u32 stat;
234 unsigned long timeout = jiffies + QSPI_COMPLETION_TIMEOUT;
235
236 do {
237 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
238 if (stat & WC)
239 return 0;
240 cpu_relax();
241 } while (time_after(timeout, jiffies));
242
243 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
244 if (stat & WC)
245 return 0;
246 return -ETIMEDOUT;
247}
248
249static int qspi_write_msg(struct ti_qspi *qspi, struct spi_transfer *t,
250 int count)
251{
252 int wlen, xfer_len;
253 unsigned int cmd;
254 const u8 *txbuf;
255 u32 data;
256
257 txbuf = t->tx_buf;
258 cmd = qspi->cmd | QSPI_WR_SNGL;
259 wlen = t->bits_per_word >> 3; /* in bytes */
260 xfer_len = wlen;
261
262 while (count) {
263 if (qspi_is_busy(qspi))
264 return -EBUSY;
265
266 switch (wlen) {
267 case 1:
268 dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %02x\n",
269 cmd, qspi->dc, *txbuf);
270 if (count >= QSPI_WLEN_MAX_BYTES) {
271 u32 *txp = (u32 *)txbuf;
272
273 data = cpu_to_be32(*txp++);
274 writel(data, qspi->base +
275 QSPI_SPI_DATA_REG_3);
276 data = cpu_to_be32(*txp++);
277 writel(data, qspi->base +
278 QSPI_SPI_DATA_REG_2);
279 data = cpu_to_be32(*txp++);
280 writel(data, qspi->base +
281 QSPI_SPI_DATA_REG_1);
282 data = cpu_to_be32(*txp++);
283 writel(data, qspi->base +
284 QSPI_SPI_DATA_REG);
285 xfer_len = QSPI_WLEN_MAX_BYTES;
286 cmd |= QSPI_WLEN(QSPI_WLEN_MAX_BITS);
287 } else {
288 writeb(*txbuf, qspi->base + QSPI_SPI_DATA_REG);
289 cmd = qspi->cmd | QSPI_WR_SNGL;
290 xfer_len = wlen;
291 cmd |= QSPI_WLEN(wlen);
292 }
293 break;
294 case 2:
295 dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %04x\n",
296 cmd, qspi->dc, *txbuf);
297 writew(*((u16 *)txbuf), qspi->base + QSPI_SPI_DATA_REG);
298 break;
299 case 4:
300 dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %08x\n",
301 cmd, qspi->dc, *txbuf);
302 writel(*((u32 *)txbuf), qspi->base + QSPI_SPI_DATA_REG);
303 break;
304 }
305
306 ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
307 if (ti_qspi_poll_wc(qspi)) {
308 dev_err(qspi->dev, "write timed out\n");
309 return -ETIMEDOUT;
310 }
311 txbuf += xfer_len;
312 count -= xfer_len;
313 }
314
315 return 0;
316}
317
318static int qspi_read_msg(struct ti_qspi *qspi, struct spi_transfer *t,
319 int count)
320{
321 int wlen;
322 unsigned int cmd;
323 u8 *rxbuf;
324
325 rxbuf = t->rx_buf;
326 cmd = qspi->cmd;
327 switch (t->rx_nbits) {
328 case SPI_NBITS_DUAL:
329 cmd |= QSPI_RD_DUAL;
330 break;
331 case SPI_NBITS_QUAD:
332 cmd |= QSPI_RD_QUAD;
333 break;
334 default:
335 cmd |= QSPI_RD_SNGL;
336 break;
337 }
338 wlen = t->bits_per_word >> 3; /* in bytes */
339
340 while (count) {
341 dev_dbg(qspi->dev, "rx cmd %08x dc %08x\n", cmd, qspi->dc);
342 if (qspi_is_busy(qspi))
343 return -EBUSY;
344
345 ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
346 if (ti_qspi_poll_wc(qspi)) {
347 dev_err(qspi->dev, "read timed out\n");
348 return -ETIMEDOUT;
349 }
350 switch (wlen) {
351 case 1:
352 *rxbuf = readb(qspi->base + QSPI_SPI_DATA_REG);
353 break;
354 case 2:
355 *((u16 *)rxbuf) = readw(qspi->base + QSPI_SPI_DATA_REG);
356 break;
357 case 4:
358 *((u32 *)rxbuf) = readl(qspi->base + QSPI_SPI_DATA_REG);
359 break;
360 }
361 rxbuf += wlen;
362 count -= wlen;
363 }
364
365 return 0;
366}
367
368static int qspi_transfer_msg(struct ti_qspi *qspi, struct spi_transfer *t,
369 int count)
370{
371 int ret;
372
373 if (t->tx_buf) {
374 ret = qspi_write_msg(qspi, t, count);
375 if (ret) {
376 dev_dbg(qspi->dev, "Error while writing\n");
377 return ret;
378 }
379 }
380
381 if (t->rx_buf) {
382 ret = qspi_read_msg(qspi, t, count);
383 if (ret) {
384 dev_dbg(qspi->dev, "Error while reading\n");
385 return ret;
386 }
387 }
388
389 return 0;
390}
391
392static void ti_qspi_dma_callback(void *param)
393{
394 struct ti_qspi *qspi = param;
395
396 complete(&qspi->transfer_complete);
397}
398
399static int ti_qspi_dma_xfer(struct ti_qspi *qspi, dma_addr_t dma_dst,
400 dma_addr_t dma_src, size_t len)
401{
402 struct dma_chan *chan = qspi->rx_chan;
403 dma_cookie_t cookie;
404 enum dma_ctrl_flags flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
405 struct dma_async_tx_descriptor *tx;
406 int ret;
407
408 tx = dmaengine_prep_dma_memcpy(chan, dma_dst, dma_src, len, flags);
409 if (!tx) {
410 dev_err(qspi->dev, "device_prep_dma_memcpy error\n");
411 return -EIO;
412 }
413
414 tx->callback = ti_qspi_dma_callback;
415 tx->callback_param = qspi;
416 cookie = tx->tx_submit(tx);
417 reinit_completion(&qspi->transfer_complete);
418
419 ret = dma_submit_error(cookie);
420 if (ret) {
421 dev_err(qspi->dev, "dma_submit_error %d\n", cookie);
422 return -EIO;
423 }
424
425 dma_async_issue_pending(chan);
426 ret = wait_for_completion_timeout(&qspi->transfer_complete,
427 msecs_to_jiffies(len));
428 if (ret <= 0) {
429 dmaengine_terminate_sync(chan);
430 dev_err(qspi->dev, "DMA wait_for_completion_timeout\n");
431 return -ETIMEDOUT;
432 }
433
434 return 0;
435}
436
437static int ti_qspi_dma_bounce_buffer(struct ti_qspi *qspi,
438 struct spi_flash_read_message *msg)
439{
440 size_t readsize = msg->len;
441 void *to = msg->buf;
442 dma_addr_t dma_src = qspi->mmap_phys_base + msg->from;
443 int ret = 0;
444
445 /*
446 * Use bounce buffer as FS like jffs2, ubifs may pass
447 * buffers that does not belong to kernel lowmem region.
448 */
449 while (readsize != 0) {
450 size_t xfer_len = min_t(size_t, QSPI_DMA_BUFFER_SIZE,
451 readsize);
452
453 ret = ti_qspi_dma_xfer(qspi, qspi->rx_bb_dma_addr,
454 dma_src, xfer_len);
455 if (ret != 0)
456 return ret;
457 memcpy(to, qspi->rx_bb_addr, xfer_len);
458 readsize -= xfer_len;
459 dma_src += xfer_len;
460 to += xfer_len;
461 }
462
463 return ret;
464}
465
466static int ti_qspi_dma_xfer_sg(struct ti_qspi *qspi, struct sg_table rx_sg,
467 loff_t from)
468{
469 struct scatterlist *sg;
470 dma_addr_t dma_src = qspi->mmap_phys_base + from;
471 dma_addr_t dma_dst;
472 int i, len, ret;
473
474 for_each_sg(rx_sg.sgl, sg, rx_sg.nents, i) {
475 dma_dst = sg_dma_address(sg);
476 len = sg_dma_len(sg);
477 ret = ti_qspi_dma_xfer(qspi, dma_dst, dma_src, len);
478 if (ret)
479 return ret;
480 dma_src += len;
481 }
482
483 return 0;
484}
485
486static void ti_qspi_enable_memory_map(struct spi_device *spi)
487{
488 struct ti_qspi *qspi = spi_master_get_devdata(spi->master);
489
490 ti_qspi_write(qspi, MM_SWITCH, QSPI_SPI_SWITCH_REG);
491 if (qspi->ctrl_base) {
492 regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg,
493 MEM_CS_EN(spi->chip_select),
494 MEM_CS_MASK);
495 }
496 qspi->mmap_enabled = true;
497}
498
499static void ti_qspi_disable_memory_map(struct spi_device *spi)
500{
501 struct ti_qspi *qspi = spi_master_get_devdata(spi->master);
502
503 ti_qspi_write(qspi, 0, QSPI_SPI_SWITCH_REG);
504 if (qspi->ctrl_base)
505 regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg,
506 0, MEM_CS_MASK);
507 qspi->mmap_enabled = false;
508}
509
510static void ti_qspi_setup_mmap_read(struct spi_device *spi,
511 struct spi_flash_read_message *msg)
512{
513 struct ti_qspi *qspi = spi_master_get_devdata(spi->master);
514 u32 memval = msg->read_opcode;
515
516 switch (msg->data_nbits) {
517 case SPI_NBITS_QUAD:
518 memval |= QSPI_SETUP_RD_QUAD;
519 break;
520 case SPI_NBITS_DUAL:
521 memval |= QSPI_SETUP_RD_DUAL;
522 break;
523 default:
524 memval |= QSPI_SETUP_RD_NORMAL;
525 break;
526 }
527 memval |= ((msg->addr_width - 1) << QSPI_SETUP_ADDR_SHIFT |
528 msg->dummy_bytes << QSPI_SETUP_DUMMY_SHIFT);
529 ti_qspi_write(qspi, memval,
530 QSPI_SPI_SETUP_REG(spi->chip_select));
531}
532
533static bool ti_qspi_spi_flash_can_dma(struct spi_device *spi,
534 struct spi_flash_read_message *msg)
535{
536 return virt_addr_valid(msg->buf);
537}
538
539static int ti_qspi_spi_flash_read(struct spi_device *spi,
540 struct spi_flash_read_message *msg)
541{
542 struct ti_qspi *qspi = spi_master_get_devdata(spi->master);
543 int ret = 0;
544
545 mutex_lock(&qspi->list_lock);
546
547 if (!qspi->mmap_enabled)
548 ti_qspi_enable_memory_map(spi);
549 ti_qspi_setup_mmap_read(spi, msg);
550
551 if (qspi->rx_chan) {
552 if (msg->cur_msg_mapped)
553 ret = ti_qspi_dma_xfer_sg(qspi, msg->rx_sg, msg->from);
554 else
555 ret = ti_qspi_dma_bounce_buffer(qspi, msg);
556 if (ret)
557 goto err_unlock;
558 } else {
559 memcpy_fromio(msg->buf, qspi->mmap_base + msg->from, msg->len);
560 }
561 msg->retlen = msg->len;
562
563err_unlock:
564 mutex_unlock(&qspi->list_lock);
565
566 return ret;
567}
568
569static int ti_qspi_start_transfer_one(struct spi_master *master,
570 struct spi_message *m)
571{
572 struct ti_qspi *qspi = spi_master_get_devdata(master);
573 struct spi_device *spi = m->spi;
574 struct spi_transfer *t;
575 int status = 0, ret;
576 unsigned int frame_len_words, transfer_len_words;
577 int wlen;
578
579 /* setup device control reg */
580 qspi->dc = 0;
581
582 if (spi->mode & SPI_CPHA)
583 qspi->dc |= QSPI_CKPHA(spi->chip_select);
584 if (spi->mode & SPI_CPOL)
585 qspi->dc |= QSPI_CKPOL(spi->chip_select);
586 if (spi->mode & SPI_CS_HIGH)
587 qspi->dc |= QSPI_CSPOL(spi->chip_select);
588
589 frame_len_words = 0;
590 list_for_each_entry(t, &m->transfers, transfer_list)
591 frame_len_words += t->len / (t->bits_per_word >> 3);
592 frame_len_words = min_t(unsigned int, frame_len_words, QSPI_FRAME);
593
594 /* setup command reg */
595 qspi->cmd = 0;
596 qspi->cmd |= QSPI_EN_CS(spi->chip_select);
597 qspi->cmd |= QSPI_FLEN(frame_len_words);
598
599 ti_qspi_write(qspi, qspi->dc, QSPI_SPI_DC_REG);
600
601 mutex_lock(&qspi->list_lock);
602
603 if (qspi->mmap_enabled)
604 ti_qspi_disable_memory_map(spi);
605
606 list_for_each_entry(t, &m->transfers, transfer_list) {
607 qspi->cmd = ((qspi->cmd & ~QSPI_WLEN_MASK) |
608 QSPI_WLEN(t->bits_per_word));
609
610 wlen = t->bits_per_word >> 3;
611 transfer_len_words = min(t->len / wlen, frame_len_words);
612
613 ret = qspi_transfer_msg(qspi, t, transfer_len_words * wlen);
614 if (ret) {
615 dev_dbg(qspi->dev, "transfer message failed\n");
616 mutex_unlock(&qspi->list_lock);
617 return -EINVAL;
618 }
619
620 m->actual_length += transfer_len_words * wlen;
621 frame_len_words -= transfer_len_words;
622 if (frame_len_words == 0)
623 break;
624 }
625
626 mutex_unlock(&qspi->list_lock);
627
628 ti_qspi_write(qspi, qspi->cmd | QSPI_INVAL, QSPI_SPI_CMD_REG);
629 m->status = status;
630 spi_finalize_current_message(master);
631
632 return status;
633}
634
635static int ti_qspi_runtime_resume(struct device *dev)
636{
637 struct ti_qspi *qspi;
638
639 qspi = dev_get_drvdata(dev);
640 ti_qspi_restore_ctx(qspi);
641
642 return 0;
643}
644
645static const struct of_device_id ti_qspi_match[] = {
646 {.compatible = "ti,dra7xxx-qspi" },
647 {.compatible = "ti,am4372-qspi" },
648 {},
649};
650MODULE_DEVICE_TABLE(of, ti_qspi_match);
651
652static int ti_qspi_probe(struct platform_device *pdev)
653{
654 struct ti_qspi *qspi;
655 struct spi_master *master;
656 struct resource *r, *res_mmap;
657 struct device_node *np = pdev->dev.of_node;
658 u32 max_freq;
659 int ret = 0, num_cs, irq;
660 dma_cap_mask_t mask;
661
662 master = spi_alloc_master(&pdev->dev, sizeof(*qspi));
663 if (!master)
664 return -ENOMEM;
665
666 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD;
667
668 master->flags = SPI_MASTER_HALF_DUPLEX;
669 master->setup = ti_qspi_setup;
670 master->auto_runtime_pm = true;
671 master->transfer_one_message = ti_qspi_start_transfer_one;
672 master->dev.of_node = pdev->dev.of_node;
673 master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) |
674 SPI_BPW_MASK(8);
675 master->spi_flash_read = ti_qspi_spi_flash_read;
676
677 if (!of_property_read_u32(np, "num-cs", &num_cs))
678 master->num_chipselect = num_cs;
679
680 qspi = spi_master_get_devdata(master);
681 qspi->master = master;
682 qspi->dev = &pdev->dev;
683 platform_set_drvdata(pdev, qspi);
684
685 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_base");
686 if (r == NULL) {
687 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
688 if (r == NULL) {
689 dev_err(&pdev->dev, "missing platform data\n");
690 ret = -ENODEV;
691 goto free_master;
692 }
693 }
694
695 res_mmap = platform_get_resource_byname(pdev,
696 IORESOURCE_MEM, "qspi_mmap");
697 if (res_mmap == NULL) {
698 res_mmap = platform_get_resource(pdev, IORESOURCE_MEM, 1);
699 if (res_mmap == NULL) {
700 dev_err(&pdev->dev,
701 "memory mapped resource not required\n");
702 }
703 }
704
705 irq = platform_get_irq(pdev, 0);
706 if (irq < 0) {
707 dev_err(&pdev->dev, "no irq resource?\n");
708 ret = irq;
709 goto free_master;
710 }
711
712 mutex_init(&qspi->list_lock);
713
714 qspi->base = devm_ioremap_resource(&pdev->dev, r);
715 if (IS_ERR(qspi->base)) {
716 ret = PTR_ERR(qspi->base);
717 goto free_master;
718 }
719
720
721 if (of_property_read_bool(np, "syscon-chipselects")) {
722 qspi->ctrl_base =
723 syscon_regmap_lookup_by_phandle(np,
724 "syscon-chipselects");
725 if (IS_ERR(qspi->ctrl_base)) {
726 ret = PTR_ERR(qspi->ctrl_base);
727 goto free_master;
728 }
729 ret = of_property_read_u32_index(np,
730 "syscon-chipselects",
731 1, &qspi->ctrl_reg);
732 if (ret) {
733 dev_err(&pdev->dev,
734 "couldn't get ctrl_mod reg index\n");
735 goto free_master;
736 }
737 }
738
739 qspi->fclk = devm_clk_get(&pdev->dev, "fck");
740 if (IS_ERR(qspi->fclk)) {
741 ret = PTR_ERR(qspi->fclk);
742 dev_err(&pdev->dev, "could not get clk: %d\n", ret);
743 }
744
745 pm_runtime_use_autosuspend(&pdev->dev);
746 pm_runtime_set_autosuspend_delay(&pdev->dev, QSPI_AUTOSUSPEND_TIMEOUT);
747 pm_runtime_enable(&pdev->dev);
748
749 if (!of_property_read_u32(np, "spi-max-frequency", &max_freq))
750 qspi->spi_max_frequency = max_freq;
751
752 dma_cap_zero(mask);
753 dma_cap_set(DMA_MEMCPY, mask);
754
755 qspi->rx_chan = dma_request_chan_by_mask(&mask);
756 if (IS_ERR(qspi->rx_chan)) {
757 dev_err(qspi->dev,
758 "No Rx DMA available, trying mmap mode\n");
759 qspi->rx_chan = NULL;
760 ret = 0;
761 goto no_dma;
762 }
763 qspi->rx_bb_addr = dma_alloc_coherent(qspi->dev,
764 QSPI_DMA_BUFFER_SIZE,
765 &qspi->rx_bb_dma_addr,
766 GFP_KERNEL | GFP_DMA);
767 if (!qspi->rx_bb_addr) {
768 dev_err(qspi->dev,
769 "dma_alloc_coherent failed, using PIO mode\n");
770 dma_release_channel(qspi->rx_chan);
771 goto no_dma;
772 }
773 master->spi_flash_can_dma = ti_qspi_spi_flash_can_dma;
774 master->dma_rx = qspi->rx_chan;
775 init_completion(&qspi->transfer_complete);
776 if (res_mmap)
777 qspi->mmap_phys_base = (dma_addr_t)res_mmap->start;
778
779no_dma:
780 if (!qspi->rx_chan && res_mmap) {
781 qspi->mmap_base = devm_ioremap_resource(&pdev->dev, res_mmap);
782 if (IS_ERR(qspi->mmap_base)) {
783 dev_info(&pdev->dev,
784 "mmap failed with error %ld using PIO mode\n",
785 PTR_ERR(qspi->mmap_base));
786 qspi->mmap_base = NULL;
787 master->spi_flash_read = NULL;
788 }
789 }
790 qspi->mmap_enabled = false;
791
792 ret = devm_spi_register_master(&pdev->dev, master);
793 if (!ret)
794 return 0;
795
796 pm_runtime_disable(&pdev->dev);
797free_master:
798 spi_master_put(master);
799 return ret;
800}
801
802static int ti_qspi_remove(struct platform_device *pdev)
803{
804 struct ti_qspi *qspi = platform_get_drvdata(pdev);
805 int rc;
806
807 rc = spi_master_suspend(qspi->master);
808 if (rc)
809 return rc;
810
811 pm_runtime_put_sync(&pdev->dev);
812 pm_runtime_disable(&pdev->dev);
813
814 if (qspi->rx_bb_addr)
815 dma_free_coherent(qspi->dev, QSPI_DMA_BUFFER_SIZE,
816 qspi->rx_bb_addr,
817 qspi->rx_bb_dma_addr);
818 if (qspi->rx_chan)
819 dma_release_channel(qspi->rx_chan);
820
821 return 0;
822}
823
824static const struct dev_pm_ops ti_qspi_pm_ops = {
825 .runtime_resume = ti_qspi_runtime_resume,
826};
827
828static struct platform_driver ti_qspi_driver = {
829 .probe = ti_qspi_probe,
830 .remove = ti_qspi_remove,
831 .driver = {
832 .name = "ti-qspi",
833 .pm = &ti_qspi_pm_ops,
834 .of_match_table = ti_qspi_match,
835 }
836};
837
838module_platform_driver(ti_qspi_driver);
839
840MODULE_AUTHOR("Sourav Poddar <sourav.poddar@ti.com>");
841MODULE_LICENSE("GPL v2");
842MODULE_DESCRIPTION("TI QSPI controller driver");
843MODULE_ALIAS("platform:ti-qspi");