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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Simple Reset Controller Driver
4 *
5 * Copyright (C) 2017 Pengutronix, Philipp Zabel <kernel@pengutronix.de>
6 *
7 * Based on Allwinner SoCs Reset Controller driver
8 *
9 * Copyright 2013 Maxime Ripard
10 *
11 * Maxime Ripard <maxime.ripard@free-electrons.com>
12 */
13
14#include <linux/delay.h>
15#include <linux/device.h>
16#include <linux/err.h>
17#include <linux/io.h>
18#include <linux/of.h>
19#include <linux/of_device.h>
20#include <linux/platform_device.h>
21#include <linux/reset-controller.h>
22#include <linux/reset/reset-simple.h>
23#include <linux/spinlock.h>
24
25static inline struct reset_simple_data *
26to_reset_simple_data(struct reset_controller_dev *rcdev)
27{
28 return container_of(rcdev, struct reset_simple_data, rcdev);
29}
30
31static int reset_simple_update(struct reset_controller_dev *rcdev,
32 unsigned long id, bool assert)
33{
34 struct reset_simple_data *data = to_reset_simple_data(rcdev);
35 int reg_width = sizeof(u32);
36 int bank = id / (reg_width * BITS_PER_BYTE);
37 int offset = id % (reg_width * BITS_PER_BYTE);
38 unsigned long flags;
39 u32 reg;
40
41 spin_lock_irqsave(&data->lock, flags);
42
43 reg = readl(data->membase + (bank * reg_width));
44 if (assert ^ data->active_low)
45 reg |= BIT(offset);
46 else
47 reg &= ~BIT(offset);
48 writel(reg, data->membase + (bank * reg_width));
49
50 spin_unlock_irqrestore(&data->lock, flags);
51
52 return 0;
53}
54
55static int reset_simple_assert(struct reset_controller_dev *rcdev,
56 unsigned long id)
57{
58 return reset_simple_update(rcdev, id, true);
59}
60
61static int reset_simple_deassert(struct reset_controller_dev *rcdev,
62 unsigned long id)
63{
64 return reset_simple_update(rcdev, id, false);
65}
66
67static int reset_simple_reset(struct reset_controller_dev *rcdev,
68 unsigned long id)
69{
70 struct reset_simple_data *data = to_reset_simple_data(rcdev);
71 int ret;
72
73 if (!data->reset_us)
74 return -ENOTSUPP;
75
76 ret = reset_simple_assert(rcdev, id);
77 if (ret)
78 return ret;
79
80 usleep_range(data->reset_us, data->reset_us * 2);
81
82 return reset_simple_deassert(rcdev, id);
83}
84
85static int reset_simple_status(struct reset_controller_dev *rcdev,
86 unsigned long id)
87{
88 struct reset_simple_data *data = to_reset_simple_data(rcdev);
89 int reg_width = sizeof(u32);
90 int bank = id / (reg_width * BITS_PER_BYTE);
91 int offset = id % (reg_width * BITS_PER_BYTE);
92 u32 reg;
93
94 reg = readl(data->membase + (bank * reg_width));
95
96 return !(reg & BIT(offset)) ^ !data->status_active_low;
97}
98
99const struct reset_control_ops reset_simple_ops = {
100 .assert = reset_simple_assert,
101 .deassert = reset_simple_deassert,
102 .reset = reset_simple_reset,
103 .status = reset_simple_status,
104};
105EXPORT_SYMBOL_GPL(reset_simple_ops);
106
107/**
108 * struct reset_simple_devdata - simple reset controller properties
109 * @reg_offset: offset between base address and first reset register.
110 * @nr_resets: number of resets. If not set, default to resource size in bits.
111 * @active_low: if true, bits are cleared to assert the reset. Otherwise, bits
112 * are set to assert the reset.
113 * @status_active_low: if true, bits read back as cleared while the reset is
114 * asserted. Otherwise, bits read back as set while the
115 * reset is asserted.
116 */
117struct reset_simple_devdata {
118 u32 reg_offset;
119 u32 nr_resets;
120 bool active_low;
121 bool status_active_low;
122};
123
124#define SOCFPGA_NR_BANKS 8
125
126static const struct reset_simple_devdata reset_simple_socfpga = {
127 .reg_offset = 0x20,
128 .nr_resets = SOCFPGA_NR_BANKS * 32,
129 .status_active_low = true,
130};
131
132static const struct reset_simple_devdata reset_simple_active_low = {
133 .active_low = true,
134 .status_active_low = true,
135};
136
137static const struct of_device_id reset_simple_dt_ids[] = {
138 { .compatible = "altr,stratix10-rst-mgr",
139 .data = &reset_simple_socfpga },
140 { .compatible = "st,stm32-rcc", },
141 { .compatible = "allwinner,sun6i-a31-clock-reset",
142 .data = &reset_simple_active_low },
143 { .compatible = "zte,zx296718-reset",
144 .data = &reset_simple_active_low },
145 { .compatible = "aspeed,ast2400-lpc-reset" },
146 { .compatible = "aspeed,ast2500-lpc-reset" },
147 { .compatible = "bitmain,bm1880-reset",
148 .data = &reset_simple_active_low },
149 { .compatible = "snps,dw-high-reset" },
150 { .compatible = "snps,dw-low-reset",
151 .data = &reset_simple_active_low },
152 { /* sentinel */ },
153};
154
155static int reset_simple_probe(struct platform_device *pdev)
156{
157 struct device *dev = &pdev->dev;
158 const struct reset_simple_devdata *devdata;
159 struct reset_simple_data *data;
160 void __iomem *membase;
161 struct resource *res;
162 u32 reg_offset = 0;
163
164 devdata = of_device_get_match_data(dev);
165
166 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
167 if (!data)
168 return -ENOMEM;
169
170 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
171 membase = devm_ioremap_resource(dev, res);
172 if (IS_ERR(membase))
173 return PTR_ERR(membase);
174
175 spin_lock_init(&data->lock);
176 data->membase = membase;
177 data->rcdev.owner = THIS_MODULE;
178 data->rcdev.nr_resets = resource_size(res) * BITS_PER_BYTE;
179 data->rcdev.ops = &reset_simple_ops;
180 data->rcdev.of_node = dev->of_node;
181
182 if (devdata) {
183 reg_offset = devdata->reg_offset;
184 if (devdata->nr_resets)
185 data->rcdev.nr_resets = devdata->nr_resets;
186 data->active_low = devdata->active_low;
187 data->status_active_low = devdata->status_active_low;
188 }
189
190 data->membase += reg_offset;
191
192 return devm_reset_controller_register(dev, &data->rcdev);
193}
194
195static struct platform_driver reset_simple_driver = {
196 .probe = reset_simple_probe,
197 .driver = {
198 .name = "simple-reset",
199 .of_match_table = reset_simple_dt_ids,
200 },
201};
202builtin_platform_driver(reset_simple_driver);
1/*
2 * Simple Reset Controller Driver
3 *
4 * Copyright (C) 2017 Pengutronix, Philipp Zabel <kernel@pengutronix.de>
5 *
6 * Based on Allwinner SoCs Reset Controller driver
7 *
8 * Copyright 2013 Maxime Ripard
9 *
10 * Maxime Ripard <maxime.ripard@free-electrons.com>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 */
17
18#include <linux/device.h>
19#include <linux/err.h>
20#include <linux/io.h>
21#include <linux/of.h>
22#include <linux/of_device.h>
23#include <linux/platform_device.h>
24#include <linux/reset-controller.h>
25#include <linux/spinlock.h>
26
27#include "reset-simple.h"
28
29static inline struct reset_simple_data *
30to_reset_simple_data(struct reset_controller_dev *rcdev)
31{
32 return container_of(rcdev, struct reset_simple_data, rcdev);
33}
34
35static int reset_simple_update(struct reset_controller_dev *rcdev,
36 unsigned long id, bool assert)
37{
38 struct reset_simple_data *data = to_reset_simple_data(rcdev);
39 int reg_width = sizeof(u32);
40 int bank = id / (reg_width * BITS_PER_BYTE);
41 int offset = id % (reg_width * BITS_PER_BYTE);
42 unsigned long flags;
43 u32 reg;
44
45 spin_lock_irqsave(&data->lock, flags);
46
47 reg = readl(data->membase + (bank * reg_width));
48 if (assert ^ data->active_low)
49 reg |= BIT(offset);
50 else
51 reg &= ~BIT(offset);
52 writel(reg, data->membase + (bank * reg_width));
53
54 spin_unlock_irqrestore(&data->lock, flags);
55
56 return 0;
57}
58
59static int reset_simple_assert(struct reset_controller_dev *rcdev,
60 unsigned long id)
61{
62 return reset_simple_update(rcdev, id, true);
63}
64
65static int reset_simple_deassert(struct reset_controller_dev *rcdev,
66 unsigned long id)
67{
68 return reset_simple_update(rcdev, id, false);
69}
70
71static int reset_simple_status(struct reset_controller_dev *rcdev,
72 unsigned long id)
73{
74 struct reset_simple_data *data = to_reset_simple_data(rcdev);
75 int reg_width = sizeof(u32);
76 int bank = id / (reg_width * BITS_PER_BYTE);
77 int offset = id % (reg_width * BITS_PER_BYTE);
78 u32 reg;
79
80 reg = readl(data->membase + (bank * reg_width));
81
82 return !(reg & BIT(offset)) ^ !data->status_active_low;
83}
84
85const struct reset_control_ops reset_simple_ops = {
86 .assert = reset_simple_assert,
87 .deassert = reset_simple_deassert,
88 .status = reset_simple_status,
89};
90
91/**
92 * struct reset_simple_devdata - simple reset controller properties
93 * @reg_offset: offset between base address and first reset register.
94 * @nr_resets: number of resets. If not set, default to resource size in bits.
95 * @active_low: if true, bits are cleared to assert the reset. Otherwise, bits
96 * are set to assert the reset.
97 * @status_active_low: if true, bits read back as cleared while the reset is
98 * asserted. Otherwise, bits read back as set while the
99 * reset is asserted.
100 */
101struct reset_simple_devdata {
102 u32 reg_offset;
103 u32 nr_resets;
104 bool active_low;
105 bool status_active_low;
106};
107
108#define SOCFPGA_NR_BANKS 8
109
110static const struct reset_simple_devdata reset_simple_socfpga = {
111 .reg_offset = 0x10,
112 .nr_resets = SOCFPGA_NR_BANKS * 32,
113 .status_active_low = true,
114};
115
116static const struct reset_simple_devdata reset_simple_active_low = {
117 .active_low = true,
118 .status_active_low = true,
119};
120
121static const struct of_device_id reset_simple_dt_ids[] = {
122 { .compatible = "altr,rst-mgr", .data = &reset_simple_socfpga },
123 { .compatible = "st,stm32-rcc", },
124 { .compatible = "allwinner,sun6i-a31-clock-reset",
125 .data = &reset_simple_active_low },
126 { .compatible = "zte,zx296718-reset",
127 .data = &reset_simple_active_low },
128 { .compatible = "aspeed,ast2400-lpc-reset" },
129 { .compatible = "aspeed,ast2500-lpc-reset" },
130 { /* sentinel */ },
131};
132
133static int reset_simple_probe(struct platform_device *pdev)
134{
135 struct device *dev = &pdev->dev;
136 const struct reset_simple_devdata *devdata;
137 struct reset_simple_data *data;
138 void __iomem *membase;
139 struct resource *res;
140 u32 reg_offset = 0;
141
142 devdata = of_device_get_match_data(dev);
143
144 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
145 if (!data)
146 return -ENOMEM;
147
148 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
149 membase = devm_ioremap_resource(dev, res);
150 if (IS_ERR(membase))
151 return PTR_ERR(membase);
152
153 spin_lock_init(&data->lock);
154 data->membase = membase;
155 data->rcdev.owner = THIS_MODULE;
156 data->rcdev.nr_resets = resource_size(res) * BITS_PER_BYTE;
157 data->rcdev.ops = &reset_simple_ops;
158 data->rcdev.of_node = dev->of_node;
159
160 if (devdata) {
161 reg_offset = devdata->reg_offset;
162 if (devdata->nr_resets)
163 data->rcdev.nr_resets = devdata->nr_resets;
164 data->active_low = devdata->active_low;
165 data->status_active_low = devdata->status_active_low;
166 }
167
168 if (of_device_is_compatible(dev->of_node, "altr,rst-mgr") &&
169 of_property_read_u32(dev->of_node, "altr,modrst-offset",
170 ®_offset)) {
171 dev_warn(dev,
172 "missing altr,modrst-offset property, assuming 0x%x!\n",
173 reg_offset);
174 }
175
176 data->membase += reg_offset;
177
178 return devm_reset_controller_register(dev, &data->rcdev);
179}
180
181static struct platform_driver reset_simple_driver = {
182 .probe = reset_simple_probe,
183 .driver = {
184 .name = "simple-reset",
185 .of_match_table = reset_simple_dt_ids,
186 },
187};
188builtin_platform_driver(reset_simple_driver);