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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * GPIO driver for Fintek Super-I/O F71869, F71869A, F71882, F71889 and F81866
4 *
5 * Copyright (C) 2010-2013 LaCie
6 *
7 * Author: Simon Guinot <simon.guinot@sequanux.org>
8 */
9
10#include <linux/module.h>
11#include <linux/init.h>
12#include <linux/platform_device.h>
13#include <linux/io.h>
14#include <linux/gpio/driver.h>
15#include <linux/bitops.h>
16
17#define DRVNAME "gpio-f7188x"
18
19/*
20 * Super-I/O registers
21 */
22#define SIO_LDSEL 0x07 /* Logical device select */
23#define SIO_DEVID 0x20 /* Device ID (2 bytes) */
24#define SIO_DEVREV 0x22 /* Device revision */
25#define SIO_MANID 0x23 /* Fintek ID (2 bytes) */
26
27#define SIO_LD_GPIO 0x06 /* GPIO logical device */
28#define SIO_UNLOCK_KEY 0x87 /* Key to enable Super-I/O */
29#define SIO_LOCK_KEY 0xAA /* Key to disable Super-I/O */
30
31#define SIO_FINTEK_ID 0x1934 /* Manufacturer ID */
32#define SIO_F71869_ID 0x0814 /* F71869 chipset ID */
33#define SIO_F71869A_ID 0x1007 /* F71869A chipset ID */
34#define SIO_F71882_ID 0x0541 /* F71882 chipset ID */
35#define SIO_F71889_ID 0x0909 /* F71889 chipset ID */
36#define SIO_F71889A_ID 0x1005 /* F71889A chipset ID */
37#define SIO_F81866_ID 0x1010 /* F81866 chipset ID */
38#define SIO_F81804_ID 0x1502 /* F81804 chipset ID, same for f81966 */
39#define SIO_F81865_ID 0x0704 /* F81865 chipset ID */
40
41
42enum chips {
43 f71869,
44 f71869a,
45 f71882fg,
46 f71889a,
47 f71889f,
48 f81866,
49 f81804,
50 f81865,
51};
52
53static const char * const f7188x_names[] = {
54 "f71869",
55 "f71869a",
56 "f71882fg",
57 "f71889a",
58 "f71889f",
59 "f81866",
60 "f81804",
61 "f81865",
62};
63
64struct f7188x_sio {
65 int addr;
66 enum chips type;
67};
68
69struct f7188x_gpio_bank {
70 struct gpio_chip chip;
71 unsigned int regbase;
72 struct f7188x_gpio_data *data;
73};
74
75struct f7188x_gpio_data {
76 struct f7188x_sio *sio;
77 int nr_bank;
78 struct f7188x_gpio_bank *bank;
79};
80
81/*
82 * Super-I/O functions.
83 */
84
85static inline int superio_inb(int base, int reg)
86{
87 outb(reg, base);
88 return inb(base + 1);
89}
90
91static int superio_inw(int base, int reg)
92{
93 int val;
94
95 outb(reg++, base);
96 val = inb(base + 1) << 8;
97 outb(reg, base);
98 val |= inb(base + 1);
99
100 return val;
101}
102
103static inline void superio_outb(int base, int reg, int val)
104{
105 outb(reg, base);
106 outb(val, base + 1);
107}
108
109static inline int superio_enter(int base)
110{
111 /* Don't step on other drivers' I/O space by accident. */
112 if (!request_muxed_region(base, 2, DRVNAME)) {
113 pr_err(DRVNAME "I/O address 0x%04x already in use\n", base);
114 return -EBUSY;
115 }
116
117 /* According to the datasheet the key must be send twice. */
118 outb(SIO_UNLOCK_KEY, base);
119 outb(SIO_UNLOCK_KEY, base);
120
121 return 0;
122}
123
124static inline void superio_select(int base, int ld)
125{
126 outb(SIO_LDSEL, base);
127 outb(ld, base + 1);
128}
129
130static inline void superio_exit(int base)
131{
132 outb(SIO_LOCK_KEY, base);
133 release_region(base, 2);
134}
135
136/*
137 * GPIO chip.
138 */
139
140static int f7188x_gpio_get_direction(struct gpio_chip *chip, unsigned offset);
141static int f7188x_gpio_direction_in(struct gpio_chip *chip, unsigned offset);
142static int f7188x_gpio_get(struct gpio_chip *chip, unsigned offset);
143static int f7188x_gpio_direction_out(struct gpio_chip *chip,
144 unsigned offset, int value);
145static void f7188x_gpio_set(struct gpio_chip *chip, unsigned offset, int value);
146static int f7188x_gpio_set_config(struct gpio_chip *chip, unsigned offset,
147 unsigned long config);
148
149#define F7188X_GPIO_BANK(_base, _ngpio, _regbase) \
150 { \
151 .chip = { \
152 .label = DRVNAME, \
153 .owner = THIS_MODULE, \
154 .get_direction = f7188x_gpio_get_direction, \
155 .direction_input = f7188x_gpio_direction_in, \
156 .get = f7188x_gpio_get, \
157 .direction_output = f7188x_gpio_direction_out, \
158 .set = f7188x_gpio_set, \
159 .set_config = f7188x_gpio_set_config, \
160 .base = _base, \
161 .ngpio = _ngpio, \
162 .can_sleep = true, \
163 }, \
164 .regbase = _regbase, \
165 }
166
167#define gpio_dir(base) (base + 0)
168#define gpio_data_out(base) (base + 1)
169#define gpio_data_in(base) (base + 2)
170/* Output mode register (0:open drain 1:push-pull). */
171#define gpio_out_mode(base) (base + 3)
172
173static struct f7188x_gpio_bank f71869_gpio_bank[] = {
174 F7188X_GPIO_BANK(0, 6, 0xF0),
175 F7188X_GPIO_BANK(10, 8, 0xE0),
176 F7188X_GPIO_BANK(20, 8, 0xD0),
177 F7188X_GPIO_BANK(30, 8, 0xC0),
178 F7188X_GPIO_BANK(40, 8, 0xB0),
179 F7188X_GPIO_BANK(50, 5, 0xA0),
180 F7188X_GPIO_BANK(60, 6, 0x90),
181};
182
183static struct f7188x_gpio_bank f71869a_gpio_bank[] = {
184 F7188X_GPIO_BANK(0, 6, 0xF0),
185 F7188X_GPIO_BANK(10, 8, 0xE0),
186 F7188X_GPIO_BANK(20, 8, 0xD0),
187 F7188X_GPIO_BANK(30, 8, 0xC0),
188 F7188X_GPIO_BANK(40, 8, 0xB0),
189 F7188X_GPIO_BANK(50, 5, 0xA0),
190 F7188X_GPIO_BANK(60, 8, 0x90),
191 F7188X_GPIO_BANK(70, 8, 0x80),
192};
193
194static struct f7188x_gpio_bank f71882_gpio_bank[] = {
195 F7188X_GPIO_BANK(0, 8, 0xF0),
196 F7188X_GPIO_BANK(10, 8, 0xE0),
197 F7188X_GPIO_BANK(20, 8, 0xD0),
198 F7188X_GPIO_BANK(30, 4, 0xC0),
199 F7188X_GPIO_BANK(40, 4, 0xB0),
200};
201
202static struct f7188x_gpio_bank f71889a_gpio_bank[] = {
203 F7188X_GPIO_BANK(0, 7, 0xF0),
204 F7188X_GPIO_BANK(10, 7, 0xE0),
205 F7188X_GPIO_BANK(20, 8, 0xD0),
206 F7188X_GPIO_BANK(30, 8, 0xC0),
207 F7188X_GPIO_BANK(40, 8, 0xB0),
208 F7188X_GPIO_BANK(50, 5, 0xA0),
209 F7188X_GPIO_BANK(60, 8, 0x90),
210 F7188X_GPIO_BANK(70, 8, 0x80),
211};
212
213static struct f7188x_gpio_bank f71889_gpio_bank[] = {
214 F7188X_GPIO_BANK(0, 7, 0xF0),
215 F7188X_GPIO_BANK(10, 7, 0xE0),
216 F7188X_GPIO_BANK(20, 8, 0xD0),
217 F7188X_GPIO_BANK(30, 8, 0xC0),
218 F7188X_GPIO_BANK(40, 8, 0xB0),
219 F7188X_GPIO_BANK(50, 5, 0xA0),
220 F7188X_GPIO_BANK(60, 8, 0x90),
221 F7188X_GPIO_BANK(70, 8, 0x80),
222};
223
224static struct f7188x_gpio_bank f81866_gpio_bank[] = {
225 F7188X_GPIO_BANK(0, 8, 0xF0),
226 F7188X_GPIO_BANK(10, 8, 0xE0),
227 F7188X_GPIO_BANK(20, 8, 0xD0),
228 F7188X_GPIO_BANK(30, 8, 0xC0),
229 F7188X_GPIO_BANK(40, 8, 0xB0),
230 F7188X_GPIO_BANK(50, 8, 0xA0),
231 F7188X_GPIO_BANK(60, 8, 0x90),
232 F7188X_GPIO_BANK(70, 8, 0x80),
233 F7188X_GPIO_BANK(80, 8, 0x88),
234};
235
236
237static struct f7188x_gpio_bank f81804_gpio_bank[] = {
238 F7188X_GPIO_BANK(0, 8, 0xF0),
239 F7188X_GPIO_BANK(10, 8, 0xE0),
240 F7188X_GPIO_BANK(20, 8, 0xD0),
241 F7188X_GPIO_BANK(50, 8, 0xA0),
242 F7188X_GPIO_BANK(60, 8, 0x90),
243 F7188X_GPIO_BANK(70, 8, 0x80),
244 F7188X_GPIO_BANK(90, 8, 0x98),
245};
246
247static struct f7188x_gpio_bank f81865_gpio_bank[] = {
248 F7188X_GPIO_BANK(0, 8, 0xF0),
249 F7188X_GPIO_BANK(10, 8, 0xE0),
250 F7188X_GPIO_BANK(20, 8, 0xD0),
251 F7188X_GPIO_BANK(30, 8, 0xC0),
252 F7188X_GPIO_BANK(40, 8, 0xB0),
253 F7188X_GPIO_BANK(50, 8, 0xA0),
254 F7188X_GPIO_BANK(60, 5, 0x90),
255};
256
257static int f7188x_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
258{
259 int err;
260 struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
261 struct f7188x_sio *sio = bank->data->sio;
262 u8 dir;
263
264 err = superio_enter(sio->addr);
265 if (err)
266 return err;
267 superio_select(sio->addr, SIO_LD_GPIO);
268
269 dir = superio_inb(sio->addr, gpio_dir(bank->regbase));
270
271 superio_exit(sio->addr);
272
273 if (dir & 1 << offset)
274 return GPIO_LINE_DIRECTION_OUT;
275
276 return GPIO_LINE_DIRECTION_IN;
277}
278
279static int f7188x_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
280{
281 int err;
282 struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
283 struct f7188x_sio *sio = bank->data->sio;
284 u8 dir;
285
286 err = superio_enter(sio->addr);
287 if (err)
288 return err;
289 superio_select(sio->addr, SIO_LD_GPIO);
290
291 dir = superio_inb(sio->addr, gpio_dir(bank->regbase));
292 dir &= ~BIT(offset);
293 superio_outb(sio->addr, gpio_dir(bank->regbase), dir);
294
295 superio_exit(sio->addr);
296
297 return 0;
298}
299
300static int f7188x_gpio_get(struct gpio_chip *chip, unsigned offset)
301{
302 int err;
303 struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
304 struct f7188x_sio *sio = bank->data->sio;
305 u8 dir, data;
306
307 err = superio_enter(sio->addr);
308 if (err)
309 return err;
310 superio_select(sio->addr, SIO_LD_GPIO);
311
312 dir = superio_inb(sio->addr, gpio_dir(bank->regbase));
313 dir = !!(dir & BIT(offset));
314 if (dir)
315 data = superio_inb(sio->addr, gpio_data_out(bank->regbase));
316 else
317 data = superio_inb(sio->addr, gpio_data_in(bank->regbase));
318
319 superio_exit(sio->addr);
320
321 return !!(data & BIT(offset));
322}
323
324static int f7188x_gpio_direction_out(struct gpio_chip *chip,
325 unsigned offset, int value)
326{
327 int err;
328 struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
329 struct f7188x_sio *sio = bank->data->sio;
330 u8 dir, data_out;
331
332 err = superio_enter(sio->addr);
333 if (err)
334 return err;
335 superio_select(sio->addr, SIO_LD_GPIO);
336
337 data_out = superio_inb(sio->addr, gpio_data_out(bank->regbase));
338 if (value)
339 data_out |= BIT(offset);
340 else
341 data_out &= ~BIT(offset);
342 superio_outb(sio->addr, gpio_data_out(bank->regbase), data_out);
343
344 dir = superio_inb(sio->addr, gpio_dir(bank->regbase));
345 dir |= BIT(offset);
346 superio_outb(sio->addr, gpio_dir(bank->regbase), dir);
347
348 superio_exit(sio->addr);
349
350 return 0;
351}
352
353static void f7188x_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
354{
355 int err;
356 struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
357 struct f7188x_sio *sio = bank->data->sio;
358 u8 data_out;
359
360 err = superio_enter(sio->addr);
361 if (err)
362 return;
363 superio_select(sio->addr, SIO_LD_GPIO);
364
365 data_out = superio_inb(sio->addr, gpio_data_out(bank->regbase));
366 if (value)
367 data_out |= BIT(offset);
368 else
369 data_out &= ~BIT(offset);
370 superio_outb(sio->addr, gpio_data_out(bank->regbase), data_out);
371
372 superio_exit(sio->addr);
373}
374
375static int f7188x_gpio_set_config(struct gpio_chip *chip, unsigned offset,
376 unsigned long config)
377{
378 int err;
379 enum pin_config_param param = pinconf_to_config_param(config);
380 struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
381 struct f7188x_sio *sio = bank->data->sio;
382 u8 data;
383
384 if (param != PIN_CONFIG_DRIVE_OPEN_DRAIN &&
385 param != PIN_CONFIG_DRIVE_PUSH_PULL)
386 return -ENOTSUPP;
387
388 err = superio_enter(sio->addr);
389 if (err)
390 return err;
391 superio_select(sio->addr, SIO_LD_GPIO);
392
393 data = superio_inb(sio->addr, gpio_out_mode(bank->regbase));
394 if (param == PIN_CONFIG_DRIVE_OPEN_DRAIN)
395 data &= ~BIT(offset);
396 else
397 data |= BIT(offset);
398 superio_outb(sio->addr, gpio_out_mode(bank->regbase), data);
399
400 superio_exit(sio->addr);
401 return 0;
402}
403
404/*
405 * Platform device and driver.
406 */
407
408static int f7188x_gpio_probe(struct platform_device *pdev)
409{
410 int err;
411 int i;
412 struct f7188x_sio *sio = dev_get_platdata(&pdev->dev);
413 struct f7188x_gpio_data *data;
414
415 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
416 if (!data)
417 return -ENOMEM;
418
419 switch (sio->type) {
420 case f71869:
421 data->nr_bank = ARRAY_SIZE(f71869_gpio_bank);
422 data->bank = f71869_gpio_bank;
423 break;
424 case f71869a:
425 data->nr_bank = ARRAY_SIZE(f71869a_gpio_bank);
426 data->bank = f71869a_gpio_bank;
427 break;
428 case f71882fg:
429 data->nr_bank = ARRAY_SIZE(f71882_gpio_bank);
430 data->bank = f71882_gpio_bank;
431 break;
432 case f71889a:
433 data->nr_bank = ARRAY_SIZE(f71889a_gpio_bank);
434 data->bank = f71889a_gpio_bank;
435 break;
436 case f71889f:
437 data->nr_bank = ARRAY_SIZE(f71889_gpio_bank);
438 data->bank = f71889_gpio_bank;
439 break;
440 case f81866:
441 data->nr_bank = ARRAY_SIZE(f81866_gpio_bank);
442 data->bank = f81866_gpio_bank;
443 break;
444 case f81804:
445 data->nr_bank = ARRAY_SIZE(f81804_gpio_bank);
446 data->bank = f81804_gpio_bank;
447 break;
448 case f81865:
449 data->nr_bank = ARRAY_SIZE(f81865_gpio_bank);
450 data->bank = f81865_gpio_bank;
451 break;
452 default:
453 return -ENODEV;
454 }
455 data->sio = sio;
456
457 platform_set_drvdata(pdev, data);
458
459 /* For each GPIO bank, register a GPIO chip. */
460 for (i = 0; i < data->nr_bank; i++) {
461 struct f7188x_gpio_bank *bank = &data->bank[i];
462
463 bank->chip.parent = &pdev->dev;
464 bank->data = data;
465
466 err = devm_gpiochip_add_data(&pdev->dev, &bank->chip, bank);
467 if (err) {
468 dev_err(&pdev->dev,
469 "Failed to register gpiochip %d: %d\n",
470 i, err);
471 return err;
472 }
473 }
474
475 return 0;
476}
477
478static int __init f7188x_find(int addr, struct f7188x_sio *sio)
479{
480 int err;
481 u16 devid;
482
483 err = superio_enter(addr);
484 if (err)
485 return err;
486
487 err = -ENODEV;
488 devid = superio_inw(addr, SIO_MANID);
489 if (devid != SIO_FINTEK_ID) {
490 pr_debug(DRVNAME ": Not a Fintek device at 0x%08x\n", addr);
491 goto err;
492 }
493
494 devid = superio_inw(addr, SIO_DEVID);
495 switch (devid) {
496 case SIO_F71869_ID:
497 sio->type = f71869;
498 break;
499 case SIO_F71869A_ID:
500 sio->type = f71869a;
501 break;
502 case SIO_F71882_ID:
503 sio->type = f71882fg;
504 break;
505 case SIO_F71889A_ID:
506 sio->type = f71889a;
507 break;
508 case SIO_F71889_ID:
509 sio->type = f71889f;
510 break;
511 case SIO_F81866_ID:
512 sio->type = f81866;
513 break;
514 case SIO_F81804_ID:
515 sio->type = f81804;
516 break;
517 case SIO_F81865_ID:
518 sio->type = f81865;
519 break;
520 default:
521 pr_info(DRVNAME ": Unsupported Fintek device 0x%04x\n", devid);
522 goto err;
523 }
524 sio->addr = addr;
525 err = 0;
526
527 pr_info(DRVNAME ": Found %s at %#x, revision %d\n",
528 f7188x_names[sio->type],
529 (unsigned int) addr,
530 (int) superio_inb(addr, SIO_DEVREV));
531
532err:
533 superio_exit(addr);
534 return err;
535}
536
537static struct platform_device *f7188x_gpio_pdev;
538
539static int __init
540f7188x_gpio_device_add(const struct f7188x_sio *sio)
541{
542 int err;
543
544 f7188x_gpio_pdev = platform_device_alloc(DRVNAME, -1);
545 if (!f7188x_gpio_pdev)
546 return -ENOMEM;
547
548 err = platform_device_add_data(f7188x_gpio_pdev,
549 sio, sizeof(*sio));
550 if (err) {
551 pr_err(DRVNAME "Platform data allocation failed\n");
552 goto err;
553 }
554
555 err = platform_device_add(f7188x_gpio_pdev);
556 if (err) {
557 pr_err(DRVNAME "Device addition failed\n");
558 goto err;
559 }
560
561 return 0;
562
563err:
564 platform_device_put(f7188x_gpio_pdev);
565
566 return err;
567}
568
569/*
570 * Try to match a supported Fintek device by reading the (hard-wired)
571 * configuration I/O ports. If available, then register both the platform
572 * device and driver to support the GPIOs.
573 */
574
575static struct platform_driver f7188x_gpio_driver = {
576 .driver = {
577 .name = DRVNAME,
578 },
579 .probe = f7188x_gpio_probe,
580};
581
582static int __init f7188x_gpio_init(void)
583{
584 int err;
585 struct f7188x_sio sio;
586
587 if (f7188x_find(0x2e, &sio) &&
588 f7188x_find(0x4e, &sio))
589 return -ENODEV;
590
591 err = platform_driver_register(&f7188x_gpio_driver);
592 if (!err) {
593 err = f7188x_gpio_device_add(&sio);
594 if (err)
595 platform_driver_unregister(&f7188x_gpio_driver);
596 }
597
598 return err;
599}
600subsys_initcall(f7188x_gpio_init);
601
602static void __exit f7188x_gpio_exit(void)
603{
604 platform_device_unregister(f7188x_gpio_pdev);
605 platform_driver_unregister(&f7188x_gpio_driver);
606}
607module_exit(f7188x_gpio_exit);
608
609MODULE_DESCRIPTION("GPIO driver for Super-I/O chips F71869, F71869A, F71882FG, F71889A, F71889F and F81866");
610MODULE_AUTHOR("Simon Guinot <simon.guinot@sequanux.org>");
611MODULE_LICENSE("GPL");
1/*
2 * GPIO driver for Fintek Super-I/O F71869, F71869A, F71882, F71889 and F81866
3 *
4 * Copyright (C) 2010-2013 LaCie
5 *
6 * Author: Simon Guinot <simon.guinot@sequanux.org>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14#include <linux/module.h>
15#include <linux/init.h>
16#include <linux/platform_device.h>
17#include <linux/io.h>
18#include <linux/gpio/driver.h>
19#include <linux/bitops.h>
20
21#define DRVNAME "gpio-f7188x"
22
23/*
24 * Super-I/O registers
25 */
26#define SIO_LDSEL 0x07 /* Logical device select */
27#define SIO_DEVID 0x20 /* Device ID (2 bytes) */
28#define SIO_DEVREV 0x22 /* Device revision */
29#define SIO_MANID 0x23 /* Fintek ID (2 bytes) */
30
31#define SIO_LD_GPIO 0x06 /* GPIO logical device */
32#define SIO_UNLOCK_KEY 0x87 /* Key to enable Super-I/O */
33#define SIO_LOCK_KEY 0xAA /* Key to disable Super-I/O */
34
35#define SIO_FINTEK_ID 0x1934 /* Manufacturer ID */
36#define SIO_F71869_ID 0x0814 /* F71869 chipset ID */
37#define SIO_F71869A_ID 0x1007 /* F71869A chipset ID */
38#define SIO_F71882_ID 0x0541 /* F71882 chipset ID */
39#define SIO_F71889_ID 0x0909 /* F71889 chipset ID */
40#define SIO_F71889A_ID 0x1005 /* F71889A chipset ID */
41#define SIO_F81866_ID 0x1010 /* F81866 chipset ID */
42
43enum chips { f71869, f71869a, f71882fg, f71889a, f71889f, f81866 };
44
45static const char * const f7188x_names[] = {
46 "f71869",
47 "f71869a",
48 "f71882fg",
49 "f71889a",
50 "f71889f",
51 "f81866",
52};
53
54struct f7188x_sio {
55 int addr;
56 enum chips type;
57};
58
59struct f7188x_gpio_bank {
60 struct gpio_chip chip;
61 unsigned int regbase;
62 struct f7188x_gpio_data *data;
63};
64
65struct f7188x_gpio_data {
66 struct f7188x_sio *sio;
67 int nr_bank;
68 struct f7188x_gpio_bank *bank;
69};
70
71/*
72 * Super-I/O functions.
73 */
74
75static inline int superio_inb(int base, int reg)
76{
77 outb(reg, base);
78 return inb(base + 1);
79}
80
81static int superio_inw(int base, int reg)
82{
83 int val;
84
85 outb(reg++, base);
86 val = inb(base + 1) << 8;
87 outb(reg, base);
88 val |= inb(base + 1);
89
90 return val;
91}
92
93static inline void superio_outb(int base, int reg, int val)
94{
95 outb(reg, base);
96 outb(val, base + 1);
97}
98
99static inline int superio_enter(int base)
100{
101 /* Don't step on other drivers' I/O space by accident. */
102 if (!request_muxed_region(base, 2, DRVNAME)) {
103 pr_err(DRVNAME "I/O address 0x%04x already in use\n", base);
104 return -EBUSY;
105 }
106
107 /* According to the datasheet the key must be send twice. */
108 outb(SIO_UNLOCK_KEY, base);
109 outb(SIO_UNLOCK_KEY, base);
110
111 return 0;
112}
113
114static inline void superio_select(int base, int ld)
115{
116 outb(SIO_LDSEL, base);
117 outb(ld, base + 1);
118}
119
120static inline void superio_exit(int base)
121{
122 outb(SIO_LOCK_KEY, base);
123 release_region(base, 2);
124}
125
126/*
127 * GPIO chip.
128 */
129
130static int f7188x_gpio_get_direction(struct gpio_chip *chip, unsigned offset);
131static int f7188x_gpio_direction_in(struct gpio_chip *chip, unsigned offset);
132static int f7188x_gpio_get(struct gpio_chip *chip, unsigned offset);
133static int f7188x_gpio_direction_out(struct gpio_chip *chip,
134 unsigned offset, int value);
135static void f7188x_gpio_set(struct gpio_chip *chip, unsigned offset, int value);
136static int f7188x_gpio_set_config(struct gpio_chip *chip, unsigned offset,
137 unsigned long config);
138
139#define F7188X_GPIO_BANK(_base, _ngpio, _regbase) \
140 { \
141 .chip = { \
142 .label = DRVNAME, \
143 .owner = THIS_MODULE, \
144 .get_direction = f7188x_gpio_get_direction, \
145 .direction_input = f7188x_gpio_direction_in, \
146 .get = f7188x_gpio_get, \
147 .direction_output = f7188x_gpio_direction_out, \
148 .set = f7188x_gpio_set, \
149 .set_config = f7188x_gpio_set_config, \
150 .base = _base, \
151 .ngpio = _ngpio, \
152 .can_sleep = true, \
153 }, \
154 .regbase = _regbase, \
155 }
156
157#define gpio_dir(base) (base + 0)
158#define gpio_data_out(base) (base + 1)
159#define gpio_data_in(base) (base + 2)
160/* Output mode register (0:open drain 1:push-pull). */
161#define gpio_out_mode(base) (base + 3)
162
163static struct f7188x_gpio_bank f71869_gpio_bank[] = {
164 F7188X_GPIO_BANK(0, 6, 0xF0),
165 F7188X_GPIO_BANK(10, 8, 0xE0),
166 F7188X_GPIO_BANK(20, 8, 0xD0),
167 F7188X_GPIO_BANK(30, 8, 0xC0),
168 F7188X_GPIO_BANK(40, 8, 0xB0),
169 F7188X_GPIO_BANK(50, 5, 0xA0),
170 F7188X_GPIO_BANK(60, 6, 0x90),
171};
172
173static struct f7188x_gpio_bank f71869a_gpio_bank[] = {
174 F7188X_GPIO_BANK(0, 6, 0xF0),
175 F7188X_GPIO_BANK(10, 8, 0xE0),
176 F7188X_GPIO_BANK(20, 8, 0xD0),
177 F7188X_GPIO_BANK(30, 8, 0xC0),
178 F7188X_GPIO_BANK(40, 8, 0xB0),
179 F7188X_GPIO_BANK(50, 5, 0xA0),
180 F7188X_GPIO_BANK(60, 8, 0x90),
181 F7188X_GPIO_BANK(70, 8, 0x80),
182};
183
184static struct f7188x_gpio_bank f71882_gpio_bank[] = {
185 F7188X_GPIO_BANK(0, 8, 0xF0),
186 F7188X_GPIO_BANK(10, 8, 0xE0),
187 F7188X_GPIO_BANK(20, 8, 0xD0),
188 F7188X_GPIO_BANK(30, 4, 0xC0),
189 F7188X_GPIO_BANK(40, 4, 0xB0),
190};
191
192static struct f7188x_gpio_bank f71889a_gpio_bank[] = {
193 F7188X_GPIO_BANK(0, 7, 0xF0),
194 F7188X_GPIO_BANK(10, 7, 0xE0),
195 F7188X_GPIO_BANK(20, 8, 0xD0),
196 F7188X_GPIO_BANK(30, 8, 0xC0),
197 F7188X_GPIO_BANK(40, 8, 0xB0),
198 F7188X_GPIO_BANK(50, 5, 0xA0),
199 F7188X_GPIO_BANK(60, 8, 0x90),
200 F7188X_GPIO_BANK(70, 8, 0x80),
201};
202
203static struct f7188x_gpio_bank f71889_gpio_bank[] = {
204 F7188X_GPIO_BANK(0, 7, 0xF0),
205 F7188X_GPIO_BANK(10, 7, 0xE0),
206 F7188X_GPIO_BANK(20, 8, 0xD0),
207 F7188X_GPIO_BANK(30, 8, 0xC0),
208 F7188X_GPIO_BANK(40, 8, 0xB0),
209 F7188X_GPIO_BANK(50, 5, 0xA0),
210 F7188X_GPIO_BANK(60, 8, 0x90),
211 F7188X_GPIO_BANK(70, 8, 0x80),
212};
213
214static struct f7188x_gpio_bank f81866_gpio_bank[] = {
215 F7188X_GPIO_BANK(0, 8, 0xF0),
216 F7188X_GPIO_BANK(10, 8, 0xE0),
217 F7188X_GPIO_BANK(20, 8, 0xD0),
218 F7188X_GPIO_BANK(30, 8, 0xC0),
219 F7188X_GPIO_BANK(40, 8, 0xB0),
220 F7188X_GPIO_BANK(50, 8, 0xA0),
221 F7188X_GPIO_BANK(60, 8, 0x90),
222 F7188X_GPIO_BANK(70, 8, 0x80),
223 F7188X_GPIO_BANK(80, 8, 0x88),
224};
225
226static int f7188x_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
227{
228 int err;
229 struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
230 struct f7188x_sio *sio = bank->data->sio;
231 u8 dir;
232
233 err = superio_enter(sio->addr);
234 if (err)
235 return err;
236 superio_select(sio->addr, SIO_LD_GPIO);
237
238 dir = superio_inb(sio->addr, gpio_dir(bank->regbase));
239
240 superio_exit(sio->addr);
241
242 return !(dir & 1 << offset);
243}
244
245static int f7188x_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
246{
247 int err;
248 struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
249 struct f7188x_sio *sio = bank->data->sio;
250 u8 dir;
251
252 err = superio_enter(sio->addr);
253 if (err)
254 return err;
255 superio_select(sio->addr, SIO_LD_GPIO);
256
257 dir = superio_inb(sio->addr, gpio_dir(bank->regbase));
258 dir &= ~BIT(offset);
259 superio_outb(sio->addr, gpio_dir(bank->regbase), dir);
260
261 superio_exit(sio->addr);
262
263 return 0;
264}
265
266static int f7188x_gpio_get(struct gpio_chip *chip, unsigned offset)
267{
268 int err;
269 struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
270 struct f7188x_sio *sio = bank->data->sio;
271 u8 dir, data;
272
273 err = superio_enter(sio->addr);
274 if (err)
275 return err;
276 superio_select(sio->addr, SIO_LD_GPIO);
277
278 dir = superio_inb(sio->addr, gpio_dir(bank->regbase));
279 dir = !!(dir & BIT(offset));
280 if (dir)
281 data = superio_inb(sio->addr, gpio_data_out(bank->regbase));
282 else
283 data = superio_inb(sio->addr, gpio_data_in(bank->regbase));
284
285 superio_exit(sio->addr);
286
287 return !!(data & BIT(offset));
288}
289
290static int f7188x_gpio_direction_out(struct gpio_chip *chip,
291 unsigned offset, int value)
292{
293 int err;
294 struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
295 struct f7188x_sio *sio = bank->data->sio;
296 u8 dir, data_out;
297
298 err = superio_enter(sio->addr);
299 if (err)
300 return err;
301 superio_select(sio->addr, SIO_LD_GPIO);
302
303 data_out = superio_inb(sio->addr, gpio_data_out(bank->regbase));
304 if (value)
305 data_out |= BIT(offset);
306 else
307 data_out &= ~BIT(offset);
308 superio_outb(sio->addr, gpio_data_out(bank->regbase), data_out);
309
310 dir = superio_inb(sio->addr, gpio_dir(bank->regbase));
311 dir |= BIT(offset);
312 superio_outb(sio->addr, gpio_dir(bank->regbase), dir);
313
314 superio_exit(sio->addr);
315
316 return 0;
317}
318
319static void f7188x_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
320{
321 int err;
322 struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
323 struct f7188x_sio *sio = bank->data->sio;
324 u8 data_out;
325
326 err = superio_enter(sio->addr);
327 if (err)
328 return;
329 superio_select(sio->addr, SIO_LD_GPIO);
330
331 data_out = superio_inb(sio->addr, gpio_data_out(bank->regbase));
332 if (value)
333 data_out |= BIT(offset);
334 else
335 data_out &= ~BIT(offset);
336 superio_outb(sio->addr, gpio_data_out(bank->regbase), data_out);
337
338 superio_exit(sio->addr);
339}
340
341static int f7188x_gpio_set_config(struct gpio_chip *chip, unsigned offset,
342 unsigned long config)
343{
344 int err;
345 enum pin_config_param param = pinconf_to_config_param(config);
346 struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
347 struct f7188x_sio *sio = bank->data->sio;
348 u8 data;
349
350 if (param != PIN_CONFIG_DRIVE_OPEN_DRAIN &&
351 param != PIN_CONFIG_DRIVE_PUSH_PULL)
352 return -ENOTSUPP;
353
354 err = superio_enter(sio->addr);
355 if (err)
356 return err;
357 superio_select(sio->addr, SIO_LD_GPIO);
358
359 data = superio_inb(sio->addr, gpio_out_mode(bank->regbase));
360 if (param == PIN_CONFIG_DRIVE_OPEN_DRAIN)
361 data &= ~BIT(offset);
362 else
363 data |= BIT(offset);
364 superio_outb(sio->addr, gpio_out_mode(bank->regbase), data);
365
366 superio_exit(sio->addr);
367 return 0;
368}
369
370/*
371 * Platform device and driver.
372 */
373
374static int f7188x_gpio_probe(struct platform_device *pdev)
375{
376 int err;
377 int i;
378 struct f7188x_sio *sio = dev_get_platdata(&pdev->dev);
379 struct f7188x_gpio_data *data;
380
381 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
382 if (!data)
383 return -ENOMEM;
384
385 switch (sio->type) {
386 case f71869:
387 data->nr_bank = ARRAY_SIZE(f71869_gpio_bank);
388 data->bank = f71869_gpio_bank;
389 break;
390 case f71869a:
391 data->nr_bank = ARRAY_SIZE(f71869a_gpio_bank);
392 data->bank = f71869a_gpio_bank;
393 break;
394 case f71882fg:
395 data->nr_bank = ARRAY_SIZE(f71882_gpio_bank);
396 data->bank = f71882_gpio_bank;
397 break;
398 case f71889a:
399 data->nr_bank = ARRAY_SIZE(f71889a_gpio_bank);
400 data->bank = f71889a_gpio_bank;
401 break;
402 case f71889f:
403 data->nr_bank = ARRAY_SIZE(f71889_gpio_bank);
404 data->bank = f71889_gpio_bank;
405 break;
406 case f81866:
407 data->nr_bank = ARRAY_SIZE(f81866_gpio_bank);
408 data->bank = f81866_gpio_bank;
409 break;
410 default:
411 return -ENODEV;
412 }
413 data->sio = sio;
414
415 platform_set_drvdata(pdev, data);
416
417 /* For each GPIO bank, register a GPIO chip. */
418 for (i = 0; i < data->nr_bank; i++) {
419 struct f7188x_gpio_bank *bank = &data->bank[i];
420
421 bank->chip.parent = &pdev->dev;
422 bank->data = data;
423
424 err = devm_gpiochip_add_data(&pdev->dev, &bank->chip, bank);
425 if (err) {
426 dev_err(&pdev->dev,
427 "Failed to register gpiochip %d: %d\n",
428 i, err);
429 return err;
430 }
431 }
432
433 return 0;
434}
435
436static int __init f7188x_find(int addr, struct f7188x_sio *sio)
437{
438 int err;
439 u16 devid;
440
441 err = superio_enter(addr);
442 if (err)
443 return err;
444
445 err = -ENODEV;
446 devid = superio_inw(addr, SIO_MANID);
447 if (devid != SIO_FINTEK_ID) {
448 pr_debug(DRVNAME ": Not a Fintek device at 0x%08x\n", addr);
449 goto err;
450 }
451
452 devid = superio_inw(addr, SIO_DEVID);
453 switch (devid) {
454 case SIO_F71869_ID:
455 sio->type = f71869;
456 break;
457 case SIO_F71869A_ID:
458 sio->type = f71869a;
459 break;
460 case SIO_F71882_ID:
461 sio->type = f71882fg;
462 break;
463 case SIO_F71889A_ID:
464 sio->type = f71889a;
465 break;
466 case SIO_F71889_ID:
467 sio->type = f71889f;
468 break;
469 case SIO_F81866_ID:
470 sio->type = f81866;
471 break;
472 default:
473 pr_info(DRVNAME ": Unsupported Fintek device 0x%04x\n", devid);
474 goto err;
475 }
476 sio->addr = addr;
477 err = 0;
478
479 pr_info(DRVNAME ": Found %s at %#x, revision %d\n",
480 f7188x_names[sio->type],
481 (unsigned int) addr,
482 (int) superio_inb(addr, SIO_DEVREV));
483
484err:
485 superio_exit(addr);
486 return err;
487}
488
489static struct platform_device *f7188x_gpio_pdev;
490
491static int __init
492f7188x_gpio_device_add(const struct f7188x_sio *sio)
493{
494 int err;
495
496 f7188x_gpio_pdev = platform_device_alloc(DRVNAME, -1);
497 if (!f7188x_gpio_pdev)
498 return -ENOMEM;
499
500 err = platform_device_add_data(f7188x_gpio_pdev,
501 sio, sizeof(*sio));
502 if (err) {
503 pr_err(DRVNAME "Platform data allocation failed\n");
504 goto err;
505 }
506
507 err = platform_device_add(f7188x_gpio_pdev);
508 if (err) {
509 pr_err(DRVNAME "Device addition failed\n");
510 goto err;
511 }
512
513 return 0;
514
515err:
516 platform_device_put(f7188x_gpio_pdev);
517
518 return err;
519}
520
521/*
522 * Try to match a supported Fintek device by reading the (hard-wired)
523 * configuration I/O ports. If available, then register both the platform
524 * device and driver to support the GPIOs.
525 */
526
527static struct platform_driver f7188x_gpio_driver = {
528 .driver = {
529 .name = DRVNAME,
530 },
531 .probe = f7188x_gpio_probe,
532};
533
534static int __init f7188x_gpio_init(void)
535{
536 int err;
537 struct f7188x_sio sio;
538
539 if (f7188x_find(0x2e, &sio) &&
540 f7188x_find(0x4e, &sio))
541 return -ENODEV;
542
543 err = platform_driver_register(&f7188x_gpio_driver);
544 if (!err) {
545 err = f7188x_gpio_device_add(&sio);
546 if (err)
547 platform_driver_unregister(&f7188x_gpio_driver);
548 }
549
550 return err;
551}
552subsys_initcall(f7188x_gpio_init);
553
554static void __exit f7188x_gpio_exit(void)
555{
556 platform_device_unregister(f7188x_gpio_pdev);
557 platform_driver_unregister(&f7188x_gpio_driver);
558}
559module_exit(f7188x_gpio_exit);
560
561MODULE_DESCRIPTION("GPIO driver for Super-I/O chips F71869, F71869A, F71882FG, F71889A, F71889F and F81866");
562MODULE_AUTHOR("Simon Guinot <simon.guinot@sequanux.org>");
563MODULE_LICENSE("GPL");