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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 *
4 * Copyright (C) STMicroelectronics SA 2017
5 * Author(s): M'boumba Cedric Madianga <cedric.madianga@gmail.com>
6 * Pierre-Yves Mordret <pierre-yves.mordret@st.com>
7 *
8 * DMA Router driver for STM32 DMA MUX
9 *
10 * Based on TI DMA Crossbar driver
11 */
12
13#include <linux/clk.h>
14#include <linux/delay.h>
15#include <linux/err.h>
16#include <linux/init.h>
17#include <linux/module.h>
18#include <linux/of_device.h>
19#include <linux/of_dma.h>
20#include <linux/pm_runtime.h>
21#include <linux/reset.h>
22#include <linux/slab.h>
23#include <linux/spinlock.h>
24
25#define STM32_DMAMUX_CCR(x) (0x4 * (x))
26#define STM32_DMAMUX_MAX_DMA_REQUESTS 32
27#define STM32_DMAMUX_MAX_REQUESTS 255
28
29struct stm32_dmamux {
30 u32 master;
31 u32 request;
32 u32 chan_id;
33};
34
35struct stm32_dmamux_data {
36 struct dma_router dmarouter;
37 struct clk *clk;
38 void __iomem *iomem;
39 u32 dma_requests; /* Number of DMA requests connected to DMAMUX */
40 u32 dmamux_requests; /* Number of DMA requests routed toward DMAs */
41 spinlock_t lock; /* Protects register access */
42 unsigned long *dma_inuse; /* Used DMA channel */
43 u32 ccr[STM32_DMAMUX_MAX_DMA_REQUESTS]; /* Used to backup CCR register
44 * in suspend
45 */
46 u32 dma_reqs[]; /* Number of DMA Request per DMA masters.
47 * [0] holds number of DMA Masters.
48 * To be kept at very end end of this structure
49 */
50};
51
52static inline u32 stm32_dmamux_read(void __iomem *iomem, u32 reg)
53{
54 return readl_relaxed(iomem + reg);
55}
56
57static inline void stm32_dmamux_write(void __iomem *iomem, u32 reg, u32 val)
58{
59 writel_relaxed(val, iomem + reg);
60}
61
62static void stm32_dmamux_free(struct device *dev, void *route_data)
63{
64 struct stm32_dmamux_data *dmamux = dev_get_drvdata(dev);
65 struct stm32_dmamux *mux = route_data;
66 unsigned long flags;
67
68 /* Clear dma request */
69 spin_lock_irqsave(&dmamux->lock, flags);
70
71 stm32_dmamux_write(dmamux->iomem, STM32_DMAMUX_CCR(mux->chan_id), 0);
72 clear_bit(mux->chan_id, dmamux->dma_inuse);
73
74 pm_runtime_put_sync(dev);
75
76 spin_unlock_irqrestore(&dmamux->lock, flags);
77
78 dev_dbg(dev, "Unmapping DMAMUX(%u) to DMA%u(%u)\n",
79 mux->request, mux->master, mux->chan_id);
80
81 kfree(mux);
82}
83
84static void *stm32_dmamux_route_allocate(struct of_phandle_args *dma_spec,
85 struct of_dma *ofdma)
86{
87 struct platform_device *pdev = of_find_device_by_node(ofdma->of_node);
88 struct stm32_dmamux_data *dmamux = platform_get_drvdata(pdev);
89 struct stm32_dmamux *mux;
90 u32 i, min, max;
91 int ret;
92 unsigned long flags;
93
94 if (dma_spec->args_count != 3) {
95 dev_err(&pdev->dev, "invalid number of dma mux args\n");
96 return ERR_PTR(-EINVAL);
97 }
98
99 if (dma_spec->args[0] > dmamux->dmamux_requests) {
100 dev_err(&pdev->dev, "invalid mux request number: %d\n",
101 dma_spec->args[0]);
102 return ERR_PTR(-EINVAL);
103 }
104
105 mux = kzalloc(sizeof(*mux), GFP_KERNEL);
106 if (!mux)
107 return ERR_PTR(-ENOMEM);
108
109 spin_lock_irqsave(&dmamux->lock, flags);
110 mux->chan_id = find_first_zero_bit(dmamux->dma_inuse,
111 dmamux->dma_requests);
112
113 if (mux->chan_id == dmamux->dma_requests) {
114 spin_unlock_irqrestore(&dmamux->lock, flags);
115 dev_err(&pdev->dev, "Run out of free DMA requests\n");
116 ret = -ENOMEM;
117 goto error_chan_id;
118 }
119 set_bit(mux->chan_id, dmamux->dma_inuse);
120 spin_unlock_irqrestore(&dmamux->lock, flags);
121
122 /* Look for DMA Master */
123 for (i = 1, min = 0, max = dmamux->dma_reqs[i];
124 i <= dmamux->dma_reqs[0];
125 min += dmamux->dma_reqs[i], max += dmamux->dma_reqs[++i])
126 if (mux->chan_id < max)
127 break;
128 mux->master = i - 1;
129
130 /* The of_node_put() will be done in of_dma_router_xlate function */
131 dma_spec->np = of_parse_phandle(ofdma->of_node, "dma-masters", i - 1);
132 if (!dma_spec->np) {
133 dev_err(&pdev->dev, "can't get dma master\n");
134 ret = -EINVAL;
135 goto error;
136 }
137
138 /* Set dma request */
139 spin_lock_irqsave(&dmamux->lock, flags);
140 ret = pm_runtime_get_sync(&pdev->dev);
141 if (ret < 0) {
142 spin_unlock_irqrestore(&dmamux->lock, flags);
143 goto error;
144 }
145 spin_unlock_irqrestore(&dmamux->lock, flags);
146
147 mux->request = dma_spec->args[0];
148
149 /* craft DMA spec */
150 dma_spec->args[3] = dma_spec->args[2];
151 dma_spec->args[2] = dma_spec->args[1];
152 dma_spec->args[1] = 0;
153 dma_spec->args[0] = mux->chan_id - min;
154 dma_spec->args_count = 4;
155
156 stm32_dmamux_write(dmamux->iomem, STM32_DMAMUX_CCR(mux->chan_id),
157 mux->request);
158 dev_dbg(&pdev->dev, "Mapping DMAMUX(%u) to DMA%u(%u)\n",
159 mux->request, mux->master, mux->chan_id);
160
161 return mux;
162
163error:
164 clear_bit(mux->chan_id, dmamux->dma_inuse);
165
166error_chan_id:
167 kfree(mux);
168 return ERR_PTR(ret);
169}
170
171static const struct of_device_id stm32_stm32dma_master_match[] = {
172 { .compatible = "st,stm32-dma", },
173 {},
174};
175
176static int stm32_dmamux_probe(struct platform_device *pdev)
177{
178 struct device_node *node = pdev->dev.of_node;
179 const struct of_device_id *match;
180 struct device_node *dma_node;
181 struct stm32_dmamux_data *stm32_dmamux;
182 struct resource *res;
183 void __iomem *iomem;
184 struct reset_control *rst;
185 int i, count, ret;
186 u32 dma_req;
187
188 if (!node)
189 return -ENODEV;
190
191 count = device_property_count_u32(&pdev->dev, "dma-masters");
192 if (count < 0) {
193 dev_err(&pdev->dev, "Can't get DMA master(s) node\n");
194 return -ENODEV;
195 }
196
197 stm32_dmamux = devm_kzalloc(&pdev->dev, sizeof(*stm32_dmamux) +
198 sizeof(u32) * (count + 1), GFP_KERNEL);
199 if (!stm32_dmamux)
200 return -ENOMEM;
201
202 dma_req = 0;
203 for (i = 1; i <= count; i++) {
204 dma_node = of_parse_phandle(node, "dma-masters", i - 1);
205
206 match = of_match_node(stm32_stm32dma_master_match, dma_node);
207 if (!match) {
208 dev_err(&pdev->dev, "DMA master is not supported\n");
209 of_node_put(dma_node);
210 return -EINVAL;
211 }
212
213 if (of_property_read_u32(dma_node, "dma-requests",
214 &stm32_dmamux->dma_reqs[i])) {
215 dev_info(&pdev->dev,
216 "Missing MUX output information, using %u.\n",
217 STM32_DMAMUX_MAX_DMA_REQUESTS);
218 stm32_dmamux->dma_reqs[i] =
219 STM32_DMAMUX_MAX_DMA_REQUESTS;
220 }
221 dma_req += stm32_dmamux->dma_reqs[i];
222 of_node_put(dma_node);
223 }
224
225 if (dma_req > STM32_DMAMUX_MAX_DMA_REQUESTS) {
226 dev_err(&pdev->dev, "Too many DMA Master Requests to manage\n");
227 return -ENODEV;
228 }
229
230 stm32_dmamux->dma_requests = dma_req;
231 stm32_dmamux->dma_reqs[0] = count;
232 stm32_dmamux->dma_inuse = devm_kcalloc(&pdev->dev,
233 BITS_TO_LONGS(dma_req),
234 sizeof(unsigned long),
235 GFP_KERNEL);
236 if (!stm32_dmamux->dma_inuse)
237 return -ENOMEM;
238
239 if (device_property_read_u32(&pdev->dev, "dma-requests",
240 &stm32_dmamux->dmamux_requests)) {
241 stm32_dmamux->dmamux_requests = STM32_DMAMUX_MAX_REQUESTS;
242 dev_warn(&pdev->dev, "DMAMUX defaulting on %u requests\n",
243 stm32_dmamux->dmamux_requests);
244 }
245 pm_runtime_get_noresume(&pdev->dev);
246
247 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
248 iomem = devm_ioremap_resource(&pdev->dev, res);
249 if (IS_ERR(iomem))
250 return PTR_ERR(iomem);
251
252 spin_lock_init(&stm32_dmamux->lock);
253
254 stm32_dmamux->clk = devm_clk_get(&pdev->dev, NULL);
255 if (IS_ERR(stm32_dmamux->clk)) {
256 ret = PTR_ERR(stm32_dmamux->clk);
257 if (ret != -EPROBE_DEFER)
258 dev_err(&pdev->dev, "Missing clock controller\n");
259 return ret;
260 }
261
262 ret = clk_prepare_enable(stm32_dmamux->clk);
263 if (ret < 0) {
264 dev_err(&pdev->dev, "clk_prep_enable error: %d\n", ret);
265 return ret;
266 }
267
268 rst = devm_reset_control_get(&pdev->dev, NULL);
269 if (IS_ERR(rst)) {
270 ret = PTR_ERR(rst);
271 if (ret == -EPROBE_DEFER)
272 goto err_clk;
273 } else {
274 reset_control_assert(rst);
275 udelay(2);
276 reset_control_deassert(rst);
277 }
278
279 stm32_dmamux->iomem = iomem;
280 stm32_dmamux->dmarouter.dev = &pdev->dev;
281 stm32_dmamux->dmarouter.route_free = stm32_dmamux_free;
282
283 platform_set_drvdata(pdev, stm32_dmamux);
284 pm_runtime_set_active(&pdev->dev);
285 pm_runtime_enable(&pdev->dev);
286
287 pm_runtime_get_noresume(&pdev->dev);
288
289 /* Reset the dmamux */
290 for (i = 0; i < stm32_dmamux->dma_requests; i++)
291 stm32_dmamux_write(stm32_dmamux->iomem, STM32_DMAMUX_CCR(i), 0);
292
293 pm_runtime_put(&pdev->dev);
294
295 ret = of_dma_router_register(node, stm32_dmamux_route_allocate,
296 &stm32_dmamux->dmarouter);
297 if (ret)
298 goto err_clk;
299
300 return 0;
301
302err_clk:
303 clk_disable_unprepare(stm32_dmamux->clk);
304
305 return ret;
306}
307
308#ifdef CONFIG_PM
309static int stm32_dmamux_runtime_suspend(struct device *dev)
310{
311 struct platform_device *pdev = to_platform_device(dev);
312 struct stm32_dmamux_data *stm32_dmamux = platform_get_drvdata(pdev);
313
314 clk_disable_unprepare(stm32_dmamux->clk);
315
316 return 0;
317}
318
319static int stm32_dmamux_runtime_resume(struct device *dev)
320{
321 struct platform_device *pdev = to_platform_device(dev);
322 struct stm32_dmamux_data *stm32_dmamux = platform_get_drvdata(pdev);
323 int ret;
324
325 ret = clk_prepare_enable(stm32_dmamux->clk);
326 if (ret) {
327 dev_err(&pdev->dev, "failed to prepare_enable clock\n");
328 return ret;
329 }
330
331 return 0;
332}
333#endif
334
335#ifdef CONFIG_PM_SLEEP
336static int stm32_dmamux_suspend(struct device *dev)
337{
338 struct platform_device *pdev = to_platform_device(dev);
339 struct stm32_dmamux_data *stm32_dmamux = platform_get_drvdata(pdev);
340 int i, ret;
341
342 ret = pm_runtime_get_sync(dev);
343 if (ret < 0)
344 return ret;
345
346 for (i = 0; i < stm32_dmamux->dma_requests; i++)
347 stm32_dmamux->ccr[i] = stm32_dmamux_read(stm32_dmamux->iomem,
348 STM32_DMAMUX_CCR(i));
349
350 pm_runtime_put_sync(dev);
351
352 pm_runtime_force_suspend(dev);
353
354 return 0;
355}
356
357static int stm32_dmamux_resume(struct device *dev)
358{
359 struct platform_device *pdev = to_platform_device(dev);
360 struct stm32_dmamux_data *stm32_dmamux = platform_get_drvdata(pdev);
361 int i, ret;
362
363 ret = pm_runtime_force_resume(dev);
364 if (ret < 0)
365 return ret;
366
367 ret = pm_runtime_get_sync(dev);
368 if (ret < 0)
369 return ret;
370
371 for (i = 0; i < stm32_dmamux->dma_requests; i++)
372 stm32_dmamux_write(stm32_dmamux->iomem, STM32_DMAMUX_CCR(i),
373 stm32_dmamux->ccr[i]);
374
375 pm_runtime_put_sync(dev);
376
377 return 0;
378}
379#endif
380
381static const struct dev_pm_ops stm32_dmamux_pm_ops = {
382 SET_SYSTEM_SLEEP_PM_OPS(stm32_dmamux_suspend, stm32_dmamux_resume)
383 SET_RUNTIME_PM_OPS(stm32_dmamux_runtime_suspend,
384 stm32_dmamux_runtime_resume, NULL)
385};
386
387static const struct of_device_id stm32_dmamux_match[] = {
388 { .compatible = "st,stm32h7-dmamux" },
389 {},
390};
391
392static struct platform_driver stm32_dmamux_driver = {
393 .probe = stm32_dmamux_probe,
394 .driver = {
395 .name = "stm32-dmamux",
396 .of_match_table = stm32_dmamux_match,
397 .pm = &stm32_dmamux_pm_ops,
398 },
399};
400
401static int __init stm32_dmamux_init(void)
402{
403 return platform_driver_register(&stm32_dmamux_driver);
404}
405arch_initcall(stm32_dmamux_init);
406
407MODULE_DESCRIPTION("DMA Router driver for STM32 DMA MUX");
408MODULE_AUTHOR("M'boumba Cedric Madianga <cedric.madianga@gmail.com>");
409MODULE_AUTHOR("Pierre-Yves Mordret <pierre-yves.mordret@st.com>");
410MODULE_LICENSE("GPL v2");
1/*
2 *
3 * Copyright (C) STMicroelectronics SA 2017
4 * Author(s): M'boumba Cedric Madianga <cedric.madianga@gmail.com>
5 * Pierre-Yves Mordret <pierre-yves.mordret@st.com>
6 *
7 * License terms: GPL V2.0.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published by
11 * the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
16 * details.
17 *
18 * DMA Router driver for STM32 DMA MUX
19 *
20 * Based on TI DMA Crossbar driver
21 *
22 */
23
24#include <linux/clk.h>
25#include <linux/delay.h>
26#include <linux/err.h>
27#include <linux/init.h>
28#include <linux/module.h>
29#include <linux/of_device.h>
30#include <linux/of_dma.h>
31#include <linux/reset.h>
32#include <linux/slab.h>
33#include <linux/spinlock.h>
34
35#define STM32_DMAMUX_CCR(x) (0x4 * (x))
36#define STM32_DMAMUX_MAX_DMA_REQUESTS 32
37#define STM32_DMAMUX_MAX_REQUESTS 255
38
39struct stm32_dmamux {
40 u32 master;
41 u32 request;
42 u32 chan_id;
43};
44
45struct stm32_dmamux_data {
46 struct dma_router dmarouter;
47 struct clk *clk;
48 struct reset_control *rst;
49 void __iomem *iomem;
50 u32 dma_requests; /* Number of DMA requests connected to DMAMUX */
51 u32 dmamux_requests; /* Number of DMA requests routed toward DMAs */
52 spinlock_t lock; /* Protects register access */
53 unsigned long *dma_inuse; /* Used DMA channel */
54 u32 dma_reqs[]; /* Number of DMA Request per DMA masters.
55 * [0] holds number of DMA Masters.
56 * To be kept at very end end of this structure
57 */
58};
59
60static inline u32 stm32_dmamux_read(void __iomem *iomem, u32 reg)
61{
62 return readl_relaxed(iomem + reg);
63}
64
65static inline void stm32_dmamux_write(void __iomem *iomem, u32 reg, u32 val)
66{
67 writel_relaxed(val, iomem + reg);
68}
69
70static void stm32_dmamux_free(struct device *dev, void *route_data)
71{
72 struct stm32_dmamux_data *dmamux = dev_get_drvdata(dev);
73 struct stm32_dmamux *mux = route_data;
74 unsigned long flags;
75
76 /* Clear dma request */
77 spin_lock_irqsave(&dmamux->lock, flags);
78
79 stm32_dmamux_write(dmamux->iomem, STM32_DMAMUX_CCR(mux->chan_id), 0);
80 clear_bit(mux->chan_id, dmamux->dma_inuse);
81
82 if (!IS_ERR(dmamux->clk))
83 clk_disable(dmamux->clk);
84
85 spin_unlock_irqrestore(&dmamux->lock, flags);
86
87 dev_dbg(dev, "Unmapping DMAMUX(%u) to DMA%u(%u)\n",
88 mux->request, mux->master, mux->chan_id);
89
90 kfree(mux);
91}
92
93static void *stm32_dmamux_route_allocate(struct of_phandle_args *dma_spec,
94 struct of_dma *ofdma)
95{
96 struct platform_device *pdev = of_find_device_by_node(ofdma->of_node);
97 struct stm32_dmamux_data *dmamux = platform_get_drvdata(pdev);
98 struct stm32_dmamux *mux;
99 u32 i, min, max;
100 int ret;
101 unsigned long flags;
102
103 if (dma_spec->args_count != 3) {
104 dev_err(&pdev->dev, "invalid number of dma mux args\n");
105 return ERR_PTR(-EINVAL);
106 }
107
108 if (dma_spec->args[0] > dmamux->dmamux_requests) {
109 dev_err(&pdev->dev, "invalid mux request number: %d\n",
110 dma_spec->args[0]);
111 return ERR_PTR(-EINVAL);
112 }
113
114 mux = kzalloc(sizeof(*mux), GFP_KERNEL);
115 if (!mux)
116 return ERR_PTR(-ENOMEM);
117
118 spin_lock_irqsave(&dmamux->lock, flags);
119 mux->chan_id = find_first_zero_bit(dmamux->dma_inuse,
120 dmamux->dma_requests);
121
122 if (mux->chan_id == dmamux->dma_requests) {
123 spin_unlock_irqrestore(&dmamux->lock, flags);
124 dev_err(&pdev->dev, "Run out of free DMA requests\n");
125 ret = -ENOMEM;
126 goto error_chan_id;
127 }
128 set_bit(mux->chan_id, dmamux->dma_inuse);
129 spin_unlock_irqrestore(&dmamux->lock, flags);
130
131 /* Look for DMA Master */
132 for (i = 1, min = 0, max = dmamux->dma_reqs[i];
133 i <= dmamux->dma_reqs[0];
134 min += dmamux->dma_reqs[i], max += dmamux->dma_reqs[++i])
135 if (mux->chan_id < max)
136 break;
137 mux->master = i - 1;
138
139 /* The of_node_put() will be done in of_dma_router_xlate function */
140 dma_spec->np = of_parse_phandle(ofdma->of_node, "dma-masters", i - 1);
141 if (!dma_spec->np) {
142 dev_err(&pdev->dev, "can't get dma master\n");
143 ret = -EINVAL;
144 goto error;
145 }
146
147 /* Set dma request */
148 spin_lock_irqsave(&dmamux->lock, flags);
149 if (!IS_ERR(dmamux->clk)) {
150 ret = clk_enable(dmamux->clk);
151 if (ret < 0) {
152 spin_unlock_irqrestore(&dmamux->lock, flags);
153 dev_err(&pdev->dev, "clk_prep_enable issue: %d\n", ret);
154 goto error;
155 }
156 }
157 spin_unlock_irqrestore(&dmamux->lock, flags);
158
159 mux->request = dma_spec->args[0];
160
161 /* craft DMA spec */
162 dma_spec->args[3] = dma_spec->args[2];
163 dma_spec->args[2] = dma_spec->args[1];
164 dma_spec->args[1] = 0;
165 dma_spec->args[0] = mux->chan_id - min;
166 dma_spec->args_count = 4;
167
168 stm32_dmamux_write(dmamux->iomem, STM32_DMAMUX_CCR(mux->chan_id),
169 mux->request);
170 dev_dbg(&pdev->dev, "Mapping DMAMUX(%u) to DMA%u(%u)\n",
171 mux->request, mux->master, mux->chan_id);
172
173 return mux;
174
175error:
176 clear_bit(mux->chan_id, dmamux->dma_inuse);
177
178error_chan_id:
179 kfree(mux);
180 return ERR_PTR(ret);
181}
182
183static const struct of_device_id stm32_stm32dma_master_match[] = {
184 { .compatible = "st,stm32-dma", },
185 {},
186};
187
188static int stm32_dmamux_probe(struct platform_device *pdev)
189{
190 struct device_node *node = pdev->dev.of_node;
191 const struct of_device_id *match;
192 struct device_node *dma_node;
193 struct stm32_dmamux_data *stm32_dmamux;
194 struct resource *res;
195 void __iomem *iomem;
196 int i, count, ret;
197 u32 dma_req;
198
199 if (!node)
200 return -ENODEV;
201
202 count = device_property_read_u32_array(&pdev->dev, "dma-masters",
203 NULL, 0);
204 if (count < 0) {
205 dev_err(&pdev->dev, "Can't get DMA master(s) node\n");
206 return -ENODEV;
207 }
208
209 stm32_dmamux = devm_kzalloc(&pdev->dev, sizeof(*stm32_dmamux) +
210 sizeof(u32) * (count + 1), GFP_KERNEL);
211 if (!stm32_dmamux)
212 return -ENOMEM;
213
214 dma_req = 0;
215 for (i = 1; i <= count; i++) {
216 dma_node = of_parse_phandle(node, "dma-masters", i - 1);
217
218 match = of_match_node(stm32_stm32dma_master_match, dma_node);
219 if (!match) {
220 dev_err(&pdev->dev, "DMA master is not supported\n");
221 of_node_put(dma_node);
222 return -EINVAL;
223 }
224
225 if (of_property_read_u32(dma_node, "dma-requests",
226 &stm32_dmamux->dma_reqs[i])) {
227 dev_info(&pdev->dev,
228 "Missing MUX output information, using %u.\n",
229 STM32_DMAMUX_MAX_DMA_REQUESTS);
230 stm32_dmamux->dma_reqs[i] =
231 STM32_DMAMUX_MAX_DMA_REQUESTS;
232 }
233 dma_req += stm32_dmamux->dma_reqs[i];
234 of_node_put(dma_node);
235 }
236
237 if (dma_req > STM32_DMAMUX_MAX_DMA_REQUESTS) {
238 dev_err(&pdev->dev, "Too many DMA Master Requests to manage\n");
239 return -ENODEV;
240 }
241
242 stm32_dmamux->dma_requests = dma_req;
243 stm32_dmamux->dma_reqs[0] = count;
244 stm32_dmamux->dma_inuse = devm_kcalloc(&pdev->dev,
245 BITS_TO_LONGS(dma_req),
246 sizeof(unsigned long),
247 GFP_KERNEL);
248 if (!stm32_dmamux->dma_inuse)
249 return -ENOMEM;
250
251 if (device_property_read_u32(&pdev->dev, "dma-requests",
252 &stm32_dmamux->dmamux_requests)) {
253 stm32_dmamux->dmamux_requests = STM32_DMAMUX_MAX_REQUESTS;
254 dev_warn(&pdev->dev, "DMAMUX defaulting on %u requests\n",
255 stm32_dmamux->dmamux_requests);
256 }
257
258 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
259 iomem = devm_ioremap_resource(&pdev->dev, res);
260 if (IS_ERR(iomem))
261 return PTR_ERR(iomem);
262
263 spin_lock_init(&stm32_dmamux->lock);
264
265 stm32_dmamux->clk = devm_clk_get(&pdev->dev, NULL);
266 if (IS_ERR(stm32_dmamux->clk)) {
267 ret = PTR_ERR(stm32_dmamux->clk);
268 if (ret == -EPROBE_DEFER)
269 dev_info(&pdev->dev, "Missing controller clock\n");
270 return ret;
271 }
272
273 stm32_dmamux->rst = devm_reset_control_get(&pdev->dev, NULL);
274 if (!IS_ERR(stm32_dmamux->rst)) {
275 reset_control_assert(stm32_dmamux->rst);
276 udelay(2);
277 reset_control_deassert(stm32_dmamux->rst);
278 }
279
280 stm32_dmamux->iomem = iomem;
281 stm32_dmamux->dmarouter.dev = &pdev->dev;
282 stm32_dmamux->dmarouter.route_free = stm32_dmamux_free;
283
284 platform_set_drvdata(pdev, stm32_dmamux);
285
286 if (!IS_ERR(stm32_dmamux->clk)) {
287 ret = clk_prepare_enable(stm32_dmamux->clk);
288 if (ret < 0) {
289 dev_err(&pdev->dev, "clk_prep_enable error: %d\n", ret);
290 return ret;
291 }
292 }
293
294 /* Reset the dmamux */
295 for (i = 0; i < stm32_dmamux->dma_requests; i++)
296 stm32_dmamux_write(stm32_dmamux->iomem, STM32_DMAMUX_CCR(i), 0);
297
298 if (!IS_ERR(stm32_dmamux->clk))
299 clk_disable(stm32_dmamux->clk);
300
301 return of_dma_router_register(node, stm32_dmamux_route_allocate,
302 &stm32_dmamux->dmarouter);
303}
304
305static const struct of_device_id stm32_dmamux_match[] = {
306 { .compatible = "st,stm32h7-dmamux" },
307 {},
308};
309
310static struct platform_driver stm32_dmamux_driver = {
311 .probe = stm32_dmamux_probe,
312 .driver = {
313 .name = "stm32-dmamux",
314 .of_match_table = stm32_dmamux_match,
315 },
316};
317
318static int __init stm32_dmamux_init(void)
319{
320 return platform_driver_register(&stm32_dmamux_driver);
321}
322arch_initcall(stm32_dmamux_init);
323
324MODULE_DESCRIPTION("DMA Router driver for STM32 DMA MUX");
325MODULE_AUTHOR("M'boumba Cedric Madianga <cedric.madianga@gmail.com>");
326MODULE_AUTHOR("Pierre-Yves Mordret <pierre-yves.mordret@st.com>");
327MODULE_LICENSE("GPL v2");