Loading...
Note: File does not exist in v4.17.
1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef _ASM_POWERPC_MMU_8XX_H_
3#define _ASM_POWERPC_MMU_8XX_H_
4/*
5 * PPC8xx support
6 */
7
8/* Control/status registers for the MPC8xx.
9 * A write operation to these registers causes serialized access.
10 * During software tablewalk, the registers used perform mask/shift-add
11 * operations when written/read. A TLB entry is created when the Mx_RPN
12 * is written, and the contents of several registers are used to
13 * create the entry.
14 */
15#define SPRN_MI_CTR 784 /* Instruction TLB control register */
16#define MI_GPM 0x80000000 /* Set domain manager mode */
17#define MI_PPM 0x40000000 /* Set subpage protection */
18#define MI_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */
19#define MI_RSV4I 0x08000000 /* Reserve 4 TLB entries */
20#define MI_PPCS 0x02000000 /* Use MI_RPN prob/priv state */
21#define MI_IDXMASK 0x00001f00 /* TLB index to be loaded */
22
23/* These are the Ks and Kp from the PowerPC books. For proper operation,
24 * Ks = 0, Kp = 1.
25 */
26#define SPRN_MI_AP 786
27#define MI_Ks 0x80000000 /* Should not be set */
28#define MI_Kp 0x40000000 /* Should always be set */
29
30/*
31 * All pages' PP data bits are set to either 001 or 011 by copying _PAGE_EXEC
32 * into bit 21 in the ITLBmiss handler (bit 21 is the middle bit), which means
33 * respectively NA for All or X for Supervisor and no access for User.
34 * Then we use the APG to say whether accesses are according to Page rules or
35 * "all Supervisor" rules (Access to all)
36 * Therefore, we define 2 APG groups. lsb is _PMD_USER
37 * 0 => Kernel => 01 (all accesses performed according to page definition)
38 * 1 => User => 00 (all accesses performed as supervisor iaw page definition)
39 * 2-15 => Not Used
40 */
41#define MI_APG_INIT 0x40000000
42
43/*
44 * 0 => Kernel => 01 (all accesses performed according to page definition)
45 * 1 => User => 10 (all accesses performed according to swaped page definition)
46 * 2-15 => Not Used
47 */
48#define MI_APG_KUEP 0x60000000
49
50/* The effective page number register. When read, contains the information
51 * about the last instruction TLB miss. When MI_RPN is written, bits in
52 * this register are used to create the TLB entry.
53 */
54#define SPRN_MI_EPN 787
55#define MI_EPNMASK 0xfffff000 /* Effective page number for entry */
56#define MI_EVALID 0x00000200 /* Entry is valid */
57#define MI_ASIDMASK 0x0000000f /* ASID match value */
58 /* Reset value is undefined */
59
60/* A "level 1" or "segment" or whatever you want to call it register.
61 * For the instruction TLB, it contains bits that get loaded into the
62 * TLB entry when the MI_RPN is written.
63 */
64#define SPRN_MI_TWC 789
65#define MI_APG 0x000001e0 /* Access protection group (0) */
66#define MI_GUARDED 0x00000010 /* Guarded storage */
67#define MI_PSMASK 0x0000000c /* Mask of page size bits */
68#define MI_PS8MEG 0x0000000c /* 8M page size */
69#define MI_PS512K 0x00000004 /* 512K page size */
70#define MI_PS4K_16K 0x00000000 /* 4K or 16K page size */
71#define MI_SVALID 0x00000001 /* Segment entry is valid */
72 /* Reset value is undefined */
73
74/* Real page number. Defined by the pte. Writing this register
75 * causes a TLB entry to be created for the instruction TLB, using
76 * additional information from the MI_EPN, and MI_TWC registers.
77 */
78#define SPRN_MI_RPN 790
79#define MI_SPS16K 0x00000008 /* Small page size (0 = 4k, 1 = 16k) */
80
81/* Define an RPN value for mapping kernel memory to large virtual
82 * pages for boot initialization. This has real page number of 0,
83 * large page size, shared page, cache enabled, and valid.
84 * Also mark all subpages valid and write access.
85 */
86#define MI_BOOTINIT 0x000001fd
87
88#define SPRN_MD_CTR 792 /* Data TLB control register */
89#define MD_GPM 0x80000000 /* Set domain manager mode */
90#define MD_PPM 0x40000000 /* Set subpage protection */
91#define MD_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */
92#define MD_WTDEF 0x10000000 /* Set writethrough when MMU dis */
93#define MD_RSV4I 0x08000000 /* Reserve 4 TLB entries */
94#define MD_TWAM 0x04000000 /* Use 4K page hardware assist */
95#define MD_PPCS 0x02000000 /* Use MI_RPN prob/priv state */
96#define MD_IDXMASK 0x00001f00 /* TLB index to be loaded */
97
98#define SPRN_M_CASID 793 /* Address space ID (context) to match */
99#define MC_ASIDMASK 0x0000000f /* Bits used for ASID value */
100
101
102/* These are the Ks and Kp from the PowerPC books. For proper operation,
103 * Ks = 0, Kp = 1.
104 */
105#define SPRN_MD_AP 794
106#define MD_Ks 0x80000000 /* Should not be set */
107#define MD_Kp 0x40000000 /* Should always be set */
108
109/*
110 * All pages' PP data bits are set to either 000 or 011 or 001, which means
111 * respectively RW for Supervisor and no access for User, or RO for
112 * Supervisor and no access for user and NA for ALL.
113 * Then we use the APG to say whether accesses are according to Page rules or
114 * "all Supervisor" rules (Access to all)
115 * Therefore, we define 2 APG groups. lsb is _PMD_USER
116 * 0 => Kernel => 01 (all accesses performed according to page definition)
117 * 1 => User => 00 (all accesses performed as supervisor iaw page definition)
118 * 2-15 => Not Used
119 */
120#define MD_APG_INIT 0x40000000
121
122/*
123 * 0 => No user => 01 (all accesses performed according to page definition)
124 * 1 => User => 10 (all accesses performed according to swaped page definition)
125 * 2-15 => Not Used
126 */
127#define MD_APG_KUAP 0x60000000
128
129/* The effective page number register. When read, contains the information
130 * about the last instruction TLB miss. When MD_RPN is written, bits in
131 * this register are used to create the TLB entry.
132 */
133#define SPRN_MD_EPN 795
134#define MD_EPNMASK 0xfffff000 /* Effective page number for entry */
135#define MD_EVALID 0x00000200 /* Entry is valid */
136#define MD_ASIDMASK 0x0000000f /* ASID match value */
137 /* Reset value is undefined */
138
139/* The pointer to the base address of the first level page table.
140 * During a software tablewalk, reading this register provides the address
141 * of the entry associated with MD_EPN.
142 */
143#define SPRN_M_TWB 796
144#define M_L1TB 0xfffff000 /* Level 1 table base address */
145#define M_L1INDX 0x00000ffc /* Level 1 index, when read */
146 /* Reset value is undefined */
147
148/* A "level 1" or "segment" or whatever you want to call it register.
149 * For the data TLB, it contains bits that get loaded into the TLB entry
150 * when the MD_RPN is written. It is also provides the hardware assist
151 * for finding the PTE address during software tablewalk.
152 */
153#define SPRN_MD_TWC 797
154#define MD_L2TB 0xfffff000 /* Level 2 table base address */
155#define MD_L2INDX 0xfffffe00 /* Level 2 index (*pte), when read */
156#define MD_APG 0x000001e0 /* Access protection group (0) */
157#define MD_GUARDED 0x00000010 /* Guarded storage */
158#define MD_PSMASK 0x0000000c /* Mask of page size bits */
159#define MD_PS8MEG 0x0000000c /* 8M page size */
160#define MD_PS512K 0x00000004 /* 512K page size */
161#define MD_PS4K_16K 0x00000000 /* 4K or 16K page size */
162#define MD_WT 0x00000002 /* Use writethrough page attribute */
163#define MD_SVALID 0x00000001 /* Segment entry is valid */
164 /* Reset value is undefined */
165
166
167/* Real page number. Defined by the pte. Writing this register
168 * causes a TLB entry to be created for the data TLB, using
169 * additional information from the MD_EPN, and MD_TWC registers.
170 */
171#define SPRN_MD_RPN 798
172#define MD_SPS16K 0x00000008 /* Small page size (0 = 4k, 1 = 16k) */
173
174/* This is a temporary storage register that could be used to save
175 * a processor working register during a tablewalk.
176 */
177#define SPRN_M_TW 799
178
179#if defined(CONFIG_PPC_4K_PAGES)
180#define mmu_virtual_psize MMU_PAGE_4K
181#elif defined(CONFIG_PPC_16K_PAGES)
182#define mmu_virtual_psize MMU_PAGE_16K
183#define PTE_FRAG_NR 4
184#define PTE_FRAG_SIZE_SHIFT 12
185#define PTE_FRAG_SIZE (1UL << 12)
186#else
187#error "Unsupported PAGE_SIZE"
188#endif
189
190#define mmu_linear_psize MMU_PAGE_8M
191
192#ifndef __ASSEMBLY__
193
194#include <linux/mmdebug.h>
195
196void mmu_pin_tlb(unsigned long top, bool readonly);
197
198typedef struct {
199 unsigned int id;
200 unsigned int active;
201 unsigned long vdso_base;
202 void *pte_frag;
203} mm_context_t;
204
205#define PHYS_IMMR_BASE (mfspr(SPRN_IMMR) & 0xfff80000)
206#define VIRT_IMMR_BASE (__fix_to_virt(FIX_IMMR_BASE))
207
208/* Page size definitions, common between 32 and 64-bit
209 *
210 * shift : is the "PAGE_SHIFT" value for that page size
211 * penc : is the pte encoding mask
212 *
213 */
214struct mmu_psize_def {
215 unsigned int shift; /* number of bits */
216 unsigned int enc; /* PTE encoding */
217 unsigned int ind; /* Corresponding indirect page size shift */
218 unsigned int flags;
219#define MMU_PAGE_SIZE_DIRECT 0x1 /* Supported as a direct size */
220#define MMU_PAGE_SIZE_INDIRECT 0x2 /* Supported as an indirect size */
221};
222
223extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
224
225static inline int shift_to_mmu_psize(unsigned int shift)
226{
227 int psize;
228
229 for (psize = 0; psize < MMU_PAGE_COUNT; ++psize)
230 if (mmu_psize_defs[psize].shift == shift)
231 return psize;
232 return -1;
233}
234
235static inline unsigned int mmu_psize_to_shift(unsigned int mmu_psize)
236{
237 if (mmu_psize_defs[mmu_psize].shift)
238 return mmu_psize_defs[mmu_psize].shift;
239 BUG();
240}
241
242/* patch sites */
243extern s32 patch__itlbmiss_exit_1, patch__dtlbmiss_exit_1;
244extern s32 patch__itlbmiss_perf, patch__dtlbmiss_perf;
245
246#endif /* !__ASSEMBLY__ */
247
248#endif /* _ASM_POWERPC_MMU_8XX_H_ */