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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * PIC32 deadman timer driver
4 *
5 * Purna Chandra Mandal <purna.mandal@microchip.com>
6 * Copyright (c) 2016, Microchip Technology Inc.
7 */
8#include <linux/clk.h>
9#include <linux/device.h>
10#include <linux/err.h>
11#include <linux/io.h>
12#include <linux/kernel.h>
13#include <linux/module.h>
14#include <linux/of.h>
15#include <linux/of_device.h>
16#include <linux/platform_device.h>
17#include <linux/pm.h>
18#include <linux/watchdog.h>
19
20#include <asm/mach-pic32/pic32.h>
21
22/* Deadman Timer Regs */
23#define DMTCON_REG 0x00
24#define DMTPRECLR_REG 0x10
25#define DMTCLR_REG 0x20
26#define DMTSTAT_REG 0x30
27#define DMTCNT_REG 0x40
28#define DMTPSCNT_REG 0x60
29#define DMTPSINTV_REG 0x70
30
31/* Deadman Timer Regs fields */
32#define DMT_ON BIT(15)
33#define DMT_STEP1_KEY BIT(6)
34#define DMT_STEP2_KEY BIT(3)
35#define DMTSTAT_WINOPN BIT(0)
36#define DMTSTAT_EVENT BIT(5)
37#define DMTSTAT_BAD2 BIT(6)
38#define DMTSTAT_BAD1 BIT(7)
39
40/* Reset Control Register fields for watchdog */
41#define RESETCON_DMT_TIMEOUT BIT(5)
42
43struct pic32_dmt {
44 void __iomem *regs;
45 struct clk *clk;
46};
47
48static inline void dmt_enable(struct pic32_dmt *dmt)
49{
50 writel(DMT_ON, PIC32_SET(dmt->regs + DMTCON_REG));
51}
52
53static inline void dmt_disable(struct pic32_dmt *dmt)
54{
55 writel(DMT_ON, PIC32_CLR(dmt->regs + DMTCON_REG));
56 /*
57 * Cannot touch registers in the CPU cycle following clearing the
58 * ON bit.
59 */
60 nop();
61}
62
63static inline int dmt_bad_status(struct pic32_dmt *dmt)
64{
65 u32 val;
66
67 val = readl(dmt->regs + DMTSTAT_REG);
68 val &= (DMTSTAT_BAD1 | DMTSTAT_BAD2 | DMTSTAT_EVENT);
69 if (val)
70 return -EAGAIN;
71
72 return 0;
73}
74
75static inline int dmt_keepalive(struct pic32_dmt *dmt)
76{
77 u32 v;
78 u32 timeout = 500;
79
80 /* set pre-clear key */
81 writel(DMT_STEP1_KEY << 8, dmt->regs + DMTPRECLR_REG);
82
83 /* wait for DMT window to open */
84 while (--timeout) {
85 v = readl(dmt->regs + DMTSTAT_REG) & DMTSTAT_WINOPN;
86 if (v == DMTSTAT_WINOPN)
87 break;
88 }
89
90 /* apply key2 */
91 writel(DMT_STEP2_KEY, dmt->regs + DMTCLR_REG);
92
93 /* check whether keys are latched correctly */
94 return dmt_bad_status(dmt);
95}
96
97static inline u32 pic32_dmt_get_timeout_secs(struct pic32_dmt *dmt)
98{
99 unsigned long rate;
100
101 rate = clk_get_rate(dmt->clk);
102 if (rate)
103 return readl(dmt->regs + DMTPSCNT_REG) / rate;
104
105 return 0;
106}
107
108static inline u32 pic32_dmt_bootstatus(struct pic32_dmt *dmt)
109{
110 u32 v;
111 void __iomem *rst_base;
112
113 rst_base = ioremap(PIC32_BASE_RESET, 0x10);
114 if (!rst_base)
115 return 0;
116
117 v = readl(rst_base);
118
119 writel(RESETCON_DMT_TIMEOUT, PIC32_CLR(rst_base));
120
121 iounmap(rst_base);
122 return v & RESETCON_DMT_TIMEOUT;
123}
124
125static int pic32_dmt_start(struct watchdog_device *wdd)
126{
127 struct pic32_dmt *dmt = watchdog_get_drvdata(wdd);
128
129 dmt_enable(dmt);
130 return dmt_keepalive(dmt);
131}
132
133static int pic32_dmt_stop(struct watchdog_device *wdd)
134{
135 struct pic32_dmt *dmt = watchdog_get_drvdata(wdd);
136
137 dmt_disable(dmt);
138
139 return 0;
140}
141
142static int pic32_dmt_ping(struct watchdog_device *wdd)
143{
144 struct pic32_dmt *dmt = watchdog_get_drvdata(wdd);
145
146 return dmt_keepalive(dmt);
147}
148
149static const struct watchdog_ops pic32_dmt_fops = {
150 .owner = THIS_MODULE,
151 .start = pic32_dmt_start,
152 .stop = pic32_dmt_stop,
153 .ping = pic32_dmt_ping,
154};
155
156static const struct watchdog_info pic32_dmt_ident = {
157 .options = WDIOF_KEEPALIVEPING |
158 WDIOF_MAGICCLOSE,
159 .identity = "PIC32 Deadman Timer",
160};
161
162static struct watchdog_device pic32_dmt_wdd = {
163 .info = &pic32_dmt_ident,
164 .ops = &pic32_dmt_fops,
165};
166
167static void pic32_clk_disable_unprepare(void *data)
168{
169 clk_disable_unprepare(data);
170}
171
172static int pic32_dmt_probe(struct platform_device *pdev)
173{
174 struct device *dev = &pdev->dev;
175 int ret;
176 struct pic32_dmt *dmt;
177 struct watchdog_device *wdd = &pic32_dmt_wdd;
178
179 dmt = devm_kzalloc(dev, sizeof(*dmt), GFP_KERNEL);
180 if (!dmt)
181 return -ENOMEM;
182
183 dmt->regs = devm_platform_ioremap_resource(pdev, 0);
184 if (IS_ERR(dmt->regs))
185 return PTR_ERR(dmt->regs);
186
187 dmt->clk = devm_clk_get(dev, NULL);
188 if (IS_ERR(dmt->clk)) {
189 dev_err(dev, "clk not found\n");
190 return PTR_ERR(dmt->clk);
191 }
192
193 ret = clk_prepare_enable(dmt->clk);
194 if (ret)
195 return ret;
196 ret = devm_add_action_or_reset(dev, pic32_clk_disable_unprepare,
197 dmt->clk);
198 if (ret)
199 return ret;
200
201 wdd->timeout = pic32_dmt_get_timeout_secs(dmt);
202 if (!wdd->timeout) {
203 dev_err(dev, "failed to read watchdog register timeout\n");
204 return -EINVAL;
205 }
206
207 dev_info(dev, "timeout %d\n", wdd->timeout);
208
209 wdd->bootstatus = pic32_dmt_bootstatus(dmt) ? WDIOF_CARDRESET : 0;
210
211 watchdog_set_nowayout(wdd, WATCHDOG_NOWAYOUT);
212 watchdog_set_drvdata(wdd, dmt);
213
214 ret = devm_watchdog_register_device(dev, wdd);
215 if (ret)
216 return ret;
217
218 platform_set_drvdata(pdev, wdd);
219 return 0;
220}
221
222static const struct of_device_id pic32_dmt_of_ids[] = {
223 { .compatible = "microchip,pic32mzda-dmt",},
224 { /* sentinel */ }
225};
226MODULE_DEVICE_TABLE(of, pic32_dmt_of_ids);
227
228static struct platform_driver pic32_dmt_driver = {
229 .probe = pic32_dmt_probe,
230 .driver = {
231 .name = "pic32-dmt",
232 .of_match_table = of_match_ptr(pic32_dmt_of_ids),
233 }
234};
235
236module_platform_driver(pic32_dmt_driver);
237
238MODULE_AUTHOR("Purna Chandra Mandal <purna.mandal@microchip.com>");
239MODULE_DESCRIPTION("Microchip PIC32 DMT Driver");
240MODULE_LICENSE("GPL");
1/*
2 * PIC32 deadman timer driver
3 *
4 * Purna Chandra Mandal <purna.mandal@microchip.com>
5 * Copyright (c) 2016, Microchip Technology Inc.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 */
12#include <linux/clk.h>
13#include <linux/device.h>
14#include <linux/err.h>
15#include <linux/io.h>
16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/of.h>
19#include <linux/of_device.h>
20#include <linux/platform_device.h>
21#include <linux/pm.h>
22#include <linux/watchdog.h>
23
24#include <asm/mach-pic32/pic32.h>
25
26/* Deadman Timer Regs */
27#define DMTCON_REG 0x00
28#define DMTPRECLR_REG 0x10
29#define DMTCLR_REG 0x20
30#define DMTSTAT_REG 0x30
31#define DMTCNT_REG 0x40
32#define DMTPSCNT_REG 0x60
33#define DMTPSINTV_REG 0x70
34
35/* Deadman Timer Regs fields */
36#define DMT_ON BIT(15)
37#define DMT_STEP1_KEY BIT(6)
38#define DMT_STEP2_KEY BIT(3)
39#define DMTSTAT_WINOPN BIT(0)
40#define DMTSTAT_EVENT BIT(5)
41#define DMTSTAT_BAD2 BIT(6)
42#define DMTSTAT_BAD1 BIT(7)
43
44/* Reset Control Register fields for watchdog */
45#define RESETCON_DMT_TIMEOUT BIT(5)
46
47struct pic32_dmt {
48 void __iomem *regs;
49 struct clk *clk;
50};
51
52static inline void dmt_enable(struct pic32_dmt *dmt)
53{
54 writel(DMT_ON, PIC32_SET(dmt->regs + DMTCON_REG));
55}
56
57static inline void dmt_disable(struct pic32_dmt *dmt)
58{
59 writel(DMT_ON, PIC32_CLR(dmt->regs + DMTCON_REG));
60 /*
61 * Cannot touch registers in the CPU cycle following clearing the
62 * ON bit.
63 */
64 nop();
65}
66
67static inline int dmt_bad_status(struct pic32_dmt *dmt)
68{
69 u32 val;
70
71 val = readl(dmt->regs + DMTSTAT_REG);
72 val &= (DMTSTAT_BAD1 | DMTSTAT_BAD2 | DMTSTAT_EVENT);
73 if (val)
74 return -EAGAIN;
75
76 return 0;
77}
78
79static inline int dmt_keepalive(struct pic32_dmt *dmt)
80{
81 u32 v;
82 u32 timeout = 500;
83
84 /* set pre-clear key */
85 writel(DMT_STEP1_KEY << 8, dmt->regs + DMTPRECLR_REG);
86
87 /* wait for DMT window to open */
88 while (--timeout) {
89 v = readl(dmt->regs + DMTSTAT_REG) & DMTSTAT_WINOPN;
90 if (v == DMTSTAT_WINOPN)
91 break;
92 }
93
94 /* apply key2 */
95 writel(DMT_STEP2_KEY, dmt->regs + DMTCLR_REG);
96
97 /* check whether keys are latched correctly */
98 return dmt_bad_status(dmt);
99}
100
101static inline u32 pic32_dmt_get_timeout_secs(struct pic32_dmt *dmt)
102{
103 unsigned long rate;
104
105 rate = clk_get_rate(dmt->clk);
106 if (rate)
107 return readl(dmt->regs + DMTPSCNT_REG) / rate;
108
109 return 0;
110}
111
112static inline u32 pic32_dmt_bootstatus(struct pic32_dmt *dmt)
113{
114 u32 v;
115 void __iomem *rst_base;
116
117 rst_base = ioremap(PIC32_BASE_RESET, 0x10);
118 if (!rst_base)
119 return 0;
120
121 v = readl(rst_base);
122
123 writel(RESETCON_DMT_TIMEOUT, PIC32_CLR(rst_base));
124
125 iounmap(rst_base);
126 return v & RESETCON_DMT_TIMEOUT;
127}
128
129static int pic32_dmt_start(struct watchdog_device *wdd)
130{
131 struct pic32_dmt *dmt = watchdog_get_drvdata(wdd);
132
133 dmt_enable(dmt);
134 return dmt_keepalive(dmt);
135}
136
137static int pic32_dmt_stop(struct watchdog_device *wdd)
138{
139 struct pic32_dmt *dmt = watchdog_get_drvdata(wdd);
140
141 dmt_disable(dmt);
142
143 return 0;
144}
145
146static int pic32_dmt_ping(struct watchdog_device *wdd)
147{
148 struct pic32_dmt *dmt = watchdog_get_drvdata(wdd);
149
150 return dmt_keepalive(dmt);
151}
152
153static const struct watchdog_ops pic32_dmt_fops = {
154 .owner = THIS_MODULE,
155 .start = pic32_dmt_start,
156 .stop = pic32_dmt_stop,
157 .ping = pic32_dmt_ping,
158};
159
160static const struct watchdog_info pic32_dmt_ident = {
161 .options = WDIOF_KEEPALIVEPING |
162 WDIOF_MAGICCLOSE,
163 .identity = "PIC32 Deadman Timer",
164};
165
166static struct watchdog_device pic32_dmt_wdd = {
167 .info = &pic32_dmt_ident,
168 .ops = &pic32_dmt_fops,
169};
170
171static int pic32_dmt_probe(struct platform_device *pdev)
172{
173 int ret;
174 struct pic32_dmt *dmt;
175 struct resource *mem;
176 struct watchdog_device *wdd = &pic32_dmt_wdd;
177
178 dmt = devm_kzalloc(&pdev->dev, sizeof(*dmt), GFP_KERNEL);
179 if (!dmt)
180 return -ENOMEM;
181
182 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
183 dmt->regs = devm_ioremap_resource(&pdev->dev, mem);
184 if (IS_ERR(dmt->regs))
185 return PTR_ERR(dmt->regs);
186
187 dmt->clk = devm_clk_get(&pdev->dev, NULL);
188 if (IS_ERR(dmt->clk)) {
189 dev_err(&pdev->dev, "clk not found\n");
190 return PTR_ERR(dmt->clk);
191 }
192
193 ret = clk_prepare_enable(dmt->clk);
194 if (ret)
195 return ret;
196
197 wdd->timeout = pic32_dmt_get_timeout_secs(dmt);
198 if (!wdd->timeout) {
199 dev_err(&pdev->dev,
200 "failed to read watchdog register timeout\n");
201 ret = -EINVAL;
202 goto out_disable_clk;
203 }
204
205 dev_info(&pdev->dev, "timeout %d\n", wdd->timeout);
206
207 wdd->bootstatus = pic32_dmt_bootstatus(dmt) ? WDIOF_CARDRESET : 0;
208
209 watchdog_set_nowayout(wdd, WATCHDOG_NOWAYOUT);
210 watchdog_set_drvdata(wdd, dmt);
211
212 ret = watchdog_register_device(wdd);
213 if (ret) {
214 dev_err(&pdev->dev, "watchdog register failed, err %d\n", ret);
215 goto out_disable_clk;
216 }
217
218 platform_set_drvdata(pdev, wdd);
219 return 0;
220
221out_disable_clk:
222 clk_disable_unprepare(dmt->clk);
223 return ret;
224}
225
226static int pic32_dmt_remove(struct platform_device *pdev)
227{
228 struct watchdog_device *wdd = platform_get_drvdata(pdev);
229 struct pic32_dmt *dmt = watchdog_get_drvdata(wdd);
230
231 watchdog_unregister_device(wdd);
232 clk_disable_unprepare(dmt->clk);
233
234 return 0;
235}
236
237static const struct of_device_id pic32_dmt_of_ids[] = {
238 { .compatible = "microchip,pic32mzda-dmt",},
239 { /* sentinel */ }
240};
241MODULE_DEVICE_TABLE(of, pic32_dmt_of_ids);
242
243static struct platform_driver pic32_dmt_driver = {
244 .probe = pic32_dmt_probe,
245 .remove = pic32_dmt_remove,
246 .driver = {
247 .name = "pic32-dmt",
248 .of_match_table = of_match_ptr(pic32_dmt_of_ids),
249 }
250};
251
252module_platform_driver(pic32_dmt_driver);
253
254MODULE_AUTHOR("Purna Chandra Mandal <purna.mandal@microchip.com>");
255MODULE_DESCRIPTION("Microchip PIC32 DMT Driver");
256MODULE_LICENSE("GPL");