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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * rtc-ds1307.c - RTC driver for some mostly-compatible I2C chips.
4 *
5 * Copyright (C) 2005 James Chapman (ds1337 core)
6 * Copyright (C) 2006 David Brownell
7 * Copyright (C) 2009 Matthias Fuchs (rx8025 support)
8 * Copyright (C) 2012 Bertrand Achard (nvram access fixes)
9 */
10
11#include <linux/acpi.h>
12#include <linux/bcd.h>
13#include <linux/i2c.h>
14#include <linux/init.h>
15#include <linux/module.h>
16#include <linux/of_device.h>
17#include <linux/rtc/ds1307.h>
18#include <linux/rtc.h>
19#include <linux/slab.h>
20#include <linux/string.h>
21#include <linux/hwmon.h>
22#include <linux/hwmon-sysfs.h>
23#include <linux/clk-provider.h>
24#include <linux/regmap.h>
25#include <linux/watchdog.h>
26
27/*
28 * We can't determine type by probing, but if we expect pre-Linux code
29 * to have set the chip up as a clock (turning on the oscillator and
30 * setting the date and time), Linux can ignore the non-clock features.
31 * That's a natural job for a factory or repair bench.
32 */
33enum ds_type {
34 ds_1307,
35 ds_1308,
36 ds_1337,
37 ds_1338,
38 ds_1339,
39 ds_1340,
40 ds_1341,
41 ds_1388,
42 ds_3231,
43 m41t0,
44 m41t00,
45 m41t11,
46 mcp794xx,
47 rx_8025,
48 rx_8130,
49 last_ds_type /* always last */
50 /* rs5c372 too? different address... */
51};
52
53/* RTC registers don't differ much, except for the century flag */
54#define DS1307_REG_SECS 0x00 /* 00-59 */
55# define DS1307_BIT_CH 0x80
56# define DS1340_BIT_nEOSC 0x80
57# define MCP794XX_BIT_ST 0x80
58#define DS1307_REG_MIN 0x01 /* 00-59 */
59# define M41T0_BIT_OF 0x80
60#define DS1307_REG_HOUR 0x02 /* 00-23, or 1-12{am,pm} */
61# define DS1307_BIT_12HR 0x40 /* in REG_HOUR */
62# define DS1307_BIT_PM 0x20 /* in REG_HOUR */
63# define DS1340_BIT_CENTURY_EN 0x80 /* in REG_HOUR */
64# define DS1340_BIT_CENTURY 0x40 /* in REG_HOUR */
65#define DS1307_REG_WDAY 0x03 /* 01-07 */
66# define MCP794XX_BIT_VBATEN 0x08
67#define DS1307_REG_MDAY 0x04 /* 01-31 */
68#define DS1307_REG_MONTH 0x05 /* 01-12 */
69# define DS1337_BIT_CENTURY 0x80 /* in REG_MONTH */
70#define DS1307_REG_YEAR 0x06 /* 00-99 */
71
72/*
73 * Other registers (control, status, alarms, trickle charge, NVRAM, etc)
74 * start at 7, and they differ a LOT. Only control and status matter for
75 * basic RTC date and time functionality; be careful using them.
76 */
77#define DS1307_REG_CONTROL 0x07 /* or ds1338 */
78# define DS1307_BIT_OUT 0x80
79# define DS1338_BIT_OSF 0x20
80# define DS1307_BIT_SQWE 0x10
81# define DS1307_BIT_RS1 0x02
82# define DS1307_BIT_RS0 0x01
83#define DS1337_REG_CONTROL 0x0e
84# define DS1337_BIT_nEOSC 0x80
85# define DS1339_BIT_BBSQI 0x20
86# define DS3231_BIT_BBSQW 0x40 /* same as BBSQI */
87# define DS1337_BIT_RS2 0x10
88# define DS1337_BIT_RS1 0x08
89# define DS1337_BIT_INTCN 0x04
90# define DS1337_BIT_A2IE 0x02
91# define DS1337_BIT_A1IE 0x01
92#define DS1340_REG_CONTROL 0x07
93# define DS1340_BIT_OUT 0x80
94# define DS1340_BIT_FT 0x40
95# define DS1340_BIT_CALIB_SIGN 0x20
96# define DS1340_M_CALIBRATION 0x1f
97#define DS1340_REG_FLAG 0x09
98# define DS1340_BIT_OSF 0x80
99#define DS1337_REG_STATUS 0x0f
100# define DS1337_BIT_OSF 0x80
101# define DS3231_BIT_EN32KHZ 0x08
102# define DS1337_BIT_A2I 0x02
103# define DS1337_BIT_A1I 0x01
104#define DS1339_REG_ALARM1_SECS 0x07
105
106#define DS13XX_TRICKLE_CHARGER_MAGIC 0xa0
107
108#define RX8025_REG_CTRL1 0x0e
109# define RX8025_BIT_2412 0x20
110#define RX8025_REG_CTRL2 0x0f
111# define RX8025_BIT_PON 0x10
112# define RX8025_BIT_VDET 0x40
113# define RX8025_BIT_XST 0x20
114
115#define RX8130_REG_ALARM_MIN 0x17
116#define RX8130_REG_ALARM_HOUR 0x18
117#define RX8130_REG_ALARM_WEEK_OR_DAY 0x19
118#define RX8130_REG_EXTENSION 0x1c
119#define RX8130_REG_EXTENSION_WADA BIT(3)
120#define RX8130_REG_FLAG 0x1d
121#define RX8130_REG_FLAG_VLF BIT(1)
122#define RX8130_REG_FLAG_AF BIT(3)
123#define RX8130_REG_CONTROL0 0x1e
124#define RX8130_REG_CONTROL0_AIE BIT(3)
125
126#define MCP794XX_REG_CONTROL 0x07
127# define MCP794XX_BIT_ALM0_EN 0x10
128# define MCP794XX_BIT_ALM1_EN 0x20
129#define MCP794XX_REG_ALARM0_BASE 0x0a
130#define MCP794XX_REG_ALARM0_CTRL 0x0d
131#define MCP794XX_REG_ALARM1_BASE 0x11
132#define MCP794XX_REG_ALARM1_CTRL 0x14
133# define MCP794XX_BIT_ALMX_IF BIT(3)
134# define MCP794XX_BIT_ALMX_C0 BIT(4)
135# define MCP794XX_BIT_ALMX_C1 BIT(5)
136# define MCP794XX_BIT_ALMX_C2 BIT(6)
137# define MCP794XX_BIT_ALMX_POL BIT(7)
138# define MCP794XX_MSK_ALMX_MATCH (MCP794XX_BIT_ALMX_C0 | \
139 MCP794XX_BIT_ALMX_C1 | \
140 MCP794XX_BIT_ALMX_C2)
141
142#define M41TXX_REG_CONTROL 0x07
143# define M41TXX_BIT_OUT BIT(7)
144# define M41TXX_BIT_FT BIT(6)
145# define M41TXX_BIT_CALIB_SIGN BIT(5)
146# define M41TXX_M_CALIBRATION GENMASK(4, 0)
147
148#define DS1388_REG_WDOG_HUN_SECS 0x08
149#define DS1388_REG_WDOG_SECS 0x09
150#define DS1388_REG_FLAG 0x0b
151# define DS1388_BIT_WF BIT(6)
152# define DS1388_BIT_OSF BIT(7)
153#define DS1388_REG_CONTROL 0x0c
154# define DS1388_BIT_RST BIT(0)
155# define DS1388_BIT_WDE BIT(1)
156
157/* negative offset step is -2.034ppm */
158#define M41TXX_NEG_OFFSET_STEP_PPB 2034
159/* positive offset step is +4.068ppm */
160#define M41TXX_POS_OFFSET_STEP_PPB 4068
161/* Min and max values supported with 'offset' interface by M41TXX */
162#define M41TXX_MIN_OFFSET ((-31) * M41TXX_NEG_OFFSET_STEP_PPB)
163#define M41TXX_MAX_OFFSET ((31) * M41TXX_POS_OFFSET_STEP_PPB)
164
165struct ds1307 {
166 enum ds_type type;
167 unsigned long flags;
168#define HAS_NVRAM 0 /* bit 0 == sysfs file active */
169#define HAS_ALARM 1 /* bit 1 == irq claimed */
170 struct device *dev;
171 struct regmap *regmap;
172 const char *name;
173 struct rtc_device *rtc;
174#ifdef CONFIG_COMMON_CLK
175 struct clk_hw clks[2];
176#endif
177};
178
179struct chip_desc {
180 unsigned alarm:1;
181 u16 nvram_offset;
182 u16 nvram_size;
183 u8 offset; /* register's offset */
184 u8 century_reg;
185 u8 century_enable_bit;
186 u8 century_bit;
187 u8 bbsqi_bit;
188 irq_handler_t irq_handler;
189 const struct rtc_class_ops *rtc_ops;
190 u16 trickle_charger_reg;
191 u8 (*do_trickle_setup)(struct ds1307 *, u32,
192 bool);
193};
194
195static const struct chip_desc chips[last_ds_type];
196
197static int ds1307_get_time(struct device *dev, struct rtc_time *t)
198{
199 struct ds1307 *ds1307 = dev_get_drvdata(dev);
200 int tmp, ret;
201 const struct chip_desc *chip = &chips[ds1307->type];
202 u8 regs[7];
203
204 if (ds1307->type == rx_8130) {
205 unsigned int regflag;
206 ret = regmap_read(ds1307->regmap, RX8130_REG_FLAG, ®flag);
207 if (ret) {
208 dev_err(dev, "%s error %d\n", "read", ret);
209 return ret;
210 }
211
212 if (regflag & RX8130_REG_FLAG_VLF) {
213 dev_warn_once(dev, "oscillator failed, set time!\n");
214 return -EINVAL;
215 }
216 }
217
218 /* read the RTC date and time registers all at once */
219 ret = regmap_bulk_read(ds1307->regmap, chip->offset, regs,
220 sizeof(regs));
221 if (ret) {
222 dev_err(dev, "%s error %d\n", "read", ret);
223 return ret;
224 }
225
226 dev_dbg(dev, "%s: %7ph\n", "read", regs);
227
228 /* if oscillator fail bit is set, no data can be trusted */
229 if (ds1307->type == m41t0 &&
230 regs[DS1307_REG_MIN] & M41T0_BIT_OF) {
231 dev_warn_once(dev, "oscillator failed, set time!\n");
232 return -EINVAL;
233 }
234
235 tmp = regs[DS1307_REG_SECS];
236 switch (ds1307->type) {
237 case ds_1307:
238 case m41t0:
239 case m41t00:
240 case m41t11:
241 if (tmp & DS1307_BIT_CH)
242 return -EINVAL;
243 break;
244 case ds_1308:
245 case ds_1338:
246 if (tmp & DS1307_BIT_CH)
247 return -EINVAL;
248
249 ret = regmap_read(ds1307->regmap, DS1307_REG_CONTROL, &tmp);
250 if (ret)
251 return ret;
252 if (tmp & DS1338_BIT_OSF)
253 return -EINVAL;
254 break;
255 case ds_1340:
256 if (tmp & DS1340_BIT_nEOSC)
257 return -EINVAL;
258
259 ret = regmap_read(ds1307->regmap, DS1340_REG_FLAG, &tmp);
260 if (ret)
261 return ret;
262 if (tmp & DS1340_BIT_OSF)
263 return -EINVAL;
264 break;
265 case ds_1388:
266 ret = regmap_read(ds1307->regmap, DS1388_REG_FLAG, &tmp);
267 if (ret)
268 return ret;
269 if (tmp & DS1388_BIT_OSF)
270 return -EINVAL;
271 break;
272 case mcp794xx:
273 if (!(tmp & MCP794XX_BIT_ST))
274 return -EINVAL;
275
276 break;
277 default:
278 break;
279 }
280
281 t->tm_sec = bcd2bin(regs[DS1307_REG_SECS] & 0x7f);
282 t->tm_min = bcd2bin(regs[DS1307_REG_MIN] & 0x7f);
283 tmp = regs[DS1307_REG_HOUR] & 0x3f;
284 t->tm_hour = bcd2bin(tmp);
285 t->tm_wday = bcd2bin(regs[DS1307_REG_WDAY] & 0x07) - 1;
286 t->tm_mday = bcd2bin(regs[DS1307_REG_MDAY] & 0x3f);
287 tmp = regs[DS1307_REG_MONTH] & 0x1f;
288 t->tm_mon = bcd2bin(tmp) - 1;
289 t->tm_year = bcd2bin(regs[DS1307_REG_YEAR]) + 100;
290
291 if (regs[chip->century_reg] & chip->century_bit &&
292 IS_ENABLED(CONFIG_RTC_DRV_DS1307_CENTURY))
293 t->tm_year += 100;
294
295 dev_dbg(dev, "%s secs=%d, mins=%d, "
296 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
297 "read", t->tm_sec, t->tm_min,
298 t->tm_hour, t->tm_mday,
299 t->tm_mon, t->tm_year, t->tm_wday);
300
301 return 0;
302}
303
304static int ds1307_set_time(struct device *dev, struct rtc_time *t)
305{
306 struct ds1307 *ds1307 = dev_get_drvdata(dev);
307 const struct chip_desc *chip = &chips[ds1307->type];
308 int result;
309 int tmp;
310 u8 regs[7];
311
312 dev_dbg(dev, "%s secs=%d, mins=%d, "
313 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
314 "write", t->tm_sec, t->tm_min,
315 t->tm_hour, t->tm_mday,
316 t->tm_mon, t->tm_year, t->tm_wday);
317
318 if (t->tm_year < 100)
319 return -EINVAL;
320
321#ifdef CONFIG_RTC_DRV_DS1307_CENTURY
322 if (t->tm_year > (chip->century_bit ? 299 : 199))
323 return -EINVAL;
324#else
325 if (t->tm_year > 199)
326 return -EINVAL;
327#endif
328
329 regs[DS1307_REG_SECS] = bin2bcd(t->tm_sec);
330 regs[DS1307_REG_MIN] = bin2bcd(t->tm_min);
331 regs[DS1307_REG_HOUR] = bin2bcd(t->tm_hour);
332 regs[DS1307_REG_WDAY] = bin2bcd(t->tm_wday + 1);
333 regs[DS1307_REG_MDAY] = bin2bcd(t->tm_mday);
334 regs[DS1307_REG_MONTH] = bin2bcd(t->tm_mon + 1);
335
336 /* assume 20YY not 19YY */
337 tmp = t->tm_year - 100;
338 regs[DS1307_REG_YEAR] = bin2bcd(tmp);
339
340 if (chip->century_enable_bit)
341 regs[chip->century_reg] |= chip->century_enable_bit;
342 if (t->tm_year > 199 && chip->century_bit)
343 regs[chip->century_reg] |= chip->century_bit;
344
345 switch (ds1307->type) {
346 case ds_1308:
347 case ds_1338:
348 regmap_update_bits(ds1307->regmap, DS1307_REG_CONTROL,
349 DS1338_BIT_OSF, 0);
350 break;
351 case ds_1340:
352 regmap_update_bits(ds1307->regmap, DS1340_REG_FLAG,
353 DS1340_BIT_OSF, 0);
354 break;
355 case mcp794xx:
356 /*
357 * these bits were cleared when preparing the date/time
358 * values and need to be set again before writing the
359 * regsfer out to the device.
360 */
361 regs[DS1307_REG_SECS] |= MCP794XX_BIT_ST;
362 regs[DS1307_REG_WDAY] |= MCP794XX_BIT_VBATEN;
363 break;
364 default:
365 break;
366 }
367
368 dev_dbg(dev, "%s: %7ph\n", "write", regs);
369
370 result = regmap_bulk_write(ds1307->regmap, chip->offset, regs,
371 sizeof(regs));
372 if (result) {
373 dev_err(dev, "%s error %d\n", "write", result);
374 return result;
375 }
376
377 if (ds1307->type == rx_8130) {
378 /* clear Voltage Loss Flag as data is available now */
379 result = regmap_write(ds1307->regmap, RX8130_REG_FLAG,
380 ~(u8)RX8130_REG_FLAG_VLF);
381 if (result) {
382 dev_err(dev, "%s error %d\n", "write", result);
383 return result;
384 }
385 }
386
387 return 0;
388}
389
390static int ds1337_read_alarm(struct device *dev, struct rtc_wkalrm *t)
391{
392 struct ds1307 *ds1307 = dev_get_drvdata(dev);
393 int ret;
394 u8 regs[9];
395
396 if (!test_bit(HAS_ALARM, &ds1307->flags))
397 return -EINVAL;
398
399 /* read all ALARM1, ALARM2, and status registers at once */
400 ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS,
401 regs, sizeof(regs));
402 if (ret) {
403 dev_err(dev, "%s error %d\n", "alarm read", ret);
404 return ret;
405 }
406
407 dev_dbg(dev, "%s: %4ph, %3ph, %2ph\n", "alarm read",
408 ®s[0], ®s[4], ®s[7]);
409
410 /*
411 * report alarm time (ALARM1); assume 24 hour and day-of-month modes,
412 * and that all four fields are checked matches
413 */
414 t->time.tm_sec = bcd2bin(regs[0] & 0x7f);
415 t->time.tm_min = bcd2bin(regs[1] & 0x7f);
416 t->time.tm_hour = bcd2bin(regs[2] & 0x3f);
417 t->time.tm_mday = bcd2bin(regs[3] & 0x3f);
418
419 /* ... and status */
420 t->enabled = !!(regs[7] & DS1337_BIT_A1IE);
421 t->pending = !!(regs[8] & DS1337_BIT_A1I);
422
423 dev_dbg(dev, "%s secs=%d, mins=%d, "
424 "hours=%d, mday=%d, enabled=%d, pending=%d\n",
425 "alarm read", t->time.tm_sec, t->time.tm_min,
426 t->time.tm_hour, t->time.tm_mday,
427 t->enabled, t->pending);
428
429 return 0;
430}
431
432static int ds1337_set_alarm(struct device *dev, struct rtc_wkalrm *t)
433{
434 struct ds1307 *ds1307 = dev_get_drvdata(dev);
435 unsigned char regs[9];
436 u8 control, status;
437 int ret;
438
439 if (!test_bit(HAS_ALARM, &ds1307->flags))
440 return -EINVAL;
441
442 dev_dbg(dev, "%s secs=%d, mins=%d, "
443 "hours=%d, mday=%d, enabled=%d, pending=%d\n",
444 "alarm set", t->time.tm_sec, t->time.tm_min,
445 t->time.tm_hour, t->time.tm_mday,
446 t->enabled, t->pending);
447
448 /* read current status of both alarms and the chip */
449 ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS, regs,
450 sizeof(regs));
451 if (ret) {
452 dev_err(dev, "%s error %d\n", "alarm write", ret);
453 return ret;
454 }
455 control = regs[7];
456 status = regs[8];
457
458 dev_dbg(dev, "%s: %4ph, %3ph, %02x %02x\n", "alarm set (old status)",
459 ®s[0], ®s[4], control, status);
460
461 /* set ALARM1, using 24 hour and day-of-month modes */
462 regs[0] = bin2bcd(t->time.tm_sec);
463 regs[1] = bin2bcd(t->time.tm_min);
464 regs[2] = bin2bcd(t->time.tm_hour);
465 regs[3] = bin2bcd(t->time.tm_mday);
466
467 /* set ALARM2 to non-garbage */
468 regs[4] = 0;
469 regs[5] = 0;
470 regs[6] = 0;
471
472 /* disable alarms */
473 regs[7] = control & ~(DS1337_BIT_A1IE | DS1337_BIT_A2IE);
474 regs[8] = status & ~(DS1337_BIT_A1I | DS1337_BIT_A2I);
475
476 ret = regmap_bulk_write(ds1307->regmap, DS1339_REG_ALARM1_SECS, regs,
477 sizeof(regs));
478 if (ret) {
479 dev_err(dev, "can't set alarm time\n");
480 return ret;
481 }
482
483 /* optionally enable ALARM1 */
484 if (t->enabled) {
485 dev_dbg(dev, "alarm IRQ armed\n");
486 regs[7] |= DS1337_BIT_A1IE; /* only ALARM1 is used */
487 regmap_write(ds1307->regmap, DS1337_REG_CONTROL, regs[7]);
488 }
489
490 return 0;
491}
492
493static int ds1307_alarm_irq_enable(struct device *dev, unsigned int enabled)
494{
495 struct ds1307 *ds1307 = dev_get_drvdata(dev);
496
497 if (!test_bit(HAS_ALARM, &ds1307->flags))
498 return -ENOTTY;
499
500 return regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
501 DS1337_BIT_A1IE,
502 enabled ? DS1337_BIT_A1IE : 0);
503}
504
505static u8 do_trickle_setup_ds1339(struct ds1307 *ds1307, u32 ohms, bool diode)
506{
507 u8 setup = (diode) ? DS1307_TRICKLE_CHARGER_DIODE :
508 DS1307_TRICKLE_CHARGER_NO_DIODE;
509
510 switch (ohms) {
511 case 250:
512 setup |= DS1307_TRICKLE_CHARGER_250_OHM;
513 break;
514 case 2000:
515 setup |= DS1307_TRICKLE_CHARGER_2K_OHM;
516 break;
517 case 4000:
518 setup |= DS1307_TRICKLE_CHARGER_4K_OHM;
519 break;
520 default:
521 dev_warn(ds1307->dev,
522 "Unsupported ohm value %u in dt\n", ohms);
523 return 0;
524 }
525 return setup;
526}
527
528static irqreturn_t rx8130_irq(int irq, void *dev_id)
529{
530 struct ds1307 *ds1307 = dev_id;
531 struct mutex *lock = &ds1307->rtc->ops_lock;
532 u8 ctl[3];
533 int ret;
534
535 mutex_lock(lock);
536
537 /* Read control registers. */
538 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
539 sizeof(ctl));
540 if (ret < 0)
541 goto out;
542 if (!(ctl[1] & RX8130_REG_FLAG_AF))
543 goto out;
544 ctl[1] &= ~RX8130_REG_FLAG_AF;
545 ctl[2] &= ~RX8130_REG_CONTROL0_AIE;
546
547 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
548 sizeof(ctl));
549 if (ret < 0)
550 goto out;
551
552 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
553
554out:
555 mutex_unlock(lock);
556
557 return IRQ_HANDLED;
558}
559
560static int rx8130_read_alarm(struct device *dev, struct rtc_wkalrm *t)
561{
562 struct ds1307 *ds1307 = dev_get_drvdata(dev);
563 u8 ald[3], ctl[3];
564 int ret;
565
566 if (!test_bit(HAS_ALARM, &ds1307->flags))
567 return -EINVAL;
568
569 /* Read alarm registers. */
570 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_ALARM_MIN, ald,
571 sizeof(ald));
572 if (ret < 0)
573 return ret;
574
575 /* Read control registers. */
576 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
577 sizeof(ctl));
578 if (ret < 0)
579 return ret;
580
581 t->enabled = !!(ctl[2] & RX8130_REG_CONTROL0_AIE);
582 t->pending = !!(ctl[1] & RX8130_REG_FLAG_AF);
583
584 /* Report alarm 0 time assuming 24-hour and day-of-month modes. */
585 t->time.tm_sec = -1;
586 t->time.tm_min = bcd2bin(ald[0] & 0x7f);
587 t->time.tm_hour = bcd2bin(ald[1] & 0x7f);
588 t->time.tm_wday = -1;
589 t->time.tm_mday = bcd2bin(ald[2] & 0x7f);
590 t->time.tm_mon = -1;
591 t->time.tm_year = -1;
592 t->time.tm_yday = -1;
593 t->time.tm_isdst = -1;
594
595 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d enabled=%d\n",
596 __func__, t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
597 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled);
598
599 return 0;
600}
601
602static int rx8130_set_alarm(struct device *dev, struct rtc_wkalrm *t)
603{
604 struct ds1307 *ds1307 = dev_get_drvdata(dev);
605 u8 ald[3], ctl[3];
606 int ret;
607
608 if (!test_bit(HAS_ALARM, &ds1307->flags))
609 return -EINVAL;
610
611 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
612 "enabled=%d pending=%d\n", __func__,
613 t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
614 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon,
615 t->enabled, t->pending);
616
617 /* Read control registers. */
618 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
619 sizeof(ctl));
620 if (ret < 0)
621 return ret;
622
623 ctl[0] &= RX8130_REG_EXTENSION_WADA;
624 ctl[1] &= ~RX8130_REG_FLAG_AF;
625 ctl[2] &= ~RX8130_REG_CONTROL0_AIE;
626
627 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
628 sizeof(ctl));
629 if (ret < 0)
630 return ret;
631
632 /* Hardware alarm precision is 1 minute! */
633 ald[0] = bin2bcd(t->time.tm_min);
634 ald[1] = bin2bcd(t->time.tm_hour);
635 ald[2] = bin2bcd(t->time.tm_mday);
636
637 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_ALARM_MIN, ald,
638 sizeof(ald));
639 if (ret < 0)
640 return ret;
641
642 if (!t->enabled)
643 return 0;
644
645 ctl[2] |= RX8130_REG_CONTROL0_AIE;
646
647 return regmap_write(ds1307->regmap, RX8130_REG_CONTROL0, ctl[2]);
648}
649
650static int rx8130_alarm_irq_enable(struct device *dev, unsigned int enabled)
651{
652 struct ds1307 *ds1307 = dev_get_drvdata(dev);
653 int ret, reg;
654
655 if (!test_bit(HAS_ALARM, &ds1307->flags))
656 return -EINVAL;
657
658 ret = regmap_read(ds1307->regmap, RX8130_REG_CONTROL0, ®);
659 if (ret < 0)
660 return ret;
661
662 if (enabled)
663 reg |= RX8130_REG_CONTROL0_AIE;
664 else
665 reg &= ~RX8130_REG_CONTROL0_AIE;
666
667 return regmap_write(ds1307->regmap, RX8130_REG_CONTROL0, reg);
668}
669
670static irqreturn_t mcp794xx_irq(int irq, void *dev_id)
671{
672 struct ds1307 *ds1307 = dev_id;
673 struct mutex *lock = &ds1307->rtc->ops_lock;
674 int reg, ret;
675
676 mutex_lock(lock);
677
678 /* Check and clear alarm 0 interrupt flag. */
679 ret = regmap_read(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, ®);
680 if (ret)
681 goto out;
682 if (!(reg & MCP794XX_BIT_ALMX_IF))
683 goto out;
684 reg &= ~MCP794XX_BIT_ALMX_IF;
685 ret = regmap_write(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, reg);
686 if (ret)
687 goto out;
688
689 /* Disable alarm 0. */
690 ret = regmap_update_bits(ds1307->regmap, MCP794XX_REG_CONTROL,
691 MCP794XX_BIT_ALM0_EN, 0);
692 if (ret)
693 goto out;
694
695 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
696
697out:
698 mutex_unlock(lock);
699
700 return IRQ_HANDLED;
701}
702
703static int mcp794xx_read_alarm(struct device *dev, struct rtc_wkalrm *t)
704{
705 struct ds1307 *ds1307 = dev_get_drvdata(dev);
706 u8 regs[10];
707 int ret;
708
709 if (!test_bit(HAS_ALARM, &ds1307->flags))
710 return -EINVAL;
711
712 /* Read control and alarm 0 registers. */
713 ret = regmap_bulk_read(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
714 sizeof(regs));
715 if (ret)
716 return ret;
717
718 t->enabled = !!(regs[0] & MCP794XX_BIT_ALM0_EN);
719
720 /* Report alarm 0 time assuming 24-hour and day-of-month modes. */
721 t->time.tm_sec = bcd2bin(regs[3] & 0x7f);
722 t->time.tm_min = bcd2bin(regs[4] & 0x7f);
723 t->time.tm_hour = bcd2bin(regs[5] & 0x3f);
724 t->time.tm_wday = bcd2bin(regs[6] & 0x7) - 1;
725 t->time.tm_mday = bcd2bin(regs[7] & 0x3f);
726 t->time.tm_mon = bcd2bin(regs[8] & 0x1f) - 1;
727 t->time.tm_year = -1;
728 t->time.tm_yday = -1;
729 t->time.tm_isdst = -1;
730
731 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
732 "enabled=%d polarity=%d irq=%d match=%lu\n", __func__,
733 t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
734 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled,
735 !!(regs[6] & MCP794XX_BIT_ALMX_POL),
736 !!(regs[6] & MCP794XX_BIT_ALMX_IF),
737 (regs[6] & MCP794XX_MSK_ALMX_MATCH) >> 4);
738
739 return 0;
740}
741
742/*
743 * We may have a random RTC weekday, therefore calculate alarm weekday based
744 * on current weekday we read from the RTC timekeeping regs
745 */
746static int mcp794xx_alm_weekday(struct device *dev, struct rtc_time *tm_alarm)
747{
748 struct rtc_time tm_now;
749 int days_now, days_alarm, ret;
750
751 ret = ds1307_get_time(dev, &tm_now);
752 if (ret)
753 return ret;
754
755 days_now = div_s64(rtc_tm_to_time64(&tm_now), 24 * 60 * 60);
756 days_alarm = div_s64(rtc_tm_to_time64(tm_alarm), 24 * 60 * 60);
757
758 return (tm_now.tm_wday + days_alarm - days_now) % 7 + 1;
759}
760
761static int mcp794xx_set_alarm(struct device *dev, struct rtc_wkalrm *t)
762{
763 struct ds1307 *ds1307 = dev_get_drvdata(dev);
764 unsigned char regs[10];
765 int wday, ret;
766
767 if (!test_bit(HAS_ALARM, &ds1307->flags))
768 return -EINVAL;
769
770 wday = mcp794xx_alm_weekday(dev, &t->time);
771 if (wday < 0)
772 return wday;
773
774 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
775 "enabled=%d pending=%d\n", __func__,
776 t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
777 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon,
778 t->enabled, t->pending);
779
780 /* Read control and alarm 0 registers. */
781 ret = regmap_bulk_read(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
782 sizeof(regs));
783 if (ret)
784 return ret;
785
786 /* Set alarm 0, using 24-hour and day-of-month modes. */
787 regs[3] = bin2bcd(t->time.tm_sec);
788 regs[4] = bin2bcd(t->time.tm_min);
789 regs[5] = bin2bcd(t->time.tm_hour);
790 regs[6] = wday;
791 regs[7] = bin2bcd(t->time.tm_mday);
792 regs[8] = bin2bcd(t->time.tm_mon + 1);
793
794 /* Clear the alarm 0 interrupt flag. */
795 regs[6] &= ~MCP794XX_BIT_ALMX_IF;
796 /* Set alarm match: second, minute, hour, day, date, month. */
797 regs[6] |= MCP794XX_MSK_ALMX_MATCH;
798 /* Disable interrupt. We will not enable until completely programmed */
799 regs[0] &= ~MCP794XX_BIT_ALM0_EN;
800
801 ret = regmap_bulk_write(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
802 sizeof(regs));
803 if (ret)
804 return ret;
805
806 if (!t->enabled)
807 return 0;
808 regs[0] |= MCP794XX_BIT_ALM0_EN;
809 return regmap_write(ds1307->regmap, MCP794XX_REG_CONTROL, regs[0]);
810}
811
812static int mcp794xx_alarm_irq_enable(struct device *dev, unsigned int enabled)
813{
814 struct ds1307 *ds1307 = dev_get_drvdata(dev);
815
816 if (!test_bit(HAS_ALARM, &ds1307->flags))
817 return -EINVAL;
818
819 return regmap_update_bits(ds1307->regmap, MCP794XX_REG_CONTROL,
820 MCP794XX_BIT_ALM0_EN,
821 enabled ? MCP794XX_BIT_ALM0_EN : 0);
822}
823
824static int m41txx_rtc_read_offset(struct device *dev, long *offset)
825{
826 struct ds1307 *ds1307 = dev_get_drvdata(dev);
827 unsigned int ctrl_reg;
828 u8 val;
829
830 regmap_read(ds1307->regmap, M41TXX_REG_CONTROL, &ctrl_reg);
831
832 val = ctrl_reg & M41TXX_M_CALIBRATION;
833
834 /* check if positive */
835 if (ctrl_reg & M41TXX_BIT_CALIB_SIGN)
836 *offset = (val * M41TXX_POS_OFFSET_STEP_PPB);
837 else
838 *offset = -(val * M41TXX_NEG_OFFSET_STEP_PPB);
839
840 return 0;
841}
842
843static int m41txx_rtc_set_offset(struct device *dev, long offset)
844{
845 struct ds1307 *ds1307 = dev_get_drvdata(dev);
846 unsigned int ctrl_reg;
847
848 if ((offset < M41TXX_MIN_OFFSET) || (offset > M41TXX_MAX_OFFSET))
849 return -ERANGE;
850
851 if (offset >= 0) {
852 ctrl_reg = DIV_ROUND_CLOSEST(offset,
853 M41TXX_POS_OFFSET_STEP_PPB);
854 ctrl_reg |= M41TXX_BIT_CALIB_SIGN;
855 } else {
856 ctrl_reg = DIV_ROUND_CLOSEST(abs(offset),
857 M41TXX_NEG_OFFSET_STEP_PPB);
858 }
859
860 return regmap_update_bits(ds1307->regmap, M41TXX_REG_CONTROL,
861 M41TXX_M_CALIBRATION | M41TXX_BIT_CALIB_SIGN,
862 ctrl_reg);
863}
864
865#ifdef CONFIG_WATCHDOG_CORE
866static int ds1388_wdt_start(struct watchdog_device *wdt_dev)
867{
868 struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev);
869 u8 regs[2];
870 int ret;
871
872 ret = regmap_update_bits(ds1307->regmap, DS1388_REG_FLAG,
873 DS1388_BIT_WF, 0);
874 if (ret)
875 return ret;
876
877 ret = regmap_update_bits(ds1307->regmap, DS1388_REG_CONTROL,
878 DS1388_BIT_WDE | DS1388_BIT_RST, 0);
879 if (ret)
880 return ret;
881
882 /*
883 * watchdog timeouts are measured in seconds. So ignore hundredths of
884 * seconds field.
885 */
886 regs[0] = 0;
887 regs[1] = bin2bcd(wdt_dev->timeout);
888
889 ret = regmap_bulk_write(ds1307->regmap, DS1388_REG_WDOG_HUN_SECS, regs,
890 sizeof(regs));
891 if (ret)
892 return ret;
893
894 return regmap_update_bits(ds1307->regmap, DS1388_REG_CONTROL,
895 DS1388_BIT_WDE | DS1388_BIT_RST,
896 DS1388_BIT_WDE | DS1388_BIT_RST);
897}
898
899static int ds1388_wdt_stop(struct watchdog_device *wdt_dev)
900{
901 struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev);
902
903 return regmap_update_bits(ds1307->regmap, DS1388_REG_CONTROL,
904 DS1388_BIT_WDE | DS1388_BIT_RST, 0);
905}
906
907static int ds1388_wdt_ping(struct watchdog_device *wdt_dev)
908{
909 struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev);
910 u8 regs[2];
911
912 return regmap_bulk_read(ds1307->regmap, DS1388_REG_WDOG_HUN_SECS, regs,
913 sizeof(regs));
914}
915
916static int ds1388_wdt_set_timeout(struct watchdog_device *wdt_dev,
917 unsigned int val)
918{
919 struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev);
920 u8 regs[2];
921
922 wdt_dev->timeout = val;
923 regs[0] = 0;
924 regs[1] = bin2bcd(wdt_dev->timeout);
925
926 return regmap_bulk_write(ds1307->regmap, DS1388_REG_WDOG_HUN_SECS, regs,
927 sizeof(regs));
928}
929#endif
930
931static const struct rtc_class_ops rx8130_rtc_ops = {
932 .read_time = ds1307_get_time,
933 .set_time = ds1307_set_time,
934 .read_alarm = rx8130_read_alarm,
935 .set_alarm = rx8130_set_alarm,
936 .alarm_irq_enable = rx8130_alarm_irq_enable,
937};
938
939static const struct rtc_class_ops mcp794xx_rtc_ops = {
940 .read_time = ds1307_get_time,
941 .set_time = ds1307_set_time,
942 .read_alarm = mcp794xx_read_alarm,
943 .set_alarm = mcp794xx_set_alarm,
944 .alarm_irq_enable = mcp794xx_alarm_irq_enable,
945};
946
947static const struct rtc_class_ops m41txx_rtc_ops = {
948 .read_time = ds1307_get_time,
949 .set_time = ds1307_set_time,
950 .read_alarm = ds1337_read_alarm,
951 .set_alarm = ds1337_set_alarm,
952 .alarm_irq_enable = ds1307_alarm_irq_enable,
953 .read_offset = m41txx_rtc_read_offset,
954 .set_offset = m41txx_rtc_set_offset,
955};
956
957static const struct chip_desc chips[last_ds_type] = {
958 [ds_1307] = {
959 .nvram_offset = 8,
960 .nvram_size = 56,
961 },
962 [ds_1308] = {
963 .nvram_offset = 8,
964 .nvram_size = 56,
965 },
966 [ds_1337] = {
967 .alarm = 1,
968 .century_reg = DS1307_REG_MONTH,
969 .century_bit = DS1337_BIT_CENTURY,
970 },
971 [ds_1338] = {
972 .nvram_offset = 8,
973 .nvram_size = 56,
974 },
975 [ds_1339] = {
976 .alarm = 1,
977 .century_reg = DS1307_REG_MONTH,
978 .century_bit = DS1337_BIT_CENTURY,
979 .bbsqi_bit = DS1339_BIT_BBSQI,
980 .trickle_charger_reg = 0x10,
981 .do_trickle_setup = &do_trickle_setup_ds1339,
982 },
983 [ds_1340] = {
984 .century_reg = DS1307_REG_HOUR,
985 .century_enable_bit = DS1340_BIT_CENTURY_EN,
986 .century_bit = DS1340_BIT_CENTURY,
987 .do_trickle_setup = &do_trickle_setup_ds1339,
988 .trickle_charger_reg = 0x08,
989 },
990 [ds_1341] = {
991 .century_reg = DS1307_REG_MONTH,
992 .century_bit = DS1337_BIT_CENTURY,
993 },
994 [ds_1388] = {
995 .offset = 1,
996 .trickle_charger_reg = 0x0a,
997 },
998 [ds_3231] = {
999 .alarm = 1,
1000 .century_reg = DS1307_REG_MONTH,
1001 .century_bit = DS1337_BIT_CENTURY,
1002 .bbsqi_bit = DS3231_BIT_BBSQW,
1003 },
1004 [rx_8130] = {
1005 .alarm = 1,
1006 /* this is battery backed SRAM */
1007 .nvram_offset = 0x20,
1008 .nvram_size = 4, /* 32bit (4 word x 8 bit) */
1009 .offset = 0x10,
1010 .irq_handler = rx8130_irq,
1011 .rtc_ops = &rx8130_rtc_ops,
1012 },
1013 [m41t0] = {
1014 .rtc_ops = &m41txx_rtc_ops,
1015 },
1016 [m41t00] = {
1017 .rtc_ops = &m41txx_rtc_ops,
1018 },
1019 [m41t11] = {
1020 /* this is battery backed SRAM */
1021 .nvram_offset = 8,
1022 .nvram_size = 56,
1023 .rtc_ops = &m41txx_rtc_ops,
1024 },
1025 [mcp794xx] = {
1026 .alarm = 1,
1027 /* this is battery backed SRAM */
1028 .nvram_offset = 0x20,
1029 .nvram_size = 0x40,
1030 .irq_handler = mcp794xx_irq,
1031 .rtc_ops = &mcp794xx_rtc_ops,
1032 },
1033};
1034
1035static const struct i2c_device_id ds1307_id[] = {
1036 { "ds1307", ds_1307 },
1037 { "ds1308", ds_1308 },
1038 { "ds1337", ds_1337 },
1039 { "ds1338", ds_1338 },
1040 { "ds1339", ds_1339 },
1041 { "ds1388", ds_1388 },
1042 { "ds1340", ds_1340 },
1043 { "ds1341", ds_1341 },
1044 { "ds3231", ds_3231 },
1045 { "m41t0", m41t0 },
1046 { "m41t00", m41t00 },
1047 { "m41t11", m41t11 },
1048 { "mcp7940x", mcp794xx },
1049 { "mcp7941x", mcp794xx },
1050 { "pt7c4338", ds_1307 },
1051 { "rx8025", rx_8025 },
1052 { "isl12057", ds_1337 },
1053 { "rx8130", rx_8130 },
1054 { }
1055};
1056MODULE_DEVICE_TABLE(i2c, ds1307_id);
1057
1058#ifdef CONFIG_OF
1059static const struct of_device_id ds1307_of_match[] = {
1060 {
1061 .compatible = "dallas,ds1307",
1062 .data = (void *)ds_1307
1063 },
1064 {
1065 .compatible = "dallas,ds1308",
1066 .data = (void *)ds_1308
1067 },
1068 {
1069 .compatible = "dallas,ds1337",
1070 .data = (void *)ds_1337
1071 },
1072 {
1073 .compatible = "dallas,ds1338",
1074 .data = (void *)ds_1338
1075 },
1076 {
1077 .compatible = "dallas,ds1339",
1078 .data = (void *)ds_1339
1079 },
1080 {
1081 .compatible = "dallas,ds1388",
1082 .data = (void *)ds_1388
1083 },
1084 {
1085 .compatible = "dallas,ds1340",
1086 .data = (void *)ds_1340
1087 },
1088 {
1089 .compatible = "dallas,ds1341",
1090 .data = (void *)ds_1341
1091 },
1092 {
1093 .compatible = "maxim,ds3231",
1094 .data = (void *)ds_3231
1095 },
1096 {
1097 .compatible = "st,m41t0",
1098 .data = (void *)m41t0
1099 },
1100 {
1101 .compatible = "st,m41t00",
1102 .data = (void *)m41t00
1103 },
1104 {
1105 .compatible = "st,m41t11",
1106 .data = (void *)m41t11
1107 },
1108 {
1109 .compatible = "microchip,mcp7940x",
1110 .data = (void *)mcp794xx
1111 },
1112 {
1113 .compatible = "microchip,mcp7941x",
1114 .data = (void *)mcp794xx
1115 },
1116 {
1117 .compatible = "pericom,pt7c4338",
1118 .data = (void *)ds_1307
1119 },
1120 {
1121 .compatible = "epson,rx8025",
1122 .data = (void *)rx_8025
1123 },
1124 {
1125 .compatible = "isil,isl12057",
1126 .data = (void *)ds_1337
1127 },
1128 {
1129 .compatible = "epson,rx8130",
1130 .data = (void *)rx_8130
1131 },
1132 { }
1133};
1134MODULE_DEVICE_TABLE(of, ds1307_of_match);
1135#endif
1136
1137#ifdef CONFIG_ACPI
1138static const struct acpi_device_id ds1307_acpi_ids[] = {
1139 { .id = "DS1307", .driver_data = ds_1307 },
1140 { .id = "DS1308", .driver_data = ds_1308 },
1141 { .id = "DS1337", .driver_data = ds_1337 },
1142 { .id = "DS1338", .driver_data = ds_1338 },
1143 { .id = "DS1339", .driver_data = ds_1339 },
1144 { .id = "DS1388", .driver_data = ds_1388 },
1145 { .id = "DS1340", .driver_data = ds_1340 },
1146 { .id = "DS1341", .driver_data = ds_1341 },
1147 { .id = "DS3231", .driver_data = ds_3231 },
1148 { .id = "M41T0", .driver_data = m41t0 },
1149 { .id = "M41T00", .driver_data = m41t00 },
1150 { .id = "M41T11", .driver_data = m41t11 },
1151 { .id = "MCP7940X", .driver_data = mcp794xx },
1152 { .id = "MCP7941X", .driver_data = mcp794xx },
1153 { .id = "PT7C4338", .driver_data = ds_1307 },
1154 { .id = "RX8025", .driver_data = rx_8025 },
1155 { .id = "ISL12057", .driver_data = ds_1337 },
1156 { .id = "RX8130", .driver_data = rx_8130 },
1157 { }
1158};
1159MODULE_DEVICE_TABLE(acpi, ds1307_acpi_ids);
1160#endif
1161
1162/*
1163 * The ds1337 and ds1339 both have two alarms, but we only use the first
1164 * one (with a "seconds" field). For ds1337 we expect nINTA is our alarm
1165 * signal; ds1339 chips have only one alarm signal.
1166 */
1167static irqreturn_t ds1307_irq(int irq, void *dev_id)
1168{
1169 struct ds1307 *ds1307 = dev_id;
1170 struct mutex *lock = &ds1307->rtc->ops_lock;
1171 int stat, ret;
1172
1173 mutex_lock(lock);
1174 ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &stat);
1175 if (ret)
1176 goto out;
1177
1178 if (stat & DS1337_BIT_A1I) {
1179 stat &= ~DS1337_BIT_A1I;
1180 regmap_write(ds1307->regmap, DS1337_REG_STATUS, stat);
1181
1182 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
1183 DS1337_BIT_A1IE, 0);
1184 if (ret)
1185 goto out;
1186
1187 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
1188 }
1189
1190out:
1191 mutex_unlock(lock);
1192
1193 return IRQ_HANDLED;
1194}
1195
1196/*----------------------------------------------------------------------*/
1197
1198static const struct rtc_class_ops ds13xx_rtc_ops = {
1199 .read_time = ds1307_get_time,
1200 .set_time = ds1307_set_time,
1201 .read_alarm = ds1337_read_alarm,
1202 .set_alarm = ds1337_set_alarm,
1203 .alarm_irq_enable = ds1307_alarm_irq_enable,
1204};
1205
1206static ssize_t frequency_test_store(struct device *dev,
1207 struct device_attribute *attr,
1208 const char *buf, size_t count)
1209{
1210 struct ds1307 *ds1307 = dev_get_drvdata(dev->parent);
1211 bool freq_test_en;
1212 int ret;
1213
1214 ret = kstrtobool(buf, &freq_test_en);
1215 if (ret) {
1216 dev_err(dev, "Failed to store RTC Frequency Test attribute\n");
1217 return ret;
1218 }
1219
1220 regmap_update_bits(ds1307->regmap, M41TXX_REG_CONTROL, M41TXX_BIT_FT,
1221 freq_test_en ? M41TXX_BIT_FT : 0);
1222
1223 return count;
1224}
1225
1226static ssize_t frequency_test_show(struct device *dev,
1227 struct device_attribute *attr,
1228 char *buf)
1229{
1230 struct ds1307 *ds1307 = dev_get_drvdata(dev->parent);
1231 unsigned int ctrl_reg;
1232
1233 regmap_read(ds1307->regmap, M41TXX_REG_CONTROL, &ctrl_reg);
1234
1235 return scnprintf(buf, PAGE_SIZE, (ctrl_reg & M41TXX_BIT_FT) ? "on\n" :
1236 "off\n");
1237}
1238
1239static DEVICE_ATTR_RW(frequency_test);
1240
1241static struct attribute *rtc_freq_test_attrs[] = {
1242 &dev_attr_frequency_test.attr,
1243 NULL,
1244};
1245
1246static const struct attribute_group rtc_freq_test_attr_group = {
1247 .attrs = rtc_freq_test_attrs,
1248};
1249
1250static int ds1307_add_frequency_test(struct ds1307 *ds1307)
1251{
1252 int err;
1253
1254 switch (ds1307->type) {
1255 case m41t0:
1256 case m41t00:
1257 case m41t11:
1258 err = rtc_add_group(ds1307->rtc, &rtc_freq_test_attr_group);
1259 if (err)
1260 return err;
1261 break;
1262 default:
1263 break;
1264 }
1265
1266 return 0;
1267}
1268
1269/*----------------------------------------------------------------------*/
1270
1271static int ds1307_nvram_read(void *priv, unsigned int offset, void *val,
1272 size_t bytes)
1273{
1274 struct ds1307 *ds1307 = priv;
1275 const struct chip_desc *chip = &chips[ds1307->type];
1276
1277 return regmap_bulk_read(ds1307->regmap, chip->nvram_offset + offset,
1278 val, bytes);
1279}
1280
1281static int ds1307_nvram_write(void *priv, unsigned int offset, void *val,
1282 size_t bytes)
1283{
1284 struct ds1307 *ds1307 = priv;
1285 const struct chip_desc *chip = &chips[ds1307->type];
1286
1287 return regmap_bulk_write(ds1307->regmap, chip->nvram_offset + offset,
1288 val, bytes);
1289}
1290
1291/*----------------------------------------------------------------------*/
1292
1293static u8 ds1307_trickle_init(struct ds1307 *ds1307,
1294 const struct chip_desc *chip)
1295{
1296 u32 ohms;
1297 bool diode = true;
1298
1299 if (!chip->do_trickle_setup)
1300 return 0;
1301
1302 if (device_property_read_u32(ds1307->dev, "trickle-resistor-ohms",
1303 &ohms))
1304 return 0;
1305
1306 if (device_property_read_bool(ds1307->dev, "trickle-diode-disable"))
1307 diode = false;
1308
1309 return chip->do_trickle_setup(ds1307, ohms, diode);
1310}
1311
1312/*----------------------------------------------------------------------*/
1313
1314#if IS_REACHABLE(CONFIG_HWMON)
1315
1316/*
1317 * Temperature sensor support for ds3231 devices.
1318 */
1319
1320#define DS3231_REG_TEMPERATURE 0x11
1321
1322/*
1323 * A user-initiated temperature conversion is not started by this function,
1324 * so the temperature is updated once every 64 seconds.
1325 */
1326static int ds3231_hwmon_read_temp(struct device *dev, s32 *mC)
1327{
1328 struct ds1307 *ds1307 = dev_get_drvdata(dev);
1329 u8 temp_buf[2];
1330 s16 temp;
1331 int ret;
1332
1333 ret = regmap_bulk_read(ds1307->regmap, DS3231_REG_TEMPERATURE,
1334 temp_buf, sizeof(temp_buf));
1335 if (ret)
1336 return ret;
1337 /*
1338 * Temperature is represented as a 10-bit code with a resolution of
1339 * 0.25 degree celsius and encoded in two's complement format.
1340 */
1341 temp = (temp_buf[0] << 8) | temp_buf[1];
1342 temp >>= 6;
1343 *mC = temp * 250;
1344
1345 return 0;
1346}
1347
1348static ssize_t ds3231_hwmon_show_temp(struct device *dev,
1349 struct device_attribute *attr, char *buf)
1350{
1351 int ret;
1352 s32 temp;
1353
1354 ret = ds3231_hwmon_read_temp(dev, &temp);
1355 if (ret)
1356 return ret;
1357
1358 return sprintf(buf, "%d\n", temp);
1359}
1360static SENSOR_DEVICE_ATTR(temp1_input, 0444, ds3231_hwmon_show_temp,
1361 NULL, 0);
1362
1363static struct attribute *ds3231_hwmon_attrs[] = {
1364 &sensor_dev_attr_temp1_input.dev_attr.attr,
1365 NULL,
1366};
1367ATTRIBUTE_GROUPS(ds3231_hwmon);
1368
1369static void ds1307_hwmon_register(struct ds1307 *ds1307)
1370{
1371 struct device *dev;
1372
1373 if (ds1307->type != ds_3231)
1374 return;
1375
1376 dev = devm_hwmon_device_register_with_groups(ds1307->dev, ds1307->name,
1377 ds1307,
1378 ds3231_hwmon_groups);
1379 if (IS_ERR(dev)) {
1380 dev_warn(ds1307->dev, "unable to register hwmon device %ld\n",
1381 PTR_ERR(dev));
1382 }
1383}
1384
1385#else
1386
1387static void ds1307_hwmon_register(struct ds1307 *ds1307)
1388{
1389}
1390
1391#endif /* CONFIG_RTC_DRV_DS1307_HWMON */
1392
1393/*----------------------------------------------------------------------*/
1394
1395/*
1396 * Square-wave output support for DS3231
1397 * Datasheet: https://datasheets.maximintegrated.com/en/ds/DS3231.pdf
1398 */
1399#ifdef CONFIG_COMMON_CLK
1400
1401enum {
1402 DS3231_CLK_SQW = 0,
1403 DS3231_CLK_32KHZ,
1404};
1405
1406#define clk_sqw_to_ds1307(clk) \
1407 container_of(clk, struct ds1307, clks[DS3231_CLK_SQW])
1408#define clk_32khz_to_ds1307(clk) \
1409 container_of(clk, struct ds1307, clks[DS3231_CLK_32KHZ])
1410
1411static int ds3231_clk_sqw_rates[] = {
1412 1,
1413 1024,
1414 4096,
1415 8192,
1416};
1417
1418static int ds1337_write_control(struct ds1307 *ds1307, u8 mask, u8 value)
1419{
1420 struct mutex *lock = &ds1307->rtc->ops_lock;
1421 int ret;
1422
1423 mutex_lock(lock);
1424 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
1425 mask, value);
1426 mutex_unlock(lock);
1427
1428 return ret;
1429}
1430
1431static unsigned long ds3231_clk_sqw_recalc_rate(struct clk_hw *hw,
1432 unsigned long parent_rate)
1433{
1434 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1435 int control, ret;
1436 int rate_sel = 0;
1437
1438 ret = regmap_read(ds1307->regmap, DS1337_REG_CONTROL, &control);
1439 if (ret)
1440 return ret;
1441 if (control & DS1337_BIT_RS1)
1442 rate_sel += 1;
1443 if (control & DS1337_BIT_RS2)
1444 rate_sel += 2;
1445
1446 return ds3231_clk_sqw_rates[rate_sel];
1447}
1448
1449static long ds3231_clk_sqw_round_rate(struct clk_hw *hw, unsigned long rate,
1450 unsigned long *prate)
1451{
1452 int i;
1453
1454 for (i = ARRAY_SIZE(ds3231_clk_sqw_rates) - 1; i >= 0; i--) {
1455 if (ds3231_clk_sqw_rates[i] <= rate)
1456 return ds3231_clk_sqw_rates[i];
1457 }
1458
1459 return 0;
1460}
1461
1462static int ds3231_clk_sqw_set_rate(struct clk_hw *hw, unsigned long rate,
1463 unsigned long parent_rate)
1464{
1465 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1466 int control = 0;
1467 int rate_sel;
1468
1469 for (rate_sel = 0; rate_sel < ARRAY_SIZE(ds3231_clk_sqw_rates);
1470 rate_sel++) {
1471 if (ds3231_clk_sqw_rates[rate_sel] == rate)
1472 break;
1473 }
1474
1475 if (rate_sel == ARRAY_SIZE(ds3231_clk_sqw_rates))
1476 return -EINVAL;
1477
1478 if (rate_sel & 1)
1479 control |= DS1337_BIT_RS1;
1480 if (rate_sel & 2)
1481 control |= DS1337_BIT_RS2;
1482
1483 return ds1337_write_control(ds1307, DS1337_BIT_RS1 | DS1337_BIT_RS2,
1484 control);
1485}
1486
1487static int ds3231_clk_sqw_prepare(struct clk_hw *hw)
1488{
1489 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1490
1491 return ds1337_write_control(ds1307, DS1337_BIT_INTCN, 0);
1492}
1493
1494static void ds3231_clk_sqw_unprepare(struct clk_hw *hw)
1495{
1496 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1497
1498 ds1337_write_control(ds1307, DS1337_BIT_INTCN, DS1337_BIT_INTCN);
1499}
1500
1501static int ds3231_clk_sqw_is_prepared(struct clk_hw *hw)
1502{
1503 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1504 int control, ret;
1505
1506 ret = regmap_read(ds1307->regmap, DS1337_REG_CONTROL, &control);
1507 if (ret)
1508 return ret;
1509
1510 return !(control & DS1337_BIT_INTCN);
1511}
1512
1513static const struct clk_ops ds3231_clk_sqw_ops = {
1514 .prepare = ds3231_clk_sqw_prepare,
1515 .unprepare = ds3231_clk_sqw_unprepare,
1516 .is_prepared = ds3231_clk_sqw_is_prepared,
1517 .recalc_rate = ds3231_clk_sqw_recalc_rate,
1518 .round_rate = ds3231_clk_sqw_round_rate,
1519 .set_rate = ds3231_clk_sqw_set_rate,
1520};
1521
1522static unsigned long ds3231_clk_32khz_recalc_rate(struct clk_hw *hw,
1523 unsigned long parent_rate)
1524{
1525 return 32768;
1526}
1527
1528static int ds3231_clk_32khz_control(struct ds1307 *ds1307, bool enable)
1529{
1530 struct mutex *lock = &ds1307->rtc->ops_lock;
1531 int ret;
1532
1533 mutex_lock(lock);
1534 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_STATUS,
1535 DS3231_BIT_EN32KHZ,
1536 enable ? DS3231_BIT_EN32KHZ : 0);
1537 mutex_unlock(lock);
1538
1539 return ret;
1540}
1541
1542static int ds3231_clk_32khz_prepare(struct clk_hw *hw)
1543{
1544 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
1545
1546 return ds3231_clk_32khz_control(ds1307, true);
1547}
1548
1549static void ds3231_clk_32khz_unprepare(struct clk_hw *hw)
1550{
1551 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
1552
1553 ds3231_clk_32khz_control(ds1307, false);
1554}
1555
1556static int ds3231_clk_32khz_is_prepared(struct clk_hw *hw)
1557{
1558 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
1559 int status, ret;
1560
1561 ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &status);
1562 if (ret)
1563 return ret;
1564
1565 return !!(status & DS3231_BIT_EN32KHZ);
1566}
1567
1568static const struct clk_ops ds3231_clk_32khz_ops = {
1569 .prepare = ds3231_clk_32khz_prepare,
1570 .unprepare = ds3231_clk_32khz_unprepare,
1571 .is_prepared = ds3231_clk_32khz_is_prepared,
1572 .recalc_rate = ds3231_clk_32khz_recalc_rate,
1573};
1574
1575static struct clk_init_data ds3231_clks_init[] = {
1576 [DS3231_CLK_SQW] = {
1577 .name = "ds3231_clk_sqw",
1578 .ops = &ds3231_clk_sqw_ops,
1579 },
1580 [DS3231_CLK_32KHZ] = {
1581 .name = "ds3231_clk_32khz",
1582 .ops = &ds3231_clk_32khz_ops,
1583 },
1584};
1585
1586static int ds3231_clks_register(struct ds1307 *ds1307)
1587{
1588 struct device_node *node = ds1307->dev->of_node;
1589 struct clk_onecell_data *onecell;
1590 int i;
1591
1592 onecell = devm_kzalloc(ds1307->dev, sizeof(*onecell), GFP_KERNEL);
1593 if (!onecell)
1594 return -ENOMEM;
1595
1596 onecell->clk_num = ARRAY_SIZE(ds3231_clks_init);
1597 onecell->clks = devm_kcalloc(ds1307->dev, onecell->clk_num,
1598 sizeof(onecell->clks[0]), GFP_KERNEL);
1599 if (!onecell->clks)
1600 return -ENOMEM;
1601
1602 for (i = 0; i < ARRAY_SIZE(ds3231_clks_init); i++) {
1603 struct clk_init_data init = ds3231_clks_init[i];
1604
1605 /*
1606 * Interrupt signal due to alarm conditions and square-wave
1607 * output share same pin, so don't initialize both.
1608 */
1609 if (i == DS3231_CLK_SQW && test_bit(HAS_ALARM, &ds1307->flags))
1610 continue;
1611
1612 /* optional override of the clockname */
1613 of_property_read_string_index(node, "clock-output-names", i,
1614 &init.name);
1615 ds1307->clks[i].init = &init;
1616
1617 onecell->clks[i] = devm_clk_register(ds1307->dev,
1618 &ds1307->clks[i]);
1619 if (IS_ERR(onecell->clks[i]))
1620 return PTR_ERR(onecell->clks[i]);
1621 }
1622
1623 if (!node)
1624 return 0;
1625
1626 of_clk_add_provider(node, of_clk_src_onecell_get, onecell);
1627
1628 return 0;
1629}
1630
1631static void ds1307_clks_register(struct ds1307 *ds1307)
1632{
1633 int ret;
1634
1635 if (ds1307->type != ds_3231)
1636 return;
1637
1638 ret = ds3231_clks_register(ds1307);
1639 if (ret) {
1640 dev_warn(ds1307->dev, "unable to register clock device %d\n",
1641 ret);
1642 }
1643}
1644
1645#else
1646
1647static void ds1307_clks_register(struct ds1307 *ds1307)
1648{
1649}
1650
1651#endif /* CONFIG_COMMON_CLK */
1652
1653#ifdef CONFIG_WATCHDOG_CORE
1654static const struct watchdog_info ds1388_wdt_info = {
1655 .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
1656 .identity = "DS1388 watchdog",
1657};
1658
1659static const struct watchdog_ops ds1388_wdt_ops = {
1660 .owner = THIS_MODULE,
1661 .start = ds1388_wdt_start,
1662 .stop = ds1388_wdt_stop,
1663 .ping = ds1388_wdt_ping,
1664 .set_timeout = ds1388_wdt_set_timeout,
1665
1666};
1667
1668static void ds1307_wdt_register(struct ds1307 *ds1307)
1669{
1670 struct watchdog_device *wdt;
1671 int err;
1672 int val;
1673
1674 if (ds1307->type != ds_1388)
1675 return;
1676
1677 wdt = devm_kzalloc(ds1307->dev, sizeof(*wdt), GFP_KERNEL);
1678 if (!wdt)
1679 return;
1680
1681 err = regmap_read(ds1307->regmap, DS1388_REG_FLAG, &val);
1682 if (!err && val & DS1388_BIT_WF)
1683 wdt->bootstatus = WDIOF_CARDRESET;
1684
1685 wdt->info = &ds1388_wdt_info;
1686 wdt->ops = &ds1388_wdt_ops;
1687 wdt->timeout = 99;
1688 wdt->max_timeout = 99;
1689 wdt->min_timeout = 1;
1690
1691 watchdog_init_timeout(wdt, 0, ds1307->dev);
1692 watchdog_set_drvdata(wdt, ds1307);
1693 devm_watchdog_register_device(ds1307->dev, wdt);
1694}
1695#else
1696static void ds1307_wdt_register(struct ds1307 *ds1307)
1697{
1698}
1699#endif /* CONFIG_WATCHDOG_CORE */
1700
1701static const struct regmap_config regmap_config = {
1702 .reg_bits = 8,
1703 .val_bits = 8,
1704};
1705
1706static int ds1307_probe(struct i2c_client *client,
1707 const struct i2c_device_id *id)
1708{
1709 struct ds1307 *ds1307;
1710 int err = -ENODEV;
1711 int tmp;
1712 const struct chip_desc *chip;
1713 bool want_irq;
1714 bool ds1307_can_wakeup_device = false;
1715 unsigned char regs[8];
1716 struct ds1307_platform_data *pdata = dev_get_platdata(&client->dev);
1717 u8 trickle_charger_setup = 0;
1718
1719 ds1307 = devm_kzalloc(&client->dev, sizeof(struct ds1307), GFP_KERNEL);
1720 if (!ds1307)
1721 return -ENOMEM;
1722
1723 dev_set_drvdata(&client->dev, ds1307);
1724 ds1307->dev = &client->dev;
1725 ds1307->name = client->name;
1726
1727 ds1307->regmap = devm_regmap_init_i2c(client, ®map_config);
1728 if (IS_ERR(ds1307->regmap)) {
1729 dev_err(ds1307->dev, "regmap allocation failed\n");
1730 return PTR_ERR(ds1307->regmap);
1731 }
1732
1733 i2c_set_clientdata(client, ds1307);
1734
1735 if (client->dev.of_node) {
1736 ds1307->type = (enum ds_type)
1737 of_device_get_match_data(&client->dev);
1738 chip = &chips[ds1307->type];
1739 } else if (id) {
1740 chip = &chips[id->driver_data];
1741 ds1307->type = id->driver_data;
1742 } else {
1743 const struct acpi_device_id *acpi_id;
1744
1745 acpi_id = acpi_match_device(ACPI_PTR(ds1307_acpi_ids),
1746 ds1307->dev);
1747 if (!acpi_id)
1748 return -ENODEV;
1749 chip = &chips[acpi_id->driver_data];
1750 ds1307->type = acpi_id->driver_data;
1751 }
1752
1753 want_irq = client->irq > 0 && chip->alarm;
1754
1755 if (!pdata)
1756 trickle_charger_setup = ds1307_trickle_init(ds1307, chip);
1757 else if (pdata->trickle_charger_setup)
1758 trickle_charger_setup = pdata->trickle_charger_setup;
1759
1760 if (trickle_charger_setup && chip->trickle_charger_reg) {
1761 trickle_charger_setup |= DS13XX_TRICKLE_CHARGER_MAGIC;
1762 dev_dbg(ds1307->dev,
1763 "writing trickle charger info 0x%x to 0x%x\n",
1764 trickle_charger_setup, chip->trickle_charger_reg);
1765 regmap_write(ds1307->regmap, chip->trickle_charger_reg,
1766 trickle_charger_setup);
1767 }
1768
1769#ifdef CONFIG_OF
1770/*
1771 * For devices with no IRQ directly connected to the SoC, the RTC chip
1772 * can be forced as a wakeup source by stating that explicitly in
1773 * the device's .dts file using the "wakeup-source" boolean property.
1774 * If the "wakeup-source" property is set, don't request an IRQ.
1775 * This will guarantee the 'wakealarm' sysfs entry is available on the device,
1776 * if supported by the RTC.
1777 */
1778 if (chip->alarm && of_property_read_bool(client->dev.of_node,
1779 "wakeup-source"))
1780 ds1307_can_wakeup_device = true;
1781#endif
1782
1783 switch (ds1307->type) {
1784 case ds_1337:
1785 case ds_1339:
1786 case ds_1341:
1787 case ds_3231:
1788 /* get registers that the "rtc" read below won't read... */
1789 err = regmap_bulk_read(ds1307->regmap, DS1337_REG_CONTROL,
1790 regs, 2);
1791 if (err) {
1792 dev_dbg(ds1307->dev, "read error %d\n", err);
1793 goto exit;
1794 }
1795
1796 /* oscillator off? turn it on, so clock can tick. */
1797 if (regs[0] & DS1337_BIT_nEOSC)
1798 regs[0] &= ~DS1337_BIT_nEOSC;
1799
1800 /*
1801 * Using IRQ or defined as wakeup-source?
1802 * Disable the square wave and both alarms.
1803 * For some variants, be sure alarms can trigger when we're
1804 * running on Vbackup (BBSQI/BBSQW)
1805 */
1806 if (want_irq || ds1307_can_wakeup_device) {
1807 regs[0] |= DS1337_BIT_INTCN | chip->bbsqi_bit;
1808 regs[0] &= ~(DS1337_BIT_A2IE | DS1337_BIT_A1IE);
1809 }
1810
1811 regmap_write(ds1307->regmap, DS1337_REG_CONTROL,
1812 regs[0]);
1813
1814 /* oscillator fault? clear flag, and warn */
1815 if (regs[1] & DS1337_BIT_OSF) {
1816 regmap_write(ds1307->regmap, DS1337_REG_STATUS,
1817 regs[1] & ~DS1337_BIT_OSF);
1818 dev_warn(ds1307->dev, "SET TIME!\n");
1819 }
1820 break;
1821
1822 case rx_8025:
1823 err = regmap_bulk_read(ds1307->regmap,
1824 RX8025_REG_CTRL1 << 4 | 0x08, regs, 2);
1825 if (err) {
1826 dev_dbg(ds1307->dev, "read error %d\n", err);
1827 goto exit;
1828 }
1829
1830 /* oscillator off? turn it on, so clock can tick. */
1831 if (!(regs[1] & RX8025_BIT_XST)) {
1832 regs[1] |= RX8025_BIT_XST;
1833 regmap_write(ds1307->regmap,
1834 RX8025_REG_CTRL2 << 4 | 0x08,
1835 regs[1]);
1836 dev_warn(ds1307->dev,
1837 "oscillator stop detected - SET TIME!\n");
1838 }
1839
1840 if (regs[1] & RX8025_BIT_PON) {
1841 regs[1] &= ~RX8025_BIT_PON;
1842 regmap_write(ds1307->regmap,
1843 RX8025_REG_CTRL2 << 4 | 0x08,
1844 regs[1]);
1845 dev_warn(ds1307->dev, "power-on detected\n");
1846 }
1847
1848 if (regs[1] & RX8025_BIT_VDET) {
1849 regs[1] &= ~RX8025_BIT_VDET;
1850 regmap_write(ds1307->regmap,
1851 RX8025_REG_CTRL2 << 4 | 0x08,
1852 regs[1]);
1853 dev_warn(ds1307->dev, "voltage drop detected\n");
1854 }
1855
1856 /* make sure we are running in 24hour mode */
1857 if (!(regs[0] & RX8025_BIT_2412)) {
1858 u8 hour;
1859
1860 /* switch to 24 hour mode */
1861 regmap_write(ds1307->regmap,
1862 RX8025_REG_CTRL1 << 4 | 0x08,
1863 regs[0] | RX8025_BIT_2412);
1864
1865 err = regmap_bulk_read(ds1307->regmap,
1866 RX8025_REG_CTRL1 << 4 | 0x08,
1867 regs, 2);
1868 if (err) {
1869 dev_dbg(ds1307->dev, "read error %d\n", err);
1870 goto exit;
1871 }
1872
1873 /* correct hour */
1874 hour = bcd2bin(regs[DS1307_REG_HOUR]);
1875 if (hour == 12)
1876 hour = 0;
1877 if (regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
1878 hour += 12;
1879
1880 regmap_write(ds1307->regmap,
1881 DS1307_REG_HOUR << 4 | 0x08, hour);
1882 }
1883 break;
1884 default:
1885 break;
1886 }
1887
1888 /* read RTC registers */
1889 err = regmap_bulk_read(ds1307->regmap, chip->offset, regs,
1890 sizeof(regs));
1891 if (err) {
1892 dev_dbg(ds1307->dev, "read error %d\n", err);
1893 goto exit;
1894 }
1895
1896 if (ds1307->type == mcp794xx &&
1897 !(regs[DS1307_REG_WDAY] & MCP794XX_BIT_VBATEN)) {
1898 regmap_write(ds1307->regmap, DS1307_REG_WDAY,
1899 regs[DS1307_REG_WDAY] |
1900 MCP794XX_BIT_VBATEN);
1901 }
1902
1903 tmp = regs[DS1307_REG_HOUR];
1904 switch (ds1307->type) {
1905 case ds_1340:
1906 case m41t0:
1907 case m41t00:
1908 case m41t11:
1909 /*
1910 * NOTE: ignores century bits; fix before deploying
1911 * systems that will run through year 2100.
1912 */
1913 break;
1914 case rx_8025:
1915 break;
1916 default:
1917 if (!(tmp & DS1307_BIT_12HR))
1918 break;
1919
1920 /*
1921 * Be sure we're in 24 hour mode. Multi-master systems
1922 * take note...
1923 */
1924 tmp = bcd2bin(tmp & 0x1f);
1925 if (tmp == 12)
1926 tmp = 0;
1927 if (regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
1928 tmp += 12;
1929 regmap_write(ds1307->regmap, chip->offset + DS1307_REG_HOUR,
1930 bin2bcd(tmp));
1931 }
1932
1933 if (want_irq || ds1307_can_wakeup_device) {
1934 device_set_wakeup_capable(ds1307->dev, true);
1935 set_bit(HAS_ALARM, &ds1307->flags);
1936 }
1937
1938 ds1307->rtc = devm_rtc_allocate_device(ds1307->dev);
1939 if (IS_ERR(ds1307->rtc))
1940 return PTR_ERR(ds1307->rtc);
1941
1942 if (ds1307_can_wakeup_device && !want_irq) {
1943 dev_info(ds1307->dev,
1944 "'wakeup-source' is set, request for an IRQ is disabled!\n");
1945 /* We cannot support UIE mode if we do not have an IRQ line */
1946 ds1307->rtc->uie_unsupported = 1;
1947 }
1948
1949 if (want_irq) {
1950 err = devm_request_threaded_irq(ds1307->dev, client->irq, NULL,
1951 chip->irq_handler ?: ds1307_irq,
1952 IRQF_SHARED | IRQF_ONESHOT,
1953 ds1307->name, ds1307);
1954 if (err) {
1955 client->irq = 0;
1956 device_set_wakeup_capable(ds1307->dev, false);
1957 clear_bit(HAS_ALARM, &ds1307->flags);
1958 dev_err(ds1307->dev, "unable to request IRQ!\n");
1959 } else {
1960 dev_dbg(ds1307->dev, "got IRQ %d\n", client->irq);
1961 }
1962 }
1963
1964 ds1307->rtc->ops = chip->rtc_ops ?: &ds13xx_rtc_ops;
1965 err = ds1307_add_frequency_test(ds1307);
1966 if (err)
1967 return err;
1968
1969 err = rtc_register_device(ds1307->rtc);
1970 if (err)
1971 return err;
1972
1973 if (chip->nvram_size) {
1974 struct nvmem_config nvmem_cfg = {
1975 .name = "ds1307_nvram",
1976 .word_size = 1,
1977 .stride = 1,
1978 .size = chip->nvram_size,
1979 .reg_read = ds1307_nvram_read,
1980 .reg_write = ds1307_nvram_write,
1981 .priv = ds1307,
1982 };
1983
1984 ds1307->rtc->nvram_old_abi = true;
1985 rtc_nvmem_register(ds1307->rtc, &nvmem_cfg);
1986 }
1987
1988 ds1307_hwmon_register(ds1307);
1989 ds1307_clks_register(ds1307);
1990 ds1307_wdt_register(ds1307);
1991
1992 return 0;
1993
1994exit:
1995 return err;
1996}
1997
1998static struct i2c_driver ds1307_driver = {
1999 .driver = {
2000 .name = "rtc-ds1307",
2001 .of_match_table = of_match_ptr(ds1307_of_match),
2002 .acpi_match_table = ACPI_PTR(ds1307_acpi_ids),
2003 },
2004 .probe = ds1307_probe,
2005 .id_table = ds1307_id,
2006};
2007
2008module_i2c_driver(ds1307_driver);
2009
2010MODULE_DESCRIPTION("RTC driver for DS1307 and similar chips");
2011MODULE_LICENSE("GPL");
1/*
2 * rtc-ds1307.c - RTC driver for some mostly-compatible I2C chips.
3 *
4 * Copyright (C) 2005 James Chapman (ds1337 core)
5 * Copyright (C) 2006 David Brownell
6 * Copyright (C) 2009 Matthias Fuchs (rx8025 support)
7 * Copyright (C) 2012 Bertrand Achard (nvram access fixes)
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/acpi.h>
15#include <linux/bcd.h>
16#include <linux/i2c.h>
17#include <linux/init.h>
18#include <linux/module.h>
19#include <linux/rtc/ds1307.h>
20#include <linux/rtc.h>
21#include <linux/slab.h>
22#include <linux/string.h>
23#include <linux/hwmon.h>
24#include <linux/hwmon-sysfs.h>
25#include <linux/clk-provider.h>
26
27/*
28 * We can't determine type by probing, but if we expect pre-Linux code
29 * to have set the chip up as a clock (turning on the oscillator and
30 * setting the date and time), Linux can ignore the non-clock features.
31 * That's a natural job for a factory or repair bench.
32 */
33enum ds_type {
34 ds_1307,
35 ds_1337,
36 ds_1338,
37 ds_1339,
38 ds_1340,
39 ds_1388,
40 ds_3231,
41 m41t00,
42 mcp794xx,
43 rx_8025,
44 last_ds_type /* always last */
45 /* rs5c372 too? different address... */
46};
47
48
49/* RTC registers don't differ much, except for the century flag */
50#define DS1307_REG_SECS 0x00 /* 00-59 */
51# define DS1307_BIT_CH 0x80
52# define DS1340_BIT_nEOSC 0x80
53# define MCP794XX_BIT_ST 0x80
54#define DS1307_REG_MIN 0x01 /* 00-59 */
55#define DS1307_REG_HOUR 0x02 /* 00-23, or 1-12{am,pm} */
56# define DS1307_BIT_12HR 0x40 /* in REG_HOUR */
57# define DS1307_BIT_PM 0x20 /* in REG_HOUR */
58# define DS1340_BIT_CENTURY_EN 0x80 /* in REG_HOUR */
59# define DS1340_BIT_CENTURY 0x40 /* in REG_HOUR */
60#define DS1307_REG_WDAY 0x03 /* 01-07 */
61# define MCP794XX_BIT_VBATEN 0x08
62#define DS1307_REG_MDAY 0x04 /* 01-31 */
63#define DS1307_REG_MONTH 0x05 /* 01-12 */
64# define DS1337_BIT_CENTURY 0x80 /* in REG_MONTH */
65#define DS1307_REG_YEAR 0x06 /* 00-99 */
66
67/*
68 * Other registers (control, status, alarms, trickle charge, NVRAM, etc)
69 * start at 7, and they differ a LOT. Only control and status matter for
70 * basic RTC date and time functionality; be careful using them.
71 */
72#define DS1307_REG_CONTROL 0x07 /* or ds1338 */
73# define DS1307_BIT_OUT 0x80
74# define DS1338_BIT_OSF 0x20
75# define DS1307_BIT_SQWE 0x10
76# define DS1307_BIT_RS1 0x02
77# define DS1307_BIT_RS0 0x01
78#define DS1337_REG_CONTROL 0x0e
79# define DS1337_BIT_nEOSC 0x80
80# define DS1339_BIT_BBSQI 0x20
81# define DS3231_BIT_BBSQW 0x40 /* same as BBSQI */
82# define DS1337_BIT_RS2 0x10
83# define DS1337_BIT_RS1 0x08
84# define DS1337_BIT_INTCN 0x04
85# define DS1337_BIT_A2IE 0x02
86# define DS1337_BIT_A1IE 0x01
87#define DS1340_REG_CONTROL 0x07
88# define DS1340_BIT_OUT 0x80
89# define DS1340_BIT_FT 0x40
90# define DS1340_BIT_CALIB_SIGN 0x20
91# define DS1340_M_CALIBRATION 0x1f
92#define DS1340_REG_FLAG 0x09
93# define DS1340_BIT_OSF 0x80
94#define DS1337_REG_STATUS 0x0f
95# define DS1337_BIT_OSF 0x80
96# define DS3231_BIT_EN32KHZ 0x08
97# define DS1337_BIT_A2I 0x02
98# define DS1337_BIT_A1I 0x01
99#define DS1339_REG_ALARM1_SECS 0x07
100
101#define DS13XX_TRICKLE_CHARGER_MAGIC 0xa0
102
103#define RX8025_REG_CTRL1 0x0e
104# define RX8025_BIT_2412 0x20
105#define RX8025_REG_CTRL2 0x0f
106# define RX8025_BIT_PON 0x10
107# define RX8025_BIT_VDET 0x40
108# define RX8025_BIT_XST 0x20
109
110
111struct ds1307 {
112 u8 offset; /* register's offset */
113 u8 regs[11];
114 u16 nvram_offset;
115 struct bin_attribute *nvram;
116 enum ds_type type;
117 unsigned long flags;
118#define HAS_NVRAM 0 /* bit 0 == sysfs file active */
119#define HAS_ALARM 1 /* bit 1 == irq claimed */
120 struct i2c_client *client;
121 struct rtc_device *rtc;
122 s32 (*read_block_data)(const struct i2c_client *client, u8 command,
123 u8 length, u8 *values);
124 s32 (*write_block_data)(const struct i2c_client *client, u8 command,
125 u8 length, const u8 *values);
126#ifdef CONFIG_COMMON_CLK
127 struct clk_hw clks[2];
128#endif
129};
130
131struct chip_desc {
132 unsigned alarm:1;
133 u16 nvram_offset;
134 u16 nvram_size;
135 u16 trickle_charger_reg;
136 u8 trickle_charger_setup;
137 u8 (*do_trickle_setup)(struct i2c_client *, uint32_t, bool);
138};
139
140static u8 do_trickle_setup_ds1339(struct i2c_client *,
141 uint32_t ohms, bool diode);
142
143static struct chip_desc chips[last_ds_type] = {
144 [ds_1307] = {
145 .nvram_offset = 8,
146 .nvram_size = 56,
147 },
148 [ds_1337] = {
149 .alarm = 1,
150 },
151 [ds_1338] = {
152 .nvram_offset = 8,
153 .nvram_size = 56,
154 },
155 [ds_1339] = {
156 .alarm = 1,
157 .trickle_charger_reg = 0x10,
158 .do_trickle_setup = &do_trickle_setup_ds1339,
159 },
160 [ds_1340] = {
161 .trickle_charger_reg = 0x08,
162 },
163 [ds_1388] = {
164 .trickle_charger_reg = 0x0a,
165 },
166 [ds_3231] = {
167 .alarm = 1,
168 },
169 [mcp794xx] = {
170 .alarm = 1,
171 /* this is battery backed SRAM */
172 .nvram_offset = 0x20,
173 .nvram_size = 0x40,
174 },
175};
176
177static const struct i2c_device_id ds1307_id[] = {
178 { "ds1307", ds_1307 },
179 { "ds1337", ds_1337 },
180 { "ds1338", ds_1338 },
181 { "ds1339", ds_1339 },
182 { "ds1388", ds_1388 },
183 { "ds1340", ds_1340 },
184 { "ds3231", ds_3231 },
185 { "m41t00", m41t00 },
186 { "mcp7940x", mcp794xx },
187 { "mcp7941x", mcp794xx },
188 { "pt7c4338", ds_1307 },
189 { "rx8025", rx_8025 },
190 { "isl12057", ds_1337 },
191 { }
192};
193MODULE_DEVICE_TABLE(i2c, ds1307_id);
194
195#ifdef CONFIG_ACPI
196static const struct acpi_device_id ds1307_acpi_ids[] = {
197 { .id = "DS1307", .driver_data = ds_1307 },
198 { .id = "DS1337", .driver_data = ds_1337 },
199 { .id = "DS1338", .driver_data = ds_1338 },
200 { .id = "DS1339", .driver_data = ds_1339 },
201 { .id = "DS1388", .driver_data = ds_1388 },
202 { .id = "DS1340", .driver_data = ds_1340 },
203 { .id = "DS3231", .driver_data = ds_3231 },
204 { .id = "M41T00", .driver_data = m41t00 },
205 { .id = "MCP7940X", .driver_data = mcp794xx },
206 { .id = "MCP7941X", .driver_data = mcp794xx },
207 { .id = "PT7C4338", .driver_data = ds_1307 },
208 { .id = "RX8025", .driver_data = rx_8025 },
209 { .id = "ISL12057", .driver_data = ds_1337 },
210 { }
211};
212MODULE_DEVICE_TABLE(acpi, ds1307_acpi_ids);
213#endif
214
215/*----------------------------------------------------------------------*/
216
217#define BLOCK_DATA_MAX_TRIES 10
218
219static s32 ds1307_read_block_data_once(const struct i2c_client *client,
220 u8 command, u8 length, u8 *values)
221{
222 s32 i, data;
223
224 for (i = 0; i < length; i++) {
225 data = i2c_smbus_read_byte_data(client, command + i);
226 if (data < 0)
227 return data;
228 values[i] = data;
229 }
230 return i;
231}
232
233static s32 ds1307_read_block_data(const struct i2c_client *client, u8 command,
234 u8 length, u8 *values)
235{
236 u8 oldvalues[255];
237 s32 ret;
238 int tries = 0;
239
240 dev_dbg(&client->dev, "ds1307_read_block_data (length=%d)\n", length);
241 ret = ds1307_read_block_data_once(client, command, length, values);
242 if (ret < 0)
243 return ret;
244 do {
245 if (++tries > BLOCK_DATA_MAX_TRIES) {
246 dev_err(&client->dev,
247 "ds1307_read_block_data failed\n");
248 return -EIO;
249 }
250 memcpy(oldvalues, values, length);
251 ret = ds1307_read_block_data_once(client, command, length,
252 values);
253 if (ret < 0)
254 return ret;
255 } while (memcmp(oldvalues, values, length));
256 return length;
257}
258
259static s32 ds1307_write_block_data(const struct i2c_client *client, u8 command,
260 u8 length, const u8 *values)
261{
262 u8 currvalues[255];
263 int tries = 0;
264
265 dev_dbg(&client->dev, "ds1307_write_block_data (length=%d)\n", length);
266 do {
267 s32 i, ret;
268
269 if (++tries > BLOCK_DATA_MAX_TRIES) {
270 dev_err(&client->dev,
271 "ds1307_write_block_data failed\n");
272 return -EIO;
273 }
274 for (i = 0; i < length; i++) {
275 ret = i2c_smbus_write_byte_data(client, command + i,
276 values[i]);
277 if (ret < 0)
278 return ret;
279 }
280 ret = ds1307_read_block_data_once(client, command, length,
281 currvalues);
282 if (ret < 0)
283 return ret;
284 } while (memcmp(currvalues, values, length));
285 return length;
286}
287
288/*----------------------------------------------------------------------*/
289
290/* These RTC devices are not designed to be connected to a SMbus adapter.
291 SMbus limits block operations length to 32 bytes, whereas it's not
292 limited on I2C buses. As a result, accesses may exceed 32 bytes;
293 in that case, split them into smaller blocks */
294
295static s32 ds1307_native_smbus_write_block_data(const struct i2c_client *client,
296 u8 command, u8 length, const u8 *values)
297{
298 u8 suboffset = 0;
299
300 if (length <= I2C_SMBUS_BLOCK_MAX) {
301 s32 retval = i2c_smbus_write_i2c_block_data(client,
302 command, length, values);
303 if (retval < 0)
304 return retval;
305 return length;
306 }
307
308 while (suboffset < length) {
309 s32 retval = i2c_smbus_write_i2c_block_data(client,
310 command + suboffset,
311 min(I2C_SMBUS_BLOCK_MAX, length - suboffset),
312 values + suboffset);
313 if (retval < 0)
314 return retval;
315
316 suboffset += I2C_SMBUS_BLOCK_MAX;
317 }
318 return length;
319}
320
321static s32 ds1307_native_smbus_read_block_data(const struct i2c_client *client,
322 u8 command, u8 length, u8 *values)
323{
324 u8 suboffset = 0;
325
326 if (length <= I2C_SMBUS_BLOCK_MAX)
327 return i2c_smbus_read_i2c_block_data(client,
328 command, length, values);
329
330 while (suboffset < length) {
331 s32 retval = i2c_smbus_read_i2c_block_data(client,
332 command + suboffset,
333 min(I2C_SMBUS_BLOCK_MAX, length - suboffset),
334 values + suboffset);
335 if (retval < 0)
336 return retval;
337
338 suboffset += I2C_SMBUS_BLOCK_MAX;
339 }
340 return length;
341}
342
343/*----------------------------------------------------------------------*/
344
345/*
346 * The ds1337 and ds1339 both have two alarms, but we only use the first
347 * one (with a "seconds" field). For ds1337 we expect nINTA is our alarm
348 * signal; ds1339 chips have only one alarm signal.
349 */
350static irqreturn_t ds1307_irq(int irq, void *dev_id)
351{
352 struct i2c_client *client = dev_id;
353 struct ds1307 *ds1307 = i2c_get_clientdata(client);
354 struct mutex *lock = &ds1307->rtc->ops_lock;
355 int stat, control;
356
357 mutex_lock(lock);
358 stat = i2c_smbus_read_byte_data(client, DS1337_REG_STATUS);
359 if (stat < 0)
360 goto out;
361
362 if (stat & DS1337_BIT_A1I) {
363 stat &= ~DS1337_BIT_A1I;
364 i2c_smbus_write_byte_data(client, DS1337_REG_STATUS, stat);
365
366 control = i2c_smbus_read_byte_data(client, DS1337_REG_CONTROL);
367 if (control < 0)
368 goto out;
369
370 control &= ~DS1337_BIT_A1IE;
371 i2c_smbus_write_byte_data(client, DS1337_REG_CONTROL, control);
372
373 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
374 }
375
376out:
377 mutex_unlock(lock);
378
379 return IRQ_HANDLED;
380}
381
382/*----------------------------------------------------------------------*/
383
384static int ds1307_get_time(struct device *dev, struct rtc_time *t)
385{
386 struct ds1307 *ds1307 = dev_get_drvdata(dev);
387 int tmp;
388
389 /* read the RTC date and time registers all at once */
390 tmp = ds1307->read_block_data(ds1307->client,
391 ds1307->offset, 7, ds1307->regs);
392 if (tmp != 7) {
393 dev_err(dev, "%s error %d\n", "read", tmp);
394 return -EIO;
395 }
396
397 dev_dbg(dev, "%s: %7ph\n", "read", ds1307->regs);
398
399 t->tm_sec = bcd2bin(ds1307->regs[DS1307_REG_SECS] & 0x7f);
400 t->tm_min = bcd2bin(ds1307->regs[DS1307_REG_MIN] & 0x7f);
401 tmp = ds1307->regs[DS1307_REG_HOUR] & 0x3f;
402 t->tm_hour = bcd2bin(tmp);
403 t->tm_wday = bcd2bin(ds1307->regs[DS1307_REG_WDAY] & 0x07) - 1;
404 t->tm_mday = bcd2bin(ds1307->regs[DS1307_REG_MDAY] & 0x3f);
405 tmp = ds1307->regs[DS1307_REG_MONTH] & 0x1f;
406 t->tm_mon = bcd2bin(tmp) - 1;
407 t->tm_year = bcd2bin(ds1307->regs[DS1307_REG_YEAR]) + 100;
408
409#ifdef CONFIG_RTC_DRV_DS1307_CENTURY
410 switch (ds1307->type) {
411 case ds_1337:
412 case ds_1339:
413 case ds_3231:
414 if (ds1307->regs[DS1307_REG_MONTH] & DS1337_BIT_CENTURY)
415 t->tm_year += 100;
416 break;
417 case ds_1340:
418 if (ds1307->regs[DS1307_REG_HOUR] & DS1340_BIT_CENTURY)
419 t->tm_year += 100;
420 break;
421 default:
422 break;
423 }
424#endif
425
426 dev_dbg(dev, "%s secs=%d, mins=%d, "
427 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
428 "read", t->tm_sec, t->tm_min,
429 t->tm_hour, t->tm_mday,
430 t->tm_mon, t->tm_year, t->tm_wday);
431
432 /* initial clock setting can be undefined */
433 return rtc_valid_tm(t);
434}
435
436static int ds1307_set_time(struct device *dev, struct rtc_time *t)
437{
438 struct ds1307 *ds1307 = dev_get_drvdata(dev);
439 int result;
440 int tmp;
441 u8 *buf = ds1307->regs;
442
443 dev_dbg(dev, "%s secs=%d, mins=%d, "
444 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
445 "write", t->tm_sec, t->tm_min,
446 t->tm_hour, t->tm_mday,
447 t->tm_mon, t->tm_year, t->tm_wday);
448
449#ifdef CONFIG_RTC_DRV_DS1307_CENTURY
450 if (t->tm_year < 100)
451 return -EINVAL;
452
453 switch (ds1307->type) {
454 case ds_1337:
455 case ds_1339:
456 case ds_3231:
457 case ds_1340:
458 if (t->tm_year > 299)
459 return -EINVAL;
460 default:
461 if (t->tm_year > 199)
462 return -EINVAL;
463 break;
464 }
465#else
466 if (t->tm_year < 100 || t->tm_year > 199)
467 return -EINVAL;
468#endif
469
470 buf[DS1307_REG_SECS] = bin2bcd(t->tm_sec);
471 buf[DS1307_REG_MIN] = bin2bcd(t->tm_min);
472 buf[DS1307_REG_HOUR] = bin2bcd(t->tm_hour);
473 buf[DS1307_REG_WDAY] = bin2bcd(t->tm_wday + 1);
474 buf[DS1307_REG_MDAY] = bin2bcd(t->tm_mday);
475 buf[DS1307_REG_MONTH] = bin2bcd(t->tm_mon + 1);
476
477 /* assume 20YY not 19YY */
478 tmp = t->tm_year - 100;
479 buf[DS1307_REG_YEAR] = bin2bcd(tmp);
480
481 switch (ds1307->type) {
482 case ds_1337:
483 case ds_1339:
484 case ds_3231:
485 if (t->tm_year > 199)
486 buf[DS1307_REG_MONTH] |= DS1337_BIT_CENTURY;
487 break;
488 case ds_1340:
489 buf[DS1307_REG_HOUR] |= DS1340_BIT_CENTURY_EN;
490 if (t->tm_year > 199)
491 buf[DS1307_REG_HOUR] |= DS1340_BIT_CENTURY;
492 break;
493 case mcp794xx:
494 /*
495 * these bits were cleared when preparing the date/time
496 * values and need to be set again before writing the
497 * buffer out to the device.
498 */
499 buf[DS1307_REG_SECS] |= MCP794XX_BIT_ST;
500 buf[DS1307_REG_WDAY] |= MCP794XX_BIT_VBATEN;
501 break;
502 default:
503 break;
504 }
505
506 dev_dbg(dev, "%s: %7ph\n", "write", buf);
507
508 result = ds1307->write_block_data(ds1307->client,
509 ds1307->offset, 7, buf);
510 if (result < 0) {
511 dev_err(dev, "%s error %d\n", "write", result);
512 return result;
513 }
514 return 0;
515}
516
517static int ds1337_read_alarm(struct device *dev, struct rtc_wkalrm *t)
518{
519 struct i2c_client *client = to_i2c_client(dev);
520 struct ds1307 *ds1307 = i2c_get_clientdata(client);
521 int ret;
522
523 if (!test_bit(HAS_ALARM, &ds1307->flags))
524 return -EINVAL;
525
526 /* read all ALARM1, ALARM2, and status registers at once */
527 ret = ds1307->read_block_data(client,
528 DS1339_REG_ALARM1_SECS, 9, ds1307->regs);
529 if (ret != 9) {
530 dev_err(dev, "%s error %d\n", "alarm read", ret);
531 return -EIO;
532 }
533
534 dev_dbg(dev, "%s: %4ph, %3ph, %2ph\n", "alarm read",
535 &ds1307->regs[0], &ds1307->regs[4], &ds1307->regs[7]);
536
537 /*
538 * report alarm time (ALARM1); assume 24 hour and day-of-month modes,
539 * and that all four fields are checked matches
540 */
541 t->time.tm_sec = bcd2bin(ds1307->regs[0] & 0x7f);
542 t->time.tm_min = bcd2bin(ds1307->regs[1] & 0x7f);
543 t->time.tm_hour = bcd2bin(ds1307->regs[2] & 0x3f);
544 t->time.tm_mday = bcd2bin(ds1307->regs[3] & 0x3f);
545
546 /* ... and status */
547 t->enabled = !!(ds1307->regs[7] & DS1337_BIT_A1IE);
548 t->pending = !!(ds1307->regs[8] & DS1337_BIT_A1I);
549
550 dev_dbg(dev, "%s secs=%d, mins=%d, "
551 "hours=%d, mday=%d, enabled=%d, pending=%d\n",
552 "alarm read", t->time.tm_sec, t->time.tm_min,
553 t->time.tm_hour, t->time.tm_mday,
554 t->enabled, t->pending);
555
556 return 0;
557}
558
559static int ds1337_set_alarm(struct device *dev, struct rtc_wkalrm *t)
560{
561 struct i2c_client *client = to_i2c_client(dev);
562 struct ds1307 *ds1307 = i2c_get_clientdata(client);
563 unsigned char *buf = ds1307->regs;
564 u8 control, status;
565 int ret;
566
567 if (!test_bit(HAS_ALARM, &ds1307->flags))
568 return -EINVAL;
569
570 dev_dbg(dev, "%s secs=%d, mins=%d, "
571 "hours=%d, mday=%d, enabled=%d, pending=%d\n",
572 "alarm set", t->time.tm_sec, t->time.tm_min,
573 t->time.tm_hour, t->time.tm_mday,
574 t->enabled, t->pending);
575
576 /* read current status of both alarms and the chip */
577 ret = ds1307->read_block_data(client,
578 DS1339_REG_ALARM1_SECS, 9, buf);
579 if (ret != 9) {
580 dev_err(dev, "%s error %d\n", "alarm write", ret);
581 return -EIO;
582 }
583 control = ds1307->regs[7];
584 status = ds1307->regs[8];
585
586 dev_dbg(dev, "%s: %4ph, %3ph, %02x %02x\n", "alarm set (old status)",
587 &ds1307->regs[0], &ds1307->regs[4], control, status);
588
589 /* set ALARM1, using 24 hour and day-of-month modes */
590 buf[0] = bin2bcd(t->time.tm_sec);
591 buf[1] = bin2bcd(t->time.tm_min);
592 buf[2] = bin2bcd(t->time.tm_hour);
593 buf[3] = bin2bcd(t->time.tm_mday);
594
595 /* set ALARM2 to non-garbage */
596 buf[4] = 0;
597 buf[5] = 0;
598 buf[6] = 0;
599
600 /* disable alarms */
601 buf[7] = control & ~(DS1337_BIT_A1IE | DS1337_BIT_A2IE);
602 buf[8] = status & ~(DS1337_BIT_A1I | DS1337_BIT_A2I);
603
604 ret = ds1307->write_block_data(client,
605 DS1339_REG_ALARM1_SECS, 9, buf);
606 if (ret < 0) {
607 dev_err(dev, "can't set alarm time\n");
608 return ret;
609 }
610
611 /* optionally enable ALARM1 */
612 if (t->enabled) {
613 dev_dbg(dev, "alarm IRQ armed\n");
614 buf[7] |= DS1337_BIT_A1IE; /* only ALARM1 is used */
615 i2c_smbus_write_byte_data(client, DS1337_REG_CONTROL, buf[7]);
616 }
617
618 return 0;
619}
620
621static int ds1307_alarm_irq_enable(struct device *dev, unsigned int enabled)
622{
623 struct i2c_client *client = to_i2c_client(dev);
624 struct ds1307 *ds1307 = i2c_get_clientdata(client);
625 int ret;
626
627 if (!test_bit(HAS_ALARM, &ds1307->flags))
628 return -ENOTTY;
629
630 ret = i2c_smbus_read_byte_data(client, DS1337_REG_CONTROL);
631 if (ret < 0)
632 return ret;
633
634 if (enabled)
635 ret |= DS1337_BIT_A1IE;
636 else
637 ret &= ~DS1337_BIT_A1IE;
638
639 ret = i2c_smbus_write_byte_data(client, DS1337_REG_CONTROL, ret);
640 if (ret < 0)
641 return ret;
642
643 return 0;
644}
645
646static const struct rtc_class_ops ds13xx_rtc_ops = {
647 .read_time = ds1307_get_time,
648 .set_time = ds1307_set_time,
649 .read_alarm = ds1337_read_alarm,
650 .set_alarm = ds1337_set_alarm,
651 .alarm_irq_enable = ds1307_alarm_irq_enable,
652};
653
654/*----------------------------------------------------------------------*/
655
656/*
657 * Alarm support for mcp794xx devices.
658 */
659
660#define MCP794XX_REG_WEEKDAY 0x3
661#define MCP794XX_REG_WEEKDAY_WDAY_MASK 0x7
662#define MCP794XX_REG_CONTROL 0x07
663# define MCP794XX_BIT_ALM0_EN 0x10
664# define MCP794XX_BIT_ALM1_EN 0x20
665#define MCP794XX_REG_ALARM0_BASE 0x0a
666#define MCP794XX_REG_ALARM0_CTRL 0x0d
667#define MCP794XX_REG_ALARM1_BASE 0x11
668#define MCP794XX_REG_ALARM1_CTRL 0x14
669# define MCP794XX_BIT_ALMX_IF (1 << 3)
670# define MCP794XX_BIT_ALMX_C0 (1 << 4)
671# define MCP794XX_BIT_ALMX_C1 (1 << 5)
672# define MCP794XX_BIT_ALMX_C2 (1 << 6)
673# define MCP794XX_BIT_ALMX_POL (1 << 7)
674# define MCP794XX_MSK_ALMX_MATCH (MCP794XX_BIT_ALMX_C0 | \
675 MCP794XX_BIT_ALMX_C1 | \
676 MCP794XX_BIT_ALMX_C2)
677
678static irqreturn_t mcp794xx_irq(int irq, void *dev_id)
679{
680 struct i2c_client *client = dev_id;
681 struct ds1307 *ds1307 = i2c_get_clientdata(client);
682 struct mutex *lock = &ds1307->rtc->ops_lock;
683 int reg, ret;
684
685 mutex_lock(lock);
686
687 /* Check and clear alarm 0 interrupt flag. */
688 reg = i2c_smbus_read_byte_data(client, MCP794XX_REG_ALARM0_CTRL);
689 if (reg < 0)
690 goto out;
691 if (!(reg & MCP794XX_BIT_ALMX_IF))
692 goto out;
693 reg &= ~MCP794XX_BIT_ALMX_IF;
694 ret = i2c_smbus_write_byte_data(client, MCP794XX_REG_ALARM0_CTRL, reg);
695 if (ret < 0)
696 goto out;
697
698 /* Disable alarm 0. */
699 reg = i2c_smbus_read_byte_data(client, MCP794XX_REG_CONTROL);
700 if (reg < 0)
701 goto out;
702 reg &= ~MCP794XX_BIT_ALM0_EN;
703 ret = i2c_smbus_write_byte_data(client, MCP794XX_REG_CONTROL, reg);
704 if (ret < 0)
705 goto out;
706
707 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
708
709out:
710 mutex_unlock(lock);
711
712 return IRQ_HANDLED;
713}
714
715static int mcp794xx_read_alarm(struct device *dev, struct rtc_wkalrm *t)
716{
717 struct i2c_client *client = to_i2c_client(dev);
718 struct ds1307 *ds1307 = i2c_get_clientdata(client);
719 u8 *regs = ds1307->regs;
720 int ret;
721
722 if (!test_bit(HAS_ALARM, &ds1307->flags))
723 return -EINVAL;
724
725 /* Read control and alarm 0 registers. */
726 ret = ds1307->read_block_data(client, MCP794XX_REG_CONTROL, 10, regs);
727 if (ret < 0)
728 return ret;
729
730 t->enabled = !!(regs[0] & MCP794XX_BIT_ALM0_EN);
731
732 /* Report alarm 0 time assuming 24-hour and day-of-month modes. */
733 t->time.tm_sec = bcd2bin(ds1307->regs[3] & 0x7f);
734 t->time.tm_min = bcd2bin(ds1307->regs[4] & 0x7f);
735 t->time.tm_hour = bcd2bin(ds1307->regs[5] & 0x3f);
736 t->time.tm_wday = bcd2bin(ds1307->regs[6] & 0x7) - 1;
737 t->time.tm_mday = bcd2bin(ds1307->regs[7] & 0x3f);
738 t->time.tm_mon = bcd2bin(ds1307->regs[8] & 0x1f) - 1;
739 t->time.tm_year = -1;
740 t->time.tm_yday = -1;
741 t->time.tm_isdst = -1;
742
743 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
744 "enabled=%d polarity=%d irq=%d match=%d\n", __func__,
745 t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
746 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled,
747 !!(ds1307->regs[6] & MCP794XX_BIT_ALMX_POL),
748 !!(ds1307->regs[6] & MCP794XX_BIT_ALMX_IF),
749 (ds1307->regs[6] & MCP794XX_MSK_ALMX_MATCH) >> 4);
750
751 return 0;
752}
753
754static int mcp794xx_set_alarm(struct device *dev, struct rtc_wkalrm *t)
755{
756 struct i2c_client *client = to_i2c_client(dev);
757 struct ds1307 *ds1307 = i2c_get_clientdata(client);
758 unsigned char *regs = ds1307->regs;
759 int ret;
760
761 if (!test_bit(HAS_ALARM, &ds1307->flags))
762 return -EINVAL;
763
764 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
765 "enabled=%d pending=%d\n", __func__,
766 t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
767 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon,
768 t->enabled, t->pending);
769
770 /* Read control and alarm 0 registers. */
771 ret = ds1307->read_block_data(client, MCP794XX_REG_CONTROL, 10, regs);
772 if (ret < 0)
773 return ret;
774
775 /* Set alarm 0, using 24-hour and day-of-month modes. */
776 regs[3] = bin2bcd(t->time.tm_sec);
777 regs[4] = bin2bcd(t->time.tm_min);
778 regs[5] = bin2bcd(t->time.tm_hour);
779 regs[6] = bin2bcd(t->time.tm_wday + 1);
780 regs[7] = bin2bcd(t->time.tm_mday);
781 regs[8] = bin2bcd(t->time.tm_mon + 1);
782
783 /* Clear the alarm 0 interrupt flag. */
784 regs[6] &= ~MCP794XX_BIT_ALMX_IF;
785 /* Set alarm match: second, minute, hour, day, date, month. */
786 regs[6] |= MCP794XX_MSK_ALMX_MATCH;
787 /* Disable interrupt. We will not enable until completely programmed */
788 regs[0] &= ~MCP794XX_BIT_ALM0_EN;
789
790 ret = ds1307->write_block_data(client, MCP794XX_REG_CONTROL, 10, regs);
791 if (ret < 0)
792 return ret;
793
794 if (!t->enabled)
795 return 0;
796 regs[0] |= MCP794XX_BIT_ALM0_EN;
797 return i2c_smbus_write_byte_data(client, MCP794XX_REG_CONTROL, regs[0]);
798}
799
800static int mcp794xx_alarm_irq_enable(struct device *dev, unsigned int enabled)
801{
802 struct i2c_client *client = to_i2c_client(dev);
803 struct ds1307 *ds1307 = i2c_get_clientdata(client);
804 int reg;
805
806 if (!test_bit(HAS_ALARM, &ds1307->flags))
807 return -EINVAL;
808
809 reg = i2c_smbus_read_byte_data(client, MCP794XX_REG_CONTROL);
810 if (reg < 0)
811 return reg;
812
813 if (enabled)
814 reg |= MCP794XX_BIT_ALM0_EN;
815 else
816 reg &= ~MCP794XX_BIT_ALM0_EN;
817
818 return i2c_smbus_write_byte_data(client, MCP794XX_REG_CONTROL, reg);
819}
820
821static const struct rtc_class_ops mcp794xx_rtc_ops = {
822 .read_time = ds1307_get_time,
823 .set_time = ds1307_set_time,
824 .read_alarm = mcp794xx_read_alarm,
825 .set_alarm = mcp794xx_set_alarm,
826 .alarm_irq_enable = mcp794xx_alarm_irq_enable,
827};
828
829/*----------------------------------------------------------------------*/
830
831static ssize_t
832ds1307_nvram_read(struct file *filp, struct kobject *kobj,
833 struct bin_attribute *attr,
834 char *buf, loff_t off, size_t count)
835{
836 struct i2c_client *client;
837 struct ds1307 *ds1307;
838 int result;
839
840 client = kobj_to_i2c_client(kobj);
841 ds1307 = i2c_get_clientdata(client);
842
843 result = ds1307->read_block_data(client, ds1307->nvram_offset + off,
844 count, buf);
845 if (result < 0)
846 dev_err(&client->dev, "%s error %d\n", "nvram read", result);
847 return result;
848}
849
850static ssize_t
851ds1307_nvram_write(struct file *filp, struct kobject *kobj,
852 struct bin_attribute *attr,
853 char *buf, loff_t off, size_t count)
854{
855 struct i2c_client *client;
856 struct ds1307 *ds1307;
857 int result;
858
859 client = kobj_to_i2c_client(kobj);
860 ds1307 = i2c_get_clientdata(client);
861
862 result = ds1307->write_block_data(client, ds1307->nvram_offset + off,
863 count, buf);
864 if (result < 0) {
865 dev_err(&client->dev, "%s error %d\n", "nvram write", result);
866 return result;
867 }
868 return count;
869}
870
871
872/*----------------------------------------------------------------------*/
873
874static u8 do_trickle_setup_ds1339(struct i2c_client *client,
875 uint32_t ohms, bool diode)
876{
877 u8 setup = (diode) ? DS1307_TRICKLE_CHARGER_DIODE :
878 DS1307_TRICKLE_CHARGER_NO_DIODE;
879
880 switch (ohms) {
881 case 250:
882 setup |= DS1307_TRICKLE_CHARGER_250_OHM;
883 break;
884 case 2000:
885 setup |= DS1307_TRICKLE_CHARGER_2K_OHM;
886 break;
887 case 4000:
888 setup |= DS1307_TRICKLE_CHARGER_4K_OHM;
889 break;
890 default:
891 dev_warn(&client->dev,
892 "Unsupported ohm value %u in dt\n", ohms);
893 return 0;
894 }
895 return setup;
896}
897
898static void ds1307_trickle_init(struct i2c_client *client,
899 struct chip_desc *chip)
900{
901 uint32_t ohms = 0;
902 bool diode = true;
903
904 if (!chip->do_trickle_setup)
905 goto out;
906 if (device_property_read_u32(&client->dev, "trickle-resistor-ohms", &ohms))
907 goto out;
908 if (device_property_read_bool(&client->dev, "trickle-diode-disable"))
909 diode = false;
910 chip->trickle_charger_setup = chip->do_trickle_setup(client,
911 ohms, diode);
912out:
913 return;
914}
915
916/*----------------------------------------------------------------------*/
917
918#ifdef CONFIG_RTC_DRV_DS1307_HWMON
919
920/*
921 * Temperature sensor support for ds3231 devices.
922 */
923
924#define DS3231_REG_TEMPERATURE 0x11
925
926/*
927 * A user-initiated temperature conversion is not started by this function,
928 * so the temperature is updated once every 64 seconds.
929 */
930static int ds3231_hwmon_read_temp(struct device *dev, s32 *mC)
931{
932 struct ds1307 *ds1307 = dev_get_drvdata(dev);
933 u8 temp_buf[2];
934 s16 temp;
935 int ret;
936
937 ret = ds1307->read_block_data(ds1307->client, DS3231_REG_TEMPERATURE,
938 sizeof(temp_buf), temp_buf);
939 if (ret < 0)
940 return ret;
941 if (ret != sizeof(temp_buf))
942 return -EIO;
943
944 /*
945 * Temperature is represented as a 10-bit code with a resolution of
946 * 0.25 degree celsius and encoded in two's complement format.
947 */
948 temp = (temp_buf[0] << 8) | temp_buf[1];
949 temp >>= 6;
950 *mC = temp * 250;
951
952 return 0;
953}
954
955static ssize_t ds3231_hwmon_show_temp(struct device *dev,
956 struct device_attribute *attr, char *buf)
957{
958 int ret;
959 s32 temp;
960
961 ret = ds3231_hwmon_read_temp(dev, &temp);
962 if (ret)
963 return ret;
964
965 return sprintf(buf, "%d\n", temp);
966}
967static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, ds3231_hwmon_show_temp,
968 NULL, 0);
969
970static struct attribute *ds3231_hwmon_attrs[] = {
971 &sensor_dev_attr_temp1_input.dev_attr.attr,
972 NULL,
973};
974ATTRIBUTE_GROUPS(ds3231_hwmon);
975
976static void ds1307_hwmon_register(struct ds1307 *ds1307)
977{
978 struct device *dev;
979
980 if (ds1307->type != ds_3231)
981 return;
982
983 dev = devm_hwmon_device_register_with_groups(&ds1307->client->dev,
984 ds1307->client->name,
985 ds1307, ds3231_hwmon_groups);
986 if (IS_ERR(dev)) {
987 dev_warn(&ds1307->client->dev,
988 "unable to register hwmon device %ld\n", PTR_ERR(dev));
989 }
990}
991
992#else
993
994static void ds1307_hwmon_register(struct ds1307 *ds1307)
995{
996}
997
998#endif /* CONFIG_RTC_DRV_DS1307_HWMON */
999
1000/*----------------------------------------------------------------------*/
1001
1002/*
1003 * Square-wave output support for DS3231
1004 * Datasheet: https://datasheets.maximintegrated.com/en/ds/DS3231.pdf
1005 */
1006#ifdef CONFIG_COMMON_CLK
1007
1008enum {
1009 DS3231_CLK_SQW = 0,
1010 DS3231_CLK_32KHZ,
1011};
1012
1013#define clk_sqw_to_ds1307(clk) \
1014 container_of(clk, struct ds1307, clks[DS3231_CLK_SQW])
1015#define clk_32khz_to_ds1307(clk) \
1016 container_of(clk, struct ds1307, clks[DS3231_CLK_32KHZ])
1017
1018static int ds3231_clk_sqw_rates[] = {
1019 1,
1020 1024,
1021 4096,
1022 8192,
1023};
1024
1025static int ds1337_write_control(struct ds1307 *ds1307, u8 mask, u8 value)
1026{
1027 struct i2c_client *client = ds1307->client;
1028 struct mutex *lock = &ds1307->rtc->ops_lock;
1029 int control;
1030 int ret;
1031
1032 mutex_lock(lock);
1033
1034 control = i2c_smbus_read_byte_data(client, DS1337_REG_CONTROL);
1035 if (control < 0) {
1036 ret = control;
1037 goto out;
1038 }
1039
1040 control &= ~mask;
1041 control |= value;
1042
1043 ret = i2c_smbus_write_byte_data(client, DS1337_REG_CONTROL, control);
1044out:
1045 mutex_unlock(lock);
1046
1047 return ret;
1048}
1049
1050static unsigned long ds3231_clk_sqw_recalc_rate(struct clk_hw *hw,
1051 unsigned long parent_rate)
1052{
1053 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1054 int control;
1055 int rate_sel = 0;
1056
1057 control = i2c_smbus_read_byte_data(ds1307->client, DS1337_REG_CONTROL);
1058 if (control < 0)
1059 return control;
1060 if (control & DS1337_BIT_RS1)
1061 rate_sel += 1;
1062 if (control & DS1337_BIT_RS2)
1063 rate_sel += 2;
1064
1065 return ds3231_clk_sqw_rates[rate_sel];
1066}
1067
1068static long ds3231_clk_sqw_round_rate(struct clk_hw *hw, unsigned long rate,
1069 unsigned long *prate)
1070{
1071 int i;
1072
1073 for (i = ARRAY_SIZE(ds3231_clk_sqw_rates) - 1; i >= 0; i--) {
1074 if (ds3231_clk_sqw_rates[i] <= rate)
1075 return ds3231_clk_sqw_rates[i];
1076 }
1077
1078 return 0;
1079}
1080
1081static int ds3231_clk_sqw_set_rate(struct clk_hw *hw, unsigned long rate,
1082 unsigned long parent_rate)
1083{
1084 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1085 int control = 0;
1086 int rate_sel;
1087
1088 for (rate_sel = 0; rate_sel < ARRAY_SIZE(ds3231_clk_sqw_rates);
1089 rate_sel++) {
1090 if (ds3231_clk_sqw_rates[rate_sel] == rate)
1091 break;
1092 }
1093
1094 if (rate_sel == ARRAY_SIZE(ds3231_clk_sqw_rates))
1095 return -EINVAL;
1096
1097 if (rate_sel & 1)
1098 control |= DS1337_BIT_RS1;
1099 if (rate_sel & 2)
1100 control |= DS1337_BIT_RS2;
1101
1102 return ds1337_write_control(ds1307, DS1337_BIT_RS1 | DS1337_BIT_RS2,
1103 control);
1104}
1105
1106static int ds3231_clk_sqw_prepare(struct clk_hw *hw)
1107{
1108 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1109
1110 return ds1337_write_control(ds1307, DS1337_BIT_INTCN, 0);
1111}
1112
1113static void ds3231_clk_sqw_unprepare(struct clk_hw *hw)
1114{
1115 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1116
1117 ds1337_write_control(ds1307, DS1337_BIT_INTCN, DS1337_BIT_INTCN);
1118}
1119
1120static int ds3231_clk_sqw_is_prepared(struct clk_hw *hw)
1121{
1122 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1123 int control;
1124
1125 control = i2c_smbus_read_byte_data(ds1307->client, DS1337_REG_CONTROL);
1126 if (control < 0)
1127 return control;
1128
1129 return !(control & DS1337_BIT_INTCN);
1130}
1131
1132static const struct clk_ops ds3231_clk_sqw_ops = {
1133 .prepare = ds3231_clk_sqw_prepare,
1134 .unprepare = ds3231_clk_sqw_unprepare,
1135 .is_prepared = ds3231_clk_sqw_is_prepared,
1136 .recalc_rate = ds3231_clk_sqw_recalc_rate,
1137 .round_rate = ds3231_clk_sqw_round_rate,
1138 .set_rate = ds3231_clk_sqw_set_rate,
1139};
1140
1141static unsigned long ds3231_clk_32khz_recalc_rate(struct clk_hw *hw,
1142 unsigned long parent_rate)
1143{
1144 return 32768;
1145}
1146
1147static int ds3231_clk_32khz_control(struct ds1307 *ds1307, bool enable)
1148{
1149 struct i2c_client *client = ds1307->client;
1150 struct mutex *lock = &ds1307->rtc->ops_lock;
1151 int status;
1152 int ret;
1153
1154 mutex_lock(lock);
1155
1156 status = i2c_smbus_read_byte_data(client, DS1337_REG_STATUS);
1157 if (status < 0) {
1158 ret = status;
1159 goto out;
1160 }
1161
1162 if (enable)
1163 status |= DS3231_BIT_EN32KHZ;
1164 else
1165 status &= ~DS3231_BIT_EN32KHZ;
1166
1167 ret = i2c_smbus_write_byte_data(client, DS1337_REG_STATUS, status);
1168out:
1169 mutex_unlock(lock);
1170
1171 return ret;
1172}
1173
1174static int ds3231_clk_32khz_prepare(struct clk_hw *hw)
1175{
1176 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
1177
1178 return ds3231_clk_32khz_control(ds1307, true);
1179}
1180
1181static void ds3231_clk_32khz_unprepare(struct clk_hw *hw)
1182{
1183 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
1184
1185 ds3231_clk_32khz_control(ds1307, false);
1186}
1187
1188static int ds3231_clk_32khz_is_prepared(struct clk_hw *hw)
1189{
1190 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
1191 int status;
1192
1193 status = i2c_smbus_read_byte_data(ds1307->client, DS1337_REG_STATUS);
1194 if (status < 0)
1195 return status;
1196
1197 return !!(status & DS3231_BIT_EN32KHZ);
1198}
1199
1200static const struct clk_ops ds3231_clk_32khz_ops = {
1201 .prepare = ds3231_clk_32khz_prepare,
1202 .unprepare = ds3231_clk_32khz_unprepare,
1203 .is_prepared = ds3231_clk_32khz_is_prepared,
1204 .recalc_rate = ds3231_clk_32khz_recalc_rate,
1205};
1206
1207static struct clk_init_data ds3231_clks_init[] = {
1208 [DS3231_CLK_SQW] = {
1209 .name = "ds3231_clk_sqw",
1210 .ops = &ds3231_clk_sqw_ops,
1211 },
1212 [DS3231_CLK_32KHZ] = {
1213 .name = "ds3231_clk_32khz",
1214 .ops = &ds3231_clk_32khz_ops,
1215 },
1216};
1217
1218static int ds3231_clks_register(struct ds1307 *ds1307)
1219{
1220 struct i2c_client *client = ds1307->client;
1221 struct device_node *node = client->dev.of_node;
1222 struct clk_onecell_data *onecell;
1223 int i;
1224
1225 onecell = devm_kzalloc(&client->dev, sizeof(*onecell), GFP_KERNEL);
1226 if (!onecell)
1227 return -ENOMEM;
1228
1229 onecell->clk_num = ARRAY_SIZE(ds3231_clks_init);
1230 onecell->clks = devm_kcalloc(&client->dev, onecell->clk_num,
1231 sizeof(onecell->clks[0]), GFP_KERNEL);
1232 if (!onecell->clks)
1233 return -ENOMEM;
1234
1235 for (i = 0; i < ARRAY_SIZE(ds3231_clks_init); i++) {
1236 struct clk_init_data init = ds3231_clks_init[i];
1237
1238 /*
1239 * Interrupt signal due to alarm conditions and square-wave
1240 * output share same pin, so don't initialize both.
1241 */
1242 if (i == DS3231_CLK_SQW && test_bit(HAS_ALARM, &ds1307->flags))
1243 continue;
1244
1245 /* optional override of the clockname */
1246 of_property_read_string_index(node, "clock-output-names", i,
1247 &init.name);
1248 ds1307->clks[i].init = &init;
1249
1250 onecell->clks[i] = devm_clk_register(&client->dev,
1251 &ds1307->clks[i]);
1252 if (IS_ERR(onecell->clks[i]))
1253 return PTR_ERR(onecell->clks[i]);
1254 }
1255
1256 if (!node)
1257 return 0;
1258
1259 of_clk_add_provider(node, of_clk_src_onecell_get, onecell);
1260
1261 return 0;
1262}
1263
1264static void ds1307_clks_register(struct ds1307 *ds1307)
1265{
1266 int ret;
1267
1268 if (ds1307->type != ds_3231)
1269 return;
1270
1271 ret = ds3231_clks_register(ds1307);
1272 if (ret) {
1273 dev_warn(&ds1307->client->dev,
1274 "unable to register clock device %d\n", ret);
1275 }
1276}
1277
1278#else
1279
1280static void ds1307_clks_register(struct ds1307 *ds1307)
1281{
1282}
1283
1284#endif /* CONFIG_COMMON_CLK */
1285
1286static int ds1307_probe(struct i2c_client *client,
1287 const struct i2c_device_id *id)
1288{
1289 struct ds1307 *ds1307;
1290 int err = -ENODEV;
1291 int tmp, wday;
1292 struct chip_desc *chip;
1293 struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent);
1294 bool want_irq = false;
1295 bool ds1307_can_wakeup_device = false;
1296 unsigned char *buf;
1297 struct ds1307_platform_data *pdata = dev_get_platdata(&client->dev);
1298 struct rtc_time tm;
1299 unsigned long timestamp;
1300
1301 irq_handler_t irq_handler = ds1307_irq;
1302
1303 static const int bbsqi_bitpos[] = {
1304 [ds_1337] = 0,
1305 [ds_1339] = DS1339_BIT_BBSQI,
1306 [ds_3231] = DS3231_BIT_BBSQW,
1307 };
1308 const struct rtc_class_ops *rtc_ops = &ds13xx_rtc_ops;
1309
1310 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)
1311 && !i2c_check_functionality(adapter, I2C_FUNC_SMBUS_I2C_BLOCK))
1312 return -EIO;
1313
1314 ds1307 = devm_kzalloc(&client->dev, sizeof(struct ds1307), GFP_KERNEL);
1315 if (!ds1307)
1316 return -ENOMEM;
1317
1318 i2c_set_clientdata(client, ds1307);
1319
1320 ds1307->client = client;
1321 if (id) {
1322 chip = &chips[id->driver_data];
1323 ds1307->type = id->driver_data;
1324 } else {
1325 const struct acpi_device_id *acpi_id;
1326
1327 acpi_id = acpi_match_device(ACPI_PTR(ds1307_acpi_ids),
1328 &client->dev);
1329 if (!acpi_id)
1330 return -ENODEV;
1331 chip = &chips[acpi_id->driver_data];
1332 ds1307->type = acpi_id->driver_data;
1333 }
1334
1335 if (!pdata)
1336 ds1307_trickle_init(client, chip);
1337 else if (pdata->trickle_charger_setup)
1338 chip->trickle_charger_setup = pdata->trickle_charger_setup;
1339
1340 if (chip->trickle_charger_setup && chip->trickle_charger_reg) {
1341 dev_dbg(&client->dev, "writing trickle charger info 0x%x to 0x%x\n",
1342 DS13XX_TRICKLE_CHARGER_MAGIC | chip->trickle_charger_setup,
1343 chip->trickle_charger_reg);
1344 i2c_smbus_write_byte_data(client, chip->trickle_charger_reg,
1345 DS13XX_TRICKLE_CHARGER_MAGIC |
1346 chip->trickle_charger_setup);
1347 }
1348
1349 buf = ds1307->regs;
1350 if (i2c_check_functionality(adapter, I2C_FUNC_SMBUS_I2C_BLOCK)) {
1351 ds1307->read_block_data = ds1307_native_smbus_read_block_data;
1352 ds1307->write_block_data = ds1307_native_smbus_write_block_data;
1353 } else {
1354 ds1307->read_block_data = ds1307_read_block_data;
1355 ds1307->write_block_data = ds1307_write_block_data;
1356 }
1357
1358#ifdef CONFIG_OF
1359/*
1360 * For devices with no IRQ directly connected to the SoC, the RTC chip
1361 * can be forced as a wakeup source by stating that explicitly in
1362 * the device's .dts file using the "wakeup-source" boolean property.
1363 * If the "wakeup-source" property is set, don't request an IRQ.
1364 * This will guarantee the 'wakealarm' sysfs entry is available on the device,
1365 * if supported by the RTC.
1366 */
1367 if (of_property_read_bool(client->dev.of_node, "wakeup-source")) {
1368 ds1307_can_wakeup_device = true;
1369 }
1370 /* Intersil ISL12057 DT backward compatibility */
1371 if (of_property_read_bool(client->dev.of_node,
1372 "isil,irq2-can-wakeup-machine")) {
1373 ds1307_can_wakeup_device = true;
1374 }
1375#endif
1376
1377 switch (ds1307->type) {
1378 case ds_1337:
1379 case ds_1339:
1380 case ds_3231:
1381 /* get registers that the "rtc" read below won't read... */
1382 tmp = ds1307->read_block_data(ds1307->client,
1383 DS1337_REG_CONTROL, 2, buf);
1384 if (tmp != 2) {
1385 dev_dbg(&client->dev, "read error %d\n", tmp);
1386 err = -EIO;
1387 goto exit;
1388 }
1389
1390 /* oscillator off? turn it on, so clock can tick. */
1391 if (ds1307->regs[0] & DS1337_BIT_nEOSC)
1392 ds1307->regs[0] &= ~DS1337_BIT_nEOSC;
1393
1394 /*
1395 * Using IRQ or defined as wakeup-source?
1396 * Disable the square wave and both alarms.
1397 * For some variants, be sure alarms can trigger when we're
1398 * running on Vbackup (BBSQI/BBSQW)
1399 */
1400 if (chip->alarm && (ds1307->client->irq > 0 ||
1401 ds1307_can_wakeup_device)) {
1402 ds1307->regs[0] |= DS1337_BIT_INTCN
1403 | bbsqi_bitpos[ds1307->type];
1404 ds1307->regs[0] &= ~(DS1337_BIT_A2IE | DS1337_BIT_A1IE);
1405
1406 want_irq = true;
1407 }
1408
1409 i2c_smbus_write_byte_data(client, DS1337_REG_CONTROL,
1410 ds1307->regs[0]);
1411
1412 /* oscillator fault? clear flag, and warn */
1413 if (ds1307->regs[1] & DS1337_BIT_OSF) {
1414 i2c_smbus_write_byte_data(client, DS1337_REG_STATUS,
1415 ds1307->regs[1] & ~DS1337_BIT_OSF);
1416 dev_warn(&client->dev, "SET TIME!\n");
1417 }
1418 break;
1419
1420 case rx_8025:
1421 tmp = i2c_smbus_read_i2c_block_data(ds1307->client,
1422 RX8025_REG_CTRL1 << 4 | 0x08, 2, buf);
1423 if (tmp != 2) {
1424 dev_dbg(&client->dev, "read error %d\n", tmp);
1425 err = -EIO;
1426 goto exit;
1427 }
1428
1429 /* oscillator off? turn it on, so clock can tick. */
1430 if (!(ds1307->regs[1] & RX8025_BIT_XST)) {
1431 ds1307->regs[1] |= RX8025_BIT_XST;
1432 i2c_smbus_write_byte_data(client,
1433 RX8025_REG_CTRL2 << 4 | 0x08,
1434 ds1307->regs[1]);
1435 dev_warn(&client->dev,
1436 "oscillator stop detected - SET TIME!\n");
1437 }
1438
1439 if (ds1307->regs[1] & RX8025_BIT_PON) {
1440 ds1307->regs[1] &= ~RX8025_BIT_PON;
1441 i2c_smbus_write_byte_data(client,
1442 RX8025_REG_CTRL2 << 4 | 0x08,
1443 ds1307->regs[1]);
1444 dev_warn(&client->dev, "power-on detected\n");
1445 }
1446
1447 if (ds1307->regs[1] & RX8025_BIT_VDET) {
1448 ds1307->regs[1] &= ~RX8025_BIT_VDET;
1449 i2c_smbus_write_byte_data(client,
1450 RX8025_REG_CTRL2 << 4 | 0x08,
1451 ds1307->regs[1]);
1452 dev_warn(&client->dev, "voltage drop detected\n");
1453 }
1454
1455 /* make sure we are running in 24hour mode */
1456 if (!(ds1307->regs[0] & RX8025_BIT_2412)) {
1457 u8 hour;
1458
1459 /* switch to 24 hour mode */
1460 i2c_smbus_write_byte_data(client,
1461 RX8025_REG_CTRL1 << 4 | 0x08,
1462 ds1307->regs[0] |
1463 RX8025_BIT_2412);
1464
1465 tmp = i2c_smbus_read_i2c_block_data(ds1307->client,
1466 RX8025_REG_CTRL1 << 4 | 0x08, 2, buf);
1467 if (tmp != 2) {
1468 dev_dbg(&client->dev, "read error %d\n", tmp);
1469 err = -EIO;
1470 goto exit;
1471 }
1472
1473 /* correct hour */
1474 hour = bcd2bin(ds1307->regs[DS1307_REG_HOUR]);
1475 if (hour == 12)
1476 hour = 0;
1477 if (ds1307->regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
1478 hour += 12;
1479
1480 i2c_smbus_write_byte_data(client,
1481 DS1307_REG_HOUR << 4 | 0x08,
1482 hour);
1483 }
1484 break;
1485 case ds_1388:
1486 ds1307->offset = 1; /* Seconds starts at 1 */
1487 break;
1488 case mcp794xx:
1489 rtc_ops = &mcp794xx_rtc_ops;
1490 if (ds1307->client->irq > 0 && chip->alarm) {
1491 irq_handler = mcp794xx_irq;
1492 want_irq = true;
1493 }
1494 break;
1495 default:
1496 break;
1497 }
1498
1499read_rtc:
1500 /* read RTC registers */
1501 tmp = ds1307->read_block_data(ds1307->client, ds1307->offset, 8, buf);
1502 if (tmp != 8) {
1503 dev_dbg(&client->dev, "read error %d\n", tmp);
1504 err = -EIO;
1505 goto exit;
1506 }
1507
1508 /*
1509 * minimal sanity checking; some chips (like DS1340) don't
1510 * specify the extra bits as must-be-zero, but there are
1511 * still a few values that are clearly out-of-range.
1512 */
1513 tmp = ds1307->regs[DS1307_REG_SECS];
1514 switch (ds1307->type) {
1515 case ds_1307:
1516 case m41t00:
1517 /* clock halted? turn it on, so clock can tick. */
1518 if (tmp & DS1307_BIT_CH) {
1519 i2c_smbus_write_byte_data(client, DS1307_REG_SECS, 0);
1520 dev_warn(&client->dev, "SET TIME!\n");
1521 goto read_rtc;
1522 }
1523 break;
1524 case ds_1338:
1525 /* clock halted? turn it on, so clock can tick. */
1526 if (tmp & DS1307_BIT_CH)
1527 i2c_smbus_write_byte_data(client, DS1307_REG_SECS, 0);
1528
1529 /* oscillator fault? clear flag, and warn */
1530 if (ds1307->regs[DS1307_REG_CONTROL] & DS1338_BIT_OSF) {
1531 i2c_smbus_write_byte_data(client, DS1307_REG_CONTROL,
1532 ds1307->regs[DS1307_REG_CONTROL]
1533 & ~DS1338_BIT_OSF);
1534 dev_warn(&client->dev, "SET TIME!\n");
1535 goto read_rtc;
1536 }
1537 break;
1538 case ds_1340:
1539 /* clock halted? turn it on, so clock can tick. */
1540 if (tmp & DS1340_BIT_nEOSC)
1541 i2c_smbus_write_byte_data(client, DS1307_REG_SECS, 0);
1542
1543 tmp = i2c_smbus_read_byte_data(client, DS1340_REG_FLAG);
1544 if (tmp < 0) {
1545 dev_dbg(&client->dev, "read error %d\n", tmp);
1546 err = -EIO;
1547 goto exit;
1548 }
1549
1550 /* oscillator fault? clear flag, and warn */
1551 if (tmp & DS1340_BIT_OSF) {
1552 i2c_smbus_write_byte_data(client, DS1340_REG_FLAG, 0);
1553 dev_warn(&client->dev, "SET TIME!\n");
1554 }
1555 break;
1556 case mcp794xx:
1557 /* make sure that the backup battery is enabled */
1558 if (!(ds1307->regs[DS1307_REG_WDAY] & MCP794XX_BIT_VBATEN)) {
1559 i2c_smbus_write_byte_data(client, DS1307_REG_WDAY,
1560 ds1307->regs[DS1307_REG_WDAY]
1561 | MCP794XX_BIT_VBATEN);
1562 }
1563
1564 /* clock halted? turn it on, so clock can tick. */
1565 if (!(tmp & MCP794XX_BIT_ST)) {
1566 i2c_smbus_write_byte_data(client, DS1307_REG_SECS,
1567 MCP794XX_BIT_ST);
1568 dev_warn(&client->dev, "SET TIME!\n");
1569 goto read_rtc;
1570 }
1571
1572 break;
1573 default:
1574 break;
1575 }
1576
1577 tmp = ds1307->regs[DS1307_REG_HOUR];
1578 switch (ds1307->type) {
1579 case ds_1340:
1580 case m41t00:
1581 /*
1582 * NOTE: ignores century bits; fix before deploying
1583 * systems that will run through year 2100.
1584 */
1585 break;
1586 case rx_8025:
1587 break;
1588 default:
1589 if (!(tmp & DS1307_BIT_12HR))
1590 break;
1591
1592 /*
1593 * Be sure we're in 24 hour mode. Multi-master systems
1594 * take note...
1595 */
1596 tmp = bcd2bin(tmp & 0x1f);
1597 if (tmp == 12)
1598 tmp = 0;
1599 if (ds1307->regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
1600 tmp += 12;
1601 i2c_smbus_write_byte_data(client,
1602 ds1307->offset + DS1307_REG_HOUR,
1603 bin2bcd(tmp));
1604 }
1605
1606 /*
1607 * Some IPs have weekday reset value = 0x1 which might not correct
1608 * hence compute the wday using the current date/month/year values
1609 */
1610 ds1307_get_time(&client->dev, &tm);
1611 wday = tm.tm_wday;
1612 timestamp = rtc_tm_to_time64(&tm);
1613 rtc_time64_to_tm(timestamp, &tm);
1614
1615 /*
1616 * Check if reset wday is different from the computed wday
1617 * If different then set the wday which we computed using
1618 * timestamp
1619 */
1620 if (wday != tm.tm_wday) {
1621 wday = i2c_smbus_read_byte_data(client, MCP794XX_REG_WEEKDAY);
1622 wday = wday & ~MCP794XX_REG_WEEKDAY_WDAY_MASK;
1623 wday = wday | (tm.tm_wday + 1);
1624 i2c_smbus_write_byte_data(client, MCP794XX_REG_WEEKDAY, wday);
1625 }
1626
1627 if (want_irq) {
1628 device_set_wakeup_capable(&client->dev, true);
1629 set_bit(HAS_ALARM, &ds1307->flags);
1630 }
1631 ds1307->rtc = devm_rtc_device_register(&client->dev, client->name,
1632 rtc_ops, THIS_MODULE);
1633 if (IS_ERR(ds1307->rtc)) {
1634 return PTR_ERR(ds1307->rtc);
1635 }
1636
1637 if (ds1307_can_wakeup_device && ds1307->client->irq <= 0) {
1638 /* Disable request for an IRQ */
1639 want_irq = false;
1640 dev_info(&client->dev, "'wakeup-source' is set, request for an IRQ is disabled!\n");
1641 /* We cannot support UIE mode if we do not have an IRQ line */
1642 ds1307->rtc->uie_unsupported = 1;
1643 }
1644
1645 if (want_irq) {
1646 err = devm_request_threaded_irq(&client->dev,
1647 client->irq, NULL, irq_handler,
1648 IRQF_SHARED | IRQF_ONESHOT,
1649 ds1307->rtc->name, client);
1650 if (err) {
1651 client->irq = 0;
1652 device_set_wakeup_capable(&client->dev, false);
1653 clear_bit(HAS_ALARM, &ds1307->flags);
1654 dev_err(&client->dev, "unable to request IRQ!\n");
1655 } else
1656 dev_dbg(&client->dev, "got IRQ %d\n", client->irq);
1657 }
1658
1659 if (chip->nvram_size) {
1660
1661 ds1307->nvram = devm_kzalloc(&client->dev,
1662 sizeof(struct bin_attribute),
1663 GFP_KERNEL);
1664 if (!ds1307->nvram) {
1665 dev_err(&client->dev, "cannot allocate memory for nvram sysfs\n");
1666 } else {
1667
1668 ds1307->nvram->attr.name = "nvram";
1669 ds1307->nvram->attr.mode = S_IRUGO | S_IWUSR;
1670
1671 sysfs_bin_attr_init(ds1307->nvram);
1672
1673 ds1307->nvram->read = ds1307_nvram_read;
1674 ds1307->nvram->write = ds1307_nvram_write;
1675 ds1307->nvram->size = chip->nvram_size;
1676 ds1307->nvram_offset = chip->nvram_offset;
1677
1678 err = sysfs_create_bin_file(&client->dev.kobj,
1679 ds1307->nvram);
1680 if (err) {
1681 dev_err(&client->dev,
1682 "unable to create sysfs file: %s\n",
1683 ds1307->nvram->attr.name);
1684 } else {
1685 set_bit(HAS_NVRAM, &ds1307->flags);
1686 dev_info(&client->dev, "%zu bytes nvram\n",
1687 ds1307->nvram->size);
1688 }
1689 }
1690 }
1691
1692 ds1307_hwmon_register(ds1307);
1693 ds1307_clks_register(ds1307);
1694
1695 return 0;
1696
1697exit:
1698 return err;
1699}
1700
1701static int ds1307_remove(struct i2c_client *client)
1702{
1703 struct ds1307 *ds1307 = i2c_get_clientdata(client);
1704
1705 if (test_and_clear_bit(HAS_NVRAM, &ds1307->flags))
1706 sysfs_remove_bin_file(&client->dev.kobj, ds1307->nvram);
1707
1708 return 0;
1709}
1710
1711static struct i2c_driver ds1307_driver = {
1712 .driver = {
1713 .name = "rtc-ds1307",
1714 .acpi_match_table = ACPI_PTR(ds1307_acpi_ids),
1715 },
1716 .probe = ds1307_probe,
1717 .remove = ds1307_remove,
1718 .id_table = ds1307_id,
1719};
1720
1721module_i2c_driver(ds1307_driver);
1722
1723MODULE_DESCRIPTION("RTC driver for DS1307 and similar chips");
1724MODULE_LICENSE("GPL");