1/*
  2 * Copyright (c) 2013-2015, Linux Foundation. All rights reserved.
  3 *
  4 * This program is free software; you can redistribute it and/or modify
  5 * it under the terms of the GNU General Public License version 2 and
  6 * only version 2 as published by the Free Software Foundation.
  7 *
  8 * This program is distributed in the hope that it will be useful,
  9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 11 * GNU General Public License for more details.
 12 *
 13 */
 14
 15#ifndef UFS_QCOM_PHY_QMP_14NM_H_
 16#define UFS_QCOM_PHY_QMP_14NM_H_
 17
 18#include "phy-qcom-ufs-i.h"
 19
 20/* QCOM UFS PHY control registers */
 21#define COM_OFF(x)	(0x000 + x)
 22#define PHY_OFF(x)	(0xC00 + x)
 23#define TX_OFF(n, x)	(0x400 + (0x400 * n) + x)
 24#define RX_OFF(n, x)	(0x600 + (0x400 * n) + x)
 25
 26/* UFS PHY QSERDES COM registers */
 27#define QSERDES_COM_BG_TIMER			COM_OFF(0x0C)
 28#define QSERDES_COM_BIAS_EN_CLKBUFLR_EN		COM_OFF(0x34)
 29#define QSERDES_COM_SYS_CLK_CTRL		COM_OFF(0x3C)
 30#define QSERDES_COM_LOCK_CMP1_MODE0		COM_OFF(0x4C)
 31#define QSERDES_COM_LOCK_CMP2_MODE0		COM_OFF(0x50)
 32#define QSERDES_COM_LOCK_CMP3_MODE0		COM_OFF(0x54)
 33#define QSERDES_COM_LOCK_CMP1_MODE1		COM_OFF(0x58)
 34#define QSERDES_COM_LOCK_CMP2_MODE1		COM_OFF(0x5C)
 35#define QSERDES_COM_LOCK_CMP3_MODE1		COM_OFF(0x60)
 36#define QSERDES_COM_CP_CTRL_MODE0		COM_OFF(0x78)
 37#define QSERDES_COM_CP_CTRL_MODE1		COM_OFF(0x7C)
 38#define QSERDES_COM_PLL_RCTRL_MODE0		COM_OFF(0x84)
 39#define QSERDES_COM_PLL_RCTRL_MODE1		COM_OFF(0x88)
 40#define QSERDES_COM_PLL_CCTRL_MODE0		COM_OFF(0x90)
 41#define QSERDES_COM_PLL_CCTRL_MODE1		COM_OFF(0x94)
 42#define QSERDES_COM_SYSCLK_EN_SEL		COM_OFF(0xAC)
 43#define QSERDES_COM_RESETSM_CNTRL		COM_OFF(0xB4)
 44#define QSERDES_COM_LOCK_CMP_EN			COM_OFF(0xC8)
 45#define QSERDES_COM_LOCK_CMP_CFG		COM_OFF(0xCC)
 46#define QSERDES_COM_DEC_START_MODE0		COM_OFF(0xD0)
 47#define QSERDES_COM_DEC_START_MODE1		COM_OFF(0xD4)
 48#define QSERDES_COM_DIV_FRAC_START1_MODE0	COM_OFF(0xDC)
 49#define QSERDES_COM_DIV_FRAC_START2_MODE0	COM_OFF(0xE0)
 50#define QSERDES_COM_DIV_FRAC_START3_MODE0	COM_OFF(0xE4)
 51#define QSERDES_COM_DIV_FRAC_START1_MODE1	COM_OFF(0xE8)
 52#define QSERDES_COM_DIV_FRAC_START2_MODE1	COM_OFF(0xEC)
 53#define QSERDES_COM_DIV_FRAC_START3_MODE1	COM_OFF(0xF0)
 54#define QSERDES_COM_INTEGLOOP_GAIN0_MODE0	COM_OFF(0x108)
 55#define QSERDES_COM_INTEGLOOP_GAIN1_MODE0	COM_OFF(0x10C)
 56#define QSERDES_COM_INTEGLOOP_GAIN0_MODE1	COM_OFF(0x110)
 57#define QSERDES_COM_INTEGLOOP_GAIN1_MODE1	COM_OFF(0x114)
 58#define QSERDES_COM_VCO_TUNE_CTRL		COM_OFF(0x124)
 59#define QSERDES_COM_VCO_TUNE_MAP		COM_OFF(0x128)
 60#define QSERDES_COM_VCO_TUNE1_MODE0		COM_OFF(0x12C)
 61#define QSERDES_COM_VCO_TUNE2_MODE0		COM_OFF(0x130)
 62#define QSERDES_COM_VCO_TUNE1_MODE1		COM_OFF(0x134)
 63#define QSERDES_COM_VCO_TUNE2_MODE1		COM_OFF(0x138)
 64#define QSERDES_COM_VCO_TUNE_TIMER1		COM_OFF(0x144)
 65#define QSERDES_COM_VCO_TUNE_TIMER2		COM_OFF(0x148)
 66#define QSERDES_COM_CLK_SELECT			COM_OFF(0x174)
 67#define QSERDES_COM_HSCLK_SEL			COM_OFF(0x178)
 68#define QSERDES_COM_CORECLK_DIV			COM_OFF(0x184)
 69#define QSERDES_COM_CORE_CLK_EN			COM_OFF(0x18C)
 70#define QSERDES_COM_CMN_CONFIG			COM_OFF(0x194)
 71#define QSERDES_COM_SVS_MODE_CLK_SEL		COM_OFF(0x19C)
 72#define QSERDES_COM_CORECLK_DIV_MODE1		COM_OFF(0x1BC)
 73
 74/* UFS PHY registers */
 75#define UFS_PHY_PHY_START			PHY_OFF(0x00)
 76#define UFS_PHY_POWER_DOWN_CONTROL		PHY_OFF(0x04)
 77#define UFS_PHY_PCS_READY_STATUS		PHY_OFF(0x168)
 78
 79/* UFS PHY TX registers */
 80#define QSERDES_TX_HIGHZ_TRANSCEIVER_BIAS_DRVR_EN	TX_OFF(0, 0x68)
 81#define QSERDES_TX_LANE_MODE				TX_OFF(0, 0x94)
 82
 83/* UFS PHY RX registers */
 84#define QSERDES_RX_UCDR_FASTLOCK_FO_GAIN	RX_OFF(0, 0x40)
 85#define QSERDES_RX_RX_TERM_BW			RX_OFF(0, 0x90)
 86#define QSERDES_RX_RX_EQ_GAIN1_LSB		RX_OFF(0, 0xC4)
 87#define QSERDES_RX_RX_EQ_GAIN1_MSB		RX_OFF(0, 0xC8)
 88#define QSERDES_RX_RX_EQ_GAIN2_LSB		RX_OFF(0, 0xCC)
 89#define QSERDES_RX_RX_EQ_GAIN2_MSB		RX_OFF(0, 0xD0)
 90#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2	RX_OFF(0, 0xD8)
 91#define QSERDES_RX_SIGDET_CNTRL			RX_OFF(0, 0x114)
 92#define QSERDES_RX_SIGDET_LVL			RX_OFF(0, 0x118)
 93#define QSERDES_RX_SIGDET_DEGLITCH_CNTRL	RX_OFF(0, 0x11C)
 94#define QSERDES_RX_RX_INTERFACE_MODE		RX_OFF(0, 0x12C)
 95
 96/*
 97 * This structure represents the 14nm specific phy.
 98 * common_cfg MUST remain the first field in this structure
 99 * in case extra fields are added. This way, when calling
100 * get_ufs_qcom_phy() of generic phy, we can extract the
101 * common phy structure (struct ufs_qcom_phy) out of it
102 * regardless of the relevant specific phy.
103 */
104struct ufs_qcom_phy_qmp_14nm {
105	struct ufs_qcom_phy common_cfg;
106};
107
108static struct ufs_qcom_phy_calibration phy_cal_table_rate_A[] = {
109	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_POWER_DOWN_CONTROL, 0x01),
110	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CMN_CONFIG, 0x0e),
111	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYSCLK_EN_SEL, 0xd7),
112	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CLK_SELECT, 0x30),
113	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYS_CLK_CTRL, 0x06),
114	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
115	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BG_TIMER, 0x0a),
116	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_HSCLK_SEL, 0x05),
117	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CORECLK_DIV, 0x0a),
118	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
119	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP_EN, 0x01),
120	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_CTRL, 0x10),
121	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_RESETSM_CNTRL, 0x20),
122	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CORE_CLK_EN, 0x00),
123	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP_CFG, 0x00),
124	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
125	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
126	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_MAP, 0x14),
127	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
128	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START_MODE0, 0x82),
129	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
130	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
131	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
132	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
133	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
134	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
135	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
136	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
137	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
138	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
139	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
140	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
141	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
142	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START_MODE1, 0x98),
143	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
144	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
145	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
146	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
147	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
148	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
149	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
150	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
151	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
152	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
153	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
154	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
155	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
156
157	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_HIGHZ_TRANSCEIVER_BIAS_DRVR_EN, 0x45),
158	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_LANE_MODE, 0x02),
159
160	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_LVL, 0x24),
161	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_CNTRL, 0x02),
162	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_INTERFACE_MODE, 0x00),
163	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x18),
164	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
165	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_TERM_BW, 0x5B),
166	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xFF),
167	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3F),
168	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xFF),
169	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x0F),
170	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E),
171};
172
173static struct ufs_qcom_phy_calibration phy_cal_table_rate_B[] = {
174	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_MAP, 0x54),
175};
176
177#endif