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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2012 Avionic Design GmbH
4 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
5 */
6
7#include <linux/clk.h>
8#include <linux/debugfs.h>
9#include <linux/delay.h>
10#include <linux/iommu.h>
11#include <linux/module.h>
12#include <linux/of_device.h>
13#include <linux/pm_runtime.h>
14#include <linux/reset.h>
15
16#include <soc/tegra/pmc.h>
17
18#include <drm/drm_atomic.h>
19#include <drm/drm_atomic_helper.h>
20#include <drm/drm_debugfs.h>
21#include <drm/drm_fourcc.h>
22#include <drm/drm_plane_helper.h>
23#include <drm/drm_vblank.h>
24
25#include "dc.h"
26#include "drm.h"
27#include "gem.h"
28#include "hub.h"
29#include "plane.h"
30
31static void tegra_crtc_atomic_destroy_state(struct drm_crtc *crtc,
32 struct drm_crtc_state *state);
33
34static void tegra_dc_stats_reset(struct tegra_dc_stats *stats)
35{
36 stats->frames = 0;
37 stats->vblank = 0;
38 stats->underflow = 0;
39 stats->overflow = 0;
40}
41
42/* Reads the active copy of a register. */
43static u32 tegra_dc_readl_active(struct tegra_dc *dc, unsigned long offset)
44{
45 u32 value;
46
47 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
48 value = tegra_dc_readl(dc, offset);
49 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
50
51 return value;
52}
53
54static inline unsigned int tegra_plane_offset(struct tegra_plane *plane,
55 unsigned int offset)
56{
57 if (offset >= 0x500 && offset <= 0x638) {
58 offset = 0x000 + (offset - 0x500);
59 return plane->offset + offset;
60 }
61
62 if (offset >= 0x700 && offset <= 0x719) {
63 offset = 0x180 + (offset - 0x700);
64 return plane->offset + offset;
65 }
66
67 if (offset >= 0x800 && offset <= 0x839) {
68 offset = 0x1c0 + (offset - 0x800);
69 return plane->offset + offset;
70 }
71
72 dev_WARN(plane->dc->dev, "invalid offset: %x\n", offset);
73
74 return plane->offset + offset;
75}
76
77static inline u32 tegra_plane_readl(struct tegra_plane *plane,
78 unsigned int offset)
79{
80 return tegra_dc_readl(plane->dc, tegra_plane_offset(plane, offset));
81}
82
83static inline void tegra_plane_writel(struct tegra_plane *plane, u32 value,
84 unsigned int offset)
85{
86 tegra_dc_writel(plane->dc, value, tegra_plane_offset(plane, offset));
87}
88
89bool tegra_dc_has_output(struct tegra_dc *dc, struct device *dev)
90{
91 struct device_node *np = dc->dev->of_node;
92 struct of_phandle_iterator it;
93 int err;
94
95 of_for_each_phandle(&it, err, np, "nvidia,outputs", NULL, 0)
96 if (it.node == dev->of_node)
97 return true;
98
99 return false;
100}
101
102/*
103 * Double-buffered registers have two copies: ASSEMBLY and ACTIVE. When the
104 * *_ACT_REQ bits are set the ASSEMBLY copy is latched into the ACTIVE copy.
105 * Latching happens mmediately if the display controller is in STOP mode or
106 * on the next frame boundary otherwise.
107 *
108 * Triple-buffered registers have three copies: ASSEMBLY, ARM and ACTIVE. The
109 * ASSEMBLY copy is latched into the ARM copy immediately after *_UPDATE bits
110 * are written. When the *_ACT_REQ bits are written, the ARM copy is latched
111 * into the ACTIVE copy, either immediately if the display controller is in
112 * STOP mode, or at the next frame boundary otherwise.
113 */
114void tegra_dc_commit(struct tegra_dc *dc)
115{
116 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
117 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
118}
119
120static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v,
121 unsigned int bpp)
122{
123 fixed20_12 outf = dfixed_init(out);
124 fixed20_12 inf = dfixed_init(in);
125 u32 dda_inc;
126 int max;
127
128 if (v)
129 max = 15;
130 else {
131 switch (bpp) {
132 case 2:
133 max = 8;
134 break;
135
136 default:
137 WARN_ON_ONCE(1);
138 fallthrough;
139 case 4:
140 max = 4;
141 break;
142 }
143 }
144
145 outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1));
146 inf.full -= dfixed_const(1);
147
148 dda_inc = dfixed_div(inf, outf);
149 dda_inc = min_t(u32, dda_inc, dfixed_const(max));
150
151 return dda_inc;
152}
153
154static inline u32 compute_initial_dda(unsigned int in)
155{
156 fixed20_12 inf = dfixed_init(in);
157 return dfixed_frac(inf);
158}
159
160static void tegra_plane_setup_blending_legacy(struct tegra_plane *plane)
161{
162 u32 background[3] = {
163 BLEND_WEIGHT1(0) | BLEND_WEIGHT0(0) | BLEND_COLOR_KEY_NONE,
164 BLEND_WEIGHT1(0) | BLEND_WEIGHT0(0) | BLEND_COLOR_KEY_NONE,
165 BLEND_WEIGHT1(0) | BLEND_WEIGHT0(0) | BLEND_COLOR_KEY_NONE,
166 };
167 u32 foreground = BLEND_WEIGHT1(255) | BLEND_WEIGHT0(255) |
168 BLEND_COLOR_KEY_NONE;
169 u32 blendnokey = BLEND_WEIGHT1(255) | BLEND_WEIGHT0(255);
170 struct tegra_plane_state *state;
171 u32 blending[2];
172 unsigned int i;
173
174 /* disable blending for non-overlapping case */
175 tegra_plane_writel(plane, blendnokey, DC_WIN_BLEND_NOKEY);
176 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_1WIN);
177
178 state = to_tegra_plane_state(plane->base.state);
179
180 if (state->opaque) {
181 /*
182 * Since custom fix-weight blending isn't utilized and weight
183 * of top window is set to max, we can enforce dependent
184 * blending which in this case results in transparent bottom
185 * window if top window is opaque and if top window enables
186 * alpha blending, then bottom window is getting alpha value
187 * of 1 minus the sum of alpha components of the overlapping
188 * plane.
189 */
190 background[0] |= BLEND_CONTROL_DEPENDENT;
191 background[1] |= BLEND_CONTROL_DEPENDENT;
192
193 /*
194 * The region where three windows overlap is the intersection
195 * of the two regions where two windows overlap. It contributes
196 * to the area if all of the windows on top of it have an alpha
197 * component.
198 */
199 switch (state->base.normalized_zpos) {
200 case 0:
201 if (state->blending[0].alpha &&
202 state->blending[1].alpha)
203 background[2] |= BLEND_CONTROL_DEPENDENT;
204 break;
205
206 case 1:
207 background[2] |= BLEND_CONTROL_DEPENDENT;
208 break;
209 }
210 } else {
211 /*
212 * Enable alpha blending if pixel format has an alpha
213 * component.
214 */
215 foreground |= BLEND_CONTROL_ALPHA;
216
217 /*
218 * If any of the windows on top of this window is opaque, it
219 * will completely conceal this window within that area. If
220 * top window has an alpha component, it is blended over the
221 * bottom window.
222 */
223 for (i = 0; i < 2; i++) {
224 if (state->blending[i].alpha &&
225 state->blending[i].top)
226 background[i] |= BLEND_CONTROL_DEPENDENT;
227 }
228
229 switch (state->base.normalized_zpos) {
230 case 0:
231 if (state->blending[0].alpha &&
232 state->blending[1].alpha)
233 background[2] |= BLEND_CONTROL_DEPENDENT;
234 break;
235
236 case 1:
237 /*
238 * When both middle and topmost windows have an alpha,
239 * these windows a mixed together and then the result
240 * is blended over the bottom window.
241 */
242 if (state->blending[0].alpha &&
243 state->blending[0].top)
244 background[2] |= BLEND_CONTROL_ALPHA;
245
246 if (state->blending[1].alpha &&
247 state->blending[1].top)
248 background[2] |= BLEND_CONTROL_ALPHA;
249 break;
250 }
251 }
252
253 switch (state->base.normalized_zpos) {
254 case 0:
255 tegra_plane_writel(plane, background[0], DC_WIN_BLEND_2WIN_X);
256 tegra_plane_writel(plane, background[1], DC_WIN_BLEND_2WIN_Y);
257 tegra_plane_writel(plane, background[2], DC_WIN_BLEND_3WIN_XY);
258 break;
259
260 case 1:
261 /*
262 * If window B / C is topmost, then X / Y registers are
263 * matching the order of blending[...] state indices,
264 * otherwise a swap is required.
265 */
266 if (!state->blending[0].top && state->blending[1].top) {
267 blending[0] = foreground;
268 blending[1] = background[1];
269 } else {
270 blending[0] = background[0];
271 blending[1] = foreground;
272 }
273
274 tegra_plane_writel(plane, blending[0], DC_WIN_BLEND_2WIN_X);
275 tegra_plane_writel(plane, blending[1], DC_WIN_BLEND_2WIN_Y);
276 tegra_plane_writel(plane, background[2], DC_WIN_BLEND_3WIN_XY);
277 break;
278
279 case 2:
280 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_2WIN_X);
281 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_2WIN_Y);
282 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_3WIN_XY);
283 break;
284 }
285}
286
287static void tegra_plane_setup_blending(struct tegra_plane *plane,
288 const struct tegra_dc_window *window)
289{
290 u32 value;
291
292 value = BLEND_FACTOR_DST_ALPHA_ZERO | BLEND_FACTOR_SRC_ALPHA_K2 |
293 BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC |
294 BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC;
295 tegra_plane_writel(plane, value, DC_WIN_BLEND_MATCH_SELECT);
296
297 value = BLEND_FACTOR_DST_ALPHA_ZERO | BLEND_FACTOR_SRC_ALPHA_K2 |
298 BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC |
299 BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC;
300 tegra_plane_writel(plane, value, DC_WIN_BLEND_NOMATCH_SELECT);
301
302 value = K2(255) | K1(255) | WINDOW_LAYER_DEPTH(255 - window->zpos);
303 tegra_plane_writel(plane, value, DC_WIN_BLEND_LAYER_CONTROL);
304}
305
306static bool
307tegra_plane_use_horizontal_filtering(struct tegra_plane *plane,
308 const struct tegra_dc_window *window)
309{
310 struct tegra_dc *dc = plane->dc;
311
312 if (window->src.w == window->dst.w)
313 return false;
314
315 if (plane->index == 0 && dc->soc->has_win_a_without_filters)
316 return false;
317
318 return true;
319}
320
321static bool
322tegra_plane_use_vertical_filtering(struct tegra_plane *plane,
323 const struct tegra_dc_window *window)
324{
325 struct tegra_dc *dc = plane->dc;
326
327 if (window->src.h == window->dst.h)
328 return false;
329
330 if (plane->index == 0 && dc->soc->has_win_a_without_filters)
331 return false;
332
333 if (plane->index == 2 && dc->soc->has_win_c_without_vert_filter)
334 return false;
335
336 return true;
337}
338
339static void tegra_dc_setup_window(struct tegra_plane *plane,
340 const struct tegra_dc_window *window)
341{
342 unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp;
343 struct tegra_dc *dc = plane->dc;
344 bool yuv, planar;
345 u32 value;
346
347 /*
348 * For YUV planar modes, the number of bytes per pixel takes into
349 * account only the luma component and therefore is 1.
350 */
351 yuv = tegra_plane_format_is_yuv(window->format, &planar);
352 if (!yuv)
353 bpp = window->bits_per_pixel / 8;
354 else
355 bpp = planar ? 1 : 2;
356
357 tegra_plane_writel(plane, window->format, DC_WIN_COLOR_DEPTH);
358 tegra_plane_writel(plane, window->swap, DC_WIN_BYTE_SWAP);
359
360 value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x);
361 tegra_plane_writel(plane, value, DC_WIN_POSITION);
362
363 value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w);
364 tegra_plane_writel(plane, value, DC_WIN_SIZE);
365
366 h_offset = window->src.x * bpp;
367 v_offset = window->src.y;
368 h_size = window->src.w * bpp;
369 v_size = window->src.h;
370
371 if (window->reflect_x)
372 h_offset += (window->src.w - 1) * bpp;
373
374 if (window->reflect_y)
375 v_offset += window->src.h - 1;
376
377 value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size);
378 tegra_plane_writel(plane, value, DC_WIN_PRESCALED_SIZE);
379
380 /*
381 * For DDA computations the number of bytes per pixel for YUV planar
382 * modes needs to take into account all Y, U and V components.
383 */
384 if (yuv && planar)
385 bpp = 2;
386
387 h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp);
388 v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp);
389
390 value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda);
391 tegra_plane_writel(plane, value, DC_WIN_DDA_INC);
392
393 h_dda = compute_initial_dda(window->src.x);
394 v_dda = compute_initial_dda(window->src.y);
395
396 tegra_plane_writel(plane, h_dda, DC_WIN_H_INITIAL_DDA);
397 tegra_plane_writel(plane, v_dda, DC_WIN_V_INITIAL_DDA);
398
399 tegra_plane_writel(plane, 0, DC_WIN_UV_BUF_STRIDE);
400 tegra_plane_writel(plane, 0, DC_WIN_BUF_STRIDE);
401
402 tegra_plane_writel(plane, window->base[0], DC_WINBUF_START_ADDR);
403
404 if (yuv && planar) {
405 tegra_plane_writel(plane, window->base[1], DC_WINBUF_START_ADDR_U);
406 tegra_plane_writel(plane, window->base[2], DC_WINBUF_START_ADDR_V);
407 value = window->stride[1] << 16 | window->stride[0];
408 tegra_plane_writel(plane, value, DC_WIN_LINE_STRIDE);
409 } else {
410 tegra_plane_writel(plane, window->stride[0], DC_WIN_LINE_STRIDE);
411 }
412
413 tegra_plane_writel(plane, h_offset, DC_WINBUF_ADDR_H_OFFSET);
414 tegra_plane_writel(plane, v_offset, DC_WINBUF_ADDR_V_OFFSET);
415
416 if (dc->soc->supports_block_linear) {
417 unsigned long height = window->tiling.value;
418
419 switch (window->tiling.mode) {
420 case TEGRA_BO_TILING_MODE_PITCH:
421 value = DC_WINBUF_SURFACE_KIND_PITCH;
422 break;
423
424 case TEGRA_BO_TILING_MODE_TILED:
425 value = DC_WINBUF_SURFACE_KIND_TILED;
426 break;
427
428 case TEGRA_BO_TILING_MODE_BLOCK:
429 value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) |
430 DC_WINBUF_SURFACE_KIND_BLOCK;
431 break;
432 }
433
434 tegra_plane_writel(plane, value, DC_WINBUF_SURFACE_KIND);
435 } else {
436 switch (window->tiling.mode) {
437 case TEGRA_BO_TILING_MODE_PITCH:
438 value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV |
439 DC_WIN_BUFFER_ADDR_MODE_LINEAR;
440 break;
441
442 case TEGRA_BO_TILING_MODE_TILED:
443 value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV |
444 DC_WIN_BUFFER_ADDR_MODE_TILE;
445 break;
446
447 case TEGRA_BO_TILING_MODE_BLOCK:
448 /*
449 * No need to handle this here because ->atomic_check
450 * will already have filtered it out.
451 */
452 break;
453 }
454
455 tegra_plane_writel(plane, value, DC_WIN_BUFFER_ADDR_MODE);
456 }
457
458 value = WIN_ENABLE;
459
460 if (yuv) {
461 /* setup default colorspace conversion coefficients */
462 tegra_plane_writel(plane, 0x00f0, DC_WIN_CSC_YOF);
463 tegra_plane_writel(plane, 0x012a, DC_WIN_CSC_KYRGB);
464 tegra_plane_writel(plane, 0x0000, DC_WIN_CSC_KUR);
465 tegra_plane_writel(plane, 0x0198, DC_WIN_CSC_KVR);
466 tegra_plane_writel(plane, 0x039b, DC_WIN_CSC_KUG);
467 tegra_plane_writel(plane, 0x032f, DC_WIN_CSC_KVG);
468 tegra_plane_writel(plane, 0x0204, DC_WIN_CSC_KUB);
469 tegra_plane_writel(plane, 0x0000, DC_WIN_CSC_KVB);
470
471 value |= CSC_ENABLE;
472 } else if (window->bits_per_pixel < 24) {
473 value |= COLOR_EXPAND;
474 }
475
476 if (window->reflect_x)
477 value |= H_DIRECTION;
478
479 if (window->reflect_y)
480 value |= V_DIRECTION;
481
482 if (tegra_plane_use_horizontal_filtering(plane, window)) {
483 /*
484 * Enable horizontal 6-tap filter and set filtering
485 * coefficients to the default values defined in TRM.
486 */
487 tegra_plane_writel(plane, 0x00008000, DC_WIN_H_FILTER_P(0));
488 tegra_plane_writel(plane, 0x3e087ce1, DC_WIN_H_FILTER_P(1));
489 tegra_plane_writel(plane, 0x3b117ac1, DC_WIN_H_FILTER_P(2));
490 tegra_plane_writel(plane, 0x591b73aa, DC_WIN_H_FILTER_P(3));
491 tegra_plane_writel(plane, 0x57256d9a, DC_WIN_H_FILTER_P(4));
492 tegra_plane_writel(plane, 0x552f668b, DC_WIN_H_FILTER_P(5));
493 tegra_plane_writel(plane, 0x73385e8b, DC_WIN_H_FILTER_P(6));
494 tegra_plane_writel(plane, 0x72435583, DC_WIN_H_FILTER_P(7));
495 tegra_plane_writel(plane, 0x714c4c8b, DC_WIN_H_FILTER_P(8));
496 tegra_plane_writel(plane, 0x70554393, DC_WIN_H_FILTER_P(9));
497 tegra_plane_writel(plane, 0x715e389b, DC_WIN_H_FILTER_P(10));
498 tegra_plane_writel(plane, 0x71662faa, DC_WIN_H_FILTER_P(11));
499 tegra_plane_writel(plane, 0x536d25ba, DC_WIN_H_FILTER_P(12));
500 tegra_plane_writel(plane, 0x55731bca, DC_WIN_H_FILTER_P(13));
501 tegra_plane_writel(plane, 0x387a11d9, DC_WIN_H_FILTER_P(14));
502 tegra_plane_writel(plane, 0x3c7c08f1, DC_WIN_H_FILTER_P(15));
503
504 value |= H_FILTER;
505 }
506
507 if (tegra_plane_use_vertical_filtering(plane, window)) {
508 unsigned int i, k;
509
510 /*
511 * Enable vertical 2-tap filter and set filtering
512 * coefficients to the default values defined in TRM.
513 */
514 for (i = 0, k = 128; i < 16; i++, k -= 8)
515 tegra_plane_writel(plane, k, DC_WIN_V_FILTER_P(i));
516
517 value |= V_FILTER;
518 }
519
520 tegra_plane_writel(plane, value, DC_WIN_WIN_OPTIONS);
521
522 if (dc->soc->has_legacy_blending)
523 tegra_plane_setup_blending_legacy(plane);
524 else
525 tegra_plane_setup_blending(plane, window);
526}
527
528static const u32 tegra20_primary_formats[] = {
529 DRM_FORMAT_ARGB4444,
530 DRM_FORMAT_ARGB1555,
531 DRM_FORMAT_RGB565,
532 DRM_FORMAT_RGBA5551,
533 DRM_FORMAT_ABGR8888,
534 DRM_FORMAT_ARGB8888,
535 /* non-native formats */
536 DRM_FORMAT_XRGB1555,
537 DRM_FORMAT_RGBX5551,
538 DRM_FORMAT_XBGR8888,
539 DRM_FORMAT_XRGB8888,
540};
541
542static const u64 tegra20_modifiers[] = {
543 DRM_FORMAT_MOD_LINEAR,
544 DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED,
545 DRM_FORMAT_MOD_INVALID
546};
547
548static const u32 tegra114_primary_formats[] = {
549 DRM_FORMAT_ARGB4444,
550 DRM_FORMAT_ARGB1555,
551 DRM_FORMAT_RGB565,
552 DRM_FORMAT_RGBA5551,
553 DRM_FORMAT_ABGR8888,
554 DRM_FORMAT_ARGB8888,
555 /* new on Tegra114 */
556 DRM_FORMAT_ABGR4444,
557 DRM_FORMAT_ABGR1555,
558 DRM_FORMAT_BGRA5551,
559 DRM_FORMAT_XRGB1555,
560 DRM_FORMAT_RGBX5551,
561 DRM_FORMAT_XBGR1555,
562 DRM_FORMAT_BGRX5551,
563 DRM_FORMAT_BGR565,
564 DRM_FORMAT_BGRA8888,
565 DRM_FORMAT_RGBA8888,
566 DRM_FORMAT_XRGB8888,
567 DRM_FORMAT_XBGR8888,
568};
569
570static const u32 tegra124_primary_formats[] = {
571 DRM_FORMAT_ARGB4444,
572 DRM_FORMAT_ARGB1555,
573 DRM_FORMAT_RGB565,
574 DRM_FORMAT_RGBA5551,
575 DRM_FORMAT_ABGR8888,
576 DRM_FORMAT_ARGB8888,
577 /* new on Tegra114 */
578 DRM_FORMAT_ABGR4444,
579 DRM_FORMAT_ABGR1555,
580 DRM_FORMAT_BGRA5551,
581 DRM_FORMAT_XRGB1555,
582 DRM_FORMAT_RGBX5551,
583 DRM_FORMAT_XBGR1555,
584 DRM_FORMAT_BGRX5551,
585 DRM_FORMAT_BGR565,
586 DRM_FORMAT_BGRA8888,
587 DRM_FORMAT_RGBA8888,
588 DRM_FORMAT_XRGB8888,
589 DRM_FORMAT_XBGR8888,
590 /* new on Tegra124 */
591 DRM_FORMAT_RGBX8888,
592 DRM_FORMAT_BGRX8888,
593};
594
595static const u64 tegra124_modifiers[] = {
596 DRM_FORMAT_MOD_LINEAR,
597 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0),
598 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1),
599 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2),
600 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3),
601 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4),
602 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5),
603 DRM_FORMAT_MOD_INVALID
604};
605
606static int tegra_plane_atomic_check(struct drm_plane *plane,
607 struct drm_plane_state *state)
608{
609 struct tegra_plane_state *plane_state = to_tegra_plane_state(state);
610 unsigned int supported_rotation = DRM_MODE_ROTATE_0 |
611 DRM_MODE_REFLECT_X |
612 DRM_MODE_REFLECT_Y;
613 unsigned int rotation = state->rotation;
614 struct tegra_bo_tiling *tiling = &plane_state->tiling;
615 struct tegra_plane *tegra = to_tegra_plane(plane);
616 struct tegra_dc *dc = to_tegra_dc(state->crtc);
617 int err;
618
619 /* no need for further checks if the plane is being disabled */
620 if (!state->crtc)
621 return 0;
622
623 err = tegra_plane_format(state->fb->format->format,
624 &plane_state->format,
625 &plane_state->swap);
626 if (err < 0)
627 return err;
628
629 /*
630 * Tegra20 and Tegra30 are special cases here because they support
631 * only variants of specific formats with an alpha component, but not
632 * the corresponding opaque formats. However, the opaque formats can
633 * be emulated by disabling alpha blending for the plane.
634 */
635 if (dc->soc->has_legacy_blending) {
636 err = tegra_plane_setup_legacy_state(tegra, plane_state);
637 if (err < 0)
638 return err;
639 }
640
641 err = tegra_fb_get_tiling(state->fb, tiling);
642 if (err < 0)
643 return err;
644
645 if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK &&
646 !dc->soc->supports_block_linear) {
647 DRM_ERROR("hardware doesn't support block linear mode\n");
648 return -EINVAL;
649 }
650
651 /*
652 * Older userspace used custom BO flag in order to specify the Y
653 * reflection, while modern userspace uses the generic DRM rotation
654 * property in order to achieve the same result. The legacy BO flag
655 * duplicates the DRM rotation property when both are set.
656 */
657 if (tegra_fb_is_bottom_up(state->fb))
658 rotation |= DRM_MODE_REFLECT_Y;
659
660 rotation = drm_rotation_simplify(rotation, supported_rotation);
661
662 if (rotation & DRM_MODE_REFLECT_X)
663 plane_state->reflect_x = true;
664 else
665 plane_state->reflect_x = false;
666
667 if (rotation & DRM_MODE_REFLECT_Y)
668 plane_state->reflect_y = true;
669 else
670 plane_state->reflect_y = false;
671
672 /*
673 * Tegra doesn't support different strides for U and V planes so we
674 * error out if the user tries to display a framebuffer with such a
675 * configuration.
676 */
677 if (state->fb->format->num_planes > 2) {
678 if (state->fb->pitches[2] != state->fb->pitches[1]) {
679 DRM_ERROR("unsupported UV-plane configuration\n");
680 return -EINVAL;
681 }
682 }
683
684 err = tegra_plane_state_add(tegra, state);
685 if (err < 0)
686 return err;
687
688 return 0;
689}
690
691static void tegra_plane_atomic_disable(struct drm_plane *plane,
692 struct drm_plane_state *old_state)
693{
694 struct tegra_plane *p = to_tegra_plane(plane);
695 u32 value;
696
697 /* rien ne va plus */
698 if (!old_state || !old_state->crtc)
699 return;
700
701 value = tegra_plane_readl(p, DC_WIN_WIN_OPTIONS);
702 value &= ~WIN_ENABLE;
703 tegra_plane_writel(p, value, DC_WIN_WIN_OPTIONS);
704}
705
706static void tegra_plane_atomic_update(struct drm_plane *plane,
707 struct drm_plane_state *old_state)
708{
709 struct tegra_plane_state *state = to_tegra_plane_state(plane->state);
710 struct drm_framebuffer *fb = plane->state->fb;
711 struct tegra_plane *p = to_tegra_plane(plane);
712 struct tegra_dc_window window;
713 unsigned int i;
714
715 /* rien ne va plus */
716 if (!plane->state->crtc || !plane->state->fb)
717 return;
718
719 if (!plane->state->visible)
720 return tegra_plane_atomic_disable(plane, old_state);
721
722 memset(&window, 0, sizeof(window));
723 window.src.x = plane->state->src.x1 >> 16;
724 window.src.y = plane->state->src.y1 >> 16;
725 window.src.w = drm_rect_width(&plane->state->src) >> 16;
726 window.src.h = drm_rect_height(&plane->state->src) >> 16;
727 window.dst.x = plane->state->dst.x1;
728 window.dst.y = plane->state->dst.y1;
729 window.dst.w = drm_rect_width(&plane->state->dst);
730 window.dst.h = drm_rect_height(&plane->state->dst);
731 window.bits_per_pixel = fb->format->cpp[0] * 8;
732 window.reflect_x = state->reflect_x;
733 window.reflect_y = state->reflect_y;
734
735 /* copy from state */
736 window.zpos = plane->state->normalized_zpos;
737 window.tiling = state->tiling;
738 window.format = state->format;
739 window.swap = state->swap;
740
741 for (i = 0; i < fb->format->num_planes; i++) {
742 window.base[i] = state->iova[i] + fb->offsets[i];
743
744 /*
745 * Tegra uses a shared stride for UV planes. Framebuffers are
746 * already checked for this in the tegra_plane_atomic_check()
747 * function, so it's safe to ignore the V-plane pitch here.
748 */
749 if (i < 2)
750 window.stride[i] = fb->pitches[i];
751 }
752
753 tegra_dc_setup_window(p, &window);
754}
755
756static const struct drm_plane_helper_funcs tegra_plane_helper_funcs = {
757 .prepare_fb = tegra_plane_prepare_fb,
758 .cleanup_fb = tegra_plane_cleanup_fb,
759 .atomic_check = tegra_plane_atomic_check,
760 .atomic_disable = tegra_plane_atomic_disable,
761 .atomic_update = tegra_plane_atomic_update,
762};
763
764static unsigned long tegra_plane_get_possible_crtcs(struct drm_device *drm)
765{
766 /*
767 * Ideally this would use drm_crtc_mask(), but that would require the
768 * CRTC to already be in the mode_config's list of CRTCs. However, it
769 * will only be added to that list in the drm_crtc_init_with_planes()
770 * (in tegra_dc_init()), which in turn requires registration of these
771 * planes. So we have ourselves a nice little chicken and egg problem
772 * here.
773 *
774 * We work around this by manually creating the mask from the number
775 * of CRTCs that have been registered, and should therefore always be
776 * the same as drm_crtc_index() after registration.
777 */
778 return 1 << drm->mode_config.num_crtc;
779}
780
781static struct drm_plane *tegra_primary_plane_create(struct drm_device *drm,
782 struct tegra_dc *dc)
783{
784 unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm);
785 enum drm_plane_type type = DRM_PLANE_TYPE_PRIMARY;
786 struct tegra_plane *plane;
787 unsigned int num_formats;
788 const u64 *modifiers;
789 const u32 *formats;
790 int err;
791
792 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
793 if (!plane)
794 return ERR_PTR(-ENOMEM);
795
796 /* Always use window A as primary window */
797 plane->offset = 0xa00;
798 plane->index = 0;
799 plane->dc = dc;
800
801 num_formats = dc->soc->num_primary_formats;
802 formats = dc->soc->primary_formats;
803 modifiers = dc->soc->modifiers;
804
805 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
806 &tegra_plane_funcs, formats,
807 num_formats, modifiers, type, NULL);
808 if (err < 0) {
809 kfree(plane);
810 return ERR_PTR(err);
811 }
812
813 drm_plane_helper_add(&plane->base, &tegra_plane_helper_funcs);
814 drm_plane_create_zpos_property(&plane->base, plane->index, 0, 255);
815
816 err = drm_plane_create_rotation_property(&plane->base,
817 DRM_MODE_ROTATE_0,
818 DRM_MODE_ROTATE_0 |
819 DRM_MODE_ROTATE_180 |
820 DRM_MODE_REFLECT_X |
821 DRM_MODE_REFLECT_Y);
822 if (err < 0)
823 dev_err(dc->dev, "failed to create rotation property: %d\n",
824 err);
825
826 return &plane->base;
827}
828
829static const u32 tegra_cursor_plane_formats[] = {
830 DRM_FORMAT_RGBA8888,
831};
832
833static int tegra_cursor_atomic_check(struct drm_plane *plane,
834 struct drm_plane_state *state)
835{
836 struct tegra_plane *tegra = to_tegra_plane(plane);
837 int err;
838
839 /* no need for further checks if the plane is being disabled */
840 if (!state->crtc)
841 return 0;
842
843 /* scaling not supported for cursor */
844 if ((state->src_w >> 16 != state->crtc_w) ||
845 (state->src_h >> 16 != state->crtc_h))
846 return -EINVAL;
847
848 /* only square cursors supported */
849 if (state->src_w != state->src_h)
850 return -EINVAL;
851
852 if (state->crtc_w != 32 && state->crtc_w != 64 &&
853 state->crtc_w != 128 && state->crtc_w != 256)
854 return -EINVAL;
855
856 err = tegra_plane_state_add(tegra, state);
857 if (err < 0)
858 return err;
859
860 return 0;
861}
862
863static void tegra_cursor_atomic_update(struct drm_plane *plane,
864 struct drm_plane_state *old_state)
865{
866 struct tegra_plane_state *state = to_tegra_plane_state(plane->state);
867 struct tegra_dc *dc = to_tegra_dc(plane->state->crtc);
868 u32 value = CURSOR_CLIP_DISPLAY;
869
870 /* rien ne va plus */
871 if (!plane->state->crtc || !plane->state->fb)
872 return;
873
874 switch (plane->state->crtc_w) {
875 case 32:
876 value |= CURSOR_SIZE_32x32;
877 break;
878
879 case 64:
880 value |= CURSOR_SIZE_64x64;
881 break;
882
883 case 128:
884 value |= CURSOR_SIZE_128x128;
885 break;
886
887 case 256:
888 value |= CURSOR_SIZE_256x256;
889 break;
890
891 default:
892 WARN(1, "cursor size %ux%u not supported\n",
893 plane->state->crtc_w, plane->state->crtc_h);
894 return;
895 }
896
897 value |= (state->iova[0] >> 10) & 0x3fffff;
898 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR);
899
900#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
901 value = (state->iova[0] >> 32) & 0x3;
902 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI);
903#endif
904
905 /* enable cursor and set blend mode */
906 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
907 value |= CURSOR_ENABLE;
908 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
909
910 value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL);
911 value &= ~CURSOR_DST_BLEND_MASK;
912 value &= ~CURSOR_SRC_BLEND_MASK;
913 value |= CURSOR_MODE_NORMAL;
914 value |= CURSOR_DST_BLEND_NEG_K1_TIMES_SRC;
915 value |= CURSOR_SRC_BLEND_K1_TIMES_SRC;
916 value |= CURSOR_ALPHA;
917 tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL);
918
919 /* position the cursor */
920 value = (plane->state->crtc_y & 0x3fff) << 16 |
921 (plane->state->crtc_x & 0x3fff);
922 tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION);
923}
924
925static void tegra_cursor_atomic_disable(struct drm_plane *plane,
926 struct drm_plane_state *old_state)
927{
928 struct tegra_dc *dc;
929 u32 value;
930
931 /* rien ne va plus */
932 if (!old_state || !old_state->crtc)
933 return;
934
935 dc = to_tegra_dc(old_state->crtc);
936
937 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
938 value &= ~CURSOR_ENABLE;
939 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
940}
941
942static const struct drm_plane_helper_funcs tegra_cursor_plane_helper_funcs = {
943 .prepare_fb = tegra_plane_prepare_fb,
944 .cleanup_fb = tegra_plane_cleanup_fb,
945 .atomic_check = tegra_cursor_atomic_check,
946 .atomic_update = tegra_cursor_atomic_update,
947 .atomic_disable = tegra_cursor_atomic_disable,
948};
949
950static struct drm_plane *tegra_dc_cursor_plane_create(struct drm_device *drm,
951 struct tegra_dc *dc)
952{
953 unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm);
954 struct tegra_plane *plane;
955 unsigned int num_formats;
956 const u32 *formats;
957 int err;
958
959 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
960 if (!plane)
961 return ERR_PTR(-ENOMEM);
962
963 /*
964 * This index is kind of fake. The cursor isn't a regular plane, but
965 * its update and activation request bits in DC_CMD_STATE_CONTROL do
966 * use the same programming. Setting this fake index here allows the
967 * code in tegra_add_plane_state() to do the right thing without the
968 * need to special-casing the cursor plane.
969 */
970 plane->index = 6;
971 plane->dc = dc;
972
973 num_formats = ARRAY_SIZE(tegra_cursor_plane_formats);
974 formats = tegra_cursor_plane_formats;
975
976 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
977 &tegra_plane_funcs, formats,
978 num_formats, NULL,
979 DRM_PLANE_TYPE_CURSOR, NULL);
980 if (err < 0) {
981 kfree(plane);
982 return ERR_PTR(err);
983 }
984
985 drm_plane_helper_add(&plane->base, &tegra_cursor_plane_helper_funcs);
986 drm_plane_create_zpos_immutable_property(&plane->base, 255);
987
988 return &plane->base;
989}
990
991static const u32 tegra20_overlay_formats[] = {
992 DRM_FORMAT_ARGB4444,
993 DRM_FORMAT_ARGB1555,
994 DRM_FORMAT_RGB565,
995 DRM_FORMAT_RGBA5551,
996 DRM_FORMAT_ABGR8888,
997 DRM_FORMAT_ARGB8888,
998 /* non-native formats */
999 DRM_FORMAT_XRGB1555,
1000 DRM_FORMAT_RGBX5551,
1001 DRM_FORMAT_XBGR8888,
1002 DRM_FORMAT_XRGB8888,
1003 /* planar formats */
1004 DRM_FORMAT_UYVY,
1005 DRM_FORMAT_YUYV,
1006 DRM_FORMAT_YUV420,
1007 DRM_FORMAT_YUV422,
1008};
1009
1010static const u32 tegra114_overlay_formats[] = {
1011 DRM_FORMAT_ARGB4444,
1012 DRM_FORMAT_ARGB1555,
1013 DRM_FORMAT_RGB565,
1014 DRM_FORMAT_RGBA5551,
1015 DRM_FORMAT_ABGR8888,
1016 DRM_FORMAT_ARGB8888,
1017 /* new on Tegra114 */
1018 DRM_FORMAT_ABGR4444,
1019 DRM_FORMAT_ABGR1555,
1020 DRM_FORMAT_BGRA5551,
1021 DRM_FORMAT_XRGB1555,
1022 DRM_FORMAT_RGBX5551,
1023 DRM_FORMAT_XBGR1555,
1024 DRM_FORMAT_BGRX5551,
1025 DRM_FORMAT_BGR565,
1026 DRM_FORMAT_BGRA8888,
1027 DRM_FORMAT_RGBA8888,
1028 DRM_FORMAT_XRGB8888,
1029 DRM_FORMAT_XBGR8888,
1030 /* planar formats */
1031 DRM_FORMAT_UYVY,
1032 DRM_FORMAT_YUYV,
1033 DRM_FORMAT_YUV420,
1034 DRM_FORMAT_YUV422,
1035};
1036
1037static const u32 tegra124_overlay_formats[] = {
1038 DRM_FORMAT_ARGB4444,
1039 DRM_FORMAT_ARGB1555,
1040 DRM_FORMAT_RGB565,
1041 DRM_FORMAT_RGBA5551,
1042 DRM_FORMAT_ABGR8888,
1043 DRM_FORMAT_ARGB8888,
1044 /* new on Tegra114 */
1045 DRM_FORMAT_ABGR4444,
1046 DRM_FORMAT_ABGR1555,
1047 DRM_FORMAT_BGRA5551,
1048 DRM_FORMAT_XRGB1555,
1049 DRM_FORMAT_RGBX5551,
1050 DRM_FORMAT_XBGR1555,
1051 DRM_FORMAT_BGRX5551,
1052 DRM_FORMAT_BGR565,
1053 DRM_FORMAT_BGRA8888,
1054 DRM_FORMAT_RGBA8888,
1055 DRM_FORMAT_XRGB8888,
1056 DRM_FORMAT_XBGR8888,
1057 /* new on Tegra124 */
1058 DRM_FORMAT_RGBX8888,
1059 DRM_FORMAT_BGRX8888,
1060 /* planar formats */
1061 DRM_FORMAT_UYVY,
1062 DRM_FORMAT_YUYV,
1063 DRM_FORMAT_YUV420,
1064 DRM_FORMAT_YUV422,
1065};
1066
1067static struct drm_plane *tegra_dc_overlay_plane_create(struct drm_device *drm,
1068 struct tegra_dc *dc,
1069 unsigned int index,
1070 bool cursor)
1071{
1072 unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm);
1073 struct tegra_plane *plane;
1074 unsigned int num_formats;
1075 enum drm_plane_type type;
1076 const u32 *formats;
1077 int err;
1078
1079 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
1080 if (!plane)
1081 return ERR_PTR(-ENOMEM);
1082
1083 plane->offset = 0xa00 + 0x200 * index;
1084 plane->index = index;
1085 plane->dc = dc;
1086
1087 num_formats = dc->soc->num_overlay_formats;
1088 formats = dc->soc->overlay_formats;
1089
1090 if (!cursor)
1091 type = DRM_PLANE_TYPE_OVERLAY;
1092 else
1093 type = DRM_PLANE_TYPE_CURSOR;
1094
1095 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
1096 &tegra_plane_funcs, formats,
1097 num_formats, NULL, type, NULL);
1098 if (err < 0) {
1099 kfree(plane);
1100 return ERR_PTR(err);
1101 }
1102
1103 drm_plane_helper_add(&plane->base, &tegra_plane_helper_funcs);
1104 drm_plane_create_zpos_property(&plane->base, plane->index, 0, 255);
1105
1106 err = drm_plane_create_rotation_property(&plane->base,
1107 DRM_MODE_ROTATE_0,
1108 DRM_MODE_ROTATE_0 |
1109 DRM_MODE_ROTATE_180 |
1110 DRM_MODE_REFLECT_X |
1111 DRM_MODE_REFLECT_Y);
1112 if (err < 0)
1113 dev_err(dc->dev, "failed to create rotation property: %d\n",
1114 err);
1115
1116 return &plane->base;
1117}
1118
1119static struct drm_plane *tegra_dc_add_shared_planes(struct drm_device *drm,
1120 struct tegra_dc *dc)
1121{
1122 struct drm_plane *plane, *primary = NULL;
1123 unsigned int i, j;
1124
1125 for (i = 0; i < dc->soc->num_wgrps; i++) {
1126 const struct tegra_windowgroup_soc *wgrp = &dc->soc->wgrps[i];
1127
1128 if (wgrp->dc == dc->pipe) {
1129 for (j = 0; j < wgrp->num_windows; j++) {
1130 unsigned int index = wgrp->windows[j];
1131
1132 plane = tegra_shared_plane_create(drm, dc,
1133 wgrp->index,
1134 index);
1135 if (IS_ERR(plane))
1136 return plane;
1137
1138 /*
1139 * Choose the first shared plane owned by this
1140 * head as the primary plane.
1141 */
1142 if (!primary) {
1143 plane->type = DRM_PLANE_TYPE_PRIMARY;
1144 primary = plane;
1145 }
1146 }
1147 }
1148 }
1149
1150 return primary;
1151}
1152
1153static struct drm_plane *tegra_dc_add_planes(struct drm_device *drm,
1154 struct tegra_dc *dc)
1155{
1156 struct drm_plane *planes[2], *primary;
1157 unsigned int planes_num;
1158 unsigned int i;
1159 int err;
1160
1161 primary = tegra_primary_plane_create(drm, dc);
1162 if (IS_ERR(primary))
1163 return primary;
1164
1165 if (dc->soc->supports_cursor)
1166 planes_num = 2;
1167 else
1168 planes_num = 1;
1169
1170 for (i = 0; i < planes_num; i++) {
1171 planes[i] = tegra_dc_overlay_plane_create(drm, dc, 1 + i,
1172 false);
1173 if (IS_ERR(planes[i])) {
1174 err = PTR_ERR(planes[i]);
1175
1176 while (i--)
1177 tegra_plane_funcs.destroy(planes[i]);
1178
1179 tegra_plane_funcs.destroy(primary);
1180 return ERR_PTR(err);
1181 }
1182 }
1183
1184 return primary;
1185}
1186
1187static void tegra_dc_destroy(struct drm_crtc *crtc)
1188{
1189 drm_crtc_cleanup(crtc);
1190}
1191
1192static void tegra_crtc_reset(struct drm_crtc *crtc)
1193{
1194 struct tegra_dc_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
1195
1196 if (crtc->state)
1197 tegra_crtc_atomic_destroy_state(crtc, crtc->state);
1198
1199 __drm_atomic_helper_crtc_reset(crtc, &state->base);
1200}
1201
1202static struct drm_crtc_state *
1203tegra_crtc_atomic_duplicate_state(struct drm_crtc *crtc)
1204{
1205 struct tegra_dc_state *state = to_dc_state(crtc->state);
1206 struct tegra_dc_state *copy;
1207
1208 copy = kmalloc(sizeof(*copy), GFP_KERNEL);
1209 if (!copy)
1210 return NULL;
1211
1212 __drm_atomic_helper_crtc_duplicate_state(crtc, ©->base);
1213 copy->clk = state->clk;
1214 copy->pclk = state->pclk;
1215 copy->div = state->div;
1216 copy->planes = state->planes;
1217
1218 return ©->base;
1219}
1220
1221static void tegra_crtc_atomic_destroy_state(struct drm_crtc *crtc,
1222 struct drm_crtc_state *state)
1223{
1224 __drm_atomic_helper_crtc_destroy_state(state);
1225 kfree(state);
1226}
1227
1228#define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name }
1229
1230static const struct debugfs_reg32 tegra_dc_regs[] = {
1231 DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT),
1232 DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL),
1233 DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT_ERROR),
1234 DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT),
1235 DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL),
1236 DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT_ERROR),
1237 DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT),
1238 DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL),
1239 DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT_ERROR),
1240 DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT),
1241 DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL),
1242 DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT_ERROR),
1243 DEBUGFS_REG32(DC_CMD_CONT_SYNCPT_VSYNC),
1244 DEBUGFS_REG32(DC_CMD_DISPLAY_COMMAND_OPTION0),
1245 DEBUGFS_REG32(DC_CMD_DISPLAY_COMMAND),
1246 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE),
1247 DEBUGFS_REG32(DC_CMD_DISPLAY_POWER_CONTROL),
1248 DEBUGFS_REG32(DC_CMD_INT_STATUS),
1249 DEBUGFS_REG32(DC_CMD_INT_MASK),
1250 DEBUGFS_REG32(DC_CMD_INT_ENABLE),
1251 DEBUGFS_REG32(DC_CMD_INT_TYPE),
1252 DEBUGFS_REG32(DC_CMD_INT_POLARITY),
1253 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE1),
1254 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE2),
1255 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE3),
1256 DEBUGFS_REG32(DC_CMD_STATE_ACCESS),
1257 DEBUGFS_REG32(DC_CMD_STATE_CONTROL),
1258 DEBUGFS_REG32(DC_CMD_DISPLAY_WINDOW_HEADER),
1259 DEBUGFS_REG32(DC_CMD_REG_ACT_CONTROL),
1260 DEBUGFS_REG32(DC_COM_CRC_CONTROL),
1261 DEBUGFS_REG32(DC_COM_CRC_CHECKSUM),
1262 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(0)),
1263 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(1)),
1264 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(2)),
1265 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(3)),
1266 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(0)),
1267 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(1)),
1268 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(2)),
1269 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(3)),
1270 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(0)),
1271 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(1)),
1272 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(2)),
1273 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(3)),
1274 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(0)),
1275 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(1)),
1276 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(2)),
1277 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(3)),
1278 DEBUGFS_REG32(DC_COM_PIN_INPUT_DATA(0)),
1279 DEBUGFS_REG32(DC_COM_PIN_INPUT_DATA(1)),
1280 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(0)),
1281 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(1)),
1282 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(2)),
1283 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(3)),
1284 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(4)),
1285 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(5)),
1286 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(6)),
1287 DEBUGFS_REG32(DC_COM_PIN_MISC_CONTROL),
1288 DEBUGFS_REG32(DC_COM_PIN_PM0_CONTROL),
1289 DEBUGFS_REG32(DC_COM_PIN_PM0_DUTY_CYCLE),
1290 DEBUGFS_REG32(DC_COM_PIN_PM1_CONTROL),
1291 DEBUGFS_REG32(DC_COM_PIN_PM1_DUTY_CYCLE),
1292 DEBUGFS_REG32(DC_COM_SPI_CONTROL),
1293 DEBUGFS_REG32(DC_COM_SPI_START_BYTE),
1294 DEBUGFS_REG32(DC_COM_HSPI_WRITE_DATA_AB),
1295 DEBUGFS_REG32(DC_COM_HSPI_WRITE_DATA_CD),
1296 DEBUGFS_REG32(DC_COM_HSPI_CS_DC),
1297 DEBUGFS_REG32(DC_COM_SCRATCH_REGISTER_A),
1298 DEBUGFS_REG32(DC_COM_SCRATCH_REGISTER_B),
1299 DEBUGFS_REG32(DC_COM_GPIO_CTRL),
1300 DEBUGFS_REG32(DC_COM_GPIO_DEBOUNCE_COUNTER),
1301 DEBUGFS_REG32(DC_COM_CRC_CHECKSUM_LATCHED),
1302 DEBUGFS_REG32(DC_DISP_DISP_SIGNAL_OPTIONS0),
1303 DEBUGFS_REG32(DC_DISP_DISP_SIGNAL_OPTIONS1),
1304 DEBUGFS_REG32(DC_DISP_DISP_WIN_OPTIONS),
1305 DEBUGFS_REG32(DC_DISP_DISP_MEM_HIGH_PRIORITY),
1306 DEBUGFS_REG32(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER),
1307 DEBUGFS_REG32(DC_DISP_DISP_TIMING_OPTIONS),
1308 DEBUGFS_REG32(DC_DISP_REF_TO_SYNC),
1309 DEBUGFS_REG32(DC_DISP_SYNC_WIDTH),
1310 DEBUGFS_REG32(DC_DISP_BACK_PORCH),
1311 DEBUGFS_REG32(DC_DISP_ACTIVE),
1312 DEBUGFS_REG32(DC_DISP_FRONT_PORCH),
1313 DEBUGFS_REG32(DC_DISP_H_PULSE0_CONTROL),
1314 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_A),
1315 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_B),
1316 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_C),
1317 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_D),
1318 DEBUGFS_REG32(DC_DISP_H_PULSE1_CONTROL),
1319 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_A),
1320 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_B),
1321 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_C),
1322 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_D),
1323 DEBUGFS_REG32(DC_DISP_H_PULSE2_CONTROL),
1324 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_A),
1325 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_B),
1326 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_C),
1327 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_D),
1328 DEBUGFS_REG32(DC_DISP_V_PULSE0_CONTROL),
1329 DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_A),
1330 DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_B),
1331 DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_C),
1332 DEBUGFS_REG32(DC_DISP_V_PULSE1_CONTROL),
1333 DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_A),
1334 DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_B),
1335 DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_C),
1336 DEBUGFS_REG32(DC_DISP_V_PULSE2_CONTROL),
1337 DEBUGFS_REG32(DC_DISP_V_PULSE2_POSITION_A),
1338 DEBUGFS_REG32(DC_DISP_V_PULSE3_CONTROL),
1339 DEBUGFS_REG32(DC_DISP_V_PULSE3_POSITION_A),
1340 DEBUGFS_REG32(DC_DISP_M0_CONTROL),
1341 DEBUGFS_REG32(DC_DISP_M1_CONTROL),
1342 DEBUGFS_REG32(DC_DISP_DI_CONTROL),
1343 DEBUGFS_REG32(DC_DISP_PP_CONTROL),
1344 DEBUGFS_REG32(DC_DISP_PP_SELECT_A),
1345 DEBUGFS_REG32(DC_DISP_PP_SELECT_B),
1346 DEBUGFS_REG32(DC_DISP_PP_SELECT_C),
1347 DEBUGFS_REG32(DC_DISP_PP_SELECT_D),
1348 DEBUGFS_REG32(DC_DISP_DISP_CLOCK_CONTROL),
1349 DEBUGFS_REG32(DC_DISP_DISP_INTERFACE_CONTROL),
1350 DEBUGFS_REG32(DC_DISP_DISP_COLOR_CONTROL),
1351 DEBUGFS_REG32(DC_DISP_SHIFT_CLOCK_OPTIONS),
1352 DEBUGFS_REG32(DC_DISP_DATA_ENABLE_OPTIONS),
1353 DEBUGFS_REG32(DC_DISP_SERIAL_INTERFACE_OPTIONS),
1354 DEBUGFS_REG32(DC_DISP_LCD_SPI_OPTIONS),
1355 DEBUGFS_REG32(DC_DISP_BORDER_COLOR),
1356 DEBUGFS_REG32(DC_DISP_COLOR_KEY0_LOWER),
1357 DEBUGFS_REG32(DC_DISP_COLOR_KEY0_UPPER),
1358 DEBUGFS_REG32(DC_DISP_COLOR_KEY1_LOWER),
1359 DEBUGFS_REG32(DC_DISP_COLOR_KEY1_UPPER),
1360 DEBUGFS_REG32(DC_DISP_CURSOR_FOREGROUND),
1361 DEBUGFS_REG32(DC_DISP_CURSOR_BACKGROUND),
1362 DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR),
1363 DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR_NS),
1364 DEBUGFS_REG32(DC_DISP_CURSOR_POSITION),
1365 DEBUGFS_REG32(DC_DISP_CURSOR_POSITION_NS),
1366 DEBUGFS_REG32(DC_DISP_INIT_SEQ_CONTROL),
1367 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_A),
1368 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_B),
1369 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_C),
1370 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_D),
1371 DEBUGFS_REG32(DC_DISP_DC_MCCIF_FIFOCTRL),
1372 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY0A_HYST),
1373 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY0B_HYST),
1374 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY1A_HYST),
1375 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY1B_HYST),
1376 DEBUGFS_REG32(DC_DISP_DAC_CRT_CTRL),
1377 DEBUGFS_REG32(DC_DISP_DISP_MISC_CONTROL),
1378 DEBUGFS_REG32(DC_DISP_SD_CONTROL),
1379 DEBUGFS_REG32(DC_DISP_SD_CSC_COEFF),
1380 DEBUGFS_REG32(DC_DISP_SD_LUT(0)),
1381 DEBUGFS_REG32(DC_DISP_SD_LUT(1)),
1382 DEBUGFS_REG32(DC_DISP_SD_LUT(2)),
1383 DEBUGFS_REG32(DC_DISP_SD_LUT(3)),
1384 DEBUGFS_REG32(DC_DISP_SD_LUT(4)),
1385 DEBUGFS_REG32(DC_DISP_SD_LUT(5)),
1386 DEBUGFS_REG32(DC_DISP_SD_LUT(6)),
1387 DEBUGFS_REG32(DC_DISP_SD_LUT(7)),
1388 DEBUGFS_REG32(DC_DISP_SD_LUT(8)),
1389 DEBUGFS_REG32(DC_DISP_SD_FLICKER_CONTROL),
1390 DEBUGFS_REG32(DC_DISP_DC_PIXEL_COUNT),
1391 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(0)),
1392 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(1)),
1393 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(2)),
1394 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(3)),
1395 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(4)),
1396 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(5)),
1397 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(6)),
1398 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(7)),
1399 DEBUGFS_REG32(DC_DISP_SD_BL_TF(0)),
1400 DEBUGFS_REG32(DC_DISP_SD_BL_TF(1)),
1401 DEBUGFS_REG32(DC_DISP_SD_BL_TF(2)),
1402 DEBUGFS_REG32(DC_DISP_SD_BL_TF(3)),
1403 DEBUGFS_REG32(DC_DISP_SD_BL_CONTROL),
1404 DEBUGFS_REG32(DC_DISP_SD_HW_K_VALUES),
1405 DEBUGFS_REG32(DC_DISP_SD_MAN_K_VALUES),
1406 DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR_HI),
1407 DEBUGFS_REG32(DC_DISP_BLEND_CURSOR_CONTROL),
1408 DEBUGFS_REG32(DC_WIN_WIN_OPTIONS),
1409 DEBUGFS_REG32(DC_WIN_BYTE_SWAP),
1410 DEBUGFS_REG32(DC_WIN_BUFFER_CONTROL),
1411 DEBUGFS_REG32(DC_WIN_COLOR_DEPTH),
1412 DEBUGFS_REG32(DC_WIN_POSITION),
1413 DEBUGFS_REG32(DC_WIN_SIZE),
1414 DEBUGFS_REG32(DC_WIN_PRESCALED_SIZE),
1415 DEBUGFS_REG32(DC_WIN_H_INITIAL_DDA),
1416 DEBUGFS_REG32(DC_WIN_V_INITIAL_DDA),
1417 DEBUGFS_REG32(DC_WIN_DDA_INC),
1418 DEBUGFS_REG32(DC_WIN_LINE_STRIDE),
1419 DEBUGFS_REG32(DC_WIN_BUF_STRIDE),
1420 DEBUGFS_REG32(DC_WIN_UV_BUF_STRIDE),
1421 DEBUGFS_REG32(DC_WIN_BUFFER_ADDR_MODE),
1422 DEBUGFS_REG32(DC_WIN_DV_CONTROL),
1423 DEBUGFS_REG32(DC_WIN_BLEND_NOKEY),
1424 DEBUGFS_REG32(DC_WIN_BLEND_1WIN),
1425 DEBUGFS_REG32(DC_WIN_BLEND_2WIN_X),
1426 DEBUGFS_REG32(DC_WIN_BLEND_2WIN_Y),
1427 DEBUGFS_REG32(DC_WIN_BLEND_3WIN_XY),
1428 DEBUGFS_REG32(DC_WIN_HP_FETCH_CONTROL),
1429 DEBUGFS_REG32(DC_WINBUF_START_ADDR),
1430 DEBUGFS_REG32(DC_WINBUF_START_ADDR_NS),
1431 DEBUGFS_REG32(DC_WINBUF_START_ADDR_U),
1432 DEBUGFS_REG32(DC_WINBUF_START_ADDR_U_NS),
1433 DEBUGFS_REG32(DC_WINBUF_START_ADDR_V),
1434 DEBUGFS_REG32(DC_WINBUF_START_ADDR_V_NS),
1435 DEBUGFS_REG32(DC_WINBUF_ADDR_H_OFFSET),
1436 DEBUGFS_REG32(DC_WINBUF_ADDR_H_OFFSET_NS),
1437 DEBUGFS_REG32(DC_WINBUF_ADDR_V_OFFSET),
1438 DEBUGFS_REG32(DC_WINBUF_ADDR_V_OFFSET_NS),
1439 DEBUGFS_REG32(DC_WINBUF_UFLOW_STATUS),
1440 DEBUGFS_REG32(DC_WINBUF_AD_UFLOW_STATUS),
1441 DEBUGFS_REG32(DC_WINBUF_BD_UFLOW_STATUS),
1442 DEBUGFS_REG32(DC_WINBUF_CD_UFLOW_STATUS),
1443};
1444
1445static int tegra_dc_show_regs(struct seq_file *s, void *data)
1446{
1447 struct drm_info_node *node = s->private;
1448 struct tegra_dc *dc = node->info_ent->data;
1449 unsigned int i;
1450 int err = 0;
1451
1452 drm_modeset_lock(&dc->base.mutex, NULL);
1453
1454 if (!dc->base.state->active) {
1455 err = -EBUSY;
1456 goto unlock;
1457 }
1458
1459 for (i = 0; i < ARRAY_SIZE(tegra_dc_regs); i++) {
1460 unsigned int offset = tegra_dc_regs[i].offset;
1461
1462 seq_printf(s, "%-40s %#05x %08x\n", tegra_dc_regs[i].name,
1463 offset, tegra_dc_readl(dc, offset));
1464 }
1465
1466unlock:
1467 drm_modeset_unlock(&dc->base.mutex);
1468 return err;
1469}
1470
1471static int tegra_dc_show_crc(struct seq_file *s, void *data)
1472{
1473 struct drm_info_node *node = s->private;
1474 struct tegra_dc *dc = node->info_ent->data;
1475 int err = 0;
1476 u32 value;
1477
1478 drm_modeset_lock(&dc->base.mutex, NULL);
1479
1480 if (!dc->base.state->active) {
1481 err = -EBUSY;
1482 goto unlock;
1483 }
1484
1485 value = DC_COM_CRC_CONTROL_ACTIVE_DATA | DC_COM_CRC_CONTROL_ENABLE;
1486 tegra_dc_writel(dc, value, DC_COM_CRC_CONTROL);
1487 tegra_dc_commit(dc);
1488
1489 drm_crtc_wait_one_vblank(&dc->base);
1490 drm_crtc_wait_one_vblank(&dc->base);
1491
1492 value = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM);
1493 seq_printf(s, "%08x\n", value);
1494
1495 tegra_dc_writel(dc, 0, DC_COM_CRC_CONTROL);
1496
1497unlock:
1498 drm_modeset_unlock(&dc->base.mutex);
1499 return err;
1500}
1501
1502static int tegra_dc_show_stats(struct seq_file *s, void *data)
1503{
1504 struct drm_info_node *node = s->private;
1505 struct tegra_dc *dc = node->info_ent->data;
1506
1507 seq_printf(s, "frames: %lu\n", dc->stats.frames);
1508 seq_printf(s, "vblank: %lu\n", dc->stats.vblank);
1509 seq_printf(s, "underflow: %lu\n", dc->stats.underflow);
1510 seq_printf(s, "overflow: %lu\n", dc->stats.overflow);
1511
1512 return 0;
1513}
1514
1515static struct drm_info_list debugfs_files[] = {
1516 { "regs", tegra_dc_show_regs, 0, NULL },
1517 { "crc", tegra_dc_show_crc, 0, NULL },
1518 { "stats", tegra_dc_show_stats, 0, NULL },
1519};
1520
1521static int tegra_dc_late_register(struct drm_crtc *crtc)
1522{
1523 unsigned int i, count = ARRAY_SIZE(debugfs_files);
1524 struct drm_minor *minor = crtc->dev->primary;
1525 struct dentry *root;
1526 struct tegra_dc *dc = to_tegra_dc(crtc);
1527
1528#ifdef CONFIG_DEBUG_FS
1529 root = crtc->debugfs_entry;
1530#else
1531 root = NULL;
1532#endif
1533
1534 dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1535 GFP_KERNEL);
1536 if (!dc->debugfs_files)
1537 return -ENOMEM;
1538
1539 for (i = 0; i < count; i++)
1540 dc->debugfs_files[i].data = dc;
1541
1542 drm_debugfs_create_files(dc->debugfs_files, count, root, minor);
1543
1544 return 0;
1545}
1546
1547static void tegra_dc_early_unregister(struct drm_crtc *crtc)
1548{
1549 unsigned int count = ARRAY_SIZE(debugfs_files);
1550 struct drm_minor *minor = crtc->dev->primary;
1551 struct tegra_dc *dc = to_tegra_dc(crtc);
1552
1553 drm_debugfs_remove_files(dc->debugfs_files, count, minor);
1554 kfree(dc->debugfs_files);
1555 dc->debugfs_files = NULL;
1556}
1557
1558static u32 tegra_dc_get_vblank_counter(struct drm_crtc *crtc)
1559{
1560 struct tegra_dc *dc = to_tegra_dc(crtc);
1561
1562 /* XXX vblank syncpoints don't work with nvdisplay yet */
1563 if (dc->syncpt && !dc->soc->has_nvdisplay)
1564 return host1x_syncpt_read(dc->syncpt);
1565
1566 /* fallback to software emulated VBLANK counter */
1567 return (u32)drm_crtc_vblank_count(&dc->base);
1568}
1569
1570static int tegra_dc_enable_vblank(struct drm_crtc *crtc)
1571{
1572 struct tegra_dc *dc = to_tegra_dc(crtc);
1573 u32 value;
1574
1575 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1576 value |= VBLANK_INT;
1577 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1578
1579 return 0;
1580}
1581
1582static void tegra_dc_disable_vblank(struct drm_crtc *crtc)
1583{
1584 struct tegra_dc *dc = to_tegra_dc(crtc);
1585 u32 value;
1586
1587 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1588 value &= ~VBLANK_INT;
1589 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1590}
1591
1592static const struct drm_crtc_funcs tegra_crtc_funcs = {
1593 .page_flip = drm_atomic_helper_page_flip,
1594 .set_config = drm_atomic_helper_set_config,
1595 .destroy = tegra_dc_destroy,
1596 .reset = tegra_crtc_reset,
1597 .atomic_duplicate_state = tegra_crtc_atomic_duplicate_state,
1598 .atomic_destroy_state = tegra_crtc_atomic_destroy_state,
1599 .late_register = tegra_dc_late_register,
1600 .early_unregister = tegra_dc_early_unregister,
1601 .get_vblank_counter = tegra_dc_get_vblank_counter,
1602 .enable_vblank = tegra_dc_enable_vblank,
1603 .disable_vblank = tegra_dc_disable_vblank,
1604};
1605
1606static int tegra_dc_set_timings(struct tegra_dc *dc,
1607 struct drm_display_mode *mode)
1608{
1609 unsigned int h_ref_to_sync = 1;
1610 unsigned int v_ref_to_sync = 1;
1611 unsigned long value;
1612
1613 if (!dc->soc->has_nvdisplay) {
1614 tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
1615
1616 value = (v_ref_to_sync << 16) | h_ref_to_sync;
1617 tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC);
1618 }
1619
1620 value = ((mode->vsync_end - mode->vsync_start) << 16) |
1621 ((mode->hsync_end - mode->hsync_start) << 0);
1622 tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH);
1623
1624 value = ((mode->vtotal - mode->vsync_end) << 16) |
1625 ((mode->htotal - mode->hsync_end) << 0);
1626 tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH);
1627
1628 value = ((mode->vsync_start - mode->vdisplay) << 16) |
1629 ((mode->hsync_start - mode->hdisplay) << 0);
1630 tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH);
1631
1632 value = (mode->vdisplay << 16) | mode->hdisplay;
1633 tegra_dc_writel(dc, value, DC_DISP_ACTIVE);
1634
1635 return 0;
1636}
1637
1638/**
1639 * tegra_dc_state_setup_clock - check clock settings and store them in atomic
1640 * state
1641 * @dc: display controller
1642 * @crtc_state: CRTC atomic state
1643 * @clk: parent clock for display controller
1644 * @pclk: pixel clock
1645 * @div: shift clock divider
1646 *
1647 * Returns:
1648 * 0 on success or a negative error-code on failure.
1649 */
1650int tegra_dc_state_setup_clock(struct tegra_dc *dc,
1651 struct drm_crtc_state *crtc_state,
1652 struct clk *clk, unsigned long pclk,
1653 unsigned int div)
1654{
1655 struct tegra_dc_state *state = to_dc_state(crtc_state);
1656
1657 if (!clk_has_parent(dc->clk, clk))
1658 return -EINVAL;
1659
1660 state->clk = clk;
1661 state->pclk = pclk;
1662 state->div = div;
1663
1664 return 0;
1665}
1666
1667static void tegra_dc_commit_state(struct tegra_dc *dc,
1668 struct tegra_dc_state *state)
1669{
1670 u32 value;
1671 int err;
1672
1673 err = clk_set_parent(dc->clk, state->clk);
1674 if (err < 0)
1675 dev_err(dc->dev, "failed to set parent clock: %d\n", err);
1676
1677 /*
1678 * Outputs may not want to change the parent clock rate. This is only
1679 * relevant to Tegra20 where only a single display PLL is available.
1680 * Since that PLL would typically be used for HDMI, an internal LVDS
1681 * panel would need to be driven by some other clock such as PLL_P
1682 * which is shared with other peripherals. Changing the clock rate
1683 * should therefore be avoided.
1684 */
1685 if (state->pclk > 0) {
1686 err = clk_set_rate(state->clk, state->pclk);
1687 if (err < 0)
1688 dev_err(dc->dev,
1689 "failed to set clock rate to %lu Hz\n",
1690 state->pclk);
1691 }
1692
1693 DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk),
1694 state->div);
1695 DRM_DEBUG_KMS("pclk: %lu\n", state->pclk);
1696
1697 if (!dc->soc->has_nvdisplay) {
1698 value = SHIFT_CLK_DIVIDER(state->div) | PIXEL_CLK_DIVIDER_PCD1;
1699 tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);
1700 }
1701
1702 err = clk_set_rate(dc->clk, state->pclk);
1703 if (err < 0)
1704 dev_err(dc->dev, "failed to set clock %pC to %lu Hz: %d\n",
1705 dc->clk, state->pclk, err);
1706}
1707
1708static void tegra_dc_stop(struct tegra_dc *dc)
1709{
1710 u32 value;
1711
1712 /* stop the display controller */
1713 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
1714 value &= ~DISP_CTRL_MODE_MASK;
1715 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
1716
1717 tegra_dc_commit(dc);
1718}
1719
1720static bool tegra_dc_idle(struct tegra_dc *dc)
1721{
1722 u32 value;
1723
1724 value = tegra_dc_readl_active(dc, DC_CMD_DISPLAY_COMMAND);
1725
1726 return (value & DISP_CTRL_MODE_MASK) == 0;
1727}
1728
1729static int tegra_dc_wait_idle(struct tegra_dc *dc, unsigned long timeout)
1730{
1731 timeout = jiffies + msecs_to_jiffies(timeout);
1732
1733 while (time_before(jiffies, timeout)) {
1734 if (tegra_dc_idle(dc))
1735 return 0;
1736
1737 usleep_range(1000, 2000);
1738 }
1739
1740 dev_dbg(dc->dev, "timeout waiting for DC to become idle\n");
1741 return -ETIMEDOUT;
1742}
1743
1744static void tegra_crtc_atomic_disable(struct drm_crtc *crtc,
1745 struct drm_crtc_state *old_state)
1746{
1747 struct tegra_dc *dc = to_tegra_dc(crtc);
1748 u32 value;
1749 int err;
1750
1751 if (!tegra_dc_idle(dc)) {
1752 tegra_dc_stop(dc);
1753
1754 /*
1755 * Ignore the return value, there isn't anything useful to do
1756 * in case this fails.
1757 */
1758 tegra_dc_wait_idle(dc, 100);
1759 }
1760
1761 /*
1762 * This should really be part of the RGB encoder driver, but clearing
1763 * these bits has the side-effect of stopping the display controller.
1764 * When that happens no VBLANK interrupts will be raised. At the same
1765 * time the encoder is disabled before the display controller, so the
1766 * above code is always going to timeout waiting for the controller
1767 * to go idle.
1768 *
1769 * Given the close coupling between the RGB encoder and the display
1770 * controller doing it here is still kind of okay. None of the other
1771 * encoder drivers require these bits to be cleared.
1772 *
1773 * XXX: Perhaps given that the display controller is switched off at
1774 * this point anyway maybe clearing these bits isn't even useful for
1775 * the RGB encoder?
1776 */
1777 if (dc->rgb) {
1778 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
1779 value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1780 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE);
1781 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
1782 }
1783
1784 tegra_dc_stats_reset(&dc->stats);
1785 drm_crtc_vblank_off(crtc);
1786
1787 spin_lock_irq(&crtc->dev->event_lock);
1788
1789 if (crtc->state->event) {
1790 drm_crtc_send_vblank_event(crtc, crtc->state->event);
1791 crtc->state->event = NULL;
1792 }
1793
1794 spin_unlock_irq(&crtc->dev->event_lock);
1795
1796 err = host1x_client_suspend(&dc->client);
1797 if (err < 0)
1798 dev_err(dc->dev, "failed to suspend: %d\n", err);
1799}
1800
1801static void tegra_crtc_atomic_enable(struct drm_crtc *crtc,
1802 struct drm_crtc_state *old_state)
1803{
1804 struct drm_display_mode *mode = &crtc->state->adjusted_mode;
1805 struct tegra_dc_state *state = to_dc_state(crtc->state);
1806 struct tegra_dc *dc = to_tegra_dc(crtc);
1807 u32 value;
1808 int err;
1809
1810 err = host1x_client_resume(&dc->client);
1811 if (err < 0) {
1812 dev_err(dc->dev, "failed to resume: %d\n", err);
1813 return;
1814 }
1815
1816 /* initialize display controller */
1817 if (dc->syncpt) {
1818 u32 syncpt = host1x_syncpt_id(dc->syncpt), enable;
1819
1820 if (dc->soc->has_nvdisplay)
1821 enable = 1 << 31;
1822 else
1823 enable = 1 << 8;
1824
1825 value = SYNCPT_CNTRL_NO_STALL;
1826 tegra_dc_writel(dc, value, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1827
1828 value = enable | syncpt;
1829 tegra_dc_writel(dc, value, DC_CMD_CONT_SYNCPT_VSYNC);
1830 }
1831
1832 if (dc->soc->has_nvdisplay) {
1833 value = DSC_TO_UF_INT | DSC_BBUF_UF_INT | DSC_RBUF_UF_INT |
1834 DSC_OBUF_UF_INT;
1835 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
1836
1837 value = DSC_TO_UF_INT | DSC_BBUF_UF_INT | DSC_RBUF_UF_INT |
1838 DSC_OBUF_UF_INT | SD3_BUCKET_WALK_DONE_INT |
1839 HEAD_UF_INT | MSF_INT | REG_TMOUT_INT |
1840 REGION_CRC_INT | V_PULSE2_INT | V_PULSE3_INT |
1841 VBLANK_INT | FRAME_END_INT;
1842 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
1843
1844 value = SD3_BUCKET_WALK_DONE_INT | HEAD_UF_INT | VBLANK_INT |
1845 FRAME_END_INT;
1846 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
1847
1848 value = HEAD_UF_INT | REG_TMOUT_INT | FRAME_END_INT;
1849 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1850
1851 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
1852 } else {
1853 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1854 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1855 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
1856
1857 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1858 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1859 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
1860
1861 /* initialize timer */
1862 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |
1863 WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20);
1864 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);
1865
1866 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |
1867 WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1);
1868 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
1869
1870 value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1871 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1872 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
1873
1874 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1875 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1876 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1877 }
1878
1879 if (dc->soc->supports_background_color)
1880 tegra_dc_writel(dc, 0, DC_DISP_BLEND_BACKGROUND_COLOR);
1881 else
1882 tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR);
1883
1884 /* apply PLL and pixel clock changes */
1885 tegra_dc_commit_state(dc, state);
1886
1887 /* program display mode */
1888 tegra_dc_set_timings(dc, mode);
1889
1890 /* interlacing isn't supported yet, so disable it */
1891 if (dc->soc->supports_interlacing) {
1892 value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL);
1893 value &= ~INTERLACE_ENABLE;
1894 tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL);
1895 }
1896
1897 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
1898 value &= ~DISP_CTRL_MODE_MASK;
1899 value |= DISP_CTRL_MODE_C_DISPLAY;
1900 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
1901
1902 if (!dc->soc->has_nvdisplay) {
1903 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
1904 value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1905 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
1906 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
1907 }
1908
1909 /* enable underflow reporting and display red for missing pixels */
1910 if (dc->soc->has_nvdisplay) {
1911 value = UNDERFLOW_MODE_RED | UNDERFLOW_REPORT_ENABLE;
1912 tegra_dc_writel(dc, value, DC_COM_RG_UNDERFLOW);
1913 }
1914
1915 tegra_dc_commit(dc);
1916
1917 drm_crtc_vblank_on(crtc);
1918}
1919
1920static void tegra_crtc_atomic_begin(struct drm_crtc *crtc,
1921 struct drm_crtc_state *old_crtc_state)
1922{
1923 unsigned long flags;
1924
1925 if (crtc->state->event) {
1926 spin_lock_irqsave(&crtc->dev->event_lock, flags);
1927
1928 if (drm_crtc_vblank_get(crtc) != 0)
1929 drm_crtc_send_vblank_event(crtc, crtc->state->event);
1930 else
1931 drm_crtc_arm_vblank_event(crtc, crtc->state->event);
1932
1933 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
1934
1935 crtc->state->event = NULL;
1936 }
1937}
1938
1939static void tegra_crtc_atomic_flush(struct drm_crtc *crtc,
1940 struct drm_crtc_state *old_crtc_state)
1941{
1942 struct tegra_dc_state *state = to_dc_state(crtc->state);
1943 struct tegra_dc *dc = to_tegra_dc(crtc);
1944 u32 value;
1945
1946 value = state->planes << 8 | GENERAL_UPDATE;
1947 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
1948 value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
1949
1950 value = state->planes | GENERAL_ACT_REQ;
1951 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
1952 value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
1953}
1954
1955static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = {
1956 .atomic_begin = tegra_crtc_atomic_begin,
1957 .atomic_flush = tegra_crtc_atomic_flush,
1958 .atomic_enable = tegra_crtc_atomic_enable,
1959 .atomic_disable = tegra_crtc_atomic_disable,
1960};
1961
1962static irqreturn_t tegra_dc_irq(int irq, void *data)
1963{
1964 struct tegra_dc *dc = data;
1965 unsigned long status;
1966
1967 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1968 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
1969
1970 if (status & FRAME_END_INT) {
1971 /*
1972 dev_dbg(dc->dev, "%s(): frame end\n", __func__);
1973 */
1974 dc->stats.frames++;
1975 }
1976
1977 if (status & VBLANK_INT) {
1978 /*
1979 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__);
1980 */
1981 drm_crtc_handle_vblank(&dc->base);
1982 dc->stats.vblank++;
1983 }
1984
1985 if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) {
1986 /*
1987 dev_dbg(dc->dev, "%s(): underflow\n", __func__);
1988 */
1989 dc->stats.underflow++;
1990 }
1991
1992 if (status & (WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT)) {
1993 /*
1994 dev_dbg(dc->dev, "%s(): overflow\n", __func__);
1995 */
1996 dc->stats.overflow++;
1997 }
1998
1999 if (status & HEAD_UF_INT) {
2000 dev_dbg_ratelimited(dc->dev, "%s(): head underflow\n", __func__);
2001 dc->stats.underflow++;
2002 }
2003
2004 return IRQ_HANDLED;
2005}
2006
2007static bool tegra_dc_has_window_groups(struct tegra_dc *dc)
2008{
2009 unsigned int i;
2010
2011 if (!dc->soc->wgrps)
2012 return true;
2013
2014 for (i = 0; i < dc->soc->num_wgrps; i++) {
2015 const struct tegra_windowgroup_soc *wgrp = &dc->soc->wgrps[i];
2016
2017 if (wgrp->dc == dc->pipe && wgrp->num_windows > 0)
2018 return true;
2019 }
2020
2021 return false;
2022}
2023
2024static int tegra_dc_init(struct host1x_client *client)
2025{
2026 struct drm_device *drm = dev_get_drvdata(client->host);
2027 unsigned long flags = HOST1X_SYNCPT_CLIENT_MANAGED;
2028 struct tegra_dc *dc = host1x_client_to_dc(client);
2029 struct tegra_drm *tegra = drm->dev_private;
2030 struct drm_plane *primary = NULL;
2031 struct drm_plane *cursor = NULL;
2032 int err;
2033
2034 /*
2035 * XXX do not register DCs with no window groups because we cannot
2036 * assign a primary plane to them, which in turn will cause KMS to
2037 * crash.
2038 */
2039 if (!tegra_dc_has_window_groups(dc))
2040 return 0;
2041
2042 /*
2043 * Set the display hub as the host1x client parent for the display
2044 * controller. This is needed for the runtime reference counting that
2045 * ensures the display hub is always powered when any of the display
2046 * controllers are.
2047 */
2048 if (dc->soc->has_nvdisplay)
2049 client->parent = &tegra->hub->client;
2050
2051 dc->syncpt = host1x_syncpt_request(client, flags);
2052 if (!dc->syncpt)
2053 dev_warn(dc->dev, "failed to allocate syncpoint\n");
2054
2055 err = host1x_client_iommu_attach(client);
2056 if (err < 0 && err != -ENODEV) {
2057 dev_err(client->dev, "failed to attach to domain: %d\n", err);
2058 return err;
2059 }
2060
2061 if (dc->soc->wgrps)
2062 primary = tegra_dc_add_shared_planes(drm, dc);
2063 else
2064 primary = tegra_dc_add_planes(drm, dc);
2065
2066 if (IS_ERR(primary)) {
2067 err = PTR_ERR(primary);
2068 goto cleanup;
2069 }
2070
2071 if (dc->soc->supports_cursor) {
2072 cursor = tegra_dc_cursor_plane_create(drm, dc);
2073 if (IS_ERR(cursor)) {
2074 err = PTR_ERR(cursor);
2075 goto cleanup;
2076 }
2077 } else {
2078 /* dedicate one overlay to mouse cursor */
2079 cursor = tegra_dc_overlay_plane_create(drm, dc, 2, true);
2080 if (IS_ERR(cursor)) {
2081 err = PTR_ERR(cursor);
2082 goto cleanup;
2083 }
2084 }
2085
2086 err = drm_crtc_init_with_planes(drm, &dc->base, primary, cursor,
2087 &tegra_crtc_funcs, NULL);
2088 if (err < 0)
2089 goto cleanup;
2090
2091 drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs);
2092
2093 /*
2094 * Keep track of the minimum pitch alignment across all display
2095 * controllers.
2096 */
2097 if (dc->soc->pitch_align > tegra->pitch_align)
2098 tegra->pitch_align = dc->soc->pitch_align;
2099
2100 err = tegra_dc_rgb_init(drm, dc);
2101 if (err < 0 && err != -ENODEV) {
2102 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err);
2103 goto cleanup;
2104 }
2105
2106 err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0,
2107 dev_name(dc->dev), dc);
2108 if (err < 0) {
2109 dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq,
2110 err);
2111 goto cleanup;
2112 }
2113
2114 /*
2115 * Inherit the DMA parameters (such as maximum segment size) from the
2116 * parent host1x device.
2117 */
2118 client->dev->dma_parms = client->host->dma_parms;
2119
2120 return 0;
2121
2122cleanup:
2123 if (!IS_ERR_OR_NULL(cursor))
2124 drm_plane_cleanup(cursor);
2125
2126 if (!IS_ERR(primary))
2127 drm_plane_cleanup(primary);
2128
2129 host1x_client_iommu_detach(client);
2130 host1x_syncpt_free(dc->syncpt);
2131
2132 return err;
2133}
2134
2135static int tegra_dc_exit(struct host1x_client *client)
2136{
2137 struct tegra_dc *dc = host1x_client_to_dc(client);
2138 int err;
2139
2140 if (!tegra_dc_has_window_groups(dc))
2141 return 0;
2142
2143 /* avoid a dangling pointer just in case this disappears */
2144 client->dev->dma_parms = NULL;
2145
2146 devm_free_irq(dc->dev, dc->irq, dc);
2147
2148 err = tegra_dc_rgb_exit(dc);
2149 if (err) {
2150 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err);
2151 return err;
2152 }
2153
2154 host1x_client_iommu_detach(client);
2155 host1x_syncpt_free(dc->syncpt);
2156
2157 return 0;
2158}
2159
2160static int tegra_dc_runtime_suspend(struct host1x_client *client)
2161{
2162 struct tegra_dc *dc = host1x_client_to_dc(client);
2163 struct device *dev = client->dev;
2164 int err;
2165
2166 err = reset_control_assert(dc->rst);
2167 if (err < 0) {
2168 dev_err(dev, "failed to assert reset: %d\n", err);
2169 return err;
2170 }
2171
2172 if (dc->soc->has_powergate)
2173 tegra_powergate_power_off(dc->powergate);
2174
2175 clk_disable_unprepare(dc->clk);
2176 pm_runtime_put_sync(dev);
2177
2178 return 0;
2179}
2180
2181static int tegra_dc_runtime_resume(struct host1x_client *client)
2182{
2183 struct tegra_dc *dc = host1x_client_to_dc(client);
2184 struct device *dev = client->dev;
2185 int err;
2186
2187 err = pm_runtime_get_sync(dev);
2188 if (err < 0) {
2189 dev_err(dev, "failed to get runtime PM: %d\n", err);
2190 return err;
2191 }
2192
2193 if (dc->soc->has_powergate) {
2194 err = tegra_powergate_sequence_power_up(dc->powergate, dc->clk,
2195 dc->rst);
2196 if (err < 0) {
2197 dev_err(dev, "failed to power partition: %d\n", err);
2198 goto put_rpm;
2199 }
2200 } else {
2201 err = clk_prepare_enable(dc->clk);
2202 if (err < 0) {
2203 dev_err(dev, "failed to enable clock: %d\n", err);
2204 goto put_rpm;
2205 }
2206
2207 err = reset_control_deassert(dc->rst);
2208 if (err < 0) {
2209 dev_err(dev, "failed to deassert reset: %d\n", err);
2210 goto disable_clk;
2211 }
2212 }
2213
2214 return 0;
2215
2216disable_clk:
2217 clk_disable_unprepare(dc->clk);
2218put_rpm:
2219 pm_runtime_put_sync(dev);
2220 return err;
2221}
2222
2223static const struct host1x_client_ops dc_client_ops = {
2224 .init = tegra_dc_init,
2225 .exit = tegra_dc_exit,
2226 .suspend = tegra_dc_runtime_suspend,
2227 .resume = tegra_dc_runtime_resume,
2228};
2229
2230static const struct tegra_dc_soc_info tegra20_dc_soc_info = {
2231 .supports_background_color = false,
2232 .supports_interlacing = false,
2233 .supports_cursor = false,
2234 .supports_block_linear = false,
2235 .has_legacy_blending = true,
2236 .pitch_align = 8,
2237 .has_powergate = false,
2238 .coupled_pm = true,
2239 .has_nvdisplay = false,
2240 .num_primary_formats = ARRAY_SIZE(tegra20_primary_formats),
2241 .primary_formats = tegra20_primary_formats,
2242 .num_overlay_formats = ARRAY_SIZE(tegra20_overlay_formats),
2243 .overlay_formats = tegra20_overlay_formats,
2244 .modifiers = tegra20_modifiers,
2245 .has_win_a_without_filters = true,
2246 .has_win_c_without_vert_filter = true,
2247};
2248
2249static const struct tegra_dc_soc_info tegra30_dc_soc_info = {
2250 .supports_background_color = false,
2251 .supports_interlacing = false,
2252 .supports_cursor = false,
2253 .supports_block_linear = false,
2254 .has_legacy_blending = true,
2255 .pitch_align = 8,
2256 .has_powergate = false,
2257 .coupled_pm = false,
2258 .has_nvdisplay = false,
2259 .num_primary_formats = ARRAY_SIZE(tegra20_primary_formats),
2260 .primary_formats = tegra20_primary_formats,
2261 .num_overlay_formats = ARRAY_SIZE(tegra20_overlay_formats),
2262 .overlay_formats = tegra20_overlay_formats,
2263 .modifiers = tegra20_modifiers,
2264 .has_win_a_without_filters = false,
2265 .has_win_c_without_vert_filter = false,
2266};
2267
2268static const struct tegra_dc_soc_info tegra114_dc_soc_info = {
2269 .supports_background_color = false,
2270 .supports_interlacing = false,
2271 .supports_cursor = false,
2272 .supports_block_linear = false,
2273 .has_legacy_blending = true,
2274 .pitch_align = 64,
2275 .has_powergate = true,
2276 .coupled_pm = false,
2277 .has_nvdisplay = false,
2278 .num_primary_formats = ARRAY_SIZE(tegra114_primary_formats),
2279 .primary_formats = tegra114_primary_formats,
2280 .num_overlay_formats = ARRAY_SIZE(tegra114_overlay_formats),
2281 .overlay_formats = tegra114_overlay_formats,
2282 .modifiers = tegra20_modifiers,
2283 .has_win_a_without_filters = false,
2284 .has_win_c_without_vert_filter = false,
2285};
2286
2287static const struct tegra_dc_soc_info tegra124_dc_soc_info = {
2288 .supports_background_color = true,
2289 .supports_interlacing = true,
2290 .supports_cursor = true,
2291 .supports_block_linear = true,
2292 .has_legacy_blending = false,
2293 .pitch_align = 64,
2294 .has_powergate = true,
2295 .coupled_pm = false,
2296 .has_nvdisplay = false,
2297 .num_primary_formats = ARRAY_SIZE(tegra124_primary_formats),
2298 .primary_formats = tegra124_primary_formats,
2299 .num_overlay_formats = ARRAY_SIZE(tegra124_overlay_formats),
2300 .overlay_formats = tegra124_overlay_formats,
2301 .modifiers = tegra124_modifiers,
2302 .has_win_a_without_filters = false,
2303 .has_win_c_without_vert_filter = false,
2304};
2305
2306static const struct tegra_dc_soc_info tegra210_dc_soc_info = {
2307 .supports_background_color = true,
2308 .supports_interlacing = true,
2309 .supports_cursor = true,
2310 .supports_block_linear = true,
2311 .has_legacy_blending = false,
2312 .pitch_align = 64,
2313 .has_powergate = true,
2314 .coupled_pm = false,
2315 .has_nvdisplay = false,
2316 .num_primary_formats = ARRAY_SIZE(tegra114_primary_formats),
2317 .primary_formats = tegra114_primary_formats,
2318 .num_overlay_formats = ARRAY_SIZE(tegra114_overlay_formats),
2319 .overlay_formats = tegra114_overlay_formats,
2320 .modifiers = tegra124_modifiers,
2321 .has_win_a_without_filters = false,
2322 .has_win_c_without_vert_filter = false,
2323};
2324
2325static const struct tegra_windowgroup_soc tegra186_dc_wgrps[] = {
2326 {
2327 .index = 0,
2328 .dc = 0,
2329 .windows = (const unsigned int[]) { 0 },
2330 .num_windows = 1,
2331 }, {
2332 .index = 1,
2333 .dc = 1,
2334 .windows = (const unsigned int[]) { 1 },
2335 .num_windows = 1,
2336 }, {
2337 .index = 2,
2338 .dc = 1,
2339 .windows = (const unsigned int[]) { 2 },
2340 .num_windows = 1,
2341 }, {
2342 .index = 3,
2343 .dc = 2,
2344 .windows = (const unsigned int[]) { 3 },
2345 .num_windows = 1,
2346 }, {
2347 .index = 4,
2348 .dc = 2,
2349 .windows = (const unsigned int[]) { 4 },
2350 .num_windows = 1,
2351 }, {
2352 .index = 5,
2353 .dc = 2,
2354 .windows = (const unsigned int[]) { 5 },
2355 .num_windows = 1,
2356 },
2357};
2358
2359static const struct tegra_dc_soc_info tegra186_dc_soc_info = {
2360 .supports_background_color = true,
2361 .supports_interlacing = true,
2362 .supports_cursor = true,
2363 .supports_block_linear = true,
2364 .has_legacy_blending = false,
2365 .pitch_align = 64,
2366 .has_powergate = false,
2367 .coupled_pm = false,
2368 .has_nvdisplay = true,
2369 .wgrps = tegra186_dc_wgrps,
2370 .num_wgrps = ARRAY_SIZE(tegra186_dc_wgrps),
2371};
2372
2373static const struct tegra_windowgroup_soc tegra194_dc_wgrps[] = {
2374 {
2375 .index = 0,
2376 .dc = 0,
2377 .windows = (const unsigned int[]) { 0 },
2378 .num_windows = 1,
2379 }, {
2380 .index = 1,
2381 .dc = 1,
2382 .windows = (const unsigned int[]) { 1 },
2383 .num_windows = 1,
2384 }, {
2385 .index = 2,
2386 .dc = 1,
2387 .windows = (const unsigned int[]) { 2 },
2388 .num_windows = 1,
2389 }, {
2390 .index = 3,
2391 .dc = 2,
2392 .windows = (const unsigned int[]) { 3 },
2393 .num_windows = 1,
2394 }, {
2395 .index = 4,
2396 .dc = 2,
2397 .windows = (const unsigned int[]) { 4 },
2398 .num_windows = 1,
2399 }, {
2400 .index = 5,
2401 .dc = 2,
2402 .windows = (const unsigned int[]) { 5 },
2403 .num_windows = 1,
2404 },
2405};
2406
2407static const struct tegra_dc_soc_info tegra194_dc_soc_info = {
2408 .supports_background_color = true,
2409 .supports_interlacing = true,
2410 .supports_cursor = true,
2411 .supports_block_linear = true,
2412 .has_legacy_blending = false,
2413 .pitch_align = 64,
2414 .has_powergate = false,
2415 .coupled_pm = false,
2416 .has_nvdisplay = true,
2417 .wgrps = tegra194_dc_wgrps,
2418 .num_wgrps = ARRAY_SIZE(tegra194_dc_wgrps),
2419};
2420
2421static const struct of_device_id tegra_dc_of_match[] = {
2422 {
2423 .compatible = "nvidia,tegra194-dc",
2424 .data = &tegra194_dc_soc_info,
2425 }, {
2426 .compatible = "nvidia,tegra186-dc",
2427 .data = &tegra186_dc_soc_info,
2428 }, {
2429 .compatible = "nvidia,tegra210-dc",
2430 .data = &tegra210_dc_soc_info,
2431 }, {
2432 .compatible = "nvidia,tegra124-dc",
2433 .data = &tegra124_dc_soc_info,
2434 }, {
2435 .compatible = "nvidia,tegra114-dc",
2436 .data = &tegra114_dc_soc_info,
2437 }, {
2438 .compatible = "nvidia,tegra30-dc",
2439 .data = &tegra30_dc_soc_info,
2440 }, {
2441 .compatible = "nvidia,tegra20-dc",
2442 .data = &tegra20_dc_soc_info,
2443 }, {
2444 /* sentinel */
2445 }
2446};
2447MODULE_DEVICE_TABLE(of, tegra_dc_of_match);
2448
2449static int tegra_dc_parse_dt(struct tegra_dc *dc)
2450{
2451 struct device_node *np;
2452 u32 value = 0;
2453 int err;
2454
2455 err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value);
2456 if (err < 0) {
2457 dev_err(dc->dev, "missing \"nvidia,head\" property\n");
2458
2459 /*
2460 * If the nvidia,head property isn't present, try to find the
2461 * correct head number by looking up the position of this
2462 * display controller's node within the device tree. Assuming
2463 * that the nodes are ordered properly in the DTS file and
2464 * that the translation into a flattened device tree blob
2465 * preserves that ordering this will actually yield the right
2466 * head number.
2467 *
2468 * If those assumptions don't hold, this will still work for
2469 * cases where only a single display controller is used.
2470 */
2471 for_each_matching_node(np, tegra_dc_of_match) {
2472 if (np == dc->dev->of_node) {
2473 of_node_put(np);
2474 break;
2475 }
2476
2477 value++;
2478 }
2479 }
2480
2481 dc->pipe = value;
2482
2483 return 0;
2484}
2485
2486static int tegra_dc_match_by_pipe(struct device *dev, const void *data)
2487{
2488 struct tegra_dc *dc = dev_get_drvdata(dev);
2489 unsigned int pipe = (unsigned long)(void *)data;
2490
2491 return dc->pipe == pipe;
2492}
2493
2494static int tegra_dc_couple(struct tegra_dc *dc)
2495{
2496 /*
2497 * On Tegra20, DC1 requires DC0 to be taken out of reset in order to
2498 * be enabled, otherwise CPU hangs on writing to CMD_DISPLAY_COMMAND /
2499 * POWER_CONTROL registers during CRTC enabling.
2500 */
2501 if (dc->soc->coupled_pm && dc->pipe == 1) {
2502 u32 flags = DL_FLAG_PM_RUNTIME | DL_FLAG_AUTOREMOVE_CONSUMER;
2503 struct device_link *link;
2504 struct device *partner;
2505
2506 partner = driver_find_device(dc->dev->driver, NULL, NULL,
2507 tegra_dc_match_by_pipe);
2508 if (!partner)
2509 return -EPROBE_DEFER;
2510
2511 link = device_link_add(dc->dev, partner, flags);
2512 if (!link) {
2513 dev_err(dc->dev, "failed to link controllers\n");
2514 return -EINVAL;
2515 }
2516
2517 dev_dbg(dc->dev, "coupled to %s\n", dev_name(partner));
2518 }
2519
2520 return 0;
2521}
2522
2523static int tegra_dc_probe(struct platform_device *pdev)
2524{
2525 struct tegra_dc *dc;
2526 int err;
2527
2528 dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL);
2529 if (!dc)
2530 return -ENOMEM;
2531
2532 dc->soc = of_device_get_match_data(&pdev->dev);
2533
2534 INIT_LIST_HEAD(&dc->list);
2535 dc->dev = &pdev->dev;
2536
2537 err = tegra_dc_parse_dt(dc);
2538 if (err < 0)
2539 return err;
2540
2541 err = tegra_dc_couple(dc);
2542 if (err < 0)
2543 return err;
2544
2545 dc->clk = devm_clk_get(&pdev->dev, NULL);
2546 if (IS_ERR(dc->clk)) {
2547 dev_err(&pdev->dev, "failed to get clock\n");
2548 return PTR_ERR(dc->clk);
2549 }
2550
2551 dc->rst = devm_reset_control_get(&pdev->dev, "dc");
2552 if (IS_ERR(dc->rst)) {
2553 dev_err(&pdev->dev, "failed to get reset\n");
2554 return PTR_ERR(dc->rst);
2555 }
2556
2557 /* assert reset and disable clock */
2558 err = clk_prepare_enable(dc->clk);
2559 if (err < 0)
2560 return err;
2561
2562 usleep_range(2000, 4000);
2563
2564 err = reset_control_assert(dc->rst);
2565 if (err < 0)
2566 return err;
2567
2568 usleep_range(2000, 4000);
2569
2570 clk_disable_unprepare(dc->clk);
2571
2572 if (dc->soc->has_powergate) {
2573 if (dc->pipe == 0)
2574 dc->powergate = TEGRA_POWERGATE_DIS;
2575 else
2576 dc->powergate = TEGRA_POWERGATE_DISB;
2577
2578 tegra_powergate_power_off(dc->powergate);
2579 }
2580
2581 dc->regs = devm_platform_ioremap_resource(pdev, 0);
2582 if (IS_ERR(dc->regs))
2583 return PTR_ERR(dc->regs);
2584
2585 dc->irq = platform_get_irq(pdev, 0);
2586 if (dc->irq < 0)
2587 return -ENXIO;
2588
2589 err = tegra_dc_rgb_probe(dc);
2590 if (err < 0 && err != -ENODEV) {
2591 const char *level = KERN_ERR;
2592
2593 if (err == -EPROBE_DEFER)
2594 level = KERN_DEBUG;
2595
2596 dev_printk(level, dc->dev, "failed to probe RGB output: %d\n",
2597 err);
2598 return err;
2599 }
2600
2601 platform_set_drvdata(pdev, dc);
2602 pm_runtime_enable(&pdev->dev);
2603
2604 INIT_LIST_HEAD(&dc->client.list);
2605 dc->client.ops = &dc_client_ops;
2606 dc->client.dev = &pdev->dev;
2607
2608 err = host1x_client_register(&dc->client);
2609 if (err < 0) {
2610 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
2611 err);
2612 goto disable_pm;
2613 }
2614
2615 return 0;
2616
2617disable_pm:
2618 pm_runtime_disable(&pdev->dev);
2619 tegra_dc_rgb_remove(dc);
2620
2621 return err;
2622}
2623
2624static int tegra_dc_remove(struct platform_device *pdev)
2625{
2626 struct tegra_dc *dc = platform_get_drvdata(pdev);
2627 int err;
2628
2629 err = host1x_client_unregister(&dc->client);
2630 if (err < 0) {
2631 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
2632 err);
2633 return err;
2634 }
2635
2636 err = tegra_dc_rgb_remove(dc);
2637 if (err < 0) {
2638 dev_err(&pdev->dev, "failed to remove RGB output: %d\n", err);
2639 return err;
2640 }
2641
2642 pm_runtime_disable(&pdev->dev);
2643
2644 return 0;
2645}
2646
2647struct platform_driver tegra_dc_driver = {
2648 .driver = {
2649 .name = "tegra-dc",
2650 .of_match_table = tegra_dc_of_match,
2651 },
2652 .probe = tegra_dc_probe,
2653 .remove = tegra_dc_remove,
2654};
1/*
2 * Copyright (C) 2012 Avionic Design GmbH
3 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#include <linux/clk.h>
11#include <linux/debugfs.h>
12#include <linux/iommu.h>
13#include <linux/pm_runtime.h>
14#include <linux/reset.h>
15
16#include <soc/tegra/pmc.h>
17
18#include "dc.h"
19#include "drm.h"
20#include "gem.h"
21
22#include <drm/drm_atomic.h>
23#include <drm/drm_atomic_helper.h>
24#include <drm/drm_plane_helper.h>
25
26struct tegra_dc_soc_info {
27 bool supports_border_color;
28 bool supports_interlacing;
29 bool supports_cursor;
30 bool supports_block_linear;
31 unsigned int pitch_align;
32 bool has_powergate;
33};
34
35struct tegra_plane {
36 struct drm_plane base;
37 unsigned int index;
38};
39
40static inline struct tegra_plane *to_tegra_plane(struct drm_plane *plane)
41{
42 return container_of(plane, struct tegra_plane, base);
43}
44
45struct tegra_dc_state {
46 struct drm_crtc_state base;
47
48 struct clk *clk;
49 unsigned long pclk;
50 unsigned int div;
51
52 u32 planes;
53};
54
55static inline struct tegra_dc_state *to_dc_state(struct drm_crtc_state *state)
56{
57 if (state)
58 return container_of(state, struct tegra_dc_state, base);
59
60 return NULL;
61}
62
63struct tegra_plane_state {
64 struct drm_plane_state base;
65
66 struct tegra_bo_tiling tiling;
67 u32 format;
68 u32 swap;
69};
70
71static inline struct tegra_plane_state *
72to_tegra_plane_state(struct drm_plane_state *state)
73{
74 if (state)
75 return container_of(state, struct tegra_plane_state, base);
76
77 return NULL;
78}
79
80static void tegra_dc_stats_reset(struct tegra_dc_stats *stats)
81{
82 stats->frames = 0;
83 stats->vblank = 0;
84 stats->underflow = 0;
85 stats->overflow = 0;
86}
87
88/*
89 * Reads the active copy of a register. This takes the dc->lock spinlock to
90 * prevent races with the VBLANK processing which also needs access to the
91 * active copy of some registers.
92 */
93static u32 tegra_dc_readl_active(struct tegra_dc *dc, unsigned long offset)
94{
95 unsigned long flags;
96 u32 value;
97
98 spin_lock_irqsave(&dc->lock, flags);
99
100 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
101 value = tegra_dc_readl(dc, offset);
102 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
103
104 spin_unlock_irqrestore(&dc->lock, flags);
105 return value;
106}
107
108/*
109 * Double-buffered registers have two copies: ASSEMBLY and ACTIVE. When the
110 * *_ACT_REQ bits are set the ASSEMBLY copy is latched into the ACTIVE copy.
111 * Latching happens mmediately if the display controller is in STOP mode or
112 * on the next frame boundary otherwise.
113 *
114 * Triple-buffered registers have three copies: ASSEMBLY, ARM and ACTIVE. The
115 * ASSEMBLY copy is latched into the ARM copy immediately after *_UPDATE bits
116 * are written. When the *_ACT_REQ bits are written, the ARM copy is latched
117 * into the ACTIVE copy, either immediately if the display controller is in
118 * STOP mode, or at the next frame boundary otherwise.
119 */
120void tegra_dc_commit(struct tegra_dc *dc)
121{
122 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
123 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
124}
125
126static int tegra_dc_format(u32 fourcc, u32 *format, u32 *swap)
127{
128 /* assume no swapping of fetched data */
129 if (swap)
130 *swap = BYTE_SWAP_NOSWAP;
131
132 switch (fourcc) {
133 case DRM_FORMAT_XBGR8888:
134 *format = WIN_COLOR_DEPTH_R8G8B8A8;
135 break;
136
137 case DRM_FORMAT_XRGB8888:
138 *format = WIN_COLOR_DEPTH_B8G8R8A8;
139 break;
140
141 case DRM_FORMAT_RGB565:
142 *format = WIN_COLOR_DEPTH_B5G6R5;
143 break;
144
145 case DRM_FORMAT_UYVY:
146 *format = WIN_COLOR_DEPTH_YCbCr422;
147 break;
148
149 case DRM_FORMAT_YUYV:
150 if (swap)
151 *swap = BYTE_SWAP_SWAP2;
152
153 *format = WIN_COLOR_DEPTH_YCbCr422;
154 break;
155
156 case DRM_FORMAT_YUV420:
157 *format = WIN_COLOR_DEPTH_YCbCr420P;
158 break;
159
160 case DRM_FORMAT_YUV422:
161 *format = WIN_COLOR_DEPTH_YCbCr422P;
162 break;
163
164 default:
165 return -EINVAL;
166 }
167
168 return 0;
169}
170
171static bool tegra_dc_format_is_yuv(unsigned int format, bool *planar)
172{
173 switch (format) {
174 case WIN_COLOR_DEPTH_YCbCr422:
175 case WIN_COLOR_DEPTH_YUV422:
176 if (planar)
177 *planar = false;
178
179 return true;
180
181 case WIN_COLOR_DEPTH_YCbCr420P:
182 case WIN_COLOR_DEPTH_YUV420P:
183 case WIN_COLOR_DEPTH_YCbCr422P:
184 case WIN_COLOR_DEPTH_YUV422P:
185 case WIN_COLOR_DEPTH_YCbCr422R:
186 case WIN_COLOR_DEPTH_YUV422R:
187 case WIN_COLOR_DEPTH_YCbCr422RA:
188 case WIN_COLOR_DEPTH_YUV422RA:
189 if (planar)
190 *planar = true;
191
192 return true;
193 }
194
195 if (planar)
196 *planar = false;
197
198 return false;
199}
200
201static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v,
202 unsigned int bpp)
203{
204 fixed20_12 outf = dfixed_init(out);
205 fixed20_12 inf = dfixed_init(in);
206 u32 dda_inc;
207 int max;
208
209 if (v)
210 max = 15;
211 else {
212 switch (bpp) {
213 case 2:
214 max = 8;
215 break;
216
217 default:
218 WARN_ON_ONCE(1);
219 /* fallthrough */
220 case 4:
221 max = 4;
222 break;
223 }
224 }
225
226 outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1));
227 inf.full -= dfixed_const(1);
228
229 dda_inc = dfixed_div(inf, outf);
230 dda_inc = min_t(u32, dda_inc, dfixed_const(max));
231
232 return dda_inc;
233}
234
235static inline u32 compute_initial_dda(unsigned int in)
236{
237 fixed20_12 inf = dfixed_init(in);
238 return dfixed_frac(inf);
239}
240
241static void tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index,
242 const struct tegra_dc_window *window)
243{
244 unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp;
245 unsigned long value, flags;
246 bool yuv, planar;
247
248 /*
249 * For YUV planar modes, the number of bytes per pixel takes into
250 * account only the luma component and therefore is 1.
251 */
252 yuv = tegra_dc_format_is_yuv(window->format, &planar);
253 if (!yuv)
254 bpp = window->bits_per_pixel / 8;
255 else
256 bpp = planar ? 1 : 2;
257
258 spin_lock_irqsave(&dc->lock, flags);
259
260 value = WINDOW_A_SELECT << index;
261 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
262
263 tegra_dc_writel(dc, window->format, DC_WIN_COLOR_DEPTH);
264 tegra_dc_writel(dc, window->swap, DC_WIN_BYTE_SWAP);
265
266 value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x);
267 tegra_dc_writel(dc, value, DC_WIN_POSITION);
268
269 value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w);
270 tegra_dc_writel(dc, value, DC_WIN_SIZE);
271
272 h_offset = window->src.x * bpp;
273 v_offset = window->src.y;
274 h_size = window->src.w * bpp;
275 v_size = window->src.h;
276
277 value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size);
278 tegra_dc_writel(dc, value, DC_WIN_PRESCALED_SIZE);
279
280 /*
281 * For DDA computations the number of bytes per pixel for YUV planar
282 * modes needs to take into account all Y, U and V components.
283 */
284 if (yuv && planar)
285 bpp = 2;
286
287 h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp);
288 v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp);
289
290 value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda);
291 tegra_dc_writel(dc, value, DC_WIN_DDA_INC);
292
293 h_dda = compute_initial_dda(window->src.x);
294 v_dda = compute_initial_dda(window->src.y);
295
296 tegra_dc_writel(dc, h_dda, DC_WIN_H_INITIAL_DDA);
297 tegra_dc_writel(dc, v_dda, DC_WIN_V_INITIAL_DDA);
298
299 tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE);
300 tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE);
301
302 tegra_dc_writel(dc, window->base[0], DC_WINBUF_START_ADDR);
303
304 if (yuv && planar) {
305 tegra_dc_writel(dc, window->base[1], DC_WINBUF_START_ADDR_U);
306 tegra_dc_writel(dc, window->base[2], DC_WINBUF_START_ADDR_V);
307 value = window->stride[1] << 16 | window->stride[0];
308 tegra_dc_writel(dc, value, DC_WIN_LINE_STRIDE);
309 } else {
310 tegra_dc_writel(dc, window->stride[0], DC_WIN_LINE_STRIDE);
311 }
312
313 if (window->bottom_up)
314 v_offset += window->src.h - 1;
315
316 tegra_dc_writel(dc, h_offset, DC_WINBUF_ADDR_H_OFFSET);
317 tegra_dc_writel(dc, v_offset, DC_WINBUF_ADDR_V_OFFSET);
318
319 if (dc->soc->supports_block_linear) {
320 unsigned long height = window->tiling.value;
321
322 switch (window->tiling.mode) {
323 case TEGRA_BO_TILING_MODE_PITCH:
324 value = DC_WINBUF_SURFACE_KIND_PITCH;
325 break;
326
327 case TEGRA_BO_TILING_MODE_TILED:
328 value = DC_WINBUF_SURFACE_KIND_TILED;
329 break;
330
331 case TEGRA_BO_TILING_MODE_BLOCK:
332 value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) |
333 DC_WINBUF_SURFACE_KIND_BLOCK;
334 break;
335 }
336
337 tegra_dc_writel(dc, value, DC_WINBUF_SURFACE_KIND);
338 } else {
339 switch (window->tiling.mode) {
340 case TEGRA_BO_TILING_MODE_PITCH:
341 value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV |
342 DC_WIN_BUFFER_ADDR_MODE_LINEAR;
343 break;
344
345 case TEGRA_BO_TILING_MODE_TILED:
346 value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV |
347 DC_WIN_BUFFER_ADDR_MODE_TILE;
348 break;
349
350 case TEGRA_BO_TILING_MODE_BLOCK:
351 /*
352 * No need to handle this here because ->atomic_check
353 * will already have filtered it out.
354 */
355 break;
356 }
357
358 tegra_dc_writel(dc, value, DC_WIN_BUFFER_ADDR_MODE);
359 }
360
361 value = WIN_ENABLE;
362
363 if (yuv) {
364 /* setup default colorspace conversion coefficients */
365 tegra_dc_writel(dc, 0x00f0, DC_WIN_CSC_YOF);
366 tegra_dc_writel(dc, 0x012a, DC_WIN_CSC_KYRGB);
367 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KUR);
368 tegra_dc_writel(dc, 0x0198, DC_WIN_CSC_KVR);
369 tegra_dc_writel(dc, 0x039b, DC_WIN_CSC_KUG);
370 tegra_dc_writel(dc, 0x032f, DC_WIN_CSC_KVG);
371 tegra_dc_writel(dc, 0x0204, DC_WIN_CSC_KUB);
372 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KVB);
373
374 value |= CSC_ENABLE;
375 } else if (window->bits_per_pixel < 24) {
376 value |= COLOR_EXPAND;
377 }
378
379 if (window->bottom_up)
380 value |= V_DIRECTION;
381
382 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
383
384 /*
385 * Disable blending and assume Window A is the bottom-most window,
386 * Window C is the top-most window and Window B is in the middle.
387 */
388 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_NOKEY);
389 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_1WIN);
390
391 switch (index) {
392 case 0:
393 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_X);
394 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
395 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
396 break;
397
398 case 1:
399 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
400 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
401 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
402 break;
403
404 case 2:
405 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
406 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_Y);
407 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_3WIN_XY);
408 break;
409 }
410
411 spin_unlock_irqrestore(&dc->lock, flags);
412}
413
414static void tegra_plane_destroy(struct drm_plane *plane)
415{
416 struct tegra_plane *p = to_tegra_plane(plane);
417
418 drm_plane_cleanup(plane);
419 kfree(p);
420}
421
422static const u32 tegra_primary_plane_formats[] = {
423 DRM_FORMAT_XBGR8888,
424 DRM_FORMAT_XRGB8888,
425 DRM_FORMAT_RGB565,
426};
427
428static void tegra_primary_plane_destroy(struct drm_plane *plane)
429{
430 tegra_plane_destroy(plane);
431}
432
433static void tegra_plane_reset(struct drm_plane *plane)
434{
435 struct tegra_plane_state *state;
436
437 if (plane->state)
438 __drm_atomic_helper_plane_destroy_state(plane->state);
439
440 kfree(plane->state);
441 plane->state = NULL;
442
443 state = kzalloc(sizeof(*state), GFP_KERNEL);
444 if (state) {
445 plane->state = &state->base;
446 plane->state->plane = plane;
447 }
448}
449
450static struct drm_plane_state *tegra_plane_atomic_duplicate_state(struct drm_plane *plane)
451{
452 struct tegra_plane_state *state = to_tegra_plane_state(plane->state);
453 struct tegra_plane_state *copy;
454
455 copy = kmalloc(sizeof(*copy), GFP_KERNEL);
456 if (!copy)
457 return NULL;
458
459 __drm_atomic_helper_plane_duplicate_state(plane, ©->base);
460 copy->tiling = state->tiling;
461 copy->format = state->format;
462 copy->swap = state->swap;
463
464 return ©->base;
465}
466
467static void tegra_plane_atomic_destroy_state(struct drm_plane *plane,
468 struct drm_plane_state *state)
469{
470 __drm_atomic_helper_plane_destroy_state(state);
471 kfree(state);
472}
473
474static const struct drm_plane_funcs tegra_primary_plane_funcs = {
475 .update_plane = drm_atomic_helper_update_plane,
476 .disable_plane = drm_atomic_helper_disable_plane,
477 .destroy = tegra_primary_plane_destroy,
478 .reset = tegra_plane_reset,
479 .atomic_duplicate_state = tegra_plane_atomic_duplicate_state,
480 .atomic_destroy_state = tegra_plane_atomic_destroy_state,
481};
482
483static int tegra_plane_state_add(struct tegra_plane *plane,
484 struct drm_plane_state *state)
485{
486 struct drm_crtc_state *crtc_state;
487 struct tegra_dc_state *tegra;
488
489 /* Propagate errors from allocation or locking failures. */
490 crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc);
491 if (IS_ERR(crtc_state))
492 return PTR_ERR(crtc_state);
493
494 tegra = to_dc_state(crtc_state);
495
496 tegra->planes |= WIN_A_ACT_REQ << plane->index;
497
498 return 0;
499}
500
501static int tegra_plane_atomic_check(struct drm_plane *plane,
502 struct drm_plane_state *state)
503{
504 struct tegra_plane_state *plane_state = to_tegra_plane_state(state);
505 struct tegra_bo_tiling *tiling = &plane_state->tiling;
506 struct tegra_plane *tegra = to_tegra_plane(plane);
507 struct tegra_dc *dc = to_tegra_dc(state->crtc);
508 int err;
509
510 /* no need for further checks if the plane is being disabled */
511 if (!state->crtc)
512 return 0;
513
514 err = tegra_dc_format(state->fb->pixel_format, &plane_state->format,
515 &plane_state->swap);
516 if (err < 0)
517 return err;
518
519 err = tegra_fb_get_tiling(state->fb, tiling);
520 if (err < 0)
521 return err;
522
523 if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK &&
524 !dc->soc->supports_block_linear) {
525 DRM_ERROR("hardware doesn't support block linear mode\n");
526 return -EINVAL;
527 }
528
529 /*
530 * Tegra doesn't support different strides for U and V planes so we
531 * error out if the user tries to display a framebuffer with such a
532 * configuration.
533 */
534 if (drm_format_num_planes(state->fb->pixel_format) > 2) {
535 if (state->fb->pitches[2] != state->fb->pitches[1]) {
536 DRM_ERROR("unsupported UV-plane configuration\n");
537 return -EINVAL;
538 }
539 }
540
541 err = tegra_plane_state_add(tegra, state);
542 if (err < 0)
543 return err;
544
545 return 0;
546}
547
548static void tegra_plane_atomic_update(struct drm_plane *plane,
549 struct drm_plane_state *old_state)
550{
551 struct tegra_plane_state *state = to_tegra_plane_state(plane->state);
552 struct tegra_dc *dc = to_tegra_dc(plane->state->crtc);
553 struct drm_framebuffer *fb = plane->state->fb;
554 struct tegra_plane *p = to_tegra_plane(plane);
555 struct tegra_dc_window window;
556 unsigned int i;
557
558 /* rien ne va plus */
559 if (!plane->state->crtc || !plane->state->fb)
560 return;
561
562 memset(&window, 0, sizeof(window));
563 window.src.x = plane->state->src_x >> 16;
564 window.src.y = plane->state->src_y >> 16;
565 window.src.w = plane->state->src_w >> 16;
566 window.src.h = plane->state->src_h >> 16;
567 window.dst.x = plane->state->crtc_x;
568 window.dst.y = plane->state->crtc_y;
569 window.dst.w = plane->state->crtc_w;
570 window.dst.h = plane->state->crtc_h;
571 window.bits_per_pixel = fb->bits_per_pixel;
572 window.bottom_up = tegra_fb_is_bottom_up(fb);
573
574 /* copy from state */
575 window.tiling = state->tiling;
576 window.format = state->format;
577 window.swap = state->swap;
578
579 for (i = 0; i < drm_format_num_planes(fb->pixel_format); i++) {
580 struct tegra_bo *bo = tegra_fb_get_plane(fb, i);
581
582 window.base[i] = bo->paddr + fb->offsets[i];
583
584 /*
585 * Tegra uses a shared stride for UV planes. Framebuffers are
586 * already checked for this in the tegra_plane_atomic_check()
587 * function, so it's safe to ignore the V-plane pitch here.
588 */
589 if (i < 2)
590 window.stride[i] = fb->pitches[i];
591 }
592
593 tegra_dc_setup_window(dc, p->index, &window);
594}
595
596static void tegra_plane_atomic_disable(struct drm_plane *plane,
597 struct drm_plane_state *old_state)
598{
599 struct tegra_plane *p = to_tegra_plane(plane);
600 struct tegra_dc *dc;
601 unsigned long flags;
602 u32 value;
603
604 /* rien ne va plus */
605 if (!old_state || !old_state->crtc)
606 return;
607
608 dc = to_tegra_dc(old_state->crtc);
609
610 spin_lock_irqsave(&dc->lock, flags);
611
612 value = WINDOW_A_SELECT << p->index;
613 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
614
615 value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
616 value &= ~WIN_ENABLE;
617 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
618
619 spin_unlock_irqrestore(&dc->lock, flags);
620}
621
622static const struct drm_plane_helper_funcs tegra_primary_plane_helper_funcs = {
623 .atomic_check = tegra_plane_atomic_check,
624 .atomic_update = tegra_plane_atomic_update,
625 .atomic_disable = tegra_plane_atomic_disable,
626};
627
628static struct drm_plane *tegra_dc_primary_plane_create(struct drm_device *drm,
629 struct tegra_dc *dc)
630{
631 /*
632 * Ideally this would use drm_crtc_mask(), but that would require the
633 * CRTC to already be in the mode_config's list of CRTCs. However, it
634 * will only be added to that list in the drm_crtc_init_with_planes()
635 * (in tegra_dc_init()), which in turn requires registration of these
636 * planes. So we have ourselves a nice little chicken and egg problem
637 * here.
638 *
639 * We work around this by manually creating the mask from the number
640 * of CRTCs that have been registered, and should therefore always be
641 * the same as drm_crtc_index() after registration.
642 */
643 unsigned long possible_crtcs = 1 << drm->mode_config.num_crtc;
644 struct tegra_plane *plane;
645 unsigned int num_formats;
646 const u32 *formats;
647 int err;
648
649 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
650 if (!plane)
651 return ERR_PTR(-ENOMEM);
652
653 num_formats = ARRAY_SIZE(tegra_primary_plane_formats);
654 formats = tegra_primary_plane_formats;
655
656 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
657 &tegra_primary_plane_funcs, formats,
658 num_formats, DRM_PLANE_TYPE_PRIMARY,
659 NULL);
660 if (err < 0) {
661 kfree(plane);
662 return ERR_PTR(err);
663 }
664
665 drm_plane_helper_add(&plane->base, &tegra_primary_plane_helper_funcs);
666
667 return &plane->base;
668}
669
670static const u32 tegra_cursor_plane_formats[] = {
671 DRM_FORMAT_RGBA8888,
672};
673
674static int tegra_cursor_atomic_check(struct drm_plane *plane,
675 struct drm_plane_state *state)
676{
677 struct tegra_plane *tegra = to_tegra_plane(plane);
678 int err;
679
680 /* no need for further checks if the plane is being disabled */
681 if (!state->crtc)
682 return 0;
683
684 /* scaling not supported for cursor */
685 if ((state->src_w >> 16 != state->crtc_w) ||
686 (state->src_h >> 16 != state->crtc_h))
687 return -EINVAL;
688
689 /* only square cursors supported */
690 if (state->src_w != state->src_h)
691 return -EINVAL;
692
693 if (state->crtc_w != 32 && state->crtc_w != 64 &&
694 state->crtc_w != 128 && state->crtc_w != 256)
695 return -EINVAL;
696
697 err = tegra_plane_state_add(tegra, state);
698 if (err < 0)
699 return err;
700
701 return 0;
702}
703
704static void tegra_cursor_atomic_update(struct drm_plane *plane,
705 struct drm_plane_state *old_state)
706{
707 struct tegra_bo *bo = tegra_fb_get_plane(plane->state->fb, 0);
708 struct tegra_dc *dc = to_tegra_dc(plane->state->crtc);
709 struct drm_plane_state *state = plane->state;
710 u32 value = CURSOR_CLIP_DISPLAY;
711
712 /* rien ne va plus */
713 if (!plane->state->crtc || !plane->state->fb)
714 return;
715
716 switch (state->crtc_w) {
717 case 32:
718 value |= CURSOR_SIZE_32x32;
719 break;
720
721 case 64:
722 value |= CURSOR_SIZE_64x64;
723 break;
724
725 case 128:
726 value |= CURSOR_SIZE_128x128;
727 break;
728
729 case 256:
730 value |= CURSOR_SIZE_256x256;
731 break;
732
733 default:
734 WARN(1, "cursor size %ux%u not supported\n", state->crtc_w,
735 state->crtc_h);
736 return;
737 }
738
739 value |= (bo->paddr >> 10) & 0x3fffff;
740 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR);
741
742#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
743 value = (bo->paddr >> 32) & 0x3;
744 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI);
745#endif
746
747 /* enable cursor and set blend mode */
748 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
749 value |= CURSOR_ENABLE;
750 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
751
752 value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL);
753 value &= ~CURSOR_DST_BLEND_MASK;
754 value &= ~CURSOR_SRC_BLEND_MASK;
755 value |= CURSOR_MODE_NORMAL;
756 value |= CURSOR_DST_BLEND_NEG_K1_TIMES_SRC;
757 value |= CURSOR_SRC_BLEND_K1_TIMES_SRC;
758 value |= CURSOR_ALPHA;
759 tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL);
760
761 /* position the cursor */
762 value = (state->crtc_y & 0x3fff) << 16 | (state->crtc_x & 0x3fff);
763 tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION);
764}
765
766static void tegra_cursor_atomic_disable(struct drm_plane *plane,
767 struct drm_plane_state *old_state)
768{
769 struct tegra_dc *dc;
770 u32 value;
771
772 /* rien ne va plus */
773 if (!old_state || !old_state->crtc)
774 return;
775
776 dc = to_tegra_dc(old_state->crtc);
777
778 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
779 value &= ~CURSOR_ENABLE;
780 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
781}
782
783static const struct drm_plane_funcs tegra_cursor_plane_funcs = {
784 .update_plane = drm_atomic_helper_update_plane,
785 .disable_plane = drm_atomic_helper_disable_plane,
786 .destroy = tegra_plane_destroy,
787 .reset = tegra_plane_reset,
788 .atomic_duplicate_state = tegra_plane_atomic_duplicate_state,
789 .atomic_destroy_state = tegra_plane_atomic_destroy_state,
790};
791
792static const struct drm_plane_helper_funcs tegra_cursor_plane_helper_funcs = {
793 .atomic_check = tegra_cursor_atomic_check,
794 .atomic_update = tegra_cursor_atomic_update,
795 .atomic_disable = tegra_cursor_atomic_disable,
796};
797
798static struct drm_plane *tegra_dc_cursor_plane_create(struct drm_device *drm,
799 struct tegra_dc *dc)
800{
801 struct tegra_plane *plane;
802 unsigned int num_formats;
803 const u32 *formats;
804 int err;
805
806 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
807 if (!plane)
808 return ERR_PTR(-ENOMEM);
809
810 /*
811 * This index is kind of fake. The cursor isn't a regular plane, but
812 * its update and activation request bits in DC_CMD_STATE_CONTROL do
813 * use the same programming. Setting this fake index here allows the
814 * code in tegra_add_plane_state() to do the right thing without the
815 * need to special-casing the cursor plane.
816 */
817 plane->index = 6;
818
819 num_formats = ARRAY_SIZE(tegra_cursor_plane_formats);
820 formats = tegra_cursor_plane_formats;
821
822 err = drm_universal_plane_init(drm, &plane->base, 1 << dc->pipe,
823 &tegra_cursor_plane_funcs, formats,
824 num_formats, DRM_PLANE_TYPE_CURSOR,
825 NULL);
826 if (err < 0) {
827 kfree(plane);
828 return ERR_PTR(err);
829 }
830
831 drm_plane_helper_add(&plane->base, &tegra_cursor_plane_helper_funcs);
832
833 return &plane->base;
834}
835
836static void tegra_overlay_plane_destroy(struct drm_plane *plane)
837{
838 tegra_plane_destroy(plane);
839}
840
841static const struct drm_plane_funcs tegra_overlay_plane_funcs = {
842 .update_plane = drm_atomic_helper_update_plane,
843 .disable_plane = drm_atomic_helper_disable_plane,
844 .destroy = tegra_overlay_plane_destroy,
845 .reset = tegra_plane_reset,
846 .atomic_duplicate_state = tegra_plane_atomic_duplicate_state,
847 .atomic_destroy_state = tegra_plane_atomic_destroy_state,
848};
849
850static const uint32_t tegra_overlay_plane_formats[] = {
851 DRM_FORMAT_XBGR8888,
852 DRM_FORMAT_XRGB8888,
853 DRM_FORMAT_RGB565,
854 DRM_FORMAT_UYVY,
855 DRM_FORMAT_YUYV,
856 DRM_FORMAT_YUV420,
857 DRM_FORMAT_YUV422,
858};
859
860static const struct drm_plane_helper_funcs tegra_overlay_plane_helper_funcs = {
861 .atomic_check = tegra_plane_atomic_check,
862 .atomic_update = tegra_plane_atomic_update,
863 .atomic_disable = tegra_plane_atomic_disable,
864};
865
866static struct drm_plane *tegra_dc_overlay_plane_create(struct drm_device *drm,
867 struct tegra_dc *dc,
868 unsigned int index)
869{
870 struct tegra_plane *plane;
871 unsigned int num_formats;
872 const u32 *formats;
873 int err;
874
875 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
876 if (!plane)
877 return ERR_PTR(-ENOMEM);
878
879 plane->index = index;
880
881 num_formats = ARRAY_SIZE(tegra_overlay_plane_formats);
882 formats = tegra_overlay_plane_formats;
883
884 err = drm_universal_plane_init(drm, &plane->base, 1 << dc->pipe,
885 &tegra_overlay_plane_funcs, formats,
886 num_formats, DRM_PLANE_TYPE_OVERLAY,
887 NULL);
888 if (err < 0) {
889 kfree(plane);
890 return ERR_PTR(err);
891 }
892
893 drm_plane_helper_add(&plane->base, &tegra_overlay_plane_helper_funcs);
894
895 return &plane->base;
896}
897
898static int tegra_dc_add_planes(struct drm_device *drm, struct tegra_dc *dc)
899{
900 struct drm_plane *plane;
901 unsigned int i;
902
903 for (i = 0; i < 2; i++) {
904 plane = tegra_dc_overlay_plane_create(drm, dc, 1 + i);
905 if (IS_ERR(plane))
906 return PTR_ERR(plane);
907 }
908
909 return 0;
910}
911
912u32 tegra_dc_get_vblank_counter(struct tegra_dc *dc)
913{
914 if (dc->syncpt)
915 return host1x_syncpt_read(dc->syncpt);
916
917 /* fallback to software emulated VBLANK counter */
918 return drm_crtc_vblank_count(&dc->base);
919}
920
921void tegra_dc_enable_vblank(struct tegra_dc *dc)
922{
923 unsigned long value, flags;
924
925 spin_lock_irqsave(&dc->lock, flags);
926
927 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
928 value |= VBLANK_INT;
929 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
930
931 spin_unlock_irqrestore(&dc->lock, flags);
932}
933
934void tegra_dc_disable_vblank(struct tegra_dc *dc)
935{
936 unsigned long value, flags;
937
938 spin_lock_irqsave(&dc->lock, flags);
939
940 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
941 value &= ~VBLANK_INT;
942 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
943
944 spin_unlock_irqrestore(&dc->lock, flags);
945}
946
947static void tegra_dc_finish_page_flip(struct tegra_dc *dc)
948{
949 struct drm_device *drm = dc->base.dev;
950 struct drm_crtc *crtc = &dc->base;
951 unsigned long flags, base;
952 struct tegra_bo *bo;
953
954 spin_lock_irqsave(&drm->event_lock, flags);
955
956 if (!dc->event) {
957 spin_unlock_irqrestore(&drm->event_lock, flags);
958 return;
959 }
960
961 bo = tegra_fb_get_plane(crtc->primary->fb, 0);
962
963 spin_lock(&dc->lock);
964
965 /* check if new start address has been latched */
966 tegra_dc_writel(dc, WINDOW_A_SELECT, DC_CMD_DISPLAY_WINDOW_HEADER);
967 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
968 base = tegra_dc_readl(dc, DC_WINBUF_START_ADDR);
969 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
970
971 spin_unlock(&dc->lock);
972
973 if (base == bo->paddr + crtc->primary->fb->offsets[0]) {
974 drm_crtc_send_vblank_event(crtc, dc->event);
975 drm_crtc_vblank_put(crtc);
976 dc->event = NULL;
977 }
978
979 spin_unlock_irqrestore(&drm->event_lock, flags);
980}
981
982static void tegra_dc_destroy(struct drm_crtc *crtc)
983{
984 drm_crtc_cleanup(crtc);
985}
986
987static void tegra_crtc_reset(struct drm_crtc *crtc)
988{
989 struct tegra_dc_state *state;
990
991 if (crtc->state)
992 __drm_atomic_helper_crtc_destroy_state(crtc->state);
993
994 kfree(crtc->state);
995 crtc->state = NULL;
996
997 state = kzalloc(sizeof(*state), GFP_KERNEL);
998 if (state) {
999 crtc->state = &state->base;
1000 crtc->state->crtc = crtc;
1001 }
1002
1003 drm_crtc_vblank_reset(crtc);
1004}
1005
1006static struct drm_crtc_state *
1007tegra_crtc_atomic_duplicate_state(struct drm_crtc *crtc)
1008{
1009 struct tegra_dc_state *state = to_dc_state(crtc->state);
1010 struct tegra_dc_state *copy;
1011
1012 copy = kmalloc(sizeof(*copy), GFP_KERNEL);
1013 if (!copy)
1014 return NULL;
1015
1016 __drm_atomic_helper_crtc_duplicate_state(crtc, ©->base);
1017 copy->clk = state->clk;
1018 copy->pclk = state->pclk;
1019 copy->div = state->div;
1020 copy->planes = state->planes;
1021
1022 return ©->base;
1023}
1024
1025static void tegra_crtc_atomic_destroy_state(struct drm_crtc *crtc,
1026 struct drm_crtc_state *state)
1027{
1028 __drm_atomic_helper_crtc_destroy_state(state);
1029 kfree(state);
1030}
1031
1032static const struct drm_crtc_funcs tegra_crtc_funcs = {
1033 .page_flip = drm_atomic_helper_page_flip,
1034 .set_config = drm_atomic_helper_set_config,
1035 .destroy = tegra_dc_destroy,
1036 .reset = tegra_crtc_reset,
1037 .atomic_duplicate_state = tegra_crtc_atomic_duplicate_state,
1038 .atomic_destroy_state = tegra_crtc_atomic_destroy_state,
1039};
1040
1041static int tegra_dc_set_timings(struct tegra_dc *dc,
1042 struct drm_display_mode *mode)
1043{
1044 unsigned int h_ref_to_sync = 1;
1045 unsigned int v_ref_to_sync = 1;
1046 unsigned long value;
1047
1048 tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
1049
1050 value = (v_ref_to_sync << 16) | h_ref_to_sync;
1051 tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC);
1052
1053 value = ((mode->vsync_end - mode->vsync_start) << 16) |
1054 ((mode->hsync_end - mode->hsync_start) << 0);
1055 tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH);
1056
1057 value = ((mode->vtotal - mode->vsync_end) << 16) |
1058 ((mode->htotal - mode->hsync_end) << 0);
1059 tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH);
1060
1061 value = ((mode->vsync_start - mode->vdisplay) << 16) |
1062 ((mode->hsync_start - mode->hdisplay) << 0);
1063 tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH);
1064
1065 value = (mode->vdisplay << 16) | mode->hdisplay;
1066 tegra_dc_writel(dc, value, DC_DISP_ACTIVE);
1067
1068 return 0;
1069}
1070
1071/**
1072 * tegra_dc_state_setup_clock - check clock settings and store them in atomic
1073 * state
1074 * @dc: display controller
1075 * @crtc_state: CRTC atomic state
1076 * @clk: parent clock for display controller
1077 * @pclk: pixel clock
1078 * @div: shift clock divider
1079 *
1080 * Returns:
1081 * 0 on success or a negative error-code on failure.
1082 */
1083int tegra_dc_state_setup_clock(struct tegra_dc *dc,
1084 struct drm_crtc_state *crtc_state,
1085 struct clk *clk, unsigned long pclk,
1086 unsigned int div)
1087{
1088 struct tegra_dc_state *state = to_dc_state(crtc_state);
1089
1090 if (!clk_has_parent(dc->clk, clk))
1091 return -EINVAL;
1092
1093 state->clk = clk;
1094 state->pclk = pclk;
1095 state->div = div;
1096
1097 return 0;
1098}
1099
1100static void tegra_dc_commit_state(struct tegra_dc *dc,
1101 struct tegra_dc_state *state)
1102{
1103 u32 value;
1104 int err;
1105
1106 err = clk_set_parent(dc->clk, state->clk);
1107 if (err < 0)
1108 dev_err(dc->dev, "failed to set parent clock: %d\n", err);
1109
1110 /*
1111 * Outputs may not want to change the parent clock rate. This is only
1112 * relevant to Tegra20 where only a single display PLL is available.
1113 * Since that PLL would typically be used for HDMI, an internal LVDS
1114 * panel would need to be driven by some other clock such as PLL_P
1115 * which is shared with other peripherals. Changing the clock rate
1116 * should therefore be avoided.
1117 */
1118 if (state->pclk > 0) {
1119 err = clk_set_rate(state->clk, state->pclk);
1120 if (err < 0)
1121 dev_err(dc->dev,
1122 "failed to set clock rate to %lu Hz\n",
1123 state->pclk);
1124 }
1125
1126 DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk),
1127 state->div);
1128 DRM_DEBUG_KMS("pclk: %lu\n", state->pclk);
1129
1130 value = SHIFT_CLK_DIVIDER(state->div) | PIXEL_CLK_DIVIDER_PCD1;
1131 tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);
1132}
1133
1134static void tegra_dc_stop(struct tegra_dc *dc)
1135{
1136 u32 value;
1137
1138 /* stop the display controller */
1139 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
1140 value &= ~DISP_CTRL_MODE_MASK;
1141 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
1142
1143 tegra_dc_commit(dc);
1144}
1145
1146static bool tegra_dc_idle(struct tegra_dc *dc)
1147{
1148 u32 value;
1149
1150 value = tegra_dc_readl_active(dc, DC_CMD_DISPLAY_COMMAND);
1151
1152 return (value & DISP_CTRL_MODE_MASK) == 0;
1153}
1154
1155static int tegra_dc_wait_idle(struct tegra_dc *dc, unsigned long timeout)
1156{
1157 timeout = jiffies + msecs_to_jiffies(timeout);
1158
1159 while (time_before(jiffies, timeout)) {
1160 if (tegra_dc_idle(dc))
1161 return 0;
1162
1163 usleep_range(1000, 2000);
1164 }
1165
1166 dev_dbg(dc->dev, "timeout waiting for DC to become idle\n");
1167 return -ETIMEDOUT;
1168}
1169
1170static void tegra_crtc_disable(struct drm_crtc *crtc)
1171{
1172 struct tegra_dc *dc = to_tegra_dc(crtc);
1173 u32 value;
1174
1175 if (!tegra_dc_idle(dc)) {
1176 tegra_dc_stop(dc);
1177
1178 /*
1179 * Ignore the return value, there isn't anything useful to do
1180 * in case this fails.
1181 */
1182 tegra_dc_wait_idle(dc, 100);
1183 }
1184
1185 /*
1186 * This should really be part of the RGB encoder driver, but clearing
1187 * these bits has the side-effect of stopping the display controller.
1188 * When that happens no VBLANK interrupts will be raised. At the same
1189 * time the encoder is disabled before the display controller, so the
1190 * above code is always going to timeout waiting for the controller
1191 * to go idle.
1192 *
1193 * Given the close coupling between the RGB encoder and the display
1194 * controller doing it here is still kind of okay. None of the other
1195 * encoder drivers require these bits to be cleared.
1196 *
1197 * XXX: Perhaps given that the display controller is switched off at
1198 * this point anyway maybe clearing these bits isn't even useful for
1199 * the RGB encoder?
1200 */
1201 if (dc->rgb) {
1202 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
1203 value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1204 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE);
1205 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
1206 }
1207
1208 tegra_dc_stats_reset(&dc->stats);
1209 drm_crtc_vblank_off(crtc);
1210
1211 pm_runtime_put_sync(dc->dev);
1212}
1213
1214static void tegra_crtc_enable(struct drm_crtc *crtc)
1215{
1216 struct drm_display_mode *mode = &crtc->state->adjusted_mode;
1217 struct tegra_dc_state *state = to_dc_state(crtc->state);
1218 struct tegra_dc *dc = to_tegra_dc(crtc);
1219 u32 value;
1220
1221 pm_runtime_get_sync(dc->dev);
1222
1223 /* initialize display controller */
1224 if (dc->syncpt) {
1225 u32 syncpt = host1x_syncpt_id(dc->syncpt);
1226
1227 value = SYNCPT_CNTRL_NO_STALL;
1228 tegra_dc_writel(dc, value, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1229
1230 value = SYNCPT_VSYNC_ENABLE | syncpt;
1231 tegra_dc_writel(dc, value, DC_CMD_CONT_SYNCPT_VSYNC);
1232 }
1233
1234 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1235 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1236 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
1237
1238 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1239 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1240 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
1241
1242 /* initialize timer */
1243 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |
1244 WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20);
1245 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);
1246
1247 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |
1248 WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1);
1249 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
1250
1251 value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1252 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1253 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
1254
1255 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1256 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1257 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1258
1259 if (dc->soc->supports_border_color)
1260 tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR);
1261
1262 /* apply PLL and pixel clock changes */
1263 tegra_dc_commit_state(dc, state);
1264
1265 /* program display mode */
1266 tegra_dc_set_timings(dc, mode);
1267
1268 /* interlacing isn't supported yet, so disable it */
1269 if (dc->soc->supports_interlacing) {
1270 value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL);
1271 value &= ~INTERLACE_ENABLE;
1272 tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL);
1273 }
1274
1275 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
1276 value &= ~DISP_CTRL_MODE_MASK;
1277 value |= DISP_CTRL_MODE_C_DISPLAY;
1278 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
1279
1280 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
1281 value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1282 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
1283 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
1284
1285 tegra_dc_commit(dc);
1286
1287 drm_crtc_vblank_on(crtc);
1288}
1289
1290static int tegra_crtc_atomic_check(struct drm_crtc *crtc,
1291 struct drm_crtc_state *state)
1292{
1293 return 0;
1294}
1295
1296static void tegra_crtc_atomic_begin(struct drm_crtc *crtc,
1297 struct drm_crtc_state *old_crtc_state)
1298{
1299 struct tegra_dc *dc = to_tegra_dc(crtc);
1300
1301 if (crtc->state->event) {
1302 crtc->state->event->pipe = drm_crtc_index(crtc);
1303
1304 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1305
1306 dc->event = crtc->state->event;
1307 crtc->state->event = NULL;
1308 }
1309}
1310
1311static void tegra_crtc_atomic_flush(struct drm_crtc *crtc,
1312 struct drm_crtc_state *old_crtc_state)
1313{
1314 struct tegra_dc_state *state = to_dc_state(crtc->state);
1315 struct tegra_dc *dc = to_tegra_dc(crtc);
1316
1317 tegra_dc_writel(dc, state->planes << 8, DC_CMD_STATE_CONTROL);
1318 tegra_dc_writel(dc, state->planes, DC_CMD_STATE_CONTROL);
1319}
1320
1321static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = {
1322 .disable = tegra_crtc_disable,
1323 .enable = tegra_crtc_enable,
1324 .atomic_check = tegra_crtc_atomic_check,
1325 .atomic_begin = tegra_crtc_atomic_begin,
1326 .atomic_flush = tegra_crtc_atomic_flush,
1327};
1328
1329static irqreturn_t tegra_dc_irq(int irq, void *data)
1330{
1331 struct tegra_dc *dc = data;
1332 unsigned long status;
1333
1334 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1335 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
1336
1337 if (status & FRAME_END_INT) {
1338 /*
1339 dev_dbg(dc->dev, "%s(): frame end\n", __func__);
1340 */
1341 dc->stats.frames++;
1342 }
1343
1344 if (status & VBLANK_INT) {
1345 /*
1346 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__);
1347 */
1348 drm_crtc_handle_vblank(&dc->base);
1349 tegra_dc_finish_page_flip(dc);
1350 dc->stats.vblank++;
1351 }
1352
1353 if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) {
1354 /*
1355 dev_dbg(dc->dev, "%s(): underflow\n", __func__);
1356 */
1357 dc->stats.underflow++;
1358 }
1359
1360 if (status & (WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT)) {
1361 /*
1362 dev_dbg(dc->dev, "%s(): overflow\n", __func__);
1363 */
1364 dc->stats.overflow++;
1365 }
1366
1367 return IRQ_HANDLED;
1368}
1369
1370static int tegra_dc_show_regs(struct seq_file *s, void *data)
1371{
1372 struct drm_info_node *node = s->private;
1373 struct tegra_dc *dc = node->info_ent->data;
1374 int err = 0;
1375
1376 drm_modeset_lock_crtc(&dc->base, NULL);
1377
1378 if (!dc->base.state->active) {
1379 err = -EBUSY;
1380 goto unlock;
1381 }
1382
1383#define DUMP_REG(name) \
1384 seq_printf(s, "%-40s %#05x %08x\n", #name, name, \
1385 tegra_dc_readl(dc, name))
1386
1387 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT);
1388 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1389 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_ERROR);
1390 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT);
1391 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL);
1392 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_ERROR);
1393 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT);
1394 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL);
1395 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_ERROR);
1396 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT);
1397 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL);
1398 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_ERROR);
1399 DUMP_REG(DC_CMD_CONT_SYNCPT_VSYNC);
1400 DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
1401 DUMP_REG(DC_CMD_DISPLAY_COMMAND);
1402 DUMP_REG(DC_CMD_SIGNAL_RAISE);
1403 DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
1404 DUMP_REG(DC_CMD_INT_STATUS);
1405 DUMP_REG(DC_CMD_INT_MASK);
1406 DUMP_REG(DC_CMD_INT_ENABLE);
1407 DUMP_REG(DC_CMD_INT_TYPE);
1408 DUMP_REG(DC_CMD_INT_POLARITY);
1409 DUMP_REG(DC_CMD_SIGNAL_RAISE1);
1410 DUMP_REG(DC_CMD_SIGNAL_RAISE2);
1411 DUMP_REG(DC_CMD_SIGNAL_RAISE3);
1412 DUMP_REG(DC_CMD_STATE_ACCESS);
1413 DUMP_REG(DC_CMD_STATE_CONTROL);
1414 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
1415 DUMP_REG(DC_CMD_REG_ACT_CONTROL);
1416 DUMP_REG(DC_COM_CRC_CONTROL);
1417 DUMP_REG(DC_COM_CRC_CHECKSUM);
1418 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(0));
1419 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(1));
1420 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(2));
1421 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(3));
1422 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(0));
1423 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(1));
1424 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(2));
1425 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(3));
1426 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(0));
1427 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(1));
1428 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(2));
1429 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(3));
1430 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(0));
1431 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(1));
1432 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(2));
1433 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(3));
1434 DUMP_REG(DC_COM_PIN_INPUT_DATA(0));
1435 DUMP_REG(DC_COM_PIN_INPUT_DATA(1));
1436 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(0));
1437 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(1));
1438 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(2));
1439 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(3));
1440 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(4));
1441 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(5));
1442 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(6));
1443 DUMP_REG(DC_COM_PIN_MISC_CONTROL);
1444 DUMP_REG(DC_COM_PIN_PM0_CONTROL);
1445 DUMP_REG(DC_COM_PIN_PM0_DUTY_CYCLE);
1446 DUMP_REG(DC_COM_PIN_PM1_CONTROL);
1447 DUMP_REG(DC_COM_PIN_PM1_DUTY_CYCLE);
1448 DUMP_REG(DC_COM_SPI_CONTROL);
1449 DUMP_REG(DC_COM_SPI_START_BYTE);
1450 DUMP_REG(DC_COM_HSPI_WRITE_DATA_AB);
1451 DUMP_REG(DC_COM_HSPI_WRITE_DATA_CD);
1452 DUMP_REG(DC_COM_HSPI_CS_DC);
1453 DUMP_REG(DC_COM_SCRATCH_REGISTER_A);
1454 DUMP_REG(DC_COM_SCRATCH_REGISTER_B);
1455 DUMP_REG(DC_COM_GPIO_CTRL);
1456 DUMP_REG(DC_COM_GPIO_DEBOUNCE_COUNTER);
1457 DUMP_REG(DC_COM_CRC_CHECKSUM_LATCHED);
1458 DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
1459 DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
1460 DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
1461 DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY);
1462 DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
1463 DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
1464 DUMP_REG(DC_DISP_REF_TO_SYNC);
1465 DUMP_REG(DC_DISP_SYNC_WIDTH);
1466 DUMP_REG(DC_DISP_BACK_PORCH);
1467 DUMP_REG(DC_DISP_ACTIVE);
1468 DUMP_REG(DC_DISP_FRONT_PORCH);
1469 DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
1470 DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
1471 DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
1472 DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
1473 DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
1474 DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
1475 DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
1476 DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
1477 DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
1478 DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
1479 DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
1480 DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
1481 DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
1482 DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
1483 DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
1484 DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
1485 DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
1486 DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
1487 DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
1488 DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
1489 DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
1490 DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
1491 DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
1492 DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
1493 DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
1494 DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
1495 DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
1496 DUMP_REG(DC_DISP_M0_CONTROL);
1497 DUMP_REG(DC_DISP_M1_CONTROL);
1498 DUMP_REG(DC_DISP_DI_CONTROL);
1499 DUMP_REG(DC_DISP_PP_CONTROL);
1500 DUMP_REG(DC_DISP_PP_SELECT_A);
1501 DUMP_REG(DC_DISP_PP_SELECT_B);
1502 DUMP_REG(DC_DISP_PP_SELECT_C);
1503 DUMP_REG(DC_DISP_PP_SELECT_D);
1504 DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
1505 DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
1506 DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
1507 DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
1508 DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
1509 DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
1510 DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
1511 DUMP_REG(DC_DISP_BORDER_COLOR);
1512 DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
1513 DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
1514 DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
1515 DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
1516 DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
1517 DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
1518 DUMP_REG(DC_DISP_CURSOR_START_ADDR);
1519 DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
1520 DUMP_REG(DC_DISP_CURSOR_POSITION);
1521 DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
1522 DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
1523 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
1524 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
1525 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
1526 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
1527 DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
1528 DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
1529 DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
1530 DUMP_REG(DC_DISP_MCCIF_DISPLAY1A_HYST);
1531 DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
1532 DUMP_REG(DC_DISP_DAC_CRT_CTRL);
1533 DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
1534 DUMP_REG(DC_DISP_SD_CONTROL);
1535 DUMP_REG(DC_DISP_SD_CSC_COEFF);
1536 DUMP_REG(DC_DISP_SD_LUT(0));
1537 DUMP_REG(DC_DISP_SD_LUT(1));
1538 DUMP_REG(DC_DISP_SD_LUT(2));
1539 DUMP_REG(DC_DISP_SD_LUT(3));
1540 DUMP_REG(DC_DISP_SD_LUT(4));
1541 DUMP_REG(DC_DISP_SD_LUT(5));
1542 DUMP_REG(DC_DISP_SD_LUT(6));
1543 DUMP_REG(DC_DISP_SD_LUT(7));
1544 DUMP_REG(DC_DISP_SD_LUT(8));
1545 DUMP_REG(DC_DISP_SD_FLICKER_CONTROL);
1546 DUMP_REG(DC_DISP_DC_PIXEL_COUNT);
1547 DUMP_REG(DC_DISP_SD_HISTOGRAM(0));
1548 DUMP_REG(DC_DISP_SD_HISTOGRAM(1));
1549 DUMP_REG(DC_DISP_SD_HISTOGRAM(2));
1550 DUMP_REG(DC_DISP_SD_HISTOGRAM(3));
1551 DUMP_REG(DC_DISP_SD_HISTOGRAM(4));
1552 DUMP_REG(DC_DISP_SD_HISTOGRAM(5));
1553 DUMP_REG(DC_DISP_SD_HISTOGRAM(6));
1554 DUMP_REG(DC_DISP_SD_HISTOGRAM(7));
1555 DUMP_REG(DC_DISP_SD_BL_TF(0));
1556 DUMP_REG(DC_DISP_SD_BL_TF(1));
1557 DUMP_REG(DC_DISP_SD_BL_TF(2));
1558 DUMP_REG(DC_DISP_SD_BL_TF(3));
1559 DUMP_REG(DC_DISP_SD_BL_CONTROL);
1560 DUMP_REG(DC_DISP_SD_HW_K_VALUES);
1561 DUMP_REG(DC_DISP_SD_MAN_K_VALUES);
1562 DUMP_REG(DC_DISP_CURSOR_START_ADDR_HI);
1563 DUMP_REG(DC_DISP_BLEND_CURSOR_CONTROL);
1564 DUMP_REG(DC_WIN_WIN_OPTIONS);
1565 DUMP_REG(DC_WIN_BYTE_SWAP);
1566 DUMP_REG(DC_WIN_BUFFER_CONTROL);
1567 DUMP_REG(DC_WIN_COLOR_DEPTH);
1568 DUMP_REG(DC_WIN_POSITION);
1569 DUMP_REG(DC_WIN_SIZE);
1570 DUMP_REG(DC_WIN_PRESCALED_SIZE);
1571 DUMP_REG(DC_WIN_H_INITIAL_DDA);
1572 DUMP_REG(DC_WIN_V_INITIAL_DDA);
1573 DUMP_REG(DC_WIN_DDA_INC);
1574 DUMP_REG(DC_WIN_LINE_STRIDE);
1575 DUMP_REG(DC_WIN_BUF_STRIDE);
1576 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
1577 DUMP_REG(DC_WIN_BUFFER_ADDR_MODE);
1578 DUMP_REG(DC_WIN_DV_CONTROL);
1579 DUMP_REG(DC_WIN_BLEND_NOKEY);
1580 DUMP_REG(DC_WIN_BLEND_1WIN);
1581 DUMP_REG(DC_WIN_BLEND_2WIN_X);
1582 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
1583 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
1584 DUMP_REG(DC_WIN_HP_FETCH_CONTROL);
1585 DUMP_REG(DC_WINBUF_START_ADDR);
1586 DUMP_REG(DC_WINBUF_START_ADDR_NS);
1587 DUMP_REG(DC_WINBUF_START_ADDR_U);
1588 DUMP_REG(DC_WINBUF_START_ADDR_U_NS);
1589 DUMP_REG(DC_WINBUF_START_ADDR_V);
1590 DUMP_REG(DC_WINBUF_START_ADDR_V_NS);
1591 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
1592 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET_NS);
1593 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
1594 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET_NS);
1595 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
1596 DUMP_REG(DC_WINBUF_AD_UFLOW_STATUS);
1597 DUMP_REG(DC_WINBUF_BD_UFLOW_STATUS);
1598 DUMP_REG(DC_WINBUF_CD_UFLOW_STATUS);
1599
1600#undef DUMP_REG
1601
1602unlock:
1603 drm_modeset_unlock_crtc(&dc->base);
1604 return err;
1605}
1606
1607static int tegra_dc_show_crc(struct seq_file *s, void *data)
1608{
1609 struct drm_info_node *node = s->private;
1610 struct tegra_dc *dc = node->info_ent->data;
1611 int err = 0;
1612 u32 value;
1613
1614 drm_modeset_lock_crtc(&dc->base, NULL);
1615
1616 if (!dc->base.state->active) {
1617 err = -EBUSY;
1618 goto unlock;
1619 }
1620
1621 value = DC_COM_CRC_CONTROL_ACTIVE_DATA | DC_COM_CRC_CONTROL_ENABLE;
1622 tegra_dc_writel(dc, value, DC_COM_CRC_CONTROL);
1623 tegra_dc_commit(dc);
1624
1625 drm_crtc_wait_one_vblank(&dc->base);
1626 drm_crtc_wait_one_vblank(&dc->base);
1627
1628 value = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM);
1629 seq_printf(s, "%08x\n", value);
1630
1631 tegra_dc_writel(dc, 0, DC_COM_CRC_CONTROL);
1632
1633unlock:
1634 drm_modeset_unlock_crtc(&dc->base);
1635 return err;
1636}
1637
1638static int tegra_dc_show_stats(struct seq_file *s, void *data)
1639{
1640 struct drm_info_node *node = s->private;
1641 struct tegra_dc *dc = node->info_ent->data;
1642
1643 seq_printf(s, "frames: %lu\n", dc->stats.frames);
1644 seq_printf(s, "vblank: %lu\n", dc->stats.vblank);
1645 seq_printf(s, "underflow: %lu\n", dc->stats.underflow);
1646 seq_printf(s, "overflow: %lu\n", dc->stats.overflow);
1647
1648 return 0;
1649}
1650
1651static struct drm_info_list debugfs_files[] = {
1652 { "regs", tegra_dc_show_regs, 0, NULL },
1653 { "crc", tegra_dc_show_crc, 0, NULL },
1654 { "stats", tegra_dc_show_stats, 0, NULL },
1655};
1656
1657static int tegra_dc_debugfs_init(struct tegra_dc *dc, struct drm_minor *minor)
1658{
1659 unsigned int i;
1660 char *name;
1661 int err;
1662
1663 name = kasprintf(GFP_KERNEL, "dc.%d", dc->pipe);
1664 dc->debugfs = debugfs_create_dir(name, minor->debugfs_root);
1665 kfree(name);
1666
1667 if (!dc->debugfs)
1668 return -ENOMEM;
1669
1670 dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1671 GFP_KERNEL);
1672 if (!dc->debugfs_files) {
1673 err = -ENOMEM;
1674 goto remove;
1675 }
1676
1677 for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
1678 dc->debugfs_files[i].data = dc;
1679
1680 err = drm_debugfs_create_files(dc->debugfs_files,
1681 ARRAY_SIZE(debugfs_files),
1682 dc->debugfs, minor);
1683 if (err < 0)
1684 goto free;
1685
1686 dc->minor = minor;
1687
1688 return 0;
1689
1690free:
1691 kfree(dc->debugfs_files);
1692 dc->debugfs_files = NULL;
1693remove:
1694 debugfs_remove(dc->debugfs);
1695 dc->debugfs = NULL;
1696
1697 return err;
1698}
1699
1700static int tegra_dc_debugfs_exit(struct tegra_dc *dc)
1701{
1702 drm_debugfs_remove_files(dc->debugfs_files, ARRAY_SIZE(debugfs_files),
1703 dc->minor);
1704 dc->minor = NULL;
1705
1706 kfree(dc->debugfs_files);
1707 dc->debugfs_files = NULL;
1708
1709 debugfs_remove(dc->debugfs);
1710 dc->debugfs = NULL;
1711
1712 return 0;
1713}
1714
1715static int tegra_dc_init(struct host1x_client *client)
1716{
1717 struct drm_device *drm = dev_get_drvdata(client->parent);
1718 unsigned long flags = HOST1X_SYNCPT_CLIENT_MANAGED;
1719 struct tegra_dc *dc = host1x_client_to_dc(client);
1720 struct tegra_drm *tegra = drm->dev_private;
1721 struct drm_plane *primary = NULL;
1722 struct drm_plane *cursor = NULL;
1723 int err;
1724
1725 dc->syncpt = host1x_syncpt_request(dc->dev, flags);
1726 if (!dc->syncpt)
1727 dev_warn(dc->dev, "failed to allocate syncpoint\n");
1728
1729 if (tegra->domain) {
1730 err = iommu_attach_device(tegra->domain, dc->dev);
1731 if (err < 0) {
1732 dev_err(dc->dev, "failed to attach to domain: %d\n",
1733 err);
1734 return err;
1735 }
1736
1737 dc->domain = tegra->domain;
1738 }
1739
1740 primary = tegra_dc_primary_plane_create(drm, dc);
1741 if (IS_ERR(primary)) {
1742 err = PTR_ERR(primary);
1743 goto cleanup;
1744 }
1745
1746 if (dc->soc->supports_cursor) {
1747 cursor = tegra_dc_cursor_plane_create(drm, dc);
1748 if (IS_ERR(cursor)) {
1749 err = PTR_ERR(cursor);
1750 goto cleanup;
1751 }
1752 }
1753
1754 err = drm_crtc_init_with_planes(drm, &dc->base, primary, cursor,
1755 &tegra_crtc_funcs, NULL);
1756 if (err < 0)
1757 goto cleanup;
1758
1759 drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs);
1760
1761 /*
1762 * Keep track of the minimum pitch alignment across all display
1763 * controllers.
1764 */
1765 if (dc->soc->pitch_align > tegra->pitch_align)
1766 tegra->pitch_align = dc->soc->pitch_align;
1767
1768 err = tegra_dc_rgb_init(drm, dc);
1769 if (err < 0 && err != -ENODEV) {
1770 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err);
1771 goto cleanup;
1772 }
1773
1774 err = tegra_dc_add_planes(drm, dc);
1775 if (err < 0)
1776 goto cleanup;
1777
1778 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1779 err = tegra_dc_debugfs_init(dc, drm->primary);
1780 if (err < 0)
1781 dev_err(dc->dev, "debugfs setup failed: %d\n", err);
1782 }
1783
1784 err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0,
1785 dev_name(dc->dev), dc);
1786 if (err < 0) {
1787 dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq,
1788 err);
1789 goto cleanup;
1790 }
1791
1792 return 0;
1793
1794cleanup:
1795 if (cursor)
1796 drm_plane_cleanup(cursor);
1797
1798 if (primary)
1799 drm_plane_cleanup(primary);
1800
1801 if (tegra->domain) {
1802 iommu_detach_device(tegra->domain, dc->dev);
1803 dc->domain = NULL;
1804 }
1805
1806 return err;
1807}
1808
1809static int tegra_dc_exit(struct host1x_client *client)
1810{
1811 struct tegra_dc *dc = host1x_client_to_dc(client);
1812 int err;
1813
1814 devm_free_irq(dc->dev, dc->irq, dc);
1815
1816 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1817 err = tegra_dc_debugfs_exit(dc);
1818 if (err < 0)
1819 dev_err(dc->dev, "debugfs cleanup failed: %d\n", err);
1820 }
1821
1822 err = tegra_dc_rgb_exit(dc);
1823 if (err) {
1824 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err);
1825 return err;
1826 }
1827
1828 if (dc->domain) {
1829 iommu_detach_device(dc->domain, dc->dev);
1830 dc->domain = NULL;
1831 }
1832
1833 host1x_syncpt_free(dc->syncpt);
1834
1835 return 0;
1836}
1837
1838static const struct host1x_client_ops dc_client_ops = {
1839 .init = tegra_dc_init,
1840 .exit = tegra_dc_exit,
1841};
1842
1843static const struct tegra_dc_soc_info tegra20_dc_soc_info = {
1844 .supports_border_color = true,
1845 .supports_interlacing = false,
1846 .supports_cursor = false,
1847 .supports_block_linear = false,
1848 .pitch_align = 8,
1849 .has_powergate = false,
1850};
1851
1852static const struct tegra_dc_soc_info tegra30_dc_soc_info = {
1853 .supports_border_color = true,
1854 .supports_interlacing = false,
1855 .supports_cursor = false,
1856 .supports_block_linear = false,
1857 .pitch_align = 8,
1858 .has_powergate = false,
1859};
1860
1861static const struct tegra_dc_soc_info tegra114_dc_soc_info = {
1862 .supports_border_color = true,
1863 .supports_interlacing = false,
1864 .supports_cursor = false,
1865 .supports_block_linear = false,
1866 .pitch_align = 64,
1867 .has_powergate = true,
1868};
1869
1870static const struct tegra_dc_soc_info tegra124_dc_soc_info = {
1871 .supports_border_color = false,
1872 .supports_interlacing = true,
1873 .supports_cursor = true,
1874 .supports_block_linear = true,
1875 .pitch_align = 64,
1876 .has_powergate = true,
1877};
1878
1879static const struct tegra_dc_soc_info tegra210_dc_soc_info = {
1880 .supports_border_color = false,
1881 .supports_interlacing = true,
1882 .supports_cursor = true,
1883 .supports_block_linear = true,
1884 .pitch_align = 64,
1885 .has_powergate = true,
1886};
1887
1888static const struct of_device_id tegra_dc_of_match[] = {
1889 {
1890 .compatible = "nvidia,tegra210-dc",
1891 .data = &tegra210_dc_soc_info,
1892 }, {
1893 .compatible = "nvidia,tegra124-dc",
1894 .data = &tegra124_dc_soc_info,
1895 }, {
1896 .compatible = "nvidia,tegra114-dc",
1897 .data = &tegra114_dc_soc_info,
1898 }, {
1899 .compatible = "nvidia,tegra30-dc",
1900 .data = &tegra30_dc_soc_info,
1901 }, {
1902 .compatible = "nvidia,tegra20-dc",
1903 .data = &tegra20_dc_soc_info,
1904 }, {
1905 /* sentinel */
1906 }
1907};
1908MODULE_DEVICE_TABLE(of, tegra_dc_of_match);
1909
1910static int tegra_dc_parse_dt(struct tegra_dc *dc)
1911{
1912 struct device_node *np;
1913 u32 value = 0;
1914 int err;
1915
1916 err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value);
1917 if (err < 0) {
1918 dev_err(dc->dev, "missing \"nvidia,head\" property\n");
1919
1920 /*
1921 * If the nvidia,head property isn't present, try to find the
1922 * correct head number by looking up the position of this
1923 * display controller's node within the device tree. Assuming
1924 * that the nodes are ordered properly in the DTS file and
1925 * that the translation into a flattened device tree blob
1926 * preserves that ordering this will actually yield the right
1927 * head number.
1928 *
1929 * If those assumptions don't hold, this will still work for
1930 * cases where only a single display controller is used.
1931 */
1932 for_each_matching_node(np, tegra_dc_of_match) {
1933 if (np == dc->dev->of_node) {
1934 of_node_put(np);
1935 break;
1936 }
1937
1938 value++;
1939 }
1940 }
1941
1942 dc->pipe = value;
1943
1944 return 0;
1945}
1946
1947static int tegra_dc_probe(struct platform_device *pdev)
1948{
1949 const struct of_device_id *id;
1950 struct resource *regs;
1951 struct tegra_dc *dc;
1952 int err;
1953
1954 dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL);
1955 if (!dc)
1956 return -ENOMEM;
1957
1958 id = of_match_node(tegra_dc_of_match, pdev->dev.of_node);
1959 if (!id)
1960 return -ENODEV;
1961
1962 spin_lock_init(&dc->lock);
1963 INIT_LIST_HEAD(&dc->list);
1964 dc->dev = &pdev->dev;
1965 dc->soc = id->data;
1966
1967 err = tegra_dc_parse_dt(dc);
1968 if (err < 0)
1969 return err;
1970
1971 dc->clk = devm_clk_get(&pdev->dev, NULL);
1972 if (IS_ERR(dc->clk)) {
1973 dev_err(&pdev->dev, "failed to get clock\n");
1974 return PTR_ERR(dc->clk);
1975 }
1976
1977 dc->rst = devm_reset_control_get(&pdev->dev, "dc");
1978 if (IS_ERR(dc->rst)) {
1979 dev_err(&pdev->dev, "failed to get reset\n");
1980 return PTR_ERR(dc->rst);
1981 }
1982
1983 reset_control_assert(dc->rst);
1984
1985 if (dc->soc->has_powergate) {
1986 if (dc->pipe == 0)
1987 dc->powergate = TEGRA_POWERGATE_DIS;
1988 else
1989 dc->powergate = TEGRA_POWERGATE_DISB;
1990
1991 tegra_powergate_power_off(dc->powergate);
1992 }
1993
1994 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1995 dc->regs = devm_ioremap_resource(&pdev->dev, regs);
1996 if (IS_ERR(dc->regs))
1997 return PTR_ERR(dc->regs);
1998
1999 dc->irq = platform_get_irq(pdev, 0);
2000 if (dc->irq < 0) {
2001 dev_err(&pdev->dev, "failed to get IRQ\n");
2002 return -ENXIO;
2003 }
2004
2005 err = tegra_dc_rgb_probe(dc);
2006 if (err < 0 && err != -ENODEV) {
2007 dev_err(&pdev->dev, "failed to probe RGB output: %d\n", err);
2008 return err;
2009 }
2010
2011 platform_set_drvdata(pdev, dc);
2012 pm_runtime_enable(&pdev->dev);
2013
2014 INIT_LIST_HEAD(&dc->client.list);
2015 dc->client.ops = &dc_client_ops;
2016 dc->client.dev = &pdev->dev;
2017
2018 err = host1x_client_register(&dc->client);
2019 if (err < 0) {
2020 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
2021 err);
2022 return err;
2023 }
2024
2025 return 0;
2026}
2027
2028static int tegra_dc_remove(struct platform_device *pdev)
2029{
2030 struct tegra_dc *dc = platform_get_drvdata(pdev);
2031 int err;
2032
2033 err = host1x_client_unregister(&dc->client);
2034 if (err < 0) {
2035 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
2036 err);
2037 return err;
2038 }
2039
2040 err = tegra_dc_rgb_remove(dc);
2041 if (err < 0) {
2042 dev_err(&pdev->dev, "failed to remove RGB output: %d\n", err);
2043 return err;
2044 }
2045
2046 pm_runtime_disable(&pdev->dev);
2047
2048 return 0;
2049}
2050
2051#ifdef CONFIG_PM
2052static int tegra_dc_suspend(struct device *dev)
2053{
2054 struct tegra_dc *dc = dev_get_drvdata(dev);
2055 int err;
2056
2057 err = reset_control_assert(dc->rst);
2058 if (err < 0) {
2059 dev_err(dev, "failed to assert reset: %d\n", err);
2060 return err;
2061 }
2062
2063 if (dc->soc->has_powergate)
2064 tegra_powergate_power_off(dc->powergate);
2065
2066 clk_disable_unprepare(dc->clk);
2067
2068 return 0;
2069}
2070
2071static int tegra_dc_resume(struct device *dev)
2072{
2073 struct tegra_dc *dc = dev_get_drvdata(dev);
2074 int err;
2075
2076 if (dc->soc->has_powergate) {
2077 err = tegra_powergate_sequence_power_up(dc->powergate, dc->clk,
2078 dc->rst);
2079 if (err < 0) {
2080 dev_err(dev, "failed to power partition: %d\n", err);
2081 return err;
2082 }
2083 } else {
2084 err = clk_prepare_enable(dc->clk);
2085 if (err < 0) {
2086 dev_err(dev, "failed to enable clock: %d\n", err);
2087 return err;
2088 }
2089
2090 err = reset_control_deassert(dc->rst);
2091 if (err < 0) {
2092 dev_err(dev, "failed to deassert reset: %d\n", err);
2093 return err;
2094 }
2095 }
2096
2097 return 0;
2098}
2099#endif
2100
2101static const struct dev_pm_ops tegra_dc_pm_ops = {
2102 SET_RUNTIME_PM_OPS(tegra_dc_suspend, tegra_dc_resume, NULL)
2103};
2104
2105struct platform_driver tegra_dc_driver = {
2106 .driver = {
2107 .name = "tegra-dc",
2108 .of_match_table = tegra_dc_of_match,
2109 .pm = &tegra_dc_pm_ops,
2110 },
2111 .probe = tegra_dc_probe,
2112 .remove = tegra_dc_remove,
2113};