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1// SPDX-License-Identifier: MIT
2
3#include <drm/drm_debugfs.h>
4#include <drm/drm_dp_mst_helper.h>
5#include <drm/drm_fb_helper.h>
6#include <drm/drm_file.h>
7#include <drm/drm_probe_helper.h>
8
9#include "atom.h"
10#include "ni_reg.h"
11#include "radeon.h"
12
13static struct radeon_encoder *radeon_dp_create_fake_mst_encoder(struct radeon_connector *connector);
14
15static int radeon_atom_set_enc_offset(int id)
16{
17 static const int offsets[] = { EVERGREEN_CRTC0_REGISTER_OFFSET,
18 EVERGREEN_CRTC1_REGISTER_OFFSET,
19 EVERGREEN_CRTC2_REGISTER_OFFSET,
20 EVERGREEN_CRTC3_REGISTER_OFFSET,
21 EVERGREEN_CRTC4_REGISTER_OFFSET,
22 EVERGREEN_CRTC5_REGISTER_OFFSET,
23 0x13830 - 0x7030 };
24
25 return offsets[id];
26}
27
28static int radeon_dp_mst_set_be_cntl(struct radeon_encoder *primary,
29 struct radeon_encoder_mst *mst_enc,
30 enum radeon_hpd_id hpd, bool enable)
31{
32 struct drm_device *dev = primary->base.dev;
33 struct radeon_device *rdev = dev->dev_private;
34 uint32_t reg;
35 int retries = 0;
36 uint32_t temp;
37
38 reg = RREG32(NI_DIG_BE_CNTL + primary->offset);
39
40 /* set MST mode */
41 reg &= ~NI_DIG_FE_DIG_MODE(7);
42 reg |= NI_DIG_FE_DIG_MODE(NI_DIG_MODE_DP_MST);
43
44 if (enable)
45 reg |= NI_DIG_FE_SOURCE_SELECT(1 << mst_enc->fe);
46 else
47 reg &= ~NI_DIG_FE_SOURCE_SELECT(1 << mst_enc->fe);
48
49 reg |= NI_DIG_HPD_SELECT(hpd);
50 DRM_DEBUG_KMS("writing 0x%08x 0x%08x\n", NI_DIG_BE_CNTL + primary->offset, reg);
51 WREG32(NI_DIG_BE_CNTL + primary->offset, reg);
52
53 if (enable) {
54 uint32_t offset = radeon_atom_set_enc_offset(mst_enc->fe);
55
56 do {
57 temp = RREG32(NI_DIG_FE_CNTL + offset);
58 } while ((temp & NI_DIG_SYMCLK_FE_ON) && retries++ < 10000);
59 if (retries == 10000)
60 DRM_ERROR("timed out waiting for FE %d %d\n", primary->offset, mst_enc->fe);
61 }
62 return 0;
63}
64
65static int radeon_dp_mst_set_stream_attrib(struct radeon_encoder *primary,
66 int stream_number,
67 int fe,
68 int slots)
69{
70 struct drm_device *dev = primary->base.dev;
71 struct radeon_device *rdev = dev->dev_private;
72 u32 temp, val;
73 int retries = 0;
74 int satreg, satidx;
75
76 satreg = stream_number >> 1;
77 satidx = stream_number & 1;
78
79 temp = RREG32(NI_DP_MSE_SAT0 + satreg + primary->offset);
80
81 val = NI_DP_MSE_SAT_SLOT_COUNT0(slots) | NI_DP_MSE_SAT_SRC0(fe);
82
83 val <<= (16 * satidx);
84
85 temp &= ~(0xffff << (16 * satidx));
86
87 temp |= val;
88
89 DRM_DEBUG_KMS("writing 0x%08x 0x%08x\n", NI_DP_MSE_SAT0 + satreg + primary->offset, temp);
90 WREG32(NI_DP_MSE_SAT0 + satreg + primary->offset, temp);
91
92 WREG32(NI_DP_MSE_SAT_UPDATE + primary->offset, 1);
93
94 do {
95 unsigned value1, value2;
96 udelay(10);
97 temp = RREG32(NI_DP_MSE_SAT_UPDATE + primary->offset);
98
99 value1 = temp & NI_DP_MSE_SAT_UPDATE_MASK;
100 value2 = temp & NI_DP_MSE_16_MTP_KEEPOUT;
101
102 if (!value1 && !value2)
103 break;
104 } while (retries++ < 50);
105
106 if (retries == 10000)
107 DRM_ERROR("timed out waitin for SAT update %d\n", primary->offset);
108
109 /* MTP 16 ? */
110 return 0;
111}
112
113static int radeon_dp_mst_update_stream_attribs(struct radeon_connector *mst_conn,
114 struct radeon_encoder *primary)
115{
116 struct drm_device *dev = mst_conn->base.dev;
117 struct stream_attribs new_attribs[6];
118 int i;
119 int idx = 0;
120 struct radeon_connector *radeon_connector;
121 struct drm_connector *connector;
122
123 memset(new_attribs, 0, sizeof(new_attribs));
124 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
125 struct radeon_encoder *subenc;
126 struct radeon_encoder_mst *mst_enc;
127
128 radeon_connector = to_radeon_connector(connector);
129 if (!radeon_connector->is_mst_connector)
130 continue;
131
132 if (radeon_connector->mst_port != mst_conn)
133 continue;
134
135 subenc = radeon_connector->mst_encoder;
136 mst_enc = subenc->enc_priv;
137
138 if (!mst_enc->enc_active)
139 continue;
140
141 new_attribs[idx].fe = mst_enc->fe;
142 new_attribs[idx].slots = drm_dp_mst_get_vcpi_slots(&mst_conn->mst_mgr, mst_enc->port);
143 idx++;
144 }
145
146 for (i = 0; i < idx; i++) {
147 if (new_attribs[i].fe != mst_conn->cur_stream_attribs[i].fe ||
148 new_attribs[i].slots != mst_conn->cur_stream_attribs[i].slots) {
149 radeon_dp_mst_set_stream_attrib(primary, i, new_attribs[i].fe, new_attribs[i].slots);
150 mst_conn->cur_stream_attribs[i].fe = new_attribs[i].fe;
151 mst_conn->cur_stream_attribs[i].slots = new_attribs[i].slots;
152 }
153 }
154
155 for (i = idx; i < mst_conn->enabled_attribs; i++) {
156 radeon_dp_mst_set_stream_attrib(primary, i, 0, 0);
157 mst_conn->cur_stream_attribs[i].fe = 0;
158 mst_conn->cur_stream_attribs[i].slots = 0;
159 }
160 mst_conn->enabled_attribs = idx;
161 return 0;
162}
163
164static int radeon_dp_mst_set_vcp_size(struct radeon_encoder *mst, s64 avg_time_slots_per_mtp)
165{
166 struct drm_device *dev = mst->base.dev;
167 struct radeon_device *rdev = dev->dev_private;
168 struct radeon_encoder_mst *mst_enc = mst->enc_priv;
169 uint32_t val, temp;
170 uint32_t offset = radeon_atom_set_enc_offset(mst_enc->fe);
171 int retries = 0;
172 uint32_t x = drm_fixp2int(avg_time_slots_per_mtp);
173 uint32_t y = drm_fixp2int_ceil((avg_time_slots_per_mtp - x) << 26);
174
175 val = NI_DP_MSE_RATE_X(x) | NI_DP_MSE_RATE_Y(y);
176
177 WREG32(NI_DP_MSE_RATE_CNTL + offset, val);
178
179 do {
180 temp = RREG32(NI_DP_MSE_RATE_UPDATE + offset);
181 udelay(10);
182 } while ((temp & 0x1) && (retries++ < 10000));
183
184 if (retries >= 10000)
185 DRM_ERROR("timed out wait for rate cntl %d\n", mst_enc->fe);
186 return 0;
187}
188
189static int radeon_dp_mst_get_ddc_modes(struct drm_connector *connector)
190{
191 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
192 struct radeon_connector *master = radeon_connector->mst_port;
193 struct edid *edid;
194 int ret = 0;
195
196 edid = drm_dp_mst_get_edid(connector, &master->mst_mgr, radeon_connector->port);
197 radeon_connector->edid = edid;
198 DRM_DEBUG_KMS("edid retrieved %p\n", edid);
199 if (radeon_connector->edid) {
200 drm_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid);
201 ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid);
202 return ret;
203 }
204 drm_connector_update_edid_property(&radeon_connector->base, NULL);
205
206 return ret;
207}
208
209static int radeon_dp_mst_get_modes(struct drm_connector *connector)
210{
211 return radeon_dp_mst_get_ddc_modes(connector);
212}
213
214static enum drm_mode_status
215radeon_dp_mst_mode_valid(struct drm_connector *connector,
216 struct drm_display_mode *mode)
217{
218 /* TODO - validate mode against available PBN for link */
219 if (mode->clock < 10000)
220 return MODE_CLOCK_LOW;
221
222 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
223 return MODE_H_ILLEGAL;
224
225 return MODE_OK;
226}
227
228static struct
229drm_encoder *radeon_mst_best_encoder(struct drm_connector *connector)
230{
231 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
232
233 return &radeon_connector->mst_encoder->base;
234}
235
236static int
237radeon_dp_mst_detect(struct drm_connector *connector,
238 struct drm_modeset_acquire_ctx *ctx,
239 bool force)
240{
241 struct radeon_connector *radeon_connector =
242 to_radeon_connector(connector);
243 struct radeon_connector *master = radeon_connector->mst_port;
244
245 return drm_dp_mst_detect_port(connector, ctx, &master->mst_mgr,
246 radeon_connector->port);
247}
248
249static const struct drm_connector_helper_funcs radeon_dp_mst_connector_helper_funcs = {
250 .get_modes = radeon_dp_mst_get_modes,
251 .mode_valid = radeon_dp_mst_mode_valid,
252 .best_encoder = radeon_mst_best_encoder,
253 .detect_ctx = radeon_dp_mst_detect,
254};
255
256static void
257radeon_dp_mst_connector_destroy(struct drm_connector *connector)
258{
259 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
260 struct radeon_encoder *radeon_encoder = radeon_connector->mst_encoder;
261
262 drm_encoder_cleanup(&radeon_encoder->base);
263 kfree(radeon_encoder);
264 drm_connector_cleanup(connector);
265 kfree(radeon_connector);
266}
267
268static const struct drm_connector_funcs radeon_dp_mst_connector_funcs = {
269 .dpms = drm_helper_connector_dpms,
270 .fill_modes = drm_helper_probe_single_connector_modes,
271 .destroy = radeon_dp_mst_connector_destroy,
272};
273
274static struct drm_connector *radeon_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
275 struct drm_dp_mst_port *port,
276 const char *pathprop)
277{
278 struct radeon_connector *master = container_of(mgr, struct radeon_connector, mst_mgr);
279 struct drm_device *dev = master->base.dev;
280 struct radeon_connector *radeon_connector;
281 struct drm_connector *connector;
282
283 radeon_connector = kzalloc(sizeof(*radeon_connector), GFP_KERNEL);
284 if (!radeon_connector)
285 return NULL;
286
287 radeon_connector->is_mst_connector = true;
288 connector = &radeon_connector->base;
289 radeon_connector->port = port;
290 radeon_connector->mst_port = master;
291 DRM_DEBUG_KMS("\n");
292
293 drm_connector_init(dev, connector, &radeon_dp_mst_connector_funcs, DRM_MODE_CONNECTOR_DisplayPort);
294 drm_connector_helper_add(connector, &radeon_dp_mst_connector_helper_funcs);
295 radeon_connector->mst_encoder = radeon_dp_create_fake_mst_encoder(master);
296
297 drm_object_attach_property(&connector->base, dev->mode_config.path_property, 0);
298 drm_object_attach_property(&connector->base, dev->mode_config.tile_property, 0);
299 drm_connector_set_path_property(connector, pathprop);
300
301 return connector;
302}
303
304static const struct drm_dp_mst_topology_cbs mst_cbs = {
305 .add_connector = radeon_dp_add_mst_connector,
306};
307
308static struct
309radeon_connector *radeon_mst_find_connector(struct drm_encoder *encoder)
310{
311 struct drm_device *dev = encoder->dev;
312 struct drm_connector *connector;
313
314 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
315 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
316 if (!connector->encoder)
317 continue;
318 if (!radeon_connector->is_mst_connector)
319 continue;
320
321 DRM_DEBUG_KMS("checking %p vs %p\n", connector->encoder, encoder);
322 if (connector->encoder == encoder)
323 return radeon_connector;
324 }
325 return NULL;
326}
327
328void radeon_dp_mst_prepare_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
329{
330 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
331 struct drm_device *dev = crtc->dev;
332 struct radeon_device *rdev = dev->dev_private;
333 struct radeon_encoder *radeon_encoder = to_radeon_encoder(radeon_crtc->encoder);
334 struct radeon_encoder_mst *mst_enc = radeon_encoder->enc_priv;
335 struct radeon_connector *radeon_connector = radeon_mst_find_connector(&radeon_encoder->base);
336 int dp_clock;
337 struct radeon_connector_atom_dig *dig_connector = mst_enc->connector->con_priv;
338
339 if (radeon_connector) {
340 radeon_connector->pixelclock_for_modeset = mode->clock;
341 if (radeon_connector->base.display_info.bpc)
342 radeon_crtc->bpc = radeon_connector->base.display_info.bpc;
343 else
344 radeon_crtc->bpc = 8;
345 }
346
347 DRM_DEBUG_KMS("dp_clock %p %d\n", dig_connector, dig_connector->dp_clock);
348 dp_clock = dig_connector->dp_clock;
349 radeon_crtc->ss_enabled =
350 radeon_atombios_get_asic_ss_info(rdev, &radeon_crtc->ss,
351 ASIC_INTERNAL_SS_ON_DP,
352 dp_clock);
353}
354
355static void
356radeon_mst_encoder_dpms(struct drm_encoder *encoder, int mode)
357{
358 struct drm_device *dev = encoder->dev;
359 struct radeon_device *rdev = dev->dev_private;
360 struct radeon_encoder *radeon_encoder, *primary;
361 struct radeon_encoder_mst *mst_enc;
362 struct radeon_encoder_atom_dig *dig_enc;
363 struct radeon_connector *radeon_connector;
364 struct drm_crtc *crtc;
365 struct radeon_crtc *radeon_crtc;
366 int ret, slots;
367 s64 fixed_pbn, fixed_pbn_per_slot, avg_time_slots_per_mtp;
368 if (!ASIC_IS_DCE5(rdev)) {
369 DRM_ERROR("got mst dpms on non-DCE5\n");
370 return;
371 }
372
373 radeon_connector = radeon_mst_find_connector(encoder);
374 if (!radeon_connector)
375 return;
376
377 radeon_encoder = to_radeon_encoder(encoder);
378
379 mst_enc = radeon_encoder->enc_priv;
380
381 primary = mst_enc->primary;
382
383 dig_enc = primary->enc_priv;
384
385 crtc = encoder->crtc;
386 DRM_DEBUG_KMS("got connector %d\n", dig_enc->active_mst_links);
387
388 switch (mode) {
389 case DRM_MODE_DPMS_ON:
390 dig_enc->active_mst_links++;
391
392 radeon_crtc = to_radeon_crtc(crtc);
393
394 if (dig_enc->active_mst_links == 1) {
395 mst_enc->fe = dig_enc->dig_encoder;
396 mst_enc->fe_from_be = true;
397 atombios_set_mst_encoder_crtc_source(encoder, mst_enc->fe);
398
399 atombios_dig_encoder_setup(&primary->base, ATOM_ENCODER_CMD_SETUP, 0);
400 atombios_dig_transmitter_setup2(&primary->base, ATOM_TRANSMITTER_ACTION_ENABLE,
401 0, 0, dig_enc->dig_encoder);
402
403 if (radeon_dp_needs_link_train(mst_enc->connector) ||
404 dig_enc->active_mst_links == 1) {
405 radeon_dp_link_train(&primary->base, &mst_enc->connector->base);
406 }
407
408 } else {
409 mst_enc->fe = radeon_atom_pick_dig_encoder(encoder, radeon_crtc->crtc_id);
410 if (mst_enc->fe == -1)
411 DRM_ERROR("failed to get frontend for dig encoder\n");
412 mst_enc->fe_from_be = false;
413 atombios_set_mst_encoder_crtc_source(encoder, mst_enc->fe);
414 }
415
416 DRM_DEBUG_KMS("dig encoder is %d %d %d\n", dig_enc->dig_encoder,
417 dig_enc->linkb, radeon_crtc->crtc_id);
418
419 slots = drm_dp_find_vcpi_slots(&radeon_connector->mst_port->mst_mgr,
420 mst_enc->pbn);
421 ret = drm_dp_mst_allocate_vcpi(&radeon_connector->mst_port->mst_mgr,
422 radeon_connector->port,
423 mst_enc->pbn, slots);
424 ret = drm_dp_update_payload_part1(&radeon_connector->mst_port->mst_mgr);
425
426 radeon_dp_mst_set_be_cntl(primary, mst_enc,
427 radeon_connector->mst_port->hpd.hpd, true);
428
429 mst_enc->enc_active = true;
430 radeon_dp_mst_update_stream_attribs(radeon_connector->mst_port, primary);
431
432 fixed_pbn = drm_int2fixp(mst_enc->pbn);
433 fixed_pbn_per_slot = drm_int2fixp(radeon_connector->mst_port->mst_mgr.pbn_div);
434 avg_time_slots_per_mtp = drm_fixp_div(fixed_pbn, fixed_pbn_per_slot);
435 radeon_dp_mst_set_vcp_size(radeon_encoder, avg_time_slots_per_mtp);
436
437 atombios_dig_encoder_setup2(&primary->base, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0,
438 mst_enc->fe);
439 ret = drm_dp_check_act_status(&radeon_connector->mst_port->mst_mgr);
440
441 ret = drm_dp_update_payload_part2(&radeon_connector->mst_port->mst_mgr);
442
443 break;
444 case DRM_MODE_DPMS_STANDBY:
445 case DRM_MODE_DPMS_SUSPEND:
446 case DRM_MODE_DPMS_OFF:
447 DRM_ERROR("DPMS OFF %d\n", dig_enc->active_mst_links);
448
449 if (!mst_enc->enc_active)
450 return;
451
452 drm_dp_mst_reset_vcpi_slots(&radeon_connector->mst_port->mst_mgr, mst_enc->port);
453 ret = drm_dp_update_payload_part1(&radeon_connector->mst_port->mst_mgr);
454
455 drm_dp_check_act_status(&radeon_connector->mst_port->mst_mgr);
456 /* and this can also fail */
457 drm_dp_update_payload_part2(&radeon_connector->mst_port->mst_mgr);
458
459 drm_dp_mst_deallocate_vcpi(&radeon_connector->mst_port->mst_mgr, mst_enc->port);
460
461 mst_enc->enc_active = false;
462 radeon_dp_mst_update_stream_attribs(radeon_connector->mst_port, primary);
463
464 radeon_dp_mst_set_be_cntl(primary, mst_enc,
465 radeon_connector->mst_port->hpd.hpd, false);
466 atombios_dig_encoder_setup2(&primary->base, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0,
467 mst_enc->fe);
468
469 if (!mst_enc->fe_from_be)
470 radeon_atom_release_dig_encoder(rdev, mst_enc->fe);
471
472 mst_enc->fe_from_be = false;
473 dig_enc->active_mst_links--;
474 if (dig_enc->active_mst_links == 0) {
475 /* drop link */
476 }
477
478 break;
479 }
480
481}
482
483static bool radeon_mst_mode_fixup(struct drm_encoder *encoder,
484 const struct drm_display_mode *mode,
485 struct drm_display_mode *adjusted_mode)
486{
487 struct radeon_encoder_mst *mst_enc;
488 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
489 struct radeon_connector_atom_dig *dig_connector;
490 int bpp = 24;
491
492 mst_enc = radeon_encoder->enc_priv;
493
494 mst_enc->pbn = drm_dp_calc_pbn_mode(adjusted_mode->clock, bpp, false);
495
496 mst_enc->primary->active_device = mst_enc->primary->devices & mst_enc->connector->devices;
497 DRM_DEBUG_KMS("setting active device to %08x from %08x %08x for encoder %d\n",
498 mst_enc->primary->active_device, mst_enc->primary->devices,
499 mst_enc->connector->devices, mst_enc->primary->base.encoder_type);
500
501
502 drm_mode_set_crtcinfo(adjusted_mode, 0);
503 dig_connector = mst_enc->connector->con_priv;
504 dig_connector->dp_lane_count = drm_dp_max_lane_count(dig_connector->dpcd);
505 dig_connector->dp_clock = drm_dp_max_link_rate(dig_connector->dpcd);
506 DRM_DEBUG_KMS("dig clock %p %d %d\n", dig_connector,
507 dig_connector->dp_lane_count, dig_connector->dp_clock);
508 return true;
509}
510
511static void radeon_mst_encoder_prepare(struct drm_encoder *encoder)
512{
513 struct radeon_connector *radeon_connector;
514 struct radeon_encoder *radeon_encoder, *primary;
515 struct radeon_encoder_mst *mst_enc;
516 struct radeon_encoder_atom_dig *dig_enc;
517
518 radeon_connector = radeon_mst_find_connector(encoder);
519 if (!radeon_connector) {
520 DRM_DEBUG_KMS("failed to find connector %p\n", encoder);
521 return;
522 }
523 radeon_encoder = to_radeon_encoder(encoder);
524
525 radeon_mst_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
526
527 mst_enc = radeon_encoder->enc_priv;
528
529 primary = mst_enc->primary;
530
531 dig_enc = primary->enc_priv;
532
533 mst_enc->port = radeon_connector->port;
534
535 if (dig_enc->dig_encoder == -1) {
536 dig_enc->dig_encoder = radeon_atom_pick_dig_encoder(&primary->base, -1);
537 primary->offset = radeon_atom_set_enc_offset(dig_enc->dig_encoder);
538 atombios_set_mst_encoder_crtc_source(encoder, dig_enc->dig_encoder);
539
540
541 }
542 DRM_DEBUG_KMS("%d %d\n", dig_enc->dig_encoder, primary->offset);
543}
544
545static void
546radeon_mst_encoder_mode_set(struct drm_encoder *encoder,
547 struct drm_display_mode *mode,
548 struct drm_display_mode *adjusted_mode)
549{
550 DRM_DEBUG_KMS("\n");
551}
552
553static void radeon_mst_encoder_commit(struct drm_encoder *encoder)
554{
555 radeon_mst_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
556 DRM_DEBUG_KMS("\n");
557}
558
559static const struct drm_encoder_helper_funcs radeon_mst_helper_funcs = {
560 .dpms = radeon_mst_encoder_dpms,
561 .mode_fixup = radeon_mst_mode_fixup,
562 .prepare = radeon_mst_encoder_prepare,
563 .mode_set = radeon_mst_encoder_mode_set,
564 .commit = radeon_mst_encoder_commit,
565};
566
567static void radeon_dp_mst_encoder_destroy(struct drm_encoder *encoder)
568{
569 drm_encoder_cleanup(encoder);
570 kfree(encoder);
571}
572
573static const struct drm_encoder_funcs radeon_dp_mst_enc_funcs = {
574 .destroy = radeon_dp_mst_encoder_destroy,
575};
576
577static struct radeon_encoder *
578radeon_dp_create_fake_mst_encoder(struct radeon_connector *connector)
579{
580 struct drm_device *dev = connector->base.dev;
581 struct radeon_device *rdev = dev->dev_private;
582 struct radeon_encoder *radeon_encoder;
583 struct radeon_encoder_mst *mst_enc;
584 struct drm_encoder *encoder;
585 const struct drm_connector_helper_funcs *connector_funcs = connector->base.helper_private;
586 struct drm_encoder *enc_master = connector_funcs->best_encoder(&connector->base);
587
588 DRM_DEBUG_KMS("enc master is %p\n", enc_master);
589 radeon_encoder = kzalloc(sizeof(*radeon_encoder), GFP_KERNEL);
590 if (!radeon_encoder)
591 return NULL;
592
593 radeon_encoder->enc_priv = kzalloc(sizeof(*mst_enc), GFP_KERNEL);
594 if (!radeon_encoder->enc_priv) {
595 kfree(radeon_encoder);
596 return NULL;
597 }
598 encoder = &radeon_encoder->base;
599 switch (rdev->num_crtc) {
600 case 1:
601 encoder->possible_crtcs = 0x1;
602 break;
603 case 2:
604 default:
605 encoder->possible_crtcs = 0x3;
606 break;
607 case 4:
608 encoder->possible_crtcs = 0xf;
609 break;
610 case 6:
611 encoder->possible_crtcs = 0x3f;
612 break;
613 }
614
615 drm_encoder_init(dev, &radeon_encoder->base, &radeon_dp_mst_enc_funcs,
616 DRM_MODE_ENCODER_DPMST, NULL);
617 drm_encoder_helper_add(encoder, &radeon_mst_helper_funcs);
618
619 mst_enc = radeon_encoder->enc_priv;
620 mst_enc->connector = connector;
621 mst_enc->primary = to_radeon_encoder(enc_master);
622 radeon_encoder->is_mst_encoder = true;
623 return radeon_encoder;
624}
625
626int
627radeon_dp_mst_init(struct radeon_connector *radeon_connector)
628{
629 struct drm_device *dev = radeon_connector->base.dev;
630
631 if (!radeon_connector->ddc_bus->has_aux)
632 return 0;
633
634 radeon_connector->mst_mgr.cbs = &mst_cbs;
635 return drm_dp_mst_topology_mgr_init(&radeon_connector->mst_mgr, dev,
636 &radeon_connector->ddc_bus->aux, 16, 6,
637 radeon_connector->base.base.id);
638}
639
640int
641radeon_dp_mst_probe(struct radeon_connector *radeon_connector)
642{
643 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
644 struct drm_device *dev = radeon_connector->base.dev;
645 struct radeon_device *rdev = dev->dev_private;
646 int ret;
647 u8 msg[1];
648
649 if (!radeon_mst)
650 return 0;
651
652 if (!ASIC_IS_DCE5(rdev))
653 return 0;
654
655 if (dig_connector->dpcd[DP_DPCD_REV] < 0x12)
656 return 0;
657
658 ret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_MSTM_CAP, msg,
659 1);
660 if (ret) {
661 if (msg[0] & DP_MST_CAP) {
662 DRM_DEBUG_KMS("Sink is MST capable\n");
663 dig_connector->is_mst = true;
664 } else {
665 DRM_DEBUG_KMS("Sink is not MST capable\n");
666 dig_connector->is_mst = false;
667 }
668
669 }
670 drm_dp_mst_topology_mgr_set_mst(&radeon_connector->mst_mgr,
671 dig_connector->is_mst);
672 return dig_connector->is_mst;
673}
674
675int
676radeon_dp_mst_check_status(struct radeon_connector *radeon_connector)
677{
678 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
679 int retry;
680
681 if (dig_connector->is_mst) {
682 u8 esi[16] = { 0 };
683 int dret;
684 int ret = 0;
685 bool handled;
686
687 dret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux,
688 DP_SINK_COUNT_ESI, esi, 8);
689go_again:
690 if (dret == 8) {
691 DRM_DEBUG_KMS("got esi %3ph\n", esi);
692 ret = drm_dp_mst_hpd_irq(&radeon_connector->mst_mgr, esi, &handled);
693
694 if (handled) {
695 for (retry = 0; retry < 3; retry++) {
696 int wret;
697 wret = drm_dp_dpcd_write(&radeon_connector->ddc_bus->aux,
698 DP_SINK_COUNT_ESI + 1, &esi[1], 3);
699 if (wret == 3)
700 break;
701 }
702
703 dret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux,
704 DP_SINK_COUNT_ESI, esi, 8);
705 if (dret == 8) {
706 DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
707 goto go_again;
708 }
709 } else
710 ret = 0;
711
712 return ret;
713 } else {
714 DRM_DEBUG_KMS("failed to get ESI - device may have failed %d\n", ret);
715 dig_connector->is_mst = false;
716 drm_dp_mst_topology_mgr_set_mst(&radeon_connector->mst_mgr,
717 dig_connector->is_mst);
718 /* send a hotplug event */
719 }
720 }
721 return -EINVAL;
722}
723
724#if defined(CONFIG_DEBUG_FS)
725
726static int radeon_debugfs_mst_info(struct seq_file *m, void *data)
727{
728 struct drm_info_node *node = (struct drm_info_node *)m->private;
729 struct drm_device *dev = node->minor->dev;
730 struct drm_connector *connector;
731 struct radeon_connector *radeon_connector;
732 struct radeon_connector_atom_dig *dig_connector;
733 int i;
734
735 drm_modeset_lock_all(dev);
736 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
737 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
738 continue;
739
740 radeon_connector = to_radeon_connector(connector);
741 dig_connector = radeon_connector->con_priv;
742 if (radeon_connector->is_mst_connector)
743 continue;
744 if (!dig_connector->is_mst)
745 continue;
746 drm_dp_mst_dump_topology(m, &radeon_connector->mst_mgr);
747
748 for (i = 0; i < radeon_connector->enabled_attribs; i++)
749 seq_printf(m, "attrib %d: %d %d\n", i,
750 radeon_connector->cur_stream_attribs[i].fe,
751 radeon_connector->cur_stream_attribs[i].slots);
752 }
753 drm_modeset_unlock_all(dev);
754 return 0;
755}
756
757static struct drm_info_list radeon_debugfs_mst_list[] = {
758 {"radeon_mst_info", &radeon_debugfs_mst_info, 0, NULL},
759};
760#endif
761
762int radeon_mst_debugfs_init(struct radeon_device *rdev)
763{
764#if defined(CONFIG_DEBUG_FS)
765 return radeon_debugfs_add_files(rdev, radeon_debugfs_mst_list, 1);
766#endif
767 return 0;
768}
1
2#include <drm/drmP.h>
3#include <drm/drm_dp_mst_helper.h>
4#include <drm/drm_fb_helper.h>
5
6#include "radeon.h"
7#include "atom.h"
8#include "ni_reg.h"
9
10static struct radeon_encoder *radeon_dp_create_fake_mst_encoder(struct radeon_connector *connector);
11
12static int radeon_atom_set_enc_offset(int id)
13{
14 static const int offsets[] = { EVERGREEN_CRTC0_REGISTER_OFFSET,
15 EVERGREEN_CRTC1_REGISTER_OFFSET,
16 EVERGREEN_CRTC2_REGISTER_OFFSET,
17 EVERGREEN_CRTC3_REGISTER_OFFSET,
18 EVERGREEN_CRTC4_REGISTER_OFFSET,
19 EVERGREEN_CRTC5_REGISTER_OFFSET,
20 0x13830 - 0x7030 };
21
22 return offsets[id];
23}
24
25static int radeon_dp_mst_set_be_cntl(struct radeon_encoder *primary,
26 struct radeon_encoder_mst *mst_enc,
27 enum radeon_hpd_id hpd, bool enable)
28{
29 struct drm_device *dev = primary->base.dev;
30 struct radeon_device *rdev = dev->dev_private;
31 uint32_t reg;
32 int retries = 0;
33 uint32_t temp;
34
35 reg = RREG32(NI_DIG_BE_CNTL + primary->offset);
36
37 /* set MST mode */
38 reg &= ~NI_DIG_FE_DIG_MODE(7);
39 reg |= NI_DIG_FE_DIG_MODE(NI_DIG_MODE_DP_MST);
40
41 if (enable)
42 reg |= NI_DIG_FE_SOURCE_SELECT(1 << mst_enc->fe);
43 else
44 reg &= ~NI_DIG_FE_SOURCE_SELECT(1 << mst_enc->fe);
45
46 reg |= NI_DIG_HPD_SELECT(hpd);
47 DRM_DEBUG_KMS("writing 0x%08x 0x%08x\n", NI_DIG_BE_CNTL + primary->offset, reg);
48 WREG32(NI_DIG_BE_CNTL + primary->offset, reg);
49
50 if (enable) {
51 uint32_t offset = radeon_atom_set_enc_offset(mst_enc->fe);
52
53 do {
54 temp = RREG32(NI_DIG_FE_CNTL + offset);
55 } while ((temp & NI_DIG_SYMCLK_FE_ON) && retries++ < 10000);
56 if (retries == 10000)
57 DRM_ERROR("timed out waiting for FE %d %d\n", primary->offset, mst_enc->fe);
58 }
59 return 0;
60}
61
62static int radeon_dp_mst_set_stream_attrib(struct radeon_encoder *primary,
63 int stream_number,
64 int fe,
65 int slots)
66{
67 struct drm_device *dev = primary->base.dev;
68 struct radeon_device *rdev = dev->dev_private;
69 u32 temp, val;
70 int retries = 0;
71 int satreg, satidx;
72
73 satreg = stream_number >> 1;
74 satidx = stream_number & 1;
75
76 temp = RREG32(NI_DP_MSE_SAT0 + satreg + primary->offset);
77
78 val = NI_DP_MSE_SAT_SLOT_COUNT0(slots) | NI_DP_MSE_SAT_SRC0(fe);
79
80 val <<= (16 * satidx);
81
82 temp &= ~(0xffff << (16 * satidx));
83
84 temp |= val;
85
86 DRM_DEBUG_KMS("writing 0x%08x 0x%08x\n", NI_DP_MSE_SAT0 + satreg + primary->offset, temp);
87 WREG32(NI_DP_MSE_SAT0 + satreg + primary->offset, temp);
88
89 WREG32(NI_DP_MSE_SAT_UPDATE + primary->offset, 1);
90
91 do {
92 unsigned value1, value2;
93 udelay(10);
94 temp = RREG32(NI_DP_MSE_SAT_UPDATE + primary->offset);
95
96 value1 = temp & NI_DP_MSE_SAT_UPDATE_MASK;
97 value2 = temp & NI_DP_MSE_16_MTP_KEEPOUT;
98
99 if (!value1 && !value2)
100 break;
101 } while (retries++ < 50);
102
103 if (retries == 10000)
104 DRM_ERROR("timed out waitin for SAT update %d\n", primary->offset);
105
106 /* MTP 16 ? */
107 return 0;
108}
109
110static int radeon_dp_mst_update_stream_attribs(struct radeon_connector *mst_conn,
111 struct radeon_encoder *primary)
112{
113 struct drm_device *dev = mst_conn->base.dev;
114 struct stream_attribs new_attribs[6];
115 int i;
116 int idx = 0;
117 struct radeon_connector *radeon_connector;
118 struct drm_connector *connector;
119
120 memset(new_attribs, 0, sizeof(new_attribs));
121 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
122 struct radeon_encoder *subenc;
123 struct radeon_encoder_mst *mst_enc;
124
125 radeon_connector = to_radeon_connector(connector);
126 if (!radeon_connector->is_mst_connector)
127 continue;
128
129 if (radeon_connector->mst_port != mst_conn)
130 continue;
131
132 subenc = radeon_connector->mst_encoder;
133 mst_enc = subenc->enc_priv;
134
135 if (!mst_enc->enc_active)
136 continue;
137
138 new_attribs[idx].fe = mst_enc->fe;
139 new_attribs[idx].slots = drm_dp_mst_get_vcpi_slots(&mst_conn->mst_mgr, mst_enc->port);
140 idx++;
141 }
142
143 for (i = 0; i < idx; i++) {
144 if (new_attribs[i].fe != mst_conn->cur_stream_attribs[i].fe ||
145 new_attribs[i].slots != mst_conn->cur_stream_attribs[i].slots) {
146 radeon_dp_mst_set_stream_attrib(primary, i, new_attribs[i].fe, new_attribs[i].slots);
147 mst_conn->cur_stream_attribs[i].fe = new_attribs[i].fe;
148 mst_conn->cur_stream_attribs[i].slots = new_attribs[i].slots;
149 }
150 }
151
152 for (i = idx; i < mst_conn->enabled_attribs; i++) {
153 radeon_dp_mst_set_stream_attrib(primary, i, 0, 0);
154 mst_conn->cur_stream_attribs[i].fe = 0;
155 mst_conn->cur_stream_attribs[i].slots = 0;
156 }
157 mst_conn->enabled_attribs = idx;
158 return 0;
159}
160
161static int radeon_dp_mst_set_vcp_size(struct radeon_encoder *mst, s64 avg_time_slots_per_mtp)
162{
163 struct drm_device *dev = mst->base.dev;
164 struct radeon_device *rdev = dev->dev_private;
165 struct radeon_encoder_mst *mst_enc = mst->enc_priv;
166 uint32_t val, temp;
167 uint32_t offset = radeon_atom_set_enc_offset(mst_enc->fe);
168 int retries = 0;
169 uint32_t x = drm_fixp2int(avg_time_slots_per_mtp);
170 uint32_t y = drm_fixp2int_ceil((avg_time_slots_per_mtp - x) << 26);
171
172 val = NI_DP_MSE_RATE_X(x) | NI_DP_MSE_RATE_Y(y);
173
174 WREG32(NI_DP_MSE_RATE_CNTL + offset, val);
175
176 do {
177 temp = RREG32(NI_DP_MSE_RATE_UPDATE + offset);
178 udelay(10);
179 } while ((temp & 0x1) && (retries++ < 10000));
180
181 if (retries >= 10000)
182 DRM_ERROR("timed out wait for rate cntl %d\n", mst_enc->fe);
183 return 0;
184}
185
186static int radeon_dp_mst_get_ddc_modes(struct drm_connector *connector)
187{
188 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
189 struct radeon_connector *master = radeon_connector->mst_port;
190 struct edid *edid;
191 int ret = 0;
192
193 edid = drm_dp_mst_get_edid(connector, &master->mst_mgr, radeon_connector->port);
194 radeon_connector->edid = edid;
195 DRM_DEBUG_KMS("edid retrieved %p\n", edid);
196 if (radeon_connector->edid) {
197 drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid);
198 ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid);
199 drm_edid_to_eld(&radeon_connector->base, radeon_connector->edid);
200 return ret;
201 }
202 drm_mode_connector_update_edid_property(&radeon_connector->base, NULL);
203
204 return ret;
205}
206
207static int radeon_dp_mst_get_modes(struct drm_connector *connector)
208{
209 return radeon_dp_mst_get_ddc_modes(connector);
210}
211
212static enum drm_mode_status
213radeon_dp_mst_mode_valid(struct drm_connector *connector,
214 struct drm_display_mode *mode)
215{
216 /* TODO - validate mode against available PBN for link */
217 if (mode->clock < 10000)
218 return MODE_CLOCK_LOW;
219
220 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
221 return MODE_H_ILLEGAL;
222
223 return MODE_OK;
224}
225
226static struct
227drm_encoder *radeon_mst_best_encoder(struct drm_connector *connector)
228{
229 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
230
231 return &radeon_connector->mst_encoder->base;
232}
233
234static const struct drm_connector_helper_funcs radeon_dp_mst_connector_helper_funcs = {
235 .get_modes = radeon_dp_mst_get_modes,
236 .mode_valid = radeon_dp_mst_mode_valid,
237 .best_encoder = radeon_mst_best_encoder,
238};
239
240static enum drm_connector_status
241radeon_dp_mst_detect(struct drm_connector *connector, bool force)
242{
243 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
244 struct radeon_connector *master = radeon_connector->mst_port;
245
246 return drm_dp_mst_detect_port(connector, &master->mst_mgr, radeon_connector->port);
247}
248
249static void
250radeon_dp_mst_connector_destroy(struct drm_connector *connector)
251{
252 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
253 struct radeon_encoder *radeon_encoder = radeon_connector->mst_encoder;
254
255 drm_encoder_cleanup(&radeon_encoder->base);
256 kfree(radeon_encoder);
257 drm_connector_cleanup(connector);
258 kfree(radeon_connector);
259}
260
261static const struct drm_connector_funcs radeon_dp_mst_connector_funcs = {
262 .dpms = drm_helper_connector_dpms,
263 .detect = radeon_dp_mst_detect,
264 .fill_modes = drm_helper_probe_single_connector_modes,
265 .destroy = radeon_dp_mst_connector_destroy,
266};
267
268static struct drm_connector *radeon_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
269 struct drm_dp_mst_port *port,
270 const char *pathprop)
271{
272 struct radeon_connector *master = container_of(mgr, struct radeon_connector, mst_mgr);
273 struct drm_device *dev = master->base.dev;
274 struct radeon_connector *radeon_connector;
275 struct drm_connector *connector;
276
277 radeon_connector = kzalloc(sizeof(*radeon_connector), GFP_KERNEL);
278 if (!radeon_connector)
279 return NULL;
280
281 radeon_connector->is_mst_connector = true;
282 connector = &radeon_connector->base;
283 radeon_connector->port = port;
284 radeon_connector->mst_port = master;
285 DRM_DEBUG_KMS("\n");
286
287 drm_connector_init(dev, connector, &radeon_dp_mst_connector_funcs, DRM_MODE_CONNECTOR_DisplayPort);
288 drm_connector_helper_add(connector, &radeon_dp_mst_connector_helper_funcs);
289 radeon_connector->mst_encoder = radeon_dp_create_fake_mst_encoder(master);
290
291 drm_object_attach_property(&connector->base, dev->mode_config.path_property, 0);
292 drm_object_attach_property(&connector->base, dev->mode_config.tile_property, 0);
293 drm_mode_connector_set_path_property(connector, pathprop);
294
295 return connector;
296}
297
298static void radeon_dp_register_mst_connector(struct drm_connector *connector)
299{
300 struct drm_device *dev = connector->dev;
301 struct radeon_device *rdev = dev->dev_private;
302
303 drm_modeset_lock_all(dev);
304 radeon_fb_add_connector(rdev, connector);
305 drm_modeset_unlock_all(dev);
306
307 drm_connector_register(connector);
308}
309
310static void radeon_dp_destroy_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
311 struct drm_connector *connector)
312{
313 struct radeon_connector *master = container_of(mgr, struct radeon_connector, mst_mgr);
314 struct drm_device *dev = master->base.dev;
315 struct radeon_device *rdev = dev->dev_private;
316
317 drm_connector_unregister(connector);
318 /* need to nuke the connector */
319 drm_modeset_lock_all(dev);
320 /* dpms off */
321 radeon_fb_remove_connector(rdev, connector);
322
323 drm_connector_cleanup(connector);
324 drm_modeset_unlock_all(dev);
325
326 kfree(connector);
327 DRM_DEBUG_KMS("\n");
328}
329
330static void radeon_dp_mst_hotplug(struct drm_dp_mst_topology_mgr *mgr)
331{
332 struct radeon_connector *master = container_of(mgr, struct radeon_connector, mst_mgr);
333 struct drm_device *dev = master->base.dev;
334
335 drm_kms_helper_hotplug_event(dev);
336}
337
338const struct drm_dp_mst_topology_cbs mst_cbs = {
339 .add_connector = radeon_dp_add_mst_connector,
340 .register_connector = radeon_dp_register_mst_connector,
341 .destroy_connector = radeon_dp_destroy_mst_connector,
342 .hotplug = radeon_dp_mst_hotplug,
343};
344
345static struct
346radeon_connector *radeon_mst_find_connector(struct drm_encoder *encoder)
347{
348 struct drm_device *dev = encoder->dev;
349 struct drm_connector *connector;
350
351 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
352 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
353 if (!connector->encoder)
354 continue;
355 if (!radeon_connector->is_mst_connector)
356 continue;
357
358 DRM_DEBUG_KMS("checking %p vs %p\n", connector->encoder, encoder);
359 if (connector->encoder == encoder)
360 return radeon_connector;
361 }
362 return NULL;
363}
364
365void radeon_dp_mst_prepare_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
366{
367 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
368 struct drm_device *dev = crtc->dev;
369 struct radeon_device *rdev = dev->dev_private;
370 struct radeon_encoder *radeon_encoder = to_radeon_encoder(radeon_crtc->encoder);
371 struct radeon_encoder_mst *mst_enc = radeon_encoder->enc_priv;
372 struct radeon_connector *radeon_connector = radeon_mst_find_connector(&radeon_encoder->base);
373 int dp_clock;
374 struct radeon_connector_atom_dig *dig_connector = mst_enc->connector->con_priv;
375
376 if (radeon_connector) {
377 radeon_connector->pixelclock_for_modeset = mode->clock;
378 if (radeon_connector->base.display_info.bpc)
379 radeon_crtc->bpc = radeon_connector->base.display_info.bpc;
380 else
381 radeon_crtc->bpc = 8;
382 }
383
384 DRM_DEBUG_KMS("dp_clock %p %d\n", dig_connector, dig_connector->dp_clock);
385 dp_clock = dig_connector->dp_clock;
386 radeon_crtc->ss_enabled =
387 radeon_atombios_get_asic_ss_info(rdev, &radeon_crtc->ss,
388 ASIC_INTERNAL_SS_ON_DP,
389 dp_clock);
390}
391
392static void
393radeon_mst_encoder_dpms(struct drm_encoder *encoder, int mode)
394{
395 struct drm_device *dev = encoder->dev;
396 struct radeon_device *rdev = dev->dev_private;
397 struct radeon_encoder *radeon_encoder, *primary;
398 struct radeon_encoder_mst *mst_enc;
399 struct radeon_encoder_atom_dig *dig_enc;
400 struct radeon_connector *radeon_connector;
401 struct drm_crtc *crtc;
402 struct radeon_crtc *radeon_crtc;
403 int ret, slots;
404 s64 fixed_pbn, fixed_pbn_per_slot, avg_time_slots_per_mtp;
405 if (!ASIC_IS_DCE5(rdev)) {
406 DRM_ERROR("got mst dpms on non-DCE5\n");
407 return;
408 }
409
410 radeon_connector = radeon_mst_find_connector(encoder);
411 if (!radeon_connector)
412 return;
413
414 radeon_encoder = to_radeon_encoder(encoder);
415
416 mst_enc = radeon_encoder->enc_priv;
417
418 primary = mst_enc->primary;
419
420 dig_enc = primary->enc_priv;
421
422 crtc = encoder->crtc;
423 DRM_DEBUG_KMS("got connector %d\n", dig_enc->active_mst_links);
424
425 switch (mode) {
426 case DRM_MODE_DPMS_ON:
427 dig_enc->active_mst_links++;
428
429 radeon_crtc = to_radeon_crtc(crtc);
430
431 if (dig_enc->active_mst_links == 1) {
432 mst_enc->fe = dig_enc->dig_encoder;
433 mst_enc->fe_from_be = true;
434 atombios_set_mst_encoder_crtc_source(encoder, mst_enc->fe);
435
436 atombios_dig_encoder_setup(&primary->base, ATOM_ENCODER_CMD_SETUP, 0);
437 atombios_dig_transmitter_setup2(&primary->base, ATOM_TRANSMITTER_ACTION_ENABLE,
438 0, 0, dig_enc->dig_encoder);
439
440 if (radeon_dp_needs_link_train(mst_enc->connector) ||
441 dig_enc->active_mst_links == 1) {
442 radeon_dp_link_train(&primary->base, &mst_enc->connector->base);
443 }
444
445 } else {
446 mst_enc->fe = radeon_atom_pick_dig_encoder(encoder, radeon_crtc->crtc_id);
447 if (mst_enc->fe == -1)
448 DRM_ERROR("failed to get frontend for dig encoder\n");
449 mst_enc->fe_from_be = false;
450 atombios_set_mst_encoder_crtc_source(encoder, mst_enc->fe);
451 }
452
453 DRM_DEBUG_KMS("dig encoder is %d %d %d\n", dig_enc->dig_encoder,
454 dig_enc->linkb, radeon_crtc->crtc_id);
455
456 ret = drm_dp_mst_allocate_vcpi(&radeon_connector->mst_port->mst_mgr,
457 radeon_connector->port,
458 mst_enc->pbn, &slots);
459 ret = drm_dp_update_payload_part1(&radeon_connector->mst_port->mst_mgr);
460
461 radeon_dp_mst_set_be_cntl(primary, mst_enc,
462 radeon_connector->mst_port->hpd.hpd, true);
463
464 mst_enc->enc_active = true;
465 radeon_dp_mst_update_stream_attribs(radeon_connector->mst_port, primary);
466
467 fixed_pbn = drm_int2fixp(mst_enc->pbn);
468 fixed_pbn_per_slot = drm_int2fixp(radeon_connector->mst_port->mst_mgr.pbn_div);
469 avg_time_slots_per_mtp = drm_fixp_div(fixed_pbn, fixed_pbn_per_slot);
470 radeon_dp_mst_set_vcp_size(radeon_encoder, avg_time_slots_per_mtp);
471
472 atombios_dig_encoder_setup2(&primary->base, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0,
473 mst_enc->fe);
474 ret = drm_dp_check_act_status(&radeon_connector->mst_port->mst_mgr);
475
476 ret = drm_dp_update_payload_part2(&radeon_connector->mst_port->mst_mgr);
477
478 break;
479 case DRM_MODE_DPMS_STANDBY:
480 case DRM_MODE_DPMS_SUSPEND:
481 case DRM_MODE_DPMS_OFF:
482 DRM_ERROR("DPMS OFF %d\n", dig_enc->active_mst_links);
483
484 if (!mst_enc->enc_active)
485 return;
486
487 drm_dp_mst_reset_vcpi_slots(&radeon_connector->mst_port->mst_mgr, mst_enc->port);
488 ret = drm_dp_update_payload_part1(&radeon_connector->mst_port->mst_mgr);
489
490 drm_dp_check_act_status(&radeon_connector->mst_port->mst_mgr);
491 /* and this can also fail */
492 drm_dp_update_payload_part2(&radeon_connector->mst_port->mst_mgr);
493
494 drm_dp_mst_deallocate_vcpi(&radeon_connector->mst_port->mst_mgr, mst_enc->port);
495
496 mst_enc->enc_active = false;
497 radeon_dp_mst_update_stream_attribs(radeon_connector->mst_port, primary);
498
499 radeon_dp_mst_set_be_cntl(primary, mst_enc,
500 radeon_connector->mst_port->hpd.hpd, false);
501 atombios_dig_encoder_setup2(&primary->base, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0,
502 mst_enc->fe);
503
504 if (!mst_enc->fe_from_be)
505 radeon_atom_release_dig_encoder(rdev, mst_enc->fe);
506
507 mst_enc->fe_from_be = false;
508 dig_enc->active_mst_links--;
509 if (dig_enc->active_mst_links == 0) {
510 /* drop link */
511 }
512
513 break;
514 }
515
516}
517
518static bool radeon_mst_mode_fixup(struct drm_encoder *encoder,
519 const struct drm_display_mode *mode,
520 struct drm_display_mode *adjusted_mode)
521{
522 struct radeon_encoder_mst *mst_enc;
523 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
524 struct radeon_connector_atom_dig *dig_connector;
525 int bpp = 24;
526
527 mst_enc = radeon_encoder->enc_priv;
528
529 mst_enc->pbn = drm_dp_calc_pbn_mode(adjusted_mode->clock, bpp);
530
531 mst_enc->primary->active_device = mst_enc->primary->devices & mst_enc->connector->devices;
532 DRM_DEBUG_KMS("setting active device to %08x from %08x %08x for encoder %d\n",
533 mst_enc->primary->active_device, mst_enc->primary->devices,
534 mst_enc->connector->devices, mst_enc->primary->base.encoder_type);
535
536
537 drm_mode_set_crtcinfo(adjusted_mode, 0);
538 dig_connector = mst_enc->connector->con_priv;
539 dig_connector->dp_lane_count = drm_dp_max_lane_count(dig_connector->dpcd);
540 dig_connector->dp_clock = drm_dp_max_link_rate(dig_connector->dpcd);
541 DRM_DEBUG_KMS("dig clock %p %d %d\n", dig_connector,
542 dig_connector->dp_lane_count, dig_connector->dp_clock);
543 return true;
544}
545
546static void radeon_mst_encoder_prepare(struct drm_encoder *encoder)
547{
548 struct radeon_connector *radeon_connector;
549 struct radeon_encoder *radeon_encoder, *primary;
550 struct radeon_encoder_mst *mst_enc;
551 struct radeon_encoder_atom_dig *dig_enc;
552
553 radeon_connector = radeon_mst_find_connector(encoder);
554 if (!radeon_connector) {
555 DRM_DEBUG_KMS("failed to find connector %p\n", encoder);
556 return;
557 }
558 radeon_encoder = to_radeon_encoder(encoder);
559
560 radeon_mst_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
561
562 mst_enc = radeon_encoder->enc_priv;
563
564 primary = mst_enc->primary;
565
566 dig_enc = primary->enc_priv;
567
568 mst_enc->port = radeon_connector->port;
569
570 if (dig_enc->dig_encoder == -1) {
571 dig_enc->dig_encoder = radeon_atom_pick_dig_encoder(&primary->base, -1);
572 primary->offset = radeon_atom_set_enc_offset(dig_enc->dig_encoder);
573 atombios_set_mst_encoder_crtc_source(encoder, dig_enc->dig_encoder);
574
575
576 }
577 DRM_DEBUG_KMS("%d %d\n", dig_enc->dig_encoder, primary->offset);
578}
579
580static void
581radeon_mst_encoder_mode_set(struct drm_encoder *encoder,
582 struct drm_display_mode *mode,
583 struct drm_display_mode *adjusted_mode)
584{
585 DRM_DEBUG_KMS("\n");
586}
587
588static void radeon_mst_encoder_commit(struct drm_encoder *encoder)
589{
590 radeon_mst_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
591 DRM_DEBUG_KMS("\n");
592}
593
594static const struct drm_encoder_helper_funcs radeon_mst_helper_funcs = {
595 .dpms = radeon_mst_encoder_dpms,
596 .mode_fixup = radeon_mst_mode_fixup,
597 .prepare = radeon_mst_encoder_prepare,
598 .mode_set = radeon_mst_encoder_mode_set,
599 .commit = radeon_mst_encoder_commit,
600};
601
602static void radeon_dp_mst_encoder_destroy(struct drm_encoder *encoder)
603{
604 drm_encoder_cleanup(encoder);
605 kfree(encoder);
606}
607
608static const struct drm_encoder_funcs radeon_dp_mst_enc_funcs = {
609 .destroy = radeon_dp_mst_encoder_destroy,
610};
611
612static struct radeon_encoder *
613radeon_dp_create_fake_mst_encoder(struct radeon_connector *connector)
614{
615 struct drm_device *dev = connector->base.dev;
616 struct radeon_device *rdev = dev->dev_private;
617 struct radeon_encoder *radeon_encoder;
618 struct radeon_encoder_mst *mst_enc;
619 struct drm_encoder *encoder;
620 const struct drm_connector_helper_funcs *connector_funcs = connector->base.helper_private;
621 struct drm_encoder *enc_master = connector_funcs->best_encoder(&connector->base);
622
623 DRM_DEBUG_KMS("enc master is %p\n", enc_master);
624 radeon_encoder = kzalloc(sizeof(*radeon_encoder), GFP_KERNEL);
625 if (!radeon_encoder)
626 return NULL;
627
628 radeon_encoder->enc_priv = kzalloc(sizeof(*mst_enc), GFP_KERNEL);
629 if (!radeon_encoder->enc_priv) {
630 kfree(radeon_encoder);
631 return NULL;
632 }
633 encoder = &radeon_encoder->base;
634 switch (rdev->num_crtc) {
635 case 1:
636 encoder->possible_crtcs = 0x1;
637 break;
638 case 2:
639 default:
640 encoder->possible_crtcs = 0x3;
641 break;
642 case 4:
643 encoder->possible_crtcs = 0xf;
644 break;
645 case 6:
646 encoder->possible_crtcs = 0x3f;
647 break;
648 }
649
650 drm_encoder_init(dev, &radeon_encoder->base, &radeon_dp_mst_enc_funcs,
651 DRM_MODE_ENCODER_DPMST, NULL);
652 drm_encoder_helper_add(encoder, &radeon_mst_helper_funcs);
653
654 mst_enc = radeon_encoder->enc_priv;
655 mst_enc->connector = connector;
656 mst_enc->primary = to_radeon_encoder(enc_master);
657 radeon_encoder->is_mst_encoder = true;
658 return radeon_encoder;
659}
660
661int
662radeon_dp_mst_init(struct radeon_connector *radeon_connector)
663{
664 struct drm_device *dev = radeon_connector->base.dev;
665
666 if (!radeon_connector->ddc_bus->has_aux)
667 return 0;
668
669 radeon_connector->mst_mgr.cbs = &mst_cbs;
670 return drm_dp_mst_topology_mgr_init(&radeon_connector->mst_mgr, dev->dev,
671 &radeon_connector->ddc_bus->aux, 16, 6,
672 radeon_connector->base.base.id);
673}
674
675int
676radeon_dp_mst_probe(struct radeon_connector *radeon_connector)
677{
678 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
679 struct drm_device *dev = radeon_connector->base.dev;
680 struct radeon_device *rdev = dev->dev_private;
681 int ret;
682 u8 msg[1];
683
684 if (!radeon_mst)
685 return 0;
686
687 if (!ASIC_IS_DCE5(rdev))
688 return 0;
689
690 if (dig_connector->dpcd[DP_DPCD_REV] < 0x12)
691 return 0;
692
693 ret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_MSTM_CAP, msg,
694 1);
695 if (ret) {
696 if (msg[0] & DP_MST_CAP) {
697 DRM_DEBUG_KMS("Sink is MST capable\n");
698 dig_connector->is_mst = true;
699 } else {
700 DRM_DEBUG_KMS("Sink is not MST capable\n");
701 dig_connector->is_mst = false;
702 }
703
704 }
705 drm_dp_mst_topology_mgr_set_mst(&radeon_connector->mst_mgr,
706 dig_connector->is_mst);
707 return dig_connector->is_mst;
708}
709
710int
711radeon_dp_mst_check_status(struct radeon_connector *radeon_connector)
712{
713 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
714 int retry;
715
716 if (dig_connector->is_mst) {
717 u8 esi[16] = { 0 };
718 int dret;
719 int ret = 0;
720 bool handled;
721
722 dret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux,
723 DP_SINK_COUNT_ESI, esi, 8);
724go_again:
725 if (dret == 8) {
726 DRM_DEBUG_KMS("got esi %02x %02x %02x\n", esi[0], esi[1], esi[2]);
727 ret = drm_dp_mst_hpd_irq(&radeon_connector->mst_mgr, esi, &handled);
728
729 if (handled) {
730 for (retry = 0; retry < 3; retry++) {
731 int wret;
732 wret = drm_dp_dpcd_write(&radeon_connector->ddc_bus->aux,
733 DP_SINK_COUNT_ESI + 1, &esi[1], 3);
734 if (wret == 3)
735 break;
736 }
737
738 dret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux,
739 DP_SINK_COUNT_ESI, esi, 8);
740 if (dret == 8) {
741 DRM_DEBUG_KMS("got esi2 %02x %02x %02x\n", esi[0], esi[1], esi[2]);
742 goto go_again;
743 }
744 } else
745 ret = 0;
746
747 return ret;
748 } else {
749 DRM_DEBUG_KMS("failed to get ESI - device may have failed %d\n", ret);
750 dig_connector->is_mst = false;
751 drm_dp_mst_topology_mgr_set_mst(&radeon_connector->mst_mgr,
752 dig_connector->is_mst);
753 /* send a hotplug event */
754 }
755 }
756 return -EINVAL;
757}
758
759#if defined(CONFIG_DEBUG_FS)
760
761static int radeon_debugfs_mst_info(struct seq_file *m, void *data)
762{
763 struct drm_info_node *node = (struct drm_info_node *)m->private;
764 struct drm_device *dev = node->minor->dev;
765 struct drm_connector *connector;
766 struct radeon_connector *radeon_connector;
767 struct radeon_connector_atom_dig *dig_connector;
768 int i;
769
770 drm_modeset_lock_all(dev);
771 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
772 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
773 continue;
774
775 radeon_connector = to_radeon_connector(connector);
776 dig_connector = radeon_connector->con_priv;
777 if (radeon_connector->is_mst_connector)
778 continue;
779 if (!dig_connector->is_mst)
780 continue;
781 drm_dp_mst_dump_topology(m, &radeon_connector->mst_mgr);
782
783 for (i = 0; i < radeon_connector->enabled_attribs; i++)
784 seq_printf(m, "attrib %d: %d %d\n", i,
785 radeon_connector->cur_stream_attribs[i].fe,
786 radeon_connector->cur_stream_attribs[i].slots);
787 }
788 drm_modeset_unlock_all(dev);
789 return 0;
790}
791
792static struct drm_info_list radeon_debugfs_mst_list[] = {
793 {"radeon_mst_info", &radeon_debugfs_mst_info, 0, NULL},
794};
795#endif
796
797int radeon_mst_debugfs_init(struct radeon_device *rdev)
798{
799#if defined(CONFIG_DEBUG_FS)
800 return radeon_debugfs_add_files(rdev, radeon_debugfs_mst_list, 1);
801#endif
802 return 0;
803}