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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2013 Red Hat
4 * Author: Rob Clark <robdclark@gmail.com>
5 */
6
7#include "msm_gpu.h"
8#include "msm_gem.h"
9#include "msm_mmu.h"
10#include "msm_fence.h"
11#include "msm_gpu_trace.h"
12#include "adreno/adreno_gpu.h"
13
14#include <generated/utsrelease.h>
15#include <linux/string_helpers.h>
16#include <linux/devfreq.h>
17#include <linux/devcoredump.h>
18#include <linux/sched/task.h>
19
20/*
21 * Power Management:
22 */
23
24static int msm_devfreq_target(struct device *dev, unsigned long *freq,
25 u32 flags)
26{
27 struct msm_gpu *gpu = platform_get_drvdata(to_platform_device(dev));
28 struct dev_pm_opp *opp;
29
30 opp = devfreq_recommended_opp(dev, freq, flags);
31
32 if (IS_ERR(opp))
33 return PTR_ERR(opp);
34
35 if (gpu->funcs->gpu_set_freq)
36 gpu->funcs->gpu_set_freq(gpu, opp);
37 else
38 clk_set_rate(gpu->core_clk, *freq);
39
40 dev_pm_opp_put(opp);
41
42 return 0;
43}
44
45static int msm_devfreq_get_dev_status(struct device *dev,
46 struct devfreq_dev_status *status)
47{
48 struct msm_gpu *gpu = platform_get_drvdata(to_platform_device(dev));
49 ktime_t time;
50
51 if (gpu->funcs->gpu_get_freq)
52 status->current_frequency = gpu->funcs->gpu_get_freq(gpu);
53 else
54 status->current_frequency = clk_get_rate(gpu->core_clk);
55
56 status->busy_time = gpu->funcs->gpu_busy(gpu);
57
58 time = ktime_get();
59 status->total_time = ktime_us_delta(time, gpu->devfreq.time);
60 gpu->devfreq.time = time;
61
62 return 0;
63}
64
65static int msm_devfreq_get_cur_freq(struct device *dev, unsigned long *freq)
66{
67 struct msm_gpu *gpu = platform_get_drvdata(to_platform_device(dev));
68
69 if (gpu->funcs->gpu_get_freq)
70 *freq = gpu->funcs->gpu_get_freq(gpu);
71 else
72 *freq = clk_get_rate(gpu->core_clk);
73
74 return 0;
75}
76
77static struct devfreq_dev_profile msm_devfreq_profile = {
78 .polling_ms = 10,
79 .target = msm_devfreq_target,
80 .get_dev_status = msm_devfreq_get_dev_status,
81 .get_cur_freq = msm_devfreq_get_cur_freq,
82};
83
84static void msm_devfreq_init(struct msm_gpu *gpu)
85{
86 /* We need target support to do devfreq */
87 if (!gpu->funcs->gpu_busy)
88 return;
89
90 msm_devfreq_profile.initial_freq = gpu->fast_rate;
91
92 /*
93 * Don't set the freq_table or max_state and let devfreq build the table
94 * from OPP
95 * After a deferred probe, these may have be left to non-zero values,
96 * so set them back to zero before creating the devfreq device
97 */
98 msm_devfreq_profile.freq_table = NULL;
99 msm_devfreq_profile.max_state = 0;
100
101 gpu->devfreq.devfreq = devm_devfreq_add_device(&gpu->pdev->dev,
102 &msm_devfreq_profile, DEVFREQ_GOV_SIMPLE_ONDEMAND,
103 NULL);
104
105 if (IS_ERR(gpu->devfreq.devfreq)) {
106 DRM_DEV_ERROR(&gpu->pdev->dev, "Couldn't initialize GPU devfreq\n");
107 gpu->devfreq.devfreq = NULL;
108 }
109
110 devfreq_suspend_device(gpu->devfreq.devfreq);
111}
112
113static int enable_pwrrail(struct msm_gpu *gpu)
114{
115 struct drm_device *dev = gpu->dev;
116 int ret = 0;
117
118 if (gpu->gpu_reg) {
119 ret = regulator_enable(gpu->gpu_reg);
120 if (ret) {
121 DRM_DEV_ERROR(dev->dev, "failed to enable 'gpu_reg': %d\n", ret);
122 return ret;
123 }
124 }
125
126 if (gpu->gpu_cx) {
127 ret = regulator_enable(gpu->gpu_cx);
128 if (ret) {
129 DRM_DEV_ERROR(dev->dev, "failed to enable 'gpu_cx': %d\n", ret);
130 return ret;
131 }
132 }
133
134 return 0;
135}
136
137static int disable_pwrrail(struct msm_gpu *gpu)
138{
139 if (gpu->gpu_cx)
140 regulator_disable(gpu->gpu_cx);
141 if (gpu->gpu_reg)
142 regulator_disable(gpu->gpu_reg);
143 return 0;
144}
145
146static int enable_clk(struct msm_gpu *gpu)
147{
148 if (gpu->core_clk && gpu->fast_rate)
149 clk_set_rate(gpu->core_clk, gpu->fast_rate);
150
151 /* Set the RBBM timer rate to 19.2Mhz */
152 if (gpu->rbbmtimer_clk)
153 clk_set_rate(gpu->rbbmtimer_clk, 19200000);
154
155 return clk_bulk_prepare_enable(gpu->nr_clocks, gpu->grp_clks);
156}
157
158static int disable_clk(struct msm_gpu *gpu)
159{
160 clk_bulk_disable_unprepare(gpu->nr_clocks, gpu->grp_clks);
161
162 /*
163 * Set the clock to a deliberately low rate. On older targets the clock
164 * speed had to be non zero to avoid problems. On newer targets this
165 * will be rounded down to zero anyway so it all works out.
166 */
167 if (gpu->core_clk)
168 clk_set_rate(gpu->core_clk, 27000000);
169
170 if (gpu->rbbmtimer_clk)
171 clk_set_rate(gpu->rbbmtimer_clk, 0);
172
173 return 0;
174}
175
176static int enable_axi(struct msm_gpu *gpu)
177{
178 if (gpu->ebi1_clk)
179 clk_prepare_enable(gpu->ebi1_clk);
180 return 0;
181}
182
183static int disable_axi(struct msm_gpu *gpu)
184{
185 if (gpu->ebi1_clk)
186 clk_disable_unprepare(gpu->ebi1_clk);
187 return 0;
188}
189
190void msm_gpu_resume_devfreq(struct msm_gpu *gpu)
191{
192 gpu->devfreq.busy_cycles = 0;
193 gpu->devfreq.time = ktime_get();
194
195 devfreq_resume_device(gpu->devfreq.devfreq);
196}
197
198int msm_gpu_pm_resume(struct msm_gpu *gpu)
199{
200 int ret;
201
202 DBG("%s", gpu->name);
203
204 ret = enable_pwrrail(gpu);
205 if (ret)
206 return ret;
207
208 ret = enable_clk(gpu);
209 if (ret)
210 return ret;
211
212 ret = enable_axi(gpu);
213 if (ret)
214 return ret;
215
216 msm_gpu_resume_devfreq(gpu);
217
218 gpu->needs_hw_init = true;
219
220 return 0;
221}
222
223int msm_gpu_pm_suspend(struct msm_gpu *gpu)
224{
225 int ret;
226
227 DBG("%s", gpu->name);
228
229 devfreq_suspend_device(gpu->devfreq.devfreq);
230
231 ret = disable_axi(gpu);
232 if (ret)
233 return ret;
234
235 ret = disable_clk(gpu);
236 if (ret)
237 return ret;
238
239 ret = disable_pwrrail(gpu);
240 if (ret)
241 return ret;
242
243 return 0;
244}
245
246int msm_gpu_hw_init(struct msm_gpu *gpu)
247{
248 int ret;
249
250 WARN_ON(!mutex_is_locked(&gpu->dev->struct_mutex));
251
252 if (!gpu->needs_hw_init)
253 return 0;
254
255 disable_irq(gpu->irq);
256 ret = gpu->funcs->hw_init(gpu);
257 if (!ret)
258 gpu->needs_hw_init = false;
259 enable_irq(gpu->irq);
260
261 return ret;
262}
263
264#ifdef CONFIG_DEV_COREDUMP
265static ssize_t msm_gpu_devcoredump_read(char *buffer, loff_t offset,
266 size_t count, void *data, size_t datalen)
267{
268 struct msm_gpu *gpu = data;
269 struct drm_print_iterator iter;
270 struct drm_printer p;
271 struct msm_gpu_state *state;
272
273 state = msm_gpu_crashstate_get(gpu);
274 if (!state)
275 return 0;
276
277 iter.data = buffer;
278 iter.offset = 0;
279 iter.start = offset;
280 iter.remain = count;
281
282 p = drm_coredump_printer(&iter);
283
284 drm_printf(&p, "---\n");
285 drm_printf(&p, "kernel: " UTS_RELEASE "\n");
286 drm_printf(&p, "module: " KBUILD_MODNAME "\n");
287 drm_printf(&p, "time: %lld.%09ld\n",
288 state->time.tv_sec, state->time.tv_nsec);
289 if (state->comm)
290 drm_printf(&p, "comm: %s\n", state->comm);
291 if (state->cmd)
292 drm_printf(&p, "cmdline: %s\n", state->cmd);
293
294 gpu->funcs->show(gpu, state, &p);
295
296 msm_gpu_crashstate_put(gpu);
297
298 return count - iter.remain;
299}
300
301static void msm_gpu_devcoredump_free(void *data)
302{
303 struct msm_gpu *gpu = data;
304
305 msm_gpu_crashstate_put(gpu);
306}
307
308static void msm_gpu_crashstate_get_bo(struct msm_gpu_state *state,
309 struct msm_gem_object *obj, u64 iova, u32 flags)
310{
311 struct msm_gpu_state_bo *state_bo = &state->bos[state->nr_bos];
312
313 /* Don't record write only objects */
314 state_bo->size = obj->base.size;
315 state_bo->iova = iova;
316
317 /* Only store data for non imported buffer objects marked for read */
318 if ((flags & MSM_SUBMIT_BO_READ) && !obj->base.import_attach) {
319 void *ptr;
320
321 state_bo->data = kvmalloc(obj->base.size, GFP_KERNEL);
322 if (!state_bo->data)
323 goto out;
324
325 ptr = msm_gem_get_vaddr_active(&obj->base);
326 if (IS_ERR(ptr)) {
327 kvfree(state_bo->data);
328 state_bo->data = NULL;
329 goto out;
330 }
331
332 memcpy(state_bo->data, ptr, obj->base.size);
333 msm_gem_put_vaddr(&obj->base);
334 }
335out:
336 state->nr_bos++;
337}
338
339static void msm_gpu_crashstate_capture(struct msm_gpu *gpu,
340 struct msm_gem_submit *submit, char *comm, char *cmd)
341{
342 struct msm_gpu_state *state;
343
344 /* Check if the target supports capturing crash state */
345 if (!gpu->funcs->gpu_state_get)
346 return;
347
348 /* Only save one crash state at a time */
349 if (gpu->crashstate)
350 return;
351
352 state = gpu->funcs->gpu_state_get(gpu);
353 if (IS_ERR_OR_NULL(state))
354 return;
355
356 /* Fill in the additional crash state information */
357 state->comm = kstrdup(comm, GFP_KERNEL);
358 state->cmd = kstrdup(cmd, GFP_KERNEL);
359
360 if (submit) {
361 int i, nr = 0;
362
363 /* count # of buffers to dump: */
364 for (i = 0; i < submit->nr_bos; i++)
365 if (should_dump(submit, i))
366 nr++;
367 /* always dump cmd bo's, but don't double count them: */
368 for (i = 0; i < submit->nr_cmds; i++)
369 if (!should_dump(submit, submit->cmd[i].idx))
370 nr++;
371
372 state->bos = kcalloc(nr,
373 sizeof(struct msm_gpu_state_bo), GFP_KERNEL);
374
375 for (i = 0; i < submit->nr_bos; i++) {
376 if (should_dump(submit, i)) {
377 msm_gpu_crashstate_get_bo(state, submit->bos[i].obj,
378 submit->bos[i].iova, submit->bos[i].flags);
379 }
380 }
381
382 for (i = 0; state->bos && i < submit->nr_cmds; i++) {
383 int idx = submit->cmd[i].idx;
384
385 if (!should_dump(submit, submit->cmd[i].idx)) {
386 msm_gpu_crashstate_get_bo(state, submit->bos[idx].obj,
387 submit->bos[idx].iova, submit->bos[idx].flags);
388 }
389 }
390 }
391
392 /* Set the active crash state to be dumped on failure */
393 gpu->crashstate = state;
394
395 /* FIXME: Release the crashstate if this errors out? */
396 dev_coredumpm(gpu->dev->dev, THIS_MODULE, gpu, 0, GFP_KERNEL,
397 msm_gpu_devcoredump_read, msm_gpu_devcoredump_free);
398}
399#else
400static void msm_gpu_crashstate_capture(struct msm_gpu *gpu,
401 struct msm_gem_submit *submit, char *comm, char *cmd)
402{
403}
404#endif
405
406/*
407 * Hangcheck detection for locked gpu:
408 */
409
410static void update_fences(struct msm_gpu *gpu, struct msm_ringbuffer *ring,
411 uint32_t fence)
412{
413 struct msm_gem_submit *submit;
414
415 list_for_each_entry(submit, &ring->submits, node) {
416 if (submit->seqno > fence)
417 break;
418
419 msm_update_fence(submit->ring->fctx,
420 submit->fence->seqno);
421 }
422}
423
424static struct msm_gem_submit *
425find_submit(struct msm_ringbuffer *ring, uint32_t fence)
426{
427 struct msm_gem_submit *submit;
428
429 WARN_ON(!mutex_is_locked(&ring->gpu->dev->struct_mutex));
430
431 list_for_each_entry(submit, &ring->submits, node)
432 if (submit->seqno == fence)
433 return submit;
434
435 return NULL;
436}
437
438static void retire_submits(struct msm_gpu *gpu);
439
440static void recover_worker(struct work_struct *work)
441{
442 struct msm_gpu *gpu = container_of(work, struct msm_gpu, recover_work);
443 struct drm_device *dev = gpu->dev;
444 struct msm_drm_private *priv = dev->dev_private;
445 struct msm_gem_submit *submit;
446 struct msm_ringbuffer *cur_ring = gpu->funcs->active_ring(gpu);
447 char *comm = NULL, *cmd = NULL;
448 int i;
449
450 mutex_lock(&dev->struct_mutex);
451
452 DRM_DEV_ERROR(dev->dev, "%s: hangcheck recover!\n", gpu->name);
453
454 submit = find_submit(cur_ring, cur_ring->memptrs->fence + 1);
455 if (submit) {
456 struct task_struct *task;
457
458 /* Increment the fault counts */
459 gpu->global_faults++;
460 submit->queue->faults++;
461
462 task = get_pid_task(submit->pid, PIDTYPE_PID);
463 if (task) {
464 comm = kstrdup(task->comm, GFP_KERNEL);
465 cmd = kstrdup_quotable_cmdline(task, GFP_KERNEL);
466 put_task_struct(task);
467 }
468
469 if (comm && cmd) {
470 DRM_DEV_ERROR(dev->dev, "%s: offending task: %s (%s)\n",
471 gpu->name, comm, cmd);
472
473 msm_rd_dump_submit(priv->hangrd, submit,
474 "offending task: %s (%s)", comm, cmd);
475 } else
476 msm_rd_dump_submit(priv->hangrd, submit, NULL);
477 }
478
479 /* Record the crash state */
480 pm_runtime_get_sync(&gpu->pdev->dev);
481 msm_gpu_crashstate_capture(gpu, submit, comm, cmd);
482 pm_runtime_put_sync(&gpu->pdev->dev);
483
484 kfree(cmd);
485 kfree(comm);
486
487 /*
488 * Update all the rings with the latest and greatest fence.. this
489 * needs to happen after msm_rd_dump_submit() to ensure that the
490 * bo's referenced by the offending submit are still around.
491 */
492 for (i = 0; i < gpu->nr_rings; i++) {
493 struct msm_ringbuffer *ring = gpu->rb[i];
494
495 uint32_t fence = ring->memptrs->fence;
496
497 /*
498 * For the current (faulting?) ring/submit advance the fence by
499 * one more to clear the faulting submit
500 */
501 if (ring == cur_ring)
502 fence++;
503
504 update_fences(gpu, ring, fence);
505 }
506
507 if (msm_gpu_active(gpu)) {
508 /* retire completed submits, plus the one that hung: */
509 retire_submits(gpu);
510
511 pm_runtime_get_sync(&gpu->pdev->dev);
512 gpu->funcs->recover(gpu);
513 pm_runtime_put_sync(&gpu->pdev->dev);
514
515 /*
516 * Replay all remaining submits starting with highest priority
517 * ring
518 */
519 for (i = 0; i < gpu->nr_rings; i++) {
520 struct msm_ringbuffer *ring = gpu->rb[i];
521
522 list_for_each_entry(submit, &ring->submits, node)
523 gpu->funcs->submit(gpu, submit, NULL);
524 }
525 }
526
527 mutex_unlock(&dev->struct_mutex);
528
529 msm_gpu_retire(gpu);
530}
531
532static void hangcheck_timer_reset(struct msm_gpu *gpu)
533{
534 DBG("%s", gpu->name);
535 mod_timer(&gpu->hangcheck_timer,
536 round_jiffies_up(jiffies + DRM_MSM_HANGCHECK_JIFFIES));
537}
538
539static void hangcheck_handler(struct timer_list *t)
540{
541 struct msm_gpu *gpu = from_timer(gpu, t, hangcheck_timer);
542 struct drm_device *dev = gpu->dev;
543 struct msm_drm_private *priv = dev->dev_private;
544 struct msm_ringbuffer *ring = gpu->funcs->active_ring(gpu);
545 uint32_t fence = ring->memptrs->fence;
546
547 if (fence != ring->hangcheck_fence) {
548 /* some progress has been made.. ya! */
549 ring->hangcheck_fence = fence;
550 } else if (fence < ring->seqno) {
551 /* no progress and not done.. hung! */
552 ring->hangcheck_fence = fence;
553 DRM_DEV_ERROR(dev->dev, "%s: hangcheck detected gpu lockup rb %d!\n",
554 gpu->name, ring->id);
555 DRM_DEV_ERROR(dev->dev, "%s: completed fence: %u\n",
556 gpu->name, fence);
557 DRM_DEV_ERROR(dev->dev, "%s: submitted fence: %u\n",
558 gpu->name, ring->seqno);
559
560 queue_work(priv->wq, &gpu->recover_work);
561 }
562
563 /* if still more pending work, reset the hangcheck timer: */
564 if (ring->seqno > ring->hangcheck_fence)
565 hangcheck_timer_reset(gpu);
566
567 /* workaround for missing irq: */
568 queue_work(priv->wq, &gpu->retire_work);
569}
570
571/*
572 * Performance Counters:
573 */
574
575/* called under perf_lock */
576static int update_hw_cntrs(struct msm_gpu *gpu, uint32_t ncntrs, uint32_t *cntrs)
577{
578 uint32_t current_cntrs[ARRAY_SIZE(gpu->last_cntrs)];
579 int i, n = min(ncntrs, gpu->num_perfcntrs);
580
581 /* read current values: */
582 for (i = 0; i < gpu->num_perfcntrs; i++)
583 current_cntrs[i] = gpu_read(gpu, gpu->perfcntrs[i].sample_reg);
584
585 /* update cntrs: */
586 for (i = 0; i < n; i++)
587 cntrs[i] = current_cntrs[i] - gpu->last_cntrs[i];
588
589 /* save current values: */
590 for (i = 0; i < gpu->num_perfcntrs; i++)
591 gpu->last_cntrs[i] = current_cntrs[i];
592
593 return n;
594}
595
596static void update_sw_cntrs(struct msm_gpu *gpu)
597{
598 ktime_t time;
599 uint32_t elapsed;
600 unsigned long flags;
601
602 spin_lock_irqsave(&gpu->perf_lock, flags);
603 if (!gpu->perfcntr_active)
604 goto out;
605
606 time = ktime_get();
607 elapsed = ktime_to_us(ktime_sub(time, gpu->last_sample.time));
608
609 gpu->totaltime += elapsed;
610 if (gpu->last_sample.active)
611 gpu->activetime += elapsed;
612
613 gpu->last_sample.active = msm_gpu_active(gpu);
614 gpu->last_sample.time = time;
615
616out:
617 spin_unlock_irqrestore(&gpu->perf_lock, flags);
618}
619
620void msm_gpu_perfcntr_start(struct msm_gpu *gpu)
621{
622 unsigned long flags;
623
624 pm_runtime_get_sync(&gpu->pdev->dev);
625
626 spin_lock_irqsave(&gpu->perf_lock, flags);
627 /* we could dynamically enable/disable perfcntr registers too.. */
628 gpu->last_sample.active = msm_gpu_active(gpu);
629 gpu->last_sample.time = ktime_get();
630 gpu->activetime = gpu->totaltime = 0;
631 gpu->perfcntr_active = true;
632 update_hw_cntrs(gpu, 0, NULL);
633 spin_unlock_irqrestore(&gpu->perf_lock, flags);
634}
635
636void msm_gpu_perfcntr_stop(struct msm_gpu *gpu)
637{
638 gpu->perfcntr_active = false;
639 pm_runtime_put_sync(&gpu->pdev->dev);
640}
641
642/* returns -errno or # of cntrs sampled */
643int msm_gpu_perfcntr_sample(struct msm_gpu *gpu, uint32_t *activetime,
644 uint32_t *totaltime, uint32_t ncntrs, uint32_t *cntrs)
645{
646 unsigned long flags;
647 int ret;
648
649 spin_lock_irqsave(&gpu->perf_lock, flags);
650
651 if (!gpu->perfcntr_active) {
652 ret = -EINVAL;
653 goto out;
654 }
655
656 *activetime = gpu->activetime;
657 *totaltime = gpu->totaltime;
658
659 gpu->activetime = gpu->totaltime = 0;
660
661 ret = update_hw_cntrs(gpu, ncntrs, cntrs);
662
663out:
664 spin_unlock_irqrestore(&gpu->perf_lock, flags);
665
666 return ret;
667}
668
669/*
670 * Cmdstream submission/retirement:
671 */
672
673static void retire_submit(struct msm_gpu *gpu, struct msm_ringbuffer *ring,
674 struct msm_gem_submit *submit)
675{
676 int index = submit->seqno % MSM_GPU_SUBMIT_STATS_COUNT;
677 volatile struct msm_gpu_submit_stats *stats;
678 u64 elapsed, clock = 0;
679 int i;
680
681 stats = &ring->memptrs->stats[index];
682 /* Convert 19.2Mhz alwayson ticks to nanoseconds for elapsed time */
683 elapsed = (stats->alwayson_end - stats->alwayson_start) * 10000;
684 do_div(elapsed, 192);
685
686 /* Calculate the clock frequency from the number of CP cycles */
687 if (elapsed) {
688 clock = (stats->cpcycles_end - stats->cpcycles_start) * 1000;
689 do_div(clock, elapsed);
690 }
691
692 trace_msm_gpu_submit_retired(submit, elapsed, clock,
693 stats->alwayson_start, stats->alwayson_end);
694
695 for (i = 0; i < submit->nr_bos; i++) {
696 struct msm_gem_object *msm_obj = submit->bos[i].obj;
697 /* move to inactive: */
698 msm_gem_move_to_inactive(&msm_obj->base);
699 msm_gem_unpin_iova(&msm_obj->base, submit->aspace);
700 drm_gem_object_put_locked(&msm_obj->base);
701 }
702
703 pm_runtime_mark_last_busy(&gpu->pdev->dev);
704 pm_runtime_put_autosuspend(&gpu->pdev->dev);
705 msm_gem_submit_free(submit);
706}
707
708static void retire_submits(struct msm_gpu *gpu)
709{
710 struct drm_device *dev = gpu->dev;
711 struct msm_gem_submit *submit, *tmp;
712 int i;
713
714 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
715
716 /* Retire the commits starting with highest priority */
717 for (i = 0; i < gpu->nr_rings; i++) {
718 struct msm_ringbuffer *ring = gpu->rb[i];
719
720 list_for_each_entry_safe(submit, tmp, &ring->submits, node) {
721 if (dma_fence_is_signaled(submit->fence))
722 retire_submit(gpu, ring, submit);
723 }
724 }
725}
726
727static void retire_worker(struct work_struct *work)
728{
729 struct msm_gpu *gpu = container_of(work, struct msm_gpu, retire_work);
730 struct drm_device *dev = gpu->dev;
731 int i;
732
733 for (i = 0; i < gpu->nr_rings; i++)
734 update_fences(gpu, gpu->rb[i], gpu->rb[i]->memptrs->fence);
735
736 mutex_lock(&dev->struct_mutex);
737 retire_submits(gpu);
738 mutex_unlock(&dev->struct_mutex);
739}
740
741/* call from irq handler to schedule work to retire bo's */
742void msm_gpu_retire(struct msm_gpu *gpu)
743{
744 struct msm_drm_private *priv = gpu->dev->dev_private;
745 queue_work(priv->wq, &gpu->retire_work);
746 update_sw_cntrs(gpu);
747}
748
749/* add bo's to gpu's ring, and kick gpu: */
750void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
751 struct msm_file_private *ctx)
752{
753 struct drm_device *dev = gpu->dev;
754 struct msm_drm_private *priv = dev->dev_private;
755 struct msm_ringbuffer *ring = submit->ring;
756 int i;
757
758 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
759
760 pm_runtime_get_sync(&gpu->pdev->dev);
761
762 msm_gpu_hw_init(gpu);
763
764 submit->seqno = ++ring->seqno;
765
766 list_add_tail(&submit->node, &ring->submits);
767
768 msm_rd_dump_submit(priv->rd, submit, NULL);
769
770 update_sw_cntrs(gpu);
771
772 for (i = 0; i < submit->nr_bos; i++) {
773 struct msm_gem_object *msm_obj = submit->bos[i].obj;
774 uint64_t iova;
775
776 /* can't happen yet.. but when we add 2d support we'll have
777 * to deal w/ cross-ring synchronization:
778 */
779 WARN_ON(is_active(msm_obj) && (msm_obj->gpu != gpu));
780
781 /* submit takes a reference to the bo and iova until retired: */
782 drm_gem_object_get(&msm_obj->base);
783 msm_gem_get_and_pin_iova(&msm_obj->base, submit->aspace, &iova);
784
785 if (submit->bos[i].flags & MSM_SUBMIT_BO_WRITE)
786 msm_gem_move_to_active(&msm_obj->base, gpu, true, submit->fence);
787 else if (submit->bos[i].flags & MSM_SUBMIT_BO_READ)
788 msm_gem_move_to_active(&msm_obj->base, gpu, false, submit->fence);
789 }
790
791 gpu->funcs->submit(gpu, submit, ctx);
792 priv->lastctx = ctx;
793
794 hangcheck_timer_reset(gpu);
795}
796
797/*
798 * Init/Cleanup:
799 */
800
801static irqreturn_t irq_handler(int irq, void *data)
802{
803 struct msm_gpu *gpu = data;
804 return gpu->funcs->irq(gpu);
805}
806
807static int get_clocks(struct platform_device *pdev, struct msm_gpu *gpu)
808{
809 int ret = devm_clk_bulk_get_all(&pdev->dev, &gpu->grp_clks);
810
811 if (ret < 1) {
812 gpu->nr_clocks = 0;
813 return ret;
814 }
815
816 gpu->nr_clocks = ret;
817
818 gpu->core_clk = msm_clk_bulk_get_clock(gpu->grp_clks,
819 gpu->nr_clocks, "core");
820
821 gpu->rbbmtimer_clk = msm_clk_bulk_get_clock(gpu->grp_clks,
822 gpu->nr_clocks, "rbbmtimer");
823
824 return 0;
825}
826
827int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
828 struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs,
829 const char *name, struct msm_gpu_config *config)
830{
831 int i, ret, nr_rings = config->nr_rings;
832 void *memptrs;
833 uint64_t memptrs_iova;
834
835 if (WARN_ON(gpu->num_perfcntrs > ARRAY_SIZE(gpu->last_cntrs)))
836 gpu->num_perfcntrs = ARRAY_SIZE(gpu->last_cntrs);
837
838 gpu->dev = drm;
839 gpu->funcs = funcs;
840 gpu->name = name;
841
842 INIT_LIST_HEAD(&gpu->active_list);
843 INIT_WORK(&gpu->retire_work, retire_worker);
844 INIT_WORK(&gpu->recover_work, recover_worker);
845
846
847 timer_setup(&gpu->hangcheck_timer, hangcheck_handler, 0);
848
849 spin_lock_init(&gpu->perf_lock);
850
851
852 /* Map registers: */
853 gpu->mmio = msm_ioremap(pdev, config->ioname, name);
854 if (IS_ERR(gpu->mmio)) {
855 ret = PTR_ERR(gpu->mmio);
856 goto fail;
857 }
858
859 /* Get Interrupt: */
860 gpu->irq = platform_get_irq(pdev, 0);
861 if (gpu->irq < 0) {
862 ret = gpu->irq;
863 DRM_DEV_ERROR(drm->dev, "failed to get irq: %d\n", ret);
864 goto fail;
865 }
866
867 ret = devm_request_irq(&pdev->dev, gpu->irq, irq_handler,
868 IRQF_TRIGGER_HIGH, gpu->name, gpu);
869 if (ret) {
870 DRM_DEV_ERROR(drm->dev, "failed to request IRQ%u: %d\n", gpu->irq, ret);
871 goto fail;
872 }
873
874 ret = get_clocks(pdev, gpu);
875 if (ret)
876 goto fail;
877
878 gpu->ebi1_clk = msm_clk_get(pdev, "bus");
879 DBG("ebi1_clk: %p", gpu->ebi1_clk);
880 if (IS_ERR(gpu->ebi1_clk))
881 gpu->ebi1_clk = NULL;
882
883 /* Acquire regulators: */
884 gpu->gpu_reg = devm_regulator_get(&pdev->dev, "vdd");
885 DBG("gpu_reg: %p", gpu->gpu_reg);
886 if (IS_ERR(gpu->gpu_reg))
887 gpu->gpu_reg = NULL;
888
889 gpu->gpu_cx = devm_regulator_get(&pdev->dev, "vddcx");
890 DBG("gpu_cx: %p", gpu->gpu_cx);
891 if (IS_ERR(gpu->gpu_cx))
892 gpu->gpu_cx = NULL;
893
894 gpu->pdev = pdev;
895 platform_set_drvdata(pdev, gpu);
896
897 msm_devfreq_init(gpu);
898
899
900 gpu->aspace = gpu->funcs->create_address_space(gpu, pdev);
901
902 if (gpu->aspace == NULL)
903 DRM_DEV_INFO(drm->dev, "%s: no IOMMU, fallback to VRAM carveout!\n", name);
904 else if (IS_ERR(gpu->aspace)) {
905 ret = PTR_ERR(gpu->aspace);
906 goto fail;
907 }
908
909 memptrs = msm_gem_kernel_new(drm,
910 sizeof(struct msm_rbmemptrs) * nr_rings,
911 check_apriv(gpu, MSM_BO_UNCACHED), gpu->aspace, &gpu->memptrs_bo,
912 &memptrs_iova);
913
914 if (IS_ERR(memptrs)) {
915 ret = PTR_ERR(memptrs);
916 DRM_DEV_ERROR(drm->dev, "could not allocate memptrs: %d\n", ret);
917 goto fail;
918 }
919
920 msm_gem_object_set_name(gpu->memptrs_bo, "memptrs");
921
922 if (nr_rings > ARRAY_SIZE(gpu->rb)) {
923 DRM_DEV_INFO_ONCE(drm->dev, "Only creating %zu ringbuffers\n",
924 ARRAY_SIZE(gpu->rb));
925 nr_rings = ARRAY_SIZE(gpu->rb);
926 }
927
928 /* Create ringbuffer(s): */
929 for (i = 0; i < nr_rings; i++) {
930 gpu->rb[i] = msm_ringbuffer_new(gpu, i, memptrs, memptrs_iova);
931
932 if (IS_ERR(gpu->rb[i])) {
933 ret = PTR_ERR(gpu->rb[i]);
934 DRM_DEV_ERROR(drm->dev,
935 "could not create ringbuffer %d: %d\n", i, ret);
936 goto fail;
937 }
938
939 memptrs += sizeof(struct msm_rbmemptrs);
940 memptrs_iova += sizeof(struct msm_rbmemptrs);
941 }
942
943 gpu->nr_rings = nr_rings;
944
945 return 0;
946
947fail:
948 for (i = 0; i < ARRAY_SIZE(gpu->rb); i++) {
949 msm_ringbuffer_destroy(gpu->rb[i]);
950 gpu->rb[i] = NULL;
951 }
952
953 msm_gem_kernel_put(gpu->memptrs_bo, gpu->aspace, false);
954
955 platform_set_drvdata(pdev, NULL);
956 return ret;
957}
958
959void msm_gpu_cleanup(struct msm_gpu *gpu)
960{
961 int i;
962
963 DBG("%s", gpu->name);
964
965 WARN_ON(!list_empty(&gpu->active_list));
966
967 for (i = 0; i < ARRAY_SIZE(gpu->rb); i++) {
968 msm_ringbuffer_destroy(gpu->rb[i]);
969 gpu->rb[i] = NULL;
970 }
971
972 msm_gem_kernel_put(gpu->memptrs_bo, gpu->aspace, false);
973
974 if (!IS_ERR_OR_NULL(gpu->aspace)) {
975 gpu->aspace->mmu->funcs->detach(gpu->aspace->mmu);
976 msm_gem_address_space_put(gpu->aspace);
977 }
978}
1/*
2 * Copyright (C) 2013 Red Hat
3 * Author: Rob Clark <robdclark@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18#include "msm_gpu.h"
19#include "msm_gem.h"
20#include "msm_mmu.h"
21#include "msm_fence.h"
22
23
24/*
25 * Power Management:
26 */
27
28#ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING
29#include <mach/board.h>
30static void bs_init(struct msm_gpu *gpu)
31{
32 if (gpu->bus_scale_table) {
33 gpu->bsc = msm_bus_scale_register_client(gpu->bus_scale_table);
34 DBG("bus scale client: %08x", gpu->bsc);
35 }
36}
37
38static void bs_fini(struct msm_gpu *gpu)
39{
40 if (gpu->bsc) {
41 msm_bus_scale_unregister_client(gpu->bsc);
42 gpu->bsc = 0;
43 }
44}
45
46static void bs_set(struct msm_gpu *gpu, int idx)
47{
48 if (gpu->bsc) {
49 DBG("set bus scaling: %d", idx);
50 msm_bus_scale_client_update_request(gpu->bsc, idx);
51 }
52}
53#else
54static void bs_init(struct msm_gpu *gpu) {}
55static void bs_fini(struct msm_gpu *gpu) {}
56static void bs_set(struct msm_gpu *gpu, int idx) {}
57#endif
58
59static int enable_pwrrail(struct msm_gpu *gpu)
60{
61 struct drm_device *dev = gpu->dev;
62 int ret = 0;
63
64 if (gpu->gpu_reg) {
65 ret = regulator_enable(gpu->gpu_reg);
66 if (ret) {
67 dev_err(dev->dev, "failed to enable 'gpu_reg': %d\n", ret);
68 return ret;
69 }
70 }
71
72 if (gpu->gpu_cx) {
73 ret = regulator_enable(gpu->gpu_cx);
74 if (ret) {
75 dev_err(dev->dev, "failed to enable 'gpu_cx': %d\n", ret);
76 return ret;
77 }
78 }
79
80 return 0;
81}
82
83static int disable_pwrrail(struct msm_gpu *gpu)
84{
85 if (gpu->gpu_cx)
86 regulator_disable(gpu->gpu_cx);
87 if (gpu->gpu_reg)
88 regulator_disable(gpu->gpu_reg);
89 return 0;
90}
91
92static int enable_clk(struct msm_gpu *gpu)
93{
94 int i;
95
96 if (gpu->grp_clks[0] && gpu->fast_rate)
97 clk_set_rate(gpu->grp_clks[0], gpu->fast_rate);
98
99 /* Set the RBBM timer rate to 19.2Mhz */
100 if (gpu->grp_clks[2])
101 clk_set_rate(gpu->grp_clks[2], 19200000);
102
103 for (i = ARRAY_SIZE(gpu->grp_clks) - 1; i >= 0; i--)
104 if (gpu->grp_clks[i])
105 clk_prepare(gpu->grp_clks[i]);
106
107 for (i = ARRAY_SIZE(gpu->grp_clks) - 1; i >= 0; i--)
108 if (gpu->grp_clks[i])
109 clk_enable(gpu->grp_clks[i]);
110
111 return 0;
112}
113
114static int disable_clk(struct msm_gpu *gpu)
115{
116 int i;
117
118 for (i = ARRAY_SIZE(gpu->grp_clks) - 1; i >= 0; i--)
119 if (gpu->grp_clks[i])
120 clk_disable(gpu->grp_clks[i]);
121
122 for (i = ARRAY_SIZE(gpu->grp_clks) - 1; i >= 0; i--)
123 if (gpu->grp_clks[i])
124 clk_unprepare(gpu->grp_clks[i]);
125
126 if (gpu->grp_clks[0] && gpu->slow_rate)
127 clk_set_rate(gpu->grp_clks[0], gpu->slow_rate);
128
129 if (gpu->grp_clks[2])
130 clk_set_rate(gpu->grp_clks[2], 0);
131
132 return 0;
133}
134
135static int enable_axi(struct msm_gpu *gpu)
136{
137 if (gpu->ebi1_clk)
138 clk_prepare_enable(gpu->ebi1_clk);
139 if (gpu->bus_freq)
140 bs_set(gpu, gpu->bus_freq);
141 return 0;
142}
143
144static int disable_axi(struct msm_gpu *gpu)
145{
146 if (gpu->ebi1_clk)
147 clk_disable_unprepare(gpu->ebi1_clk);
148 if (gpu->bus_freq)
149 bs_set(gpu, 0);
150 return 0;
151}
152
153int msm_gpu_pm_resume(struct msm_gpu *gpu)
154{
155 struct drm_device *dev = gpu->dev;
156 int ret;
157
158 DBG("%s: active_cnt=%d", gpu->name, gpu->active_cnt);
159
160 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
161
162 if (gpu->active_cnt++ > 0)
163 return 0;
164
165 if (WARN_ON(gpu->active_cnt <= 0))
166 return -EINVAL;
167
168 ret = enable_pwrrail(gpu);
169 if (ret)
170 return ret;
171
172 ret = enable_clk(gpu);
173 if (ret)
174 return ret;
175
176 ret = enable_axi(gpu);
177 if (ret)
178 return ret;
179
180 return 0;
181}
182
183int msm_gpu_pm_suspend(struct msm_gpu *gpu)
184{
185 struct drm_device *dev = gpu->dev;
186 int ret;
187
188 DBG("%s: active_cnt=%d", gpu->name, gpu->active_cnt);
189
190 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
191
192 if (--gpu->active_cnt > 0)
193 return 0;
194
195 if (WARN_ON(gpu->active_cnt < 0))
196 return -EINVAL;
197
198 ret = disable_axi(gpu);
199 if (ret)
200 return ret;
201
202 ret = disable_clk(gpu);
203 if (ret)
204 return ret;
205
206 ret = disable_pwrrail(gpu);
207 if (ret)
208 return ret;
209
210 return 0;
211}
212
213/*
214 * Inactivity detection (for suspend):
215 */
216
217static void inactive_worker(struct work_struct *work)
218{
219 struct msm_gpu *gpu = container_of(work, struct msm_gpu, inactive_work);
220 struct drm_device *dev = gpu->dev;
221
222 if (gpu->inactive)
223 return;
224
225 DBG("%s: inactive!\n", gpu->name);
226 mutex_lock(&dev->struct_mutex);
227 if (!(msm_gpu_active(gpu) || gpu->inactive)) {
228 disable_axi(gpu);
229 disable_clk(gpu);
230 gpu->inactive = true;
231 }
232 mutex_unlock(&dev->struct_mutex);
233}
234
235static void inactive_handler(unsigned long data)
236{
237 struct msm_gpu *gpu = (struct msm_gpu *)data;
238 struct msm_drm_private *priv = gpu->dev->dev_private;
239
240 queue_work(priv->wq, &gpu->inactive_work);
241}
242
243/* cancel inactive timer and make sure we are awake: */
244static void inactive_cancel(struct msm_gpu *gpu)
245{
246 DBG("%s", gpu->name);
247 del_timer(&gpu->inactive_timer);
248 if (gpu->inactive) {
249 enable_clk(gpu);
250 enable_axi(gpu);
251 gpu->inactive = false;
252 }
253}
254
255static void inactive_start(struct msm_gpu *gpu)
256{
257 DBG("%s", gpu->name);
258 mod_timer(&gpu->inactive_timer,
259 round_jiffies_up(jiffies + DRM_MSM_INACTIVE_JIFFIES));
260}
261
262/*
263 * Hangcheck detection for locked gpu:
264 */
265
266static void retire_submits(struct msm_gpu *gpu);
267
268static void recover_worker(struct work_struct *work)
269{
270 struct msm_gpu *gpu = container_of(work, struct msm_gpu, recover_work);
271 struct drm_device *dev = gpu->dev;
272 struct msm_gem_submit *submit;
273 uint32_t fence = gpu->funcs->last_fence(gpu);
274
275 msm_update_fence(gpu->fctx, fence + 1);
276
277 mutex_lock(&dev->struct_mutex);
278
279 dev_err(dev->dev, "%s: hangcheck recover!\n", gpu->name);
280 list_for_each_entry(submit, &gpu->submit_list, node) {
281 if (submit->fence->seqno == (fence + 1)) {
282 struct task_struct *task;
283
284 rcu_read_lock();
285 task = pid_task(submit->pid, PIDTYPE_PID);
286 if (task) {
287 dev_err(dev->dev, "%s: offending task: %s\n",
288 gpu->name, task->comm);
289 }
290 rcu_read_unlock();
291 break;
292 }
293 }
294
295 if (msm_gpu_active(gpu)) {
296 /* retire completed submits, plus the one that hung: */
297 retire_submits(gpu);
298
299 inactive_cancel(gpu);
300 gpu->funcs->recover(gpu);
301
302 /* replay the remaining submits after the one that hung: */
303 list_for_each_entry(submit, &gpu->submit_list, node) {
304 gpu->funcs->submit(gpu, submit, NULL);
305 }
306 }
307
308 mutex_unlock(&dev->struct_mutex);
309
310 msm_gpu_retire(gpu);
311}
312
313static void hangcheck_timer_reset(struct msm_gpu *gpu)
314{
315 DBG("%s", gpu->name);
316 mod_timer(&gpu->hangcheck_timer,
317 round_jiffies_up(jiffies + DRM_MSM_HANGCHECK_JIFFIES));
318}
319
320static void hangcheck_handler(unsigned long data)
321{
322 struct msm_gpu *gpu = (struct msm_gpu *)data;
323 struct drm_device *dev = gpu->dev;
324 struct msm_drm_private *priv = dev->dev_private;
325 uint32_t fence = gpu->funcs->last_fence(gpu);
326
327 if (fence != gpu->hangcheck_fence) {
328 /* some progress has been made.. ya! */
329 gpu->hangcheck_fence = fence;
330 } else if (fence < gpu->fctx->last_fence) {
331 /* no progress and not done.. hung! */
332 gpu->hangcheck_fence = fence;
333 dev_err(dev->dev, "%s: hangcheck detected gpu lockup!\n",
334 gpu->name);
335 dev_err(dev->dev, "%s: completed fence: %u\n",
336 gpu->name, fence);
337 dev_err(dev->dev, "%s: submitted fence: %u\n",
338 gpu->name, gpu->fctx->last_fence);
339 queue_work(priv->wq, &gpu->recover_work);
340 }
341
342 /* if still more pending work, reset the hangcheck timer: */
343 if (gpu->fctx->last_fence > gpu->hangcheck_fence)
344 hangcheck_timer_reset(gpu);
345
346 /* workaround for missing irq: */
347 queue_work(priv->wq, &gpu->retire_work);
348}
349
350/*
351 * Performance Counters:
352 */
353
354/* called under perf_lock */
355static int update_hw_cntrs(struct msm_gpu *gpu, uint32_t ncntrs, uint32_t *cntrs)
356{
357 uint32_t current_cntrs[ARRAY_SIZE(gpu->last_cntrs)];
358 int i, n = min(ncntrs, gpu->num_perfcntrs);
359
360 /* read current values: */
361 for (i = 0; i < gpu->num_perfcntrs; i++)
362 current_cntrs[i] = gpu_read(gpu, gpu->perfcntrs[i].sample_reg);
363
364 /* update cntrs: */
365 for (i = 0; i < n; i++)
366 cntrs[i] = current_cntrs[i] - gpu->last_cntrs[i];
367
368 /* save current values: */
369 for (i = 0; i < gpu->num_perfcntrs; i++)
370 gpu->last_cntrs[i] = current_cntrs[i];
371
372 return n;
373}
374
375static void update_sw_cntrs(struct msm_gpu *gpu)
376{
377 ktime_t time;
378 uint32_t elapsed;
379 unsigned long flags;
380
381 spin_lock_irqsave(&gpu->perf_lock, flags);
382 if (!gpu->perfcntr_active)
383 goto out;
384
385 time = ktime_get();
386 elapsed = ktime_to_us(ktime_sub(time, gpu->last_sample.time));
387
388 gpu->totaltime += elapsed;
389 if (gpu->last_sample.active)
390 gpu->activetime += elapsed;
391
392 gpu->last_sample.active = msm_gpu_active(gpu);
393 gpu->last_sample.time = time;
394
395out:
396 spin_unlock_irqrestore(&gpu->perf_lock, flags);
397}
398
399void msm_gpu_perfcntr_start(struct msm_gpu *gpu)
400{
401 unsigned long flags;
402
403 spin_lock_irqsave(&gpu->perf_lock, flags);
404 /* we could dynamically enable/disable perfcntr registers too.. */
405 gpu->last_sample.active = msm_gpu_active(gpu);
406 gpu->last_sample.time = ktime_get();
407 gpu->activetime = gpu->totaltime = 0;
408 gpu->perfcntr_active = true;
409 update_hw_cntrs(gpu, 0, NULL);
410 spin_unlock_irqrestore(&gpu->perf_lock, flags);
411}
412
413void msm_gpu_perfcntr_stop(struct msm_gpu *gpu)
414{
415 gpu->perfcntr_active = false;
416}
417
418/* returns -errno or # of cntrs sampled */
419int msm_gpu_perfcntr_sample(struct msm_gpu *gpu, uint32_t *activetime,
420 uint32_t *totaltime, uint32_t ncntrs, uint32_t *cntrs)
421{
422 unsigned long flags;
423 int ret;
424
425 spin_lock_irqsave(&gpu->perf_lock, flags);
426
427 if (!gpu->perfcntr_active) {
428 ret = -EINVAL;
429 goto out;
430 }
431
432 *activetime = gpu->activetime;
433 *totaltime = gpu->totaltime;
434
435 gpu->activetime = gpu->totaltime = 0;
436
437 ret = update_hw_cntrs(gpu, ncntrs, cntrs);
438
439out:
440 spin_unlock_irqrestore(&gpu->perf_lock, flags);
441
442 return ret;
443}
444
445/*
446 * Cmdstream submission/retirement:
447 */
448
449static void retire_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
450{
451 int i;
452
453 for (i = 0; i < submit->nr_bos; i++) {
454 struct msm_gem_object *msm_obj = submit->bos[i].obj;
455 /* move to inactive: */
456 msm_gem_move_to_inactive(&msm_obj->base);
457 msm_gem_put_iova(&msm_obj->base, gpu->id);
458 drm_gem_object_unreference(&msm_obj->base);
459 }
460
461 msm_gem_submit_free(submit);
462}
463
464static void retire_submits(struct msm_gpu *gpu)
465{
466 struct drm_device *dev = gpu->dev;
467
468 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
469
470 while (!list_empty(&gpu->submit_list)) {
471 struct msm_gem_submit *submit;
472
473 submit = list_first_entry(&gpu->submit_list,
474 struct msm_gem_submit, node);
475
476 if (dma_fence_is_signaled(submit->fence)) {
477 retire_submit(gpu, submit);
478 } else {
479 break;
480 }
481 }
482}
483
484static void retire_worker(struct work_struct *work)
485{
486 struct msm_gpu *gpu = container_of(work, struct msm_gpu, retire_work);
487 struct drm_device *dev = gpu->dev;
488 uint32_t fence = gpu->funcs->last_fence(gpu);
489
490 msm_update_fence(gpu->fctx, fence);
491
492 mutex_lock(&dev->struct_mutex);
493 retire_submits(gpu);
494 mutex_unlock(&dev->struct_mutex);
495
496 if (!msm_gpu_active(gpu))
497 inactive_start(gpu);
498}
499
500/* call from irq handler to schedule work to retire bo's */
501void msm_gpu_retire(struct msm_gpu *gpu)
502{
503 struct msm_drm_private *priv = gpu->dev->dev_private;
504 queue_work(priv->wq, &gpu->retire_work);
505 update_sw_cntrs(gpu);
506}
507
508/* add bo's to gpu's ring, and kick gpu: */
509void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
510 struct msm_file_private *ctx)
511{
512 struct drm_device *dev = gpu->dev;
513 struct msm_drm_private *priv = dev->dev_private;
514 int i;
515
516 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
517
518 inactive_cancel(gpu);
519
520 list_add_tail(&submit->node, &gpu->submit_list);
521
522 msm_rd_dump_submit(submit);
523
524 update_sw_cntrs(gpu);
525
526 for (i = 0; i < submit->nr_bos; i++) {
527 struct msm_gem_object *msm_obj = submit->bos[i].obj;
528 uint64_t iova;
529
530 /* can't happen yet.. but when we add 2d support we'll have
531 * to deal w/ cross-ring synchronization:
532 */
533 WARN_ON(is_active(msm_obj) && (msm_obj->gpu != gpu));
534
535 /* submit takes a reference to the bo and iova until retired: */
536 drm_gem_object_reference(&msm_obj->base);
537 msm_gem_get_iova_locked(&msm_obj->base,
538 submit->gpu->id, &iova);
539
540 if (submit->bos[i].flags & MSM_SUBMIT_BO_WRITE)
541 msm_gem_move_to_active(&msm_obj->base, gpu, true, submit->fence);
542 else if (submit->bos[i].flags & MSM_SUBMIT_BO_READ)
543 msm_gem_move_to_active(&msm_obj->base, gpu, false, submit->fence);
544 }
545
546 gpu->funcs->submit(gpu, submit, ctx);
547 priv->lastctx = ctx;
548
549 hangcheck_timer_reset(gpu);
550}
551
552/*
553 * Init/Cleanup:
554 */
555
556static irqreturn_t irq_handler(int irq, void *data)
557{
558 struct msm_gpu *gpu = data;
559 return gpu->funcs->irq(gpu);
560}
561
562static const char *clk_names[] = {
563 "core_clk", "iface_clk", "rbbmtimer_clk", "mem_clk",
564 "mem_iface_clk", "alt_mem_iface_clk",
565};
566
567int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
568 struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs,
569 const char *name, const char *ioname, const char *irqname, int ringsz)
570{
571 struct iommu_domain *iommu;
572 int i, ret;
573
574 if (WARN_ON(gpu->num_perfcntrs > ARRAY_SIZE(gpu->last_cntrs)))
575 gpu->num_perfcntrs = ARRAY_SIZE(gpu->last_cntrs);
576
577 gpu->dev = drm;
578 gpu->funcs = funcs;
579 gpu->name = name;
580 gpu->inactive = true;
581 gpu->fctx = msm_fence_context_alloc(drm, name);
582 if (IS_ERR(gpu->fctx)) {
583 ret = PTR_ERR(gpu->fctx);
584 gpu->fctx = NULL;
585 goto fail;
586 }
587
588 INIT_LIST_HEAD(&gpu->active_list);
589 INIT_WORK(&gpu->retire_work, retire_worker);
590 INIT_WORK(&gpu->inactive_work, inactive_worker);
591 INIT_WORK(&gpu->recover_work, recover_worker);
592
593 INIT_LIST_HEAD(&gpu->submit_list);
594
595 setup_timer(&gpu->inactive_timer, inactive_handler,
596 (unsigned long)gpu);
597 setup_timer(&gpu->hangcheck_timer, hangcheck_handler,
598 (unsigned long)gpu);
599
600 spin_lock_init(&gpu->perf_lock);
601
602 BUG_ON(ARRAY_SIZE(clk_names) != ARRAY_SIZE(gpu->grp_clks));
603
604 /* Map registers: */
605 gpu->mmio = msm_ioremap(pdev, ioname, name);
606 if (IS_ERR(gpu->mmio)) {
607 ret = PTR_ERR(gpu->mmio);
608 goto fail;
609 }
610
611 /* Get Interrupt: */
612 gpu->irq = platform_get_irq_byname(pdev, irqname);
613 if (gpu->irq < 0) {
614 ret = gpu->irq;
615 dev_err(drm->dev, "failed to get irq: %d\n", ret);
616 goto fail;
617 }
618
619 ret = devm_request_irq(&pdev->dev, gpu->irq, irq_handler,
620 IRQF_TRIGGER_HIGH, gpu->name, gpu);
621 if (ret) {
622 dev_err(drm->dev, "failed to request IRQ%u: %d\n", gpu->irq, ret);
623 goto fail;
624 }
625
626 /* Acquire clocks: */
627 for (i = 0; i < ARRAY_SIZE(clk_names); i++) {
628 gpu->grp_clks[i] = devm_clk_get(&pdev->dev, clk_names[i]);
629 DBG("grp_clks[%s]: %p", clk_names[i], gpu->grp_clks[i]);
630 if (IS_ERR(gpu->grp_clks[i]))
631 gpu->grp_clks[i] = NULL;
632 }
633
634 gpu->ebi1_clk = devm_clk_get(&pdev->dev, "bus_clk");
635 DBG("ebi1_clk: %p", gpu->ebi1_clk);
636 if (IS_ERR(gpu->ebi1_clk))
637 gpu->ebi1_clk = NULL;
638
639 /* Acquire regulators: */
640 gpu->gpu_reg = devm_regulator_get(&pdev->dev, "vdd");
641 DBG("gpu_reg: %p", gpu->gpu_reg);
642 if (IS_ERR(gpu->gpu_reg))
643 gpu->gpu_reg = NULL;
644
645 gpu->gpu_cx = devm_regulator_get(&pdev->dev, "vddcx");
646 DBG("gpu_cx: %p", gpu->gpu_cx);
647 if (IS_ERR(gpu->gpu_cx))
648 gpu->gpu_cx = NULL;
649
650 /* Setup IOMMU.. eventually we will (I think) do this once per context
651 * and have separate page tables per context. For now, to keep things
652 * simple and to get something working, just use a single address space:
653 */
654 iommu = iommu_domain_alloc(&platform_bus_type);
655 if (iommu) {
656 /* TODO 32b vs 64b address space.. */
657 iommu->geometry.aperture_start = SZ_16M;
658 iommu->geometry.aperture_end = 0xffffffff;
659
660 dev_info(drm->dev, "%s: using IOMMU\n", name);
661 gpu->aspace = msm_gem_address_space_create(&pdev->dev,
662 iommu, "gpu");
663 if (IS_ERR(gpu->aspace)) {
664 ret = PTR_ERR(gpu->aspace);
665 dev_err(drm->dev, "failed to init iommu: %d\n", ret);
666 gpu->aspace = NULL;
667 iommu_domain_free(iommu);
668 goto fail;
669 }
670
671 } else {
672 dev_info(drm->dev, "%s: no IOMMU, fallback to VRAM carveout!\n", name);
673 }
674 gpu->id = msm_register_address_space(drm, gpu->aspace);
675
676
677 /* Create ringbuffer: */
678 mutex_lock(&drm->struct_mutex);
679 gpu->rb = msm_ringbuffer_new(gpu, ringsz);
680 mutex_unlock(&drm->struct_mutex);
681 if (IS_ERR(gpu->rb)) {
682 ret = PTR_ERR(gpu->rb);
683 gpu->rb = NULL;
684 dev_err(drm->dev, "could not create ringbuffer: %d\n", ret);
685 goto fail;
686 }
687
688 bs_init(gpu);
689
690 return 0;
691
692fail:
693 return ret;
694}
695
696void msm_gpu_cleanup(struct msm_gpu *gpu)
697{
698 DBG("%s", gpu->name);
699
700 WARN_ON(!list_empty(&gpu->active_list));
701
702 bs_fini(gpu);
703
704 if (gpu->rb) {
705 if (gpu->rb_iova)
706 msm_gem_put_iova(gpu->rb->bo, gpu->id);
707 msm_ringbuffer_destroy(gpu->rb);
708 }
709
710 if (gpu->aspace)
711 msm_gem_address_space_destroy(gpu->aspace);
712
713 if (gpu->fctx)
714 msm_fence_context_free(gpu->fctx);
715}