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1/*
2 * Copyright 2009 Jerome Glisse.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 */
26/*
27 * Authors:
28 * Jerome Glisse <glisse@freedesktop.org>
29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
30 * Dave Airlie
31 */
32
33#include <linux/dma-mapping.h>
34#include <linux/iommu.h>
35#include <linux/hmm.h>
36#include <linux/pagemap.h>
37#include <linux/sched/task.h>
38#include <linux/sched/mm.h>
39#include <linux/seq_file.h>
40#include <linux/slab.h>
41#include <linux/swap.h>
42#include <linux/swiotlb.h>
43#include <linux/dma-buf.h>
44#include <linux/sizes.h>
45
46#include <drm/ttm/ttm_bo_api.h>
47#include <drm/ttm/ttm_bo_driver.h>
48#include <drm/ttm/ttm_placement.h>
49#include <drm/ttm/ttm_module.h>
50#include <drm/ttm/ttm_page_alloc.h>
51
52#include <drm/drm_debugfs.h>
53#include <drm/amdgpu_drm.h>
54
55#include "amdgpu.h"
56#include "amdgpu_object.h"
57#include "amdgpu_trace.h"
58#include "amdgpu_amdkfd.h"
59#include "amdgpu_sdma.h"
60#include "amdgpu_ras.h"
61#include "amdgpu_atomfirmware.h"
62#include "bif/bif_4_1_d.h"
63
64#define AMDGPU_TTM_VRAM_MAX_DW_READ (size_t)128
65
66
67/**
68 * amdgpu_init_mem_type - Initialize a memory manager for a specific type of
69 * memory request.
70 *
71 * @bdev: The TTM BO device object (contains a reference to amdgpu_device)
72 * @type: The type of memory requested
73 * @man: The memory type manager for each domain
74 *
75 * This is called by ttm_bo_init_mm() when a buffer object is being
76 * initialized.
77 */
78static int amdgpu_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
79 struct ttm_mem_type_manager *man)
80{
81 struct amdgpu_device *adev;
82
83 adev = amdgpu_ttm_adev(bdev);
84
85 switch (type) {
86 case TTM_PL_SYSTEM:
87 /* System memory */
88 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
89 man->available_caching = TTM_PL_MASK_CACHING;
90 man->default_caching = TTM_PL_FLAG_CACHED;
91 break;
92 case TTM_PL_TT:
93 /* GTT memory */
94 man->func = &amdgpu_gtt_mgr_func;
95 man->available_caching = TTM_PL_MASK_CACHING;
96 man->default_caching = TTM_PL_FLAG_CACHED;
97 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
98 break;
99 case TTM_PL_VRAM:
100 /* "On-card" video ram */
101 man->func = &amdgpu_vram_mgr_func;
102 man->flags = TTM_MEMTYPE_FLAG_FIXED |
103 TTM_MEMTYPE_FLAG_MAPPABLE;
104 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
105 man->default_caching = TTM_PL_FLAG_WC;
106 break;
107 case AMDGPU_PL_GDS:
108 case AMDGPU_PL_GWS:
109 case AMDGPU_PL_OA:
110 /* On-chip GDS memory*/
111 man->func = &ttm_bo_manager_func;
112 man->flags = TTM_MEMTYPE_FLAG_FIXED;
113 man->available_caching = TTM_PL_FLAG_UNCACHED;
114 man->default_caching = TTM_PL_FLAG_UNCACHED;
115 break;
116 default:
117 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
118 return -EINVAL;
119 }
120 return 0;
121}
122
123/**
124 * amdgpu_evict_flags - Compute placement flags
125 *
126 * @bo: The buffer object to evict
127 * @placement: Possible destination(s) for evicted BO
128 *
129 * Fill in placement data when ttm_bo_evict() is called
130 */
131static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
132 struct ttm_placement *placement)
133{
134 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
135 struct amdgpu_bo *abo;
136 static const struct ttm_place placements = {
137 .fpfn = 0,
138 .lpfn = 0,
139 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM
140 };
141
142 /* Don't handle scatter gather BOs */
143 if (bo->type == ttm_bo_type_sg) {
144 placement->num_placement = 0;
145 placement->num_busy_placement = 0;
146 return;
147 }
148
149 /* Object isn't an AMDGPU object so ignore */
150 if (!amdgpu_bo_is_amdgpu_bo(bo)) {
151 placement->placement = &placements;
152 placement->busy_placement = &placements;
153 placement->num_placement = 1;
154 placement->num_busy_placement = 1;
155 return;
156 }
157
158 abo = ttm_to_amdgpu_bo(bo);
159 switch (bo->mem.mem_type) {
160 case AMDGPU_PL_GDS:
161 case AMDGPU_PL_GWS:
162 case AMDGPU_PL_OA:
163 placement->num_placement = 0;
164 placement->num_busy_placement = 0;
165 return;
166
167 case TTM_PL_VRAM:
168 if (!adev->mman.buffer_funcs_enabled) {
169 /* Move to system memory */
170 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
171 } else if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
172 !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) &&
173 amdgpu_bo_in_cpu_visible_vram(abo)) {
174
175 /* Try evicting to the CPU inaccessible part of VRAM
176 * first, but only set GTT as busy placement, so this
177 * BO will be evicted to GTT rather than causing other
178 * BOs to be evicted from VRAM
179 */
180 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
181 AMDGPU_GEM_DOMAIN_GTT);
182 abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
183 abo->placements[0].lpfn = 0;
184 abo->placement.busy_placement = &abo->placements[1];
185 abo->placement.num_busy_placement = 1;
186 } else {
187 /* Move to GTT memory */
188 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT);
189 }
190 break;
191 case TTM_PL_TT:
192 default:
193 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
194 break;
195 }
196 *placement = abo->placement;
197}
198
199/**
200 * amdgpu_verify_access - Verify access for a mmap call
201 *
202 * @bo: The buffer object to map
203 * @filp: The file pointer from the process performing the mmap
204 *
205 * This is called by ttm_bo_mmap() to verify whether a process
206 * has the right to mmap a BO to their process space.
207 */
208static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
209{
210 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
211
212 /*
213 * Don't verify access for KFD BOs. They don't have a GEM
214 * object associated with them.
215 */
216 if (abo->kfd_bo)
217 return 0;
218
219 if (amdgpu_ttm_tt_get_usermm(bo->ttm))
220 return -EPERM;
221 return drm_vma_node_verify_access(&abo->tbo.base.vma_node,
222 filp->private_data);
223}
224
225/**
226 * amdgpu_move_null - Register memory for a buffer object
227 *
228 * @bo: The bo to assign the memory to
229 * @new_mem: The memory to be assigned.
230 *
231 * Assign the memory from new_mem to the memory of the buffer object bo.
232 */
233static void amdgpu_move_null(struct ttm_buffer_object *bo,
234 struct ttm_mem_reg *new_mem)
235{
236 struct ttm_mem_reg *old_mem = &bo->mem;
237
238 BUG_ON(old_mem->mm_node != NULL);
239 *old_mem = *new_mem;
240 new_mem->mm_node = NULL;
241}
242
243/**
244 * amdgpu_mm_node_addr - Compute the GPU relative offset of a GTT buffer.
245 *
246 * @bo: The bo to assign the memory to.
247 * @mm_node: Memory manager node for drm allocator.
248 * @mem: The region where the bo resides.
249 *
250 */
251static uint64_t amdgpu_mm_node_addr(struct ttm_buffer_object *bo,
252 struct drm_mm_node *mm_node,
253 struct ttm_mem_reg *mem)
254{
255 uint64_t addr = 0;
256
257 if (mm_node->start != AMDGPU_BO_INVALID_OFFSET) {
258 addr = mm_node->start << PAGE_SHIFT;
259 addr += amdgpu_ttm_domain_start(amdgpu_ttm_adev(bo->bdev),
260 mem->mem_type);
261 }
262 return addr;
263}
264
265/**
266 * amdgpu_find_mm_node - Helper function finds the drm_mm_node corresponding to
267 * @offset. It also modifies the offset to be within the drm_mm_node returned
268 *
269 * @mem: The region where the bo resides.
270 * @offset: The offset that drm_mm_node is used for finding.
271 *
272 */
273static struct drm_mm_node *amdgpu_find_mm_node(struct ttm_mem_reg *mem,
274 uint64_t *offset)
275{
276 struct drm_mm_node *mm_node = mem->mm_node;
277
278 while (*offset >= (mm_node->size << PAGE_SHIFT)) {
279 *offset -= (mm_node->size << PAGE_SHIFT);
280 ++mm_node;
281 }
282 return mm_node;
283}
284
285/**
286 * amdgpu_ttm_map_buffer - Map memory into the GART windows
287 * @bo: buffer object to map
288 * @mem: memory object to map
289 * @mm_node: drm_mm node object to map
290 * @num_pages: number of pages to map
291 * @offset: offset into @mm_node where to start
292 * @window: which GART window to use
293 * @ring: DMA ring to use for the copy
294 * @tmz: if we should setup a TMZ enabled mapping
295 * @addr: resulting address inside the MC address space
296 *
297 * Setup one of the GART windows to access a specific piece of memory or return
298 * the physical address for local memory.
299 */
300static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo,
301 struct ttm_mem_reg *mem,
302 struct drm_mm_node *mm_node,
303 unsigned num_pages, uint64_t offset,
304 unsigned window, struct amdgpu_ring *ring,
305 bool tmz, uint64_t *addr)
306{
307 struct amdgpu_device *adev = ring->adev;
308 struct amdgpu_job *job;
309 unsigned num_dw, num_bytes;
310 struct dma_fence *fence;
311 uint64_t src_addr, dst_addr;
312 void *cpu_addr;
313 uint64_t flags;
314 unsigned int i;
315 int r;
316
317 BUG_ON(adev->mman.buffer_funcs->copy_max_bytes <
318 AMDGPU_GTT_MAX_TRANSFER_SIZE * 8);
319
320 /* Map only what can't be accessed directly */
321 if (!tmz && mem->start != AMDGPU_BO_INVALID_OFFSET) {
322 *addr = amdgpu_mm_node_addr(bo, mm_node, mem) + offset;
323 return 0;
324 }
325
326 *addr = adev->gmc.gart_start;
327 *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE *
328 AMDGPU_GPU_PAGE_SIZE;
329 *addr += offset & ~PAGE_MASK;
330
331 num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8);
332 num_bytes = num_pages * 8;
333
334 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes,
335 AMDGPU_IB_POOL_DELAYED, &job);
336 if (r)
337 return r;
338
339 src_addr = num_dw * 4;
340 src_addr += job->ibs[0].gpu_addr;
341
342 dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
343 dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8;
344 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr,
345 dst_addr, num_bytes, false);
346
347 amdgpu_ring_pad_ib(ring, &job->ibs[0]);
348 WARN_ON(job->ibs[0].length_dw > num_dw);
349
350 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, mem);
351 if (tmz)
352 flags |= AMDGPU_PTE_TMZ;
353
354 cpu_addr = &job->ibs[0].ptr[num_dw];
355
356 if (mem->mem_type == TTM_PL_TT) {
357 struct ttm_dma_tt *dma;
358 dma_addr_t *dma_address;
359
360 dma = container_of(bo->ttm, struct ttm_dma_tt, ttm);
361 dma_address = &dma->dma_address[offset >> PAGE_SHIFT];
362 r = amdgpu_gart_map(adev, 0, num_pages, dma_address, flags,
363 cpu_addr);
364 if (r)
365 goto error_free;
366 } else {
367 dma_addr_t dma_address;
368
369 dma_address = (mm_node->start << PAGE_SHIFT) + offset;
370 dma_address += adev->vm_manager.vram_base_offset;
371
372 for (i = 0; i < num_pages; ++i) {
373 r = amdgpu_gart_map(adev, i << PAGE_SHIFT, 1,
374 &dma_address, flags, cpu_addr);
375 if (r)
376 goto error_free;
377
378 dma_address += PAGE_SIZE;
379 }
380 }
381
382 r = amdgpu_job_submit(job, &adev->mman.entity,
383 AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
384 if (r)
385 goto error_free;
386
387 dma_fence_put(fence);
388
389 return r;
390
391error_free:
392 amdgpu_job_free(job);
393 return r;
394}
395
396/**
397 * amdgpu_copy_ttm_mem_to_mem - Helper function for copy
398 * @adev: amdgpu device
399 * @src: buffer/address where to read from
400 * @dst: buffer/address where to write to
401 * @size: number of bytes to copy
402 * @tmz: if a secure copy should be used
403 * @resv: resv object to sync to
404 * @f: Returns the last fence if multiple jobs are submitted.
405 *
406 * The function copies @size bytes from {src->mem + src->offset} to
407 * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a
408 * move and different for a BO to BO copy.
409 *
410 */
411int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
412 const struct amdgpu_copy_mem *src,
413 const struct amdgpu_copy_mem *dst,
414 uint64_t size, bool tmz,
415 struct dma_resv *resv,
416 struct dma_fence **f)
417{
418 const uint32_t GTT_MAX_BYTES = (AMDGPU_GTT_MAX_TRANSFER_SIZE *
419 AMDGPU_GPU_PAGE_SIZE);
420
421 uint64_t src_node_size, dst_node_size, src_offset, dst_offset;
422 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
423 struct drm_mm_node *src_mm, *dst_mm;
424 struct dma_fence *fence = NULL;
425 int r = 0;
426
427 if (!adev->mman.buffer_funcs_enabled) {
428 DRM_ERROR("Trying to move memory with ring turned off.\n");
429 return -EINVAL;
430 }
431
432 src_offset = src->offset;
433 if (src->mem->mm_node) {
434 src_mm = amdgpu_find_mm_node(src->mem, &src_offset);
435 src_node_size = (src_mm->size << PAGE_SHIFT) - src_offset;
436 } else {
437 src_mm = NULL;
438 src_node_size = ULLONG_MAX;
439 }
440
441 dst_offset = dst->offset;
442 if (dst->mem->mm_node) {
443 dst_mm = amdgpu_find_mm_node(dst->mem, &dst_offset);
444 dst_node_size = (dst_mm->size << PAGE_SHIFT) - dst_offset;
445 } else {
446 dst_mm = NULL;
447 dst_node_size = ULLONG_MAX;
448 }
449
450 mutex_lock(&adev->mman.gtt_window_lock);
451
452 while (size) {
453 uint32_t src_page_offset = src_offset & ~PAGE_MASK;
454 uint32_t dst_page_offset = dst_offset & ~PAGE_MASK;
455 struct dma_fence *next;
456 uint32_t cur_size;
457 uint64_t from, to;
458
459 /* Copy size cannot exceed GTT_MAX_BYTES. So if src or dst
460 * begins at an offset, then adjust the size accordingly
461 */
462 cur_size = max(src_page_offset, dst_page_offset);
463 cur_size = min(min3(src_node_size, dst_node_size, size),
464 (uint64_t)(GTT_MAX_BYTES - cur_size));
465
466 /* Map src to window 0 and dst to window 1. */
467 r = amdgpu_ttm_map_buffer(src->bo, src->mem, src_mm,
468 PFN_UP(cur_size + src_page_offset),
469 src_offset, 0, ring, tmz, &from);
470 if (r)
471 goto error;
472
473 r = amdgpu_ttm_map_buffer(dst->bo, dst->mem, dst_mm,
474 PFN_UP(cur_size + dst_page_offset),
475 dst_offset, 1, ring, tmz, &to);
476 if (r)
477 goto error;
478
479 r = amdgpu_copy_buffer(ring, from, to, cur_size,
480 resv, &next, false, true, tmz);
481 if (r)
482 goto error;
483
484 dma_fence_put(fence);
485 fence = next;
486
487 size -= cur_size;
488 if (!size)
489 break;
490
491 src_node_size -= cur_size;
492 if (!src_node_size) {
493 ++src_mm;
494 src_node_size = src_mm->size << PAGE_SHIFT;
495 src_offset = 0;
496 } else {
497 src_offset += cur_size;
498 }
499
500 dst_node_size -= cur_size;
501 if (!dst_node_size) {
502 ++dst_mm;
503 dst_node_size = dst_mm->size << PAGE_SHIFT;
504 dst_offset = 0;
505 } else {
506 dst_offset += cur_size;
507 }
508 }
509error:
510 mutex_unlock(&adev->mman.gtt_window_lock);
511 if (f)
512 *f = dma_fence_get(fence);
513 dma_fence_put(fence);
514 return r;
515}
516
517/**
518 * amdgpu_move_blit - Copy an entire buffer to another buffer
519 *
520 * This is a helper called by amdgpu_bo_move() and amdgpu_move_vram_ram() to
521 * help move buffers to and from VRAM.
522 */
523static int amdgpu_move_blit(struct ttm_buffer_object *bo,
524 bool evict, bool no_wait_gpu,
525 struct ttm_mem_reg *new_mem,
526 struct ttm_mem_reg *old_mem)
527{
528 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
529 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
530 struct amdgpu_copy_mem src, dst;
531 struct dma_fence *fence = NULL;
532 int r;
533
534 src.bo = bo;
535 dst.bo = bo;
536 src.mem = old_mem;
537 dst.mem = new_mem;
538 src.offset = 0;
539 dst.offset = 0;
540
541 r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst,
542 new_mem->num_pages << PAGE_SHIFT,
543 amdgpu_bo_encrypted(abo),
544 bo->base.resv, &fence);
545 if (r)
546 goto error;
547
548 /* clear the space being freed */
549 if (old_mem->mem_type == TTM_PL_VRAM &&
550 (abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) {
551 struct dma_fence *wipe_fence = NULL;
552
553 r = amdgpu_fill_buffer(ttm_to_amdgpu_bo(bo), AMDGPU_POISON,
554 NULL, &wipe_fence);
555 if (r) {
556 goto error;
557 } else if (wipe_fence) {
558 dma_fence_put(fence);
559 fence = wipe_fence;
560 }
561 }
562
563 /* Always block for VM page tables before committing the new location */
564 if (bo->type == ttm_bo_type_kernel)
565 r = ttm_bo_move_accel_cleanup(bo, fence, true, new_mem);
566 else
567 r = ttm_bo_pipeline_move(bo, fence, evict, new_mem);
568 dma_fence_put(fence);
569 return r;
570
571error:
572 if (fence)
573 dma_fence_wait(fence, false);
574 dma_fence_put(fence);
575 return r;
576}
577
578/**
579 * amdgpu_move_vram_ram - Copy VRAM buffer to RAM buffer
580 *
581 * Called by amdgpu_bo_move().
582 */
583static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo, bool evict,
584 struct ttm_operation_ctx *ctx,
585 struct ttm_mem_reg *new_mem)
586{
587 struct ttm_mem_reg *old_mem = &bo->mem;
588 struct ttm_mem_reg tmp_mem;
589 struct ttm_place placements;
590 struct ttm_placement placement;
591 int r;
592
593 /* create space/pages for new_mem in GTT space */
594 tmp_mem = *new_mem;
595 tmp_mem.mm_node = NULL;
596 placement.num_placement = 1;
597 placement.placement = &placements;
598 placement.num_busy_placement = 1;
599 placement.busy_placement = &placements;
600 placements.fpfn = 0;
601 placements.lpfn = 0;
602 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
603 r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
604 if (unlikely(r)) {
605 pr_err("Failed to find GTT space for blit from VRAM\n");
606 return r;
607 }
608
609 /* set caching flags */
610 r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
611 if (unlikely(r)) {
612 goto out_cleanup;
613 }
614
615 /* Bind the memory to the GTT space */
616 r = ttm_tt_bind(bo->ttm, &tmp_mem, ctx);
617 if (unlikely(r)) {
618 goto out_cleanup;
619 }
620
621 /* blit VRAM to GTT */
622 r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu, &tmp_mem, old_mem);
623 if (unlikely(r)) {
624 goto out_cleanup;
625 }
626
627 /* move BO (in tmp_mem) to new_mem */
628 r = ttm_bo_move_ttm(bo, ctx, new_mem);
629out_cleanup:
630 ttm_bo_mem_put(bo, &tmp_mem);
631 return r;
632}
633
634/**
635 * amdgpu_move_ram_vram - Copy buffer from RAM to VRAM
636 *
637 * Called by amdgpu_bo_move().
638 */
639static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo, bool evict,
640 struct ttm_operation_ctx *ctx,
641 struct ttm_mem_reg *new_mem)
642{
643 struct ttm_mem_reg *old_mem = &bo->mem;
644 struct ttm_mem_reg tmp_mem;
645 struct ttm_placement placement;
646 struct ttm_place placements;
647 int r;
648
649 /* make space in GTT for old_mem buffer */
650 tmp_mem = *new_mem;
651 tmp_mem.mm_node = NULL;
652 placement.num_placement = 1;
653 placement.placement = &placements;
654 placement.num_busy_placement = 1;
655 placement.busy_placement = &placements;
656 placements.fpfn = 0;
657 placements.lpfn = 0;
658 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
659 r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
660 if (unlikely(r)) {
661 pr_err("Failed to find GTT space for blit to VRAM\n");
662 return r;
663 }
664
665 /* move/bind old memory to GTT space */
666 r = ttm_bo_move_ttm(bo, ctx, &tmp_mem);
667 if (unlikely(r)) {
668 goto out_cleanup;
669 }
670
671 /* copy to VRAM */
672 r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu, new_mem, old_mem);
673 if (unlikely(r)) {
674 goto out_cleanup;
675 }
676out_cleanup:
677 ttm_bo_mem_put(bo, &tmp_mem);
678 return r;
679}
680
681/**
682 * amdgpu_mem_visible - Check that memory can be accessed by ttm_bo_move_memcpy
683 *
684 * Called by amdgpu_bo_move()
685 */
686static bool amdgpu_mem_visible(struct amdgpu_device *adev,
687 struct ttm_mem_reg *mem)
688{
689 struct drm_mm_node *nodes = mem->mm_node;
690
691 if (mem->mem_type == TTM_PL_SYSTEM ||
692 mem->mem_type == TTM_PL_TT)
693 return true;
694 if (mem->mem_type != TTM_PL_VRAM)
695 return false;
696
697 /* ttm_mem_reg_ioremap only supports contiguous memory */
698 if (nodes->size != mem->num_pages)
699 return false;
700
701 return ((nodes->start + nodes->size) << PAGE_SHIFT)
702 <= adev->gmc.visible_vram_size;
703}
704
705/**
706 * amdgpu_bo_move - Move a buffer object to a new memory location
707 *
708 * Called by ttm_bo_handle_move_mem()
709 */
710static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict,
711 struct ttm_operation_ctx *ctx,
712 struct ttm_mem_reg *new_mem)
713{
714 struct amdgpu_device *adev;
715 struct amdgpu_bo *abo;
716 struct ttm_mem_reg *old_mem = &bo->mem;
717 int r;
718
719 /* Can't move a pinned BO */
720 abo = ttm_to_amdgpu_bo(bo);
721 if (WARN_ON_ONCE(abo->pin_count > 0))
722 return -EINVAL;
723
724 adev = amdgpu_ttm_adev(bo->bdev);
725
726 if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
727 amdgpu_move_null(bo, new_mem);
728 return 0;
729 }
730 if ((old_mem->mem_type == TTM_PL_TT &&
731 new_mem->mem_type == TTM_PL_SYSTEM) ||
732 (old_mem->mem_type == TTM_PL_SYSTEM &&
733 new_mem->mem_type == TTM_PL_TT)) {
734 /* bind is enough */
735 amdgpu_move_null(bo, new_mem);
736 return 0;
737 }
738 if (old_mem->mem_type == AMDGPU_PL_GDS ||
739 old_mem->mem_type == AMDGPU_PL_GWS ||
740 old_mem->mem_type == AMDGPU_PL_OA ||
741 new_mem->mem_type == AMDGPU_PL_GDS ||
742 new_mem->mem_type == AMDGPU_PL_GWS ||
743 new_mem->mem_type == AMDGPU_PL_OA) {
744 /* Nothing to save here */
745 amdgpu_move_null(bo, new_mem);
746 return 0;
747 }
748
749 if (!adev->mman.buffer_funcs_enabled) {
750 r = -ENODEV;
751 goto memcpy;
752 }
753
754 if (old_mem->mem_type == TTM_PL_VRAM &&
755 new_mem->mem_type == TTM_PL_SYSTEM) {
756 r = amdgpu_move_vram_ram(bo, evict, ctx, new_mem);
757 } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
758 new_mem->mem_type == TTM_PL_VRAM) {
759 r = amdgpu_move_ram_vram(bo, evict, ctx, new_mem);
760 } else {
761 r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu,
762 new_mem, old_mem);
763 }
764
765 if (r) {
766memcpy:
767 /* Check that all memory is CPU accessible */
768 if (!amdgpu_mem_visible(adev, old_mem) ||
769 !amdgpu_mem_visible(adev, new_mem)) {
770 pr_err("Move buffer fallback to memcpy unavailable\n");
771 return r;
772 }
773
774 r = ttm_bo_move_memcpy(bo, ctx, new_mem);
775 if (r)
776 return r;
777 }
778
779 if (bo->type == ttm_bo_type_device &&
780 new_mem->mem_type == TTM_PL_VRAM &&
781 old_mem->mem_type != TTM_PL_VRAM) {
782 /* amdgpu_bo_fault_reserve_notify will re-set this if the CPU
783 * accesses the BO after it's moved.
784 */
785 abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
786 }
787
788 /* update statistics */
789 atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved);
790 return 0;
791}
792
793/**
794 * amdgpu_ttm_io_mem_reserve - Reserve a block of memory during a fault
795 *
796 * Called by ttm_mem_io_reserve() ultimately via ttm_bo_vm_fault()
797 */
798static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
799{
800 struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
801 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
802 struct drm_mm_node *mm_node = mem->mm_node;
803
804 mem->bus.addr = NULL;
805 mem->bus.offset = 0;
806 mem->bus.size = mem->num_pages << PAGE_SHIFT;
807 mem->bus.base = 0;
808 mem->bus.is_iomem = false;
809 if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
810 return -EINVAL;
811 switch (mem->mem_type) {
812 case TTM_PL_SYSTEM:
813 /* system memory */
814 return 0;
815 case TTM_PL_TT:
816 break;
817 case TTM_PL_VRAM:
818 mem->bus.offset = mem->start << PAGE_SHIFT;
819 /* check if it's visible */
820 if ((mem->bus.offset + mem->bus.size) > adev->gmc.visible_vram_size)
821 return -EINVAL;
822 /* Only physically contiguous buffers apply. In a contiguous
823 * buffer, size of the first mm_node would match the number of
824 * pages in ttm_mem_reg.
825 */
826 if (adev->mman.aper_base_kaddr &&
827 (mm_node->size == mem->num_pages))
828 mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr +
829 mem->bus.offset;
830
831 mem->bus.base = adev->gmc.aper_base;
832 mem->bus.is_iomem = true;
833 break;
834 default:
835 return -EINVAL;
836 }
837 return 0;
838}
839
840static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo,
841 unsigned long page_offset)
842{
843 uint64_t offset = (page_offset << PAGE_SHIFT);
844 struct drm_mm_node *mm;
845
846 mm = amdgpu_find_mm_node(&bo->mem, &offset);
847 return (bo->mem.bus.base >> PAGE_SHIFT) + mm->start +
848 (offset >> PAGE_SHIFT);
849}
850
851/**
852 * amdgpu_ttm_domain_start - Returns GPU start address
853 * @adev: amdgpu device object
854 * @type: type of the memory
855 *
856 * Returns:
857 * GPU start address of a memory domain
858 */
859
860uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type)
861{
862 switch (type) {
863 case TTM_PL_TT:
864 return adev->gmc.gart_start;
865 case TTM_PL_VRAM:
866 return adev->gmc.vram_start;
867 }
868
869 return 0;
870}
871
872/*
873 * TTM backend functions.
874 */
875struct amdgpu_ttm_tt {
876 struct ttm_dma_tt ttm;
877 struct drm_gem_object *gobj;
878 u64 offset;
879 uint64_t userptr;
880 struct task_struct *usertask;
881 uint32_t userflags;
882#if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
883 struct hmm_range *range;
884#endif
885};
886
887#ifdef CONFIG_DRM_AMDGPU_USERPTR
888/**
889 * amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user
890 * memory and start HMM tracking CPU page table update
891 *
892 * Calling function must call amdgpu_ttm_tt_userptr_range_done() once and only
893 * once afterwards to stop HMM tracking
894 */
895int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages)
896{
897 struct ttm_tt *ttm = bo->tbo.ttm;
898 struct amdgpu_ttm_tt *gtt = (void *)ttm;
899 unsigned long start = gtt->userptr;
900 struct vm_area_struct *vma;
901 struct hmm_range *range;
902 unsigned long timeout;
903 struct mm_struct *mm;
904 unsigned long i;
905 int r = 0;
906
907 mm = bo->notifier.mm;
908 if (unlikely(!mm)) {
909 DRM_DEBUG_DRIVER("BO is not registered?\n");
910 return -EFAULT;
911 }
912
913 /* Another get_user_pages is running at the same time?? */
914 if (WARN_ON(gtt->range))
915 return -EFAULT;
916
917 if (!mmget_not_zero(mm)) /* Happens during process shutdown */
918 return -ESRCH;
919
920 range = kzalloc(sizeof(*range), GFP_KERNEL);
921 if (unlikely(!range)) {
922 r = -ENOMEM;
923 goto out;
924 }
925 range->notifier = &bo->notifier;
926 range->start = bo->notifier.interval_tree.start;
927 range->end = bo->notifier.interval_tree.last + 1;
928 range->default_flags = HMM_PFN_REQ_FAULT;
929 if (!amdgpu_ttm_tt_is_readonly(ttm))
930 range->default_flags |= HMM_PFN_REQ_WRITE;
931
932 range->hmm_pfns = kvmalloc_array(ttm->num_pages,
933 sizeof(*range->hmm_pfns), GFP_KERNEL);
934 if (unlikely(!range->hmm_pfns)) {
935 r = -ENOMEM;
936 goto out_free_ranges;
937 }
938
939 mmap_read_lock(mm);
940 vma = find_vma(mm, start);
941 if (unlikely(!vma || start < vma->vm_start)) {
942 r = -EFAULT;
943 goto out_unlock;
944 }
945 if (unlikely((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) &&
946 vma->vm_file)) {
947 r = -EPERM;
948 goto out_unlock;
949 }
950 mmap_read_unlock(mm);
951 timeout = jiffies + msecs_to_jiffies(HMM_RANGE_DEFAULT_TIMEOUT);
952
953retry:
954 range->notifier_seq = mmu_interval_read_begin(&bo->notifier);
955
956 mmap_read_lock(mm);
957 r = hmm_range_fault(range);
958 mmap_read_unlock(mm);
959 if (unlikely(r)) {
960 /*
961 * FIXME: This timeout should encompass the retry from
962 * mmu_interval_read_retry() as well.
963 */
964 if (r == -EBUSY && !time_after(jiffies, timeout))
965 goto retry;
966 goto out_free_pfns;
967 }
968
969 /*
970 * Due to default_flags, all pages are HMM_PFN_VALID or
971 * hmm_range_fault() fails. FIXME: The pages cannot be touched outside
972 * the notifier_lock, and mmu_interval_read_retry() must be done first.
973 */
974 for (i = 0; i < ttm->num_pages; i++)
975 pages[i] = hmm_pfn_to_page(range->hmm_pfns[i]);
976
977 gtt->range = range;
978 mmput(mm);
979
980 return 0;
981
982out_unlock:
983 mmap_read_unlock(mm);
984out_free_pfns:
985 kvfree(range->hmm_pfns);
986out_free_ranges:
987 kfree(range);
988out:
989 mmput(mm);
990 return r;
991}
992
993/**
994 * amdgpu_ttm_tt_userptr_range_done - stop HMM track the CPU page table change
995 * Check if the pages backing this ttm range have been invalidated
996 *
997 * Returns: true if pages are still valid
998 */
999bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm)
1000{
1001 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1002 bool r = false;
1003
1004 if (!gtt || !gtt->userptr)
1005 return false;
1006
1007 DRM_DEBUG_DRIVER("user_pages_done 0x%llx pages 0x%lx\n",
1008 gtt->userptr, ttm->num_pages);
1009
1010 WARN_ONCE(!gtt->range || !gtt->range->hmm_pfns,
1011 "No user pages to check\n");
1012
1013 if (gtt->range) {
1014 /*
1015 * FIXME: Must always hold notifier_lock for this, and must
1016 * not ignore the return code.
1017 */
1018 r = mmu_interval_read_retry(gtt->range->notifier,
1019 gtt->range->notifier_seq);
1020 kvfree(gtt->range->hmm_pfns);
1021 kfree(gtt->range);
1022 gtt->range = NULL;
1023 }
1024
1025 return !r;
1026}
1027#endif
1028
1029/**
1030 * amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary.
1031 *
1032 * Called by amdgpu_cs_list_validate(). This creates the page list
1033 * that backs user memory and will ultimately be mapped into the device
1034 * address space.
1035 */
1036void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages)
1037{
1038 unsigned long i;
1039
1040 for (i = 0; i < ttm->num_pages; ++i)
1041 ttm->pages[i] = pages ? pages[i] : NULL;
1042}
1043
1044/**
1045 * amdgpu_ttm_tt_pin_userptr - prepare the sg table with the user pages
1046 *
1047 * Called by amdgpu_ttm_backend_bind()
1048 **/
1049static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm)
1050{
1051 struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1052 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1053 int r;
1054
1055 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1056 enum dma_data_direction direction = write ?
1057 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
1058
1059 /* Allocate an SG array and squash pages into it */
1060 r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
1061 ttm->num_pages << PAGE_SHIFT,
1062 GFP_KERNEL);
1063 if (r)
1064 goto release_sg;
1065
1066 /* Map SG to device */
1067 r = dma_map_sgtable(adev->dev, ttm->sg, direction, 0);
1068 if (r)
1069 goto release_sg;
1070
1071 /* convert SG to linear array of pages and dma addresses */
1072 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
1073 gtt->ttm.dma_address, ttm->num_pages);
1074
1075 return 0;
1076
1077release_sg:
1078 kfree(ttm->sg);
1079 ttm->sg = NULL;
1080 return r;
1081}
1082
1083/**
1084 * amdgpu_ttm_tt_unpin_userptr - Unpin and unmap userptr pages
1085 */
1086static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
1087{
1088 struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1089 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1090
1091 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1092 enum dma_data_direction direction = write ?
1093 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
1094
1095 /* double check that we don't free the table twice */
1096 if (!ttm->sg->sgl)
1097 return;
1098
1099 /* unmap the pages mapped to the device */
1100 dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0);
1101 sg_free_table(ttm->sg);
1102
1103#if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
1104 if (gtt->range) {
1105 unsigned long i;
1106
1107 for (i = 0; i < ttm->num_pages; i++) {
1108 if (ttm->pages[i] !=
1109 hmm_pfn_to_page(gtt->range->hmm_pfns[i]))
1110 break;
1111 }
1112
1113 WARN((i == ttm->num_pages), "Missing get_user_page_done\n");
1114 }
1115#endif
1116}
1117
1118static int amdgpu_ttm_gart_bind(struct amdgpu_device *adev,
1119 struct ttm_buffer_object *tbo,
1120 uint64_t flags)
1121{
1122 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo);
1123 struct ttm_tt *ttm = tbo->ttm;
1124 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1125 int r;
1126
1127 if (amdgpu_bo_encrypted(abo))
1128 flags |= AMDGPU_PTE_TMZ;
1129
1130 if (abo->flags & AMDGPU_GEM_CREATE_CP_MQD_GFX9) {
1131 uint64_t page_idx = 1;
1132
1133 r = amdgpu_gart_bind(adev, gtt->offset, page_idx,
1134 ttm->pages, gtt->ttm.dma_address, flags);
1135 if (r)
1136 goto gart_bind_fail;
1137
1138 /* The memory type of the first page defaults to UC. Now
1139 * modify the memory type to NC from the second page of
1140 * the BO onward.
1141 */
1142 flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK;
1143 flags |= AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_NC);
1144
1145 r = amdgpu_gart_bind(adev,
1146 gtt->offset + (page_idx << PAGE_SHIFT),
1147 ttm->num_pages - page_idx,
1148 &ttm->pages[page_idx],
1149 &(gtt->ttm.dma_address[page_idx]), flags);
1150 } else {
1151 r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
1152 ttm->pages, gtt->ttm.dma_address, flags);
1153 }
1154
1155gart_bind_fail:
1156 if (r)
1157 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
1158 ttm->num_pages, gtt->offset);
1159
1160 return r;
1161}
1162
1163/**
1164 * amdgpu_ttm_backend_bind - Bind GTT memory
1165 *
1166 * Called by ttm_tt_bind() on behalf of ttm_bo_handle_move_mem().
1167 * This handles binding GTT memory to the device address space.
1168 */
1169static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm,
1170 struct ttm_mem_reg *bo_mem)
1171{
1172 struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1173 struct amdgpu_ttm_tt *gtt = (void*)ttm;
1174 uint64_t flags;
1175 int r = 0;
1176
1177 if (gtt->userptr) {
1178 r = amdgpu_ttm_tt_pin_userptr(ttm);
1179 if (r) {
1180 DRM_ERROR("failed to pin userptr\n");
1181 return r;
1182 }
1183 }
1184 if (!ttm->num_pages) {
1185 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
1186 ttm->num_pages, bo_mem, ttm);
1187 }
1188
1189 if (bo_mem->mem_type == AMDGPU_PL_GDS ||
1190 bo_mem->mem_type == AMDGPU_PL_GWS ||
1191 bo_mem->mem_type == AMDGPU_PL_OA)
1192 return -EINVAL;
1193
1194 if (!amdgpu_gtt_mgr_has_gart_addr(bo_mem)) {
1195 gtt->offset = AMDGPU_BO_INVALID_OFFSET;
1196 return 0;
1197 }
1198
1199 /* compute PTE flags relevant to this BO memory */
1200 flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem);
1201
1202 /* bind pages into GART page tables */
1203 gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
1204 r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
1205 ttm->pages, gtt->ttm.dma_address, flags);
1206
1207 if (r)
1208 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
1209 ttm->num_pages, gtt->offset);
1210 return r;
1211}
1212
1213/**
1214 * amdgpu_ttm_alloc_gart - Allocate GART memory for buffer object
1215 */
1216int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
1217{
1218 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
1219 struct ttm_operation_ctx ctx = { false, false };
1220 struct amdgpu_ttm_tt *gtt = (void*)bo->ttm;
1221 struct ttm_mem_reg tmp;
1222 struct ttm_placement placement;
1223 struct ttm_place placements;
1224 uint64_t addr, flags;
1225 int r;
1226
1227 if (bo->mem.start != AMDGPU_BO_INVALID_OFFSET)
1228 return 0;
1229
1230 addr = amdgpu_gmc_agp_addr(bo);
1231 if (addr != AMDGPU_BO_INVALID_OFFSET) {
1232 bo->mem.start = addr >> PAGE_SHIFT;
1233 } else {
1234
1235 /* allocate GART space */
1236 tmp = bo->mem;
1237 tmp.mm_node = NULL;
1238 placement.num_placement = 1;
1239 placement.placement = &placements;
1240 placement.num_busy_placement = 1;
1241 placement.busy_placement = &placements;
1242 placements.fpfn = 0;
1243 placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
1244 placements.flags = (bo->mem.placement & ~TTM_PL_MASK_MEM) |
1245 TTM_PL_FLAG_TT;
1246
1247 r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx);
1248 if (unlikely(r))
1249 return r;
1250
1251 /* compute PTE flags for this buffer object */
1252 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, &tmp);
1253
1254 /* Bind pages */
1255 gtt->offset = (u64)tmp.start << PAGE_SHIFT;
1256 r = amdgpu_ttm_gart_bind(adev, bo, flags);
1257 if (unlikely(r)) {
1258 ttm_bo_mem_put(bo, &tmp);
1259 return r;
1260 }
1261
1262 ttm_bo_mem_put(bo, &bo->mem);
1263 bo->mem = tmp;
1264 }
1265
1266 return 0;
1267}
1268
1269/**
1270 * amdgpu_ttm_recover_gart - Rebind GTT pages
1271 *
1272 * Called by amdgpu_gtt_mgr_recover() from amdgpu_device_reset() to
1273 * rebind GTT pages during a GPU reset.
1274 */
1275int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo)
1276{
1277 struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
1278 uint64_t flags;
1279 int r;
1280
1281 if (!tbo->ttm)
1282 return 0;
1283
1284 flags = amdgpu_ttm_tt_pte_flags(adev, tbo->ttm, &tbo->mem);
1285 r = amdgpu_ttm_gart_bind(adev, tbo, flags);
1286
1287 return r;
1288}
1289
1290/**
1291 * amdgpu_ttm_backend_unbind - Unbind GTT mapped pages
1292 *
1293 * Called by ttm_tt_unbind() on behalf of ttm_bo_move_ttm() and
1294 * ttm_tt_destroy().
1295 */
1296static void amdgpu_ttm_backend_unbind(struct ttm_tt *ttm)
1297{
1298 struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1299 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1300 int r;
1301
1302 /* if the pages have userptr pinning then clear that first */
1303 if (gtt->userptr)
1304 amdgpu_ttm_tt_unpin_userptr(ttm);
1305
1306 if (gtt->offset == AMDGPU_BO_INVALID_OFFSET)
1307 return;
1308
1309 /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
1310 r = amdgpu_gart_unbind(adev, gtt->offset, ttm->num_pages);
1311 if (r)
1312 DRM_ERROR("failed to unbind %lu pages at 0x%08llX\n",
1313 gtt->ttm.ttm.num_pages, gtt->offset);
1314}
1315
1316static void amdgpu_ttm_backend_destroy(struct ttm_tt *ttm)
1317{
1318 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1319
1320 if (gtt->usertask)
1321 put_task_struct(gtt->usertask);
1322
1323 ttm_dma_tt_fini(>t->ttm);
1324 kfree(gtt);
1325}
1326
1327static struct ttm_backend_func amdgpu_backend_func = {
1328 .bind = &amdgpu_ttm_backend_bind,
1329 .unbind = &amdgpu_ttm_backend_unbind,
1330 .destroy = &amdgpu_ttm_backend_destroy,
1331};
1332
1333/**
1334 * amdgpu_ttm_tt_create - Create a ttm_tt object for a given BO
1335 *
1336 * @bo: The buffer object to create a GTT ttm_tt object around
1337 *
1338 * Called by ttm_tt_create().
1339 */
1340static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo,
1341 uint32_t page_flags)
1342{
1343 struct amdgpu_ttm_tt *gtt;
1344
1345 gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
1346 if (gtt == NULL) {
1347 return NULL;
1348 }
1349 gtt->ttm.ttm.func = &amdgpu_backend_func;
1350 gtt->gobj = &bo->base;
1351
1352 /* allocate space for the uninitialized page entries */
1353 if (ttm_sg_tt_init(>t->ttm, bo, page_flags)) {
1354 kfree(gtt);
1355 return NULL;
1356 }
1357 return >t->ttm.ttm;
1358}
1359
1360/**
1361 * amdgpu_ttm_tt_populate - Map GTT pages visible to the device
1362 *
1363 * Map the pages of a ttm_tt object to an address space visible
1364 * to the underlying device.
1365 */
1366static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm,
1367 struct ttm_operation_ctx *ctx)
1368{
1369 struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1370 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1371
1372 /* user pages are bound by amdgpu_ttm_tt_pin_userptr() */
1373 if (gtt && gtt->userptr) {
1374 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
1375 if (!ttm->sg)
1376 return -ENOMEM;
1377
1378 ttm->page_flags |= TTM_PAGE_FLAG_SG;
1379 ttm->state = tt_unbound;
1380 return 0;
1381 }
1382
1383 if (ttm->page_flags & TTM_PAGE_FLAG_SG) {
1384 if (!ttm->sg) {
1385 struct dma_buf_attachment *attach;
1386 struct sg_table *sgt;
1387
1388 attach = gtt->gobj->import_attach;
1389 sgt = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL);
1390 if (IS_ERR(sgt))
1391 return PTR_ERR(sgt);
1392
1393 ttm->sg = sgt;
1394 }
1395
1396 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
1397 gtt->ttm.dma_address,
1398 ttm->num_pages);
1399 ttm->state = tt_unbound;
1400 return 0;
1401 }
1402
1403#ifdef CONFIG_SWIOTLB
1404 if (adev->need_swiotlb && swiotlb_nr_tbl()) {
1405 return ttm_dma_populate(>t->ttm, adev->dev, ctx);
1406 }
1407#endif
1408
1409 /* fall back to generic helper to populate the page array
1410 * and map them to the device */
1411 return ttm_populate_and_map_pages(adev->dev, >t->ttm, ctx);
1412}
1413
1414/**
1415 * amdgpu_ttm_tt_unpopulate - unmap GTT pages and unpopulate page arrays
1416 *
1417 * Unmaps pages of a ttm_tt object from the device address space and
1418 * unpopulates the page array backing it.
1419 */
1420static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm)
1421{
1422 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1423 struct amdgpu_device *adev;
1424
1425 if (gtt && gtt->userptr) {
1426 amdgpu_ttm_tt_set_user_pages(ttm, NULL);
1427 kfree(ttm->sg);
1428 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
1429 return;
1430 }
1431
1432 if (ttm->sg && gtt->gobj->import_attach) {
1433 struct dma_buf_attachment *attach;
1434
1435 attach = gtt->gobj->import_attach;
1436 dma_buf_unmap_attachment(attach, ttm->sg, DMA_BIDIRECTIONAL);
1437 ttm->sg = NULL;
1438 return;
1439 }
1440
1441 if (ttm->page_flags & TTM_PAGE_FLAG_SG)
1442 return;
1443
1444 adev = amdgpu_ttm_adev(ttm->bdev);
1445
1446#ifdef CONFIG_SWIOTLB
1447 if (adev->need_swiotlb && swiotlb_nr_tbl()) {
1448 ttm_dma_unpopulate(>t->ttm, adev->dev);
1449 return;
1450 }
1451#endif
1452
1453 /* fall back to generic helper to unmap and unpopulate array */
1454 ttm_unmap_and_unpopulate_pages(adev->dev, >t->ttm);
1455}
1456
1457/**
1458 * amdgpu_ttm_tt_set_userptr - Initialize userptr GTT ttm_tt for the current
1459 * task
1460 *
1461 * @ttm: The ttm_tt object to bind this userptr object to
1462 * @addr: The address in the current tasks VM space to use
1463 * @flags: Requirements of userptr object.
1464 *
1465 * Called by amdgpu_gem_userptr_ioctl() to bind userptr pages
1466 * to current task
1467 */
1468int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
1469 uint32_t flags)
1470{
1471 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1472
1473 if (gtt == NULL)
1474 return -EINVAL;
1475
1476 gtt->userptr = addr;
1477 gtt->userflags = flags;
1478
1479 if (gtt->usertask)
1480 put_task_struct(gtt->usertask);
1481 gtt->usertask = current->group_leader;
1482 get_task_struct(gtt->usertask);
1483
1484 return 0;
1485}
1486
1487/**
1488 * amdgpu_ttm_tt_get_usermm - Return memory manager for ttm_tt object
1489 */
1490struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
1491{
1492 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1493
1494 if (gtt == NULL)
1495 return NULL;
1496
1497 if (gtt->usertask == NULL)
1498 return NULL;
1499
1500 return gtt->usertask->mm;
1501}
1502
1503/**
1504 * amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an
1505 * address range for the current task.
1506 *
1507 */
1508bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
1509 unsigned long end)
1510{
1511 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1512 unsigned long size;
1513
1514 if (gtt == NULL || !gtt->userptr)
1515 return false;
1516
1517 /* Return false if no part of the ttm_tt object lies within
1518 * the range
1519 */
1520 size = (unsigned long)gtt->ttm.ttm.num_pages * PAGE_SIZE;
1521 if (gtt->userptr > end || gtt->userptr + size <= start)
1522 return false;
1523
1524 return true;
1525}
1526
1527/**
1528 * amdgpu_ttm_tt_is_userptr - Have the pages backing by userptr?
1529 */
1530bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm)
1531{
1532 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1533
1534 if (gtt == NULL || !gtt->userptr)
1535 return false;
1536
1537 return true;
1538}
1539
1540/**
1541 * amdgpu_ttm_tt_is_readonly - Is the ttm_tt object read only?
1542 */
1543bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
1544{
1545 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1546
1547 if (gtt == NULL)
1548 return false;
1549
1550 return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1551}
1552
1553/**
1554 * amdgpu_ttm_tt_pde_flags - Compute PDE flags for ttm_tt object
1555 *
1556 * @ttm: The ttm_tt object to compute the flags for
1557 * @mem: The memory registry backing this ttm_tt object
1558 *
1559 * Figure out the flags to use for a VM PDE (Page Directory Entry).
1560 */
1561uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_mem_reg *mem)
1562{
1563 uint64_t flags = 0;
1564
1565 if (mem && mem->mem_type != TTM_PL_SYSTEM)
1566 flags |= AMDGPU_PTE_VALID;
1567
1568 if (mem && mem->mem_type == TTM_PL_TT) {
1569 flags |= AMDGPU_PTE_SYSTEM;
1570
1571 if (ttm->caching_state == tt_cached)
1572 flags |= AMDGPU_PTE_SNOOPED;
1573 }
1574
1575 return flags;
1576}
1577
1578/**
1579 * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object
1580 *
1581 * @ttm: The ttm_tt object to compute the flags for
1582 * @mem: The memory registry backing this ttm_tt object
1583
1584 * Figure out the flags to use for a VM PTE (Page Table Entry).
1585 */
1586uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
1587 struct ttm_mem_reg *mem)
1588{
1589 uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem);
1590
1591 flags |= adev->gart.gart_pte_flags;
1592 flags |= AMDGPU_PTE_READABLE;
1593
1594 if (!amdgpu_ttm_tt_is_readonly(ttm))
1595 flags |= AMDGPU_PTE_WRITEABLE;
1596
1597 return flags;
1598}
1599
1600/**
1601 * amdgpu_ttm_bo_eviction_valuable - Check to see if we can evict a buffer
1602 * object.
1603 *
1604 * Return true if eviction is sensible. Called by ttm_mem_evict_first() on
1605 * behalf of ttm_bo_mem_force_space() which tries to evict buffer objects until
1606 * it can find space for a new object and by ttm_bo_force_list_clean() which is
1607 * used to clean out a memory space.
1608 */
1609static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
1610 const struct ttm_place *place)
1611{
1612 unsigned long num_pages = bo->mem.num_pages;
1613 struct drm_mm_node *node = bo->mem.mm_node;
1614 struct dma_resv_list *flist;
1615 struct dma_fence *f;
1616 int i;
1617
1618 if (bo->type == ttm_bo_type_kernel &&
1619 !amdgpu_vm_evictable(ttm_to_amdgpu_bo(bo)))
1620 return false;
1621
1622 /* If bo is a KFD BO, check if the bo belongs to the current process.
1623 * If true, then return false as any KFD process needs all its BOs to
1624 * be resident to run successfully
1625 */
1626 flist = dma_resv_get_list(bo->base.resv);
1627 if (flist) {
1628 for (i = 0; i < flist->shared_count; ++i) {
1629 f = rcu_dereference_protected(flist->shared[i],
1630 dma_resv_held(bo->base.resv));
1631 if (amdkfd_fence_check_mm(f, current->mm))
1632 return false;
1633 }
1634 }
1635
1636 switch (bo->mem.mem_type) {
1637 case TTM_PL_TT:
1638 if (amdgpu_bo_is_amdgpu_bo(bo) &&
1639 amdgpu_bo_encrypted(ttm_to_amdgpu_bo(bo)))
1640 return false;
1641 return true;
1642
1643 case TTM_PL_VRAM:
1644 /* Check each drm MM node individually */
1645 while (num_pages) {
1646 if (place->fpfn < (node->start + node->size) &&
1647 !(place->lpfn && place->lpfn <= node->start))
1648 return true;
1649
1650 num_pages -= node->size;
1651 ++node;
1652 }
1653 return false;
1654
1655 default:
1656 break;
1657 }
1658
1659 return ttm_bo_eviction_valuable(bo, place);
1660}
1661
1662/**
1663 * amdgpu_ttm_access_memory - Read or Write memory that backs a buffer object.
1664 *
1665 * @bo: The buffer object to read/write
1666 * @offset: Offset into buffer object
1667 * @buf: Secondary buffer to write/read from
1668 * @len: Length in bytes of access
1669 * @write: true if writing
1670 *
1671 * This is used to access VRAM that backs a buffer object via MMIO
1672 * access for debugging purposes.
1673 */
1674static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo,
1675 unsigned long offset,
1676 void *buf, int len, int write)
1677{
1678 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1679 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
1680 struct drm_mm_node *nodes;
1681 uint32_t value = 0;
1682 int ret = 0;
1683 uint64_t pos;
1684 unsigned long flags;
1685
1686 if (bo->mem.mem_type != TTM_PL_VRAM)
1687 return -EIO;
1688
1689 pos = offset;
1690 nodes = amdgpu_find_mm_node(&abo->tbo.mem, &pos);
1691 pos += (nodes->start << PAGE_SHIFT);
1692
1693 while (len && pos < adev->gmc.mc_vram_size) {
1694 uint64_t aligned_pos = pos & ~(uint64_t)3;
1695 uint64_t bytes = 4 - (pos & 3);
1696 uint32_t shift = (pos & 3) * 8;
1697 uint32_t mask = 0xffffffff << shift;
1698
1699 if (len < bytes) {
1700 mask &= 0xffffffff >> (bytes - len) * 8;
1701 bytes = len;
1702 }
1703
1704 if (mask != 0xffffffff) {
1705 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1706 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)aligned_pos) | 0x80000000);
1707 WREG32_NO_KIQ(mmMM_INDEX_HI, aligned_pos >> 31);
1708 if (!write || mask != 0xffffffff)
1709 value = RREG32_NO_KIQ(mmMM_DATA);
1710 if (write) {
1711 value &= ~mask;
1712 value |= (*(uint32_t *)buf << shift) & mask;
1713 WREG32_NO_KIQ(mmMM_DATA, value);
1714 }
1715 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1716 if (!write) {
1717 value = (value & mask) >> shift;
1718 memcpy(buf, &value, bytes);
1719 }
1720 } else {
1721 bytes = (nodes->start + nodes->size) << PAGE_SHIFT;
1722 bytes = min(bytes - pos, (uint64_t)len & ~0x3ull);
1723
1724 amdgpu_device_vram_access(adev, pos, (uint32_t *)buf,
1725 bytes, write);
1726 }
1727
1728 ret += bytes;
1729 buf = (uint8_t *)buf + bytes;
1730 pos += bytes;
1731 len -= bytes;
1732 if (pos >= (nodes->start + nodes->size) << PAGE_SHIFT) {
1733 ++nodes;
1734 pos = (nodes->start << PAGE_SHIFT);
1735 }
1736 }
1737
1738 return ret;
1739}
1740
1741static struct ttm_bo_driver amdgpu_bo_driver = {
1742 .ttm_tt_create = &amdgpu_ttm_tt_create,
1743 .ttm_tt_populate = &amdgpu_ttm_tt_populate,
1744 .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
1745 .init_mem_type = &amdgpu_init_mem_type,
1746 .eviction_valuable = amdgpu_ttm_bo_eviction_valuable,
1747 .evict_flags = &amdgpu_evict_flags,
1748 .move = &amdgpu_bo_move,
1749 .verify_access = &amdgpu_verify_access,
1750 .move_notify = &amdgpu_bo_move_notify,
1751 .release_notify = &amdgpu_bo_release_notify,
1752 .fault_reserve_notify = &amdgpu_bo_fault_reserve_notify,
1753 .io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
1754 .io_mem_pfn = amdgpu_ttm_io_mem_pfn,
1755 .access_memory = &amdgpu_ttm_access_memory,
1756 .del_from_lru_notify = &amdgpu_vm_del_from_lru_notify
1757};
1758
1759/*
1760 * Firmware Reservation functions
1761 */
1762/**
1763 * amdgpu_ttm_fw_reserve_vram_fini - free fw reserved vram
1764 *
1765 * @adev: amdgpu_device pointer
1766 *
1767 * free fw reserved vram if it has been reserved.
1768 */
1769static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev)
1770{
1771 amdgpu_bo_free_kernel(&adev->fw_vram_usage.reserved_bo,
1772 NULL, &adev->fw_vram_usage.va);
1773}
1774
1775/**
1776 * amdgpu_ttm_fw_reserve_vram_init - create bo vram reservation from fw
1777 *
1778 * @adev: amdgpu_device pointer
1779 *
1780 * create bo vram reservation from fw.
1781 */
1782static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev)
1783{
1784 uint64_t vram_size = adev->gmc.visible_vram_size;
1785
1786 adev->fw_vram_usage.va = NULL;
1787 adev->fw_vram_usage.reserved_bo = NULL;
1788
1789 if (adev->fw_vram_usage.size == 0 ||
1790 adev->fw_vram_usage.size > vram_size)
1791 return 0;
1792
1793 return amdgpu_bo_create_kernel_at(adev,
1794 adev->fw_vram_usage.start_offset,
1795 adev->fw_vram_usage.size,
1796 AMDGPU_GEM_DOMAIN_VRAM,
1797 &adev->fw_vram_usage.reserved_bo,
1798 &adev->fw_vram_usage.va);
1799}
1800
1801/*
1802 * Memoy training reservation functions
1803 */
1804
1805/**
1806 * amdgpu_ttm_training_reserve_vram_fini - free memory training reserved vram
1807 *
1808 * @adev: amdgpu_device pointer
1809 *
1810 * free memory training reserved vram if it has been reserved.
1811 */
1812static int amdgpu_ttm_training_reserve_vram_fini(struct amdgpu_device *adev)
1813{
1814 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1815
1816 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
1817 amdgpu_bo_free_kernel(&ctx->c2p_bo, NULL, NULL);
1818 ctx->c2p_bo = NULL;
1819
1820 return 0;
1821}
1822
1823static void amdgpu_ttm_training_data_block_init(struct amdgpu_device *adev)
1824{
1825 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1826
1827 memset(ctx, 0, sizeof(*ctx));
1828
1829 ctx->c2p_train_data_offset =
1830 ALIGN((adev->gmc.mc_vram_size - adev->discovery_tmr_size - SZ_1M), SZ_1M);
1831 ctx->p2c_train_data_offset =
1832 (adev->gmc.mc_vram_size - GDDR6_MEM_TRAINING_OFFSET);
1833 ctx->train_data_size =
1834 GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES;
1835
1836 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
1837 ctx->train_data_size,
1838 ctx->p2c_train_data_offset,
1839 ctx->c2p_train_data_offset);
1840}
1841
1842/*
1843 * reserve TMR memory at the top of VRAM which holds
1844 * IP Discovery data and is protected by PSP.
1845 */
1846static int amdgpu_ttm_reserve_tmr(struct amdgpu_device *adev)
1847{
1848 int ret;
1849 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1850 bool mem_train_support = false;
1851
1852 if (!amdgpu_sriov_vf(adev)) {
1853 ret = amdgpu_mem_train_support(adev);
1854 if (ret == 1)
1855 mem_train_support = true;
1856 else if (ret == -1)
1857 return -EINVAL;
1858 else
1859 DRM_DEBUG("memory training does not support!\n");
1860 }
1861
1862 /*
1863 * Query reserved tmr size through atom firmwareinfo for Sienna_Cichlid and onwards for all
1864 * the use cases (IP discovery/G6 memory training/profiling/diagnostic data.etc)
1865 *
1866 * Otherwise, fallback to legacy approach to check and reserve tmr block for ip
1867 * discovery data and G6 memory training data respectively
1868 */
1869 adev->discovery_tmr_size =
1870 amdgpu_atomfirmware_get_fw_reserved_fb_size(adev);
1871 if (!adev->discovery_tmr_size)
1872 adev->discovery_tmr_size = DISCOVERY_TMR_OFFSET;
1873
1874 if (mem_train_support) {
1875 /* reserve vram for mem train according to TMR location */
1876 amdgpu_ttm_training_data_block_init(adev);
1877 ret = amdgpu_bo_create_kernel_at(adev,
1878 ctx->c2p_train_data_offset,
1879 ctx->train_data_size,
1880 AMDGPU_GEM_DOMAIN_VRAM,
1881 &ctx->c2p_bo,
1882 NULL);
1883 if (ret) {
1884 DRM_ERROR("alloc c2p_bo failed(%d)!\n", ret);
1885 amdgpu_ttm_training_reserve_vram_fini(adev);
1886 return ret;
1887 }
1888 ctx->init = PSP_MEM_TRAIN_RESERVE_SUCCESS;
1889 }
1890
1891 ret = amdgpu_bo_create_kernel_at(adev,
1892 adev->gmc.real_vram_size - adev->discovery_tmr_size,
1893 adev->discovery_tmr_size,
1894 AMDGPU_GEM_DOMAIN_VRAM,
1895 &adev->discovery_memory,
1896 NULL);
1897 if (ret) {
1898 DRM_ERROR("alloc tmr failed(%d)!\n", ret);
1899 amdgpu_bo_free_kernel(&adev->discovery_memory, NULL, NULL);
1900 return ret;
1901 }
1902
1903 return 0;
1904}
1905
1906/**
1907 * amdgpu_ttm_init - Init the memory management (ttm) as well as various
1908 * gtt/vram related fields.
1909 *
1910 * This initializes all of the memory space pools that the TTM layer
1911 * will need such as the GTT space (system memory mapped to the device),
1912 * VRAM (on-board memory), and on-chip memories (GDS, GWS, OA) which
1913 * can be mapped per VMID.
1914 */
1915int amdgpu_ttm_init(struct amdgpu_device *adev)
1916{
1917 uint64_t gtt_size;
1918 int r;
1919 u64 vis_vram_limit;
1920 void *stolen_vga_buf;
1921
1922 mutex_init(&adev->mman.gtt_window_lock);
1923
1924 /* No others user of address space so set it to 0 */
1925 r = ttm_bo_device_init(&adev->mman.bdev,
1926 &amdgpu_bo_driver,
1927 adev->ddev->anon_inode->i_mapping,
1928 adev->ddev->vma_offset_manager,
1929 dma_addressing_limited(adev->dev));
1930 if (r) {
1931 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
1932 return r;
1933 }
1934 adev->mman.initialized = true;
1935
1936 /* We opt to avoid OOM on system pages allocations */
1937 adev->mman.bdev.no_retry = true;
1938
1939 /* Initialize VRAM pool with all of VRAM divided into pages */
1940 r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_VRAM,
1941 adev->gmc.real_vram_size >> PAGE_SHIFT);
1942 if (r) {
1943 DRM_ERROR("Failed initializing VRAM heap.\n");
1944 return r;
1945 }
1946
1947 /* Reduce size of CPU-visible VRAM if requested */
1948 vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024;
1949 if (amdgpu_vis_vram_limit > 0 &&
1950 vis_vram_limit <= adev->gmc.visible_vram_size)
1951 adev->gmc.visible_vram_size = vis_vram_limit;
1952
1953 /* Change the size here instead of the init above so only lpfn is affected */
1954 amdgpu_ttm_set_buffer_funcs_status(adev, false);
1955#ifdef CONFIG_64BIT
1956 adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base,
1957 adev->gmc.visible_vram_size);
1958#endif
1959
1960 /*
1961 *The reserved vram for firmware must be pinned to the specified
1962 *place on the VRAM, so reserve it early.
1963 */
1964 r = amdgpu_ttm_fw_reserve_vram_init(adev);
1965 if (r) {
1966 return r;
1967 }
1968
1969 /*
1970 * only NAVI10 and onwards ASIC support for IP discovery.
1971 * If IP discovery enabled, a block of memory should be
1972 * reserved for IP discovey.
1973 */
1974 if (adev->discovery_bin) {
1975 r = amdgpu_ttm_reserve_tmr(adev);
1976 if (r)
1977 return r;
1978 }
1979
1980 /* allocate memory as required for VGA
1981 * This is used for VGA emulation and pre-OS scanout buffers to
1982 * avoid display artifacts while transitioning between pre-OS
1983 * and driver. */
1984 r = amdgpu_bo_create_kernel(adev, adev->gmc.stolen_size, PAGE_SIZE,
1985 AMDGPU_GEM_DOMAIN_VRAM,
1986 &adev->stolen_vga_memory,
1987 NULL, &stolen_vga_buf);
1988 if (r)
1989 return r;
1990
1991 DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
1992 (unsigned) (adev->gmc.real_vram_size / (1024 * 1024)));
1993
1994 /* Compute GTT size, either bsaed on 3/4th the size of RAM size
1995 * or whatever the user passed on module init */
1996 if (amdgpu_gtt_size == -1) {
1997 struct sysinfo si;
1998
1999 si_meminfo(&si);
2000 gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
2001 adev->gmc.mc_vram_size),
2002 ((uint64_t)si.totalram * si.mem_unit * 3/4));
2003 }
2004 else
2005 gtt_size = (uint64_t)amdgpu_gtt_size << 20;
2006
2007 /* Initialize GTT memory pool */
2008 r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_TT, gtt_size >> PAGE_SHIFT);
2009 if (r) {
2010 DRM_ERROR("Failed initializing GTT heap.\n");
2011 return r;
2012 }
2013 DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
2014 (unsigned)(gtt_size / (1024 * 1024)));
2015
2016 /* Initialize various on-chip memory pools */
2017 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GDS,
2018 adev->gds.gds_size);
2019 if (r) {
2020 DRM_ERROR("Failed initializing GDS heap.\n");
2021 return r;
2022 }
2023
2024 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GWS,
2025 adev->gds.gws_size);
2026 if (r) {
2027 DRM_ERROR("Failed initializing gws heap.\n");
2028 return r;
2029 }
2030
2031 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_OA,
2032 adev->gds.oa_size);
2033 if (r) {
2034 DRM_ERROR("Failed initializing oa heap.\n");
2035 return r;
2036 }
2037
2038 return 0;
2039}
2040
2041/**
2042 * amdgpu_ttm_late_init - Handle any late initialization for amdgpu_ttm
2043 */
2044void amdgpu_ttm_late_init(struct amdgpu_device *adev)
2045{
2046 void *stolen_vga_buf;
2047 /* return the VGA stolen memory (if any) back to VRAM */
2048 amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, &stolen_vga_buf);
2049}
2050
2051/**
2052 * amdgpu_ttm_fini - De-initialize the TTM memory pools
2053 */
2054void amdgpu_ttm_fini(struct amdgpu_device *adev)
2055{
2056 if (!adev->mman.initialized)
2057 return;
2058
2059 amdgpu_ttm_training_reserve_vram_fini(adev);
2060 /* return the IP Discovery TMR memory back to VRAM */
2061 amdgpu_bo_free_kernel(&adev->discovery_memory, NULL, NULL);
2062 amdgpu_ttm_fw_reserve_vram_fini(adev);
2063
2064 if (adev->mman.aper_base_kaddr)
2065 iounmap(adev->mman.aper_base_kaddr);
2066 adev->mman.aper_base_kaddr = NULL;
2067
2068 ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_VRAM);
2069 ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_TT);
2070 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GDS);
2071 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GWS);
2072 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_OA);
2073 ttm_bo_device_release(&adev->mman.bdev);
2074 adev->mman.initialized = false;
2075 DRM_INFO("amdgpu: ttm finalized\n");
2076}
2077
2078/**
2079 * amdgpu_ttm_set_buffer_funcs_status - enable/disable use of buffer functions
2080 *
2081 * @adev: amdgpu_device pointer
2082 * @enable: true when we can use buffer functions.
2083 *
2084 * Enable/disable use of buffer functions during suspend/resume. This should
2085 * only be called at bootup or when userspace isn't running.
2086 */
2087void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
2088{
2089 struct ttm_mem_type_manager *man = &adev->mman.bdev.man[TTM_PL_VRAM];
2090 uint64_t size;
2091 int r;
2092
2093 if (!adev->mman.initialized || adev->in_gpu_reset ||
2094 adev->mman.buffer_funcs_enabled == enable)
2095 return;
2096
2097 if (enable) {
2098 struct amdgpu_ring *ring;
2099 struct drm_gpu_scheduler *sched;
2100
2101 ring = adev->mman.buffer_funcs_ring;
2102 sched = &ring->sched;
2103 r = drm_sched_entity_init(&adev->mman.entity,
2104 DRM_SCHED_PRIORITY_KERNEL, &sched,
2105 1, NULL);
2106 if (r) {
2107 DRM_ERROR("Failed setting up TTM BO move entity (%d)\n",
2108 r);
2109 return;
2110 }
2111 } else {
2112 drm_sched_entity_destroy(&adev->mman.entity);
2113 dma_fence_put(man->move);
2114 man->move = NULL;
2115 }
2116
2117 /* this just adjusts TTM size idea, which sets lpfn to the correct value */
2118 if (enable)
2119 size = adev->gmc.real_vram_size;
2120 else
2121 size = adev->gmc.visible_vram_size;
2122 man->size = size >> PAGE_SHIFT;
2123 adev->mman.buffer_funcs_enabled = enable;
2124}
2125
2126int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma)
2127{
2128 struct drm_file *file_priv = filp->private_data;
2129 struct amdgpu_device *adev = file_priv->minor->dev->dev_private;
2130
2131 if (adev == NULL)
2132 return -EINVAL;
2133
2134 return ttm_bo_mmap(filp, vma, &adev->mman.bdev);
2135}
2136
2137int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
2138 uint64_t dst_offset, uint32_t byte_count,
2139 struct dma_resv *resv,
2140 struct dma_fence **fence, bool direct_submit,
2141 bool vm_needs_flush, bool tmz)
2142{
2143 enum amdgpu_ib_pool_type pool = direct_submit ? AMDGPU_IB_POOL_DIRECT :
2144 AMDGPU_IB_POOL_DELAYED;
2145 struct amdgpu_device *adev = ring->adev;
2146 struct amdgpu_job *job;
2147
2148 uint32_t max_bytes;
2149 unsigned num_loops, num_dw;
2150 unsigned i;
2151 int r;
2152
2153 if (direct_submit && !ring->sched.ready) {
2154 DRM_ERROR("Trying to move memory with ring turned off.\n");
2155 return -EINVAL;
2156 }
2157
2158 max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
2159 num_loops = DIV_ROUND_UP(byte_count, max_bytes);
2160 num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->copy_num_dw, 8);
2161
2162 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, pool, &job);
2163 if (r)
2164 return r;
2165
2166 if (vm_needs_flush) {
2167 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo);
2168 job->vm_needs_flush = true;
2169 }
2170 if (resv) {
2171 r = amdgpu_sync_resv(adev, &job->sync, resv,
2172 AMDGPU_SYNC_ALWAYS,
2173 AMDGPU_FENCE_OWNER_UNDEFINED);
2174 if (r) {
2175 DRM_ERROR("sync failed (%d).\n", r);
2176 goto error_free;
2177 }
2178 }
2179
2180 for (i = 0; i < num_loops; i++) {
2181 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
2182
2183 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
2184 dst_offset, cur_size_in_bytes, tmz);
2185
2186 src_offset += cur_size_in_bytes;
2187 dst_offset += cur_size_in_bytes;
2188 byte_count -= cur_size_in_bytes;
2189 }
2190
2191 amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2192 WARN_ON(job->ibs[0].length_dw > num_dw);
2193 if (direct_submit)
2194 r = amdgpu_job_submit_direct(job, ring, fence);
2195 else
2196 r = amdgpu_job_submit(job, &adev->mman.entity,
2197 AMDGPU_FENCE_OWNER_UNDEFINED, fence);
2198 if (r)
2199 goto error_free;
2200
2201 return r;
2202
2203error_free:
2204 amdgpu_job_free(job);
2205 DRM_ERROR("Error scheduling IBs (%d)\n", r);
2206 return r;
2207}
2208
2209int amdgpu_fill_buffer(struct amdgpu_bo *bo,
2210 uint32_t src_data,
2211 struct dma_resv *resv,
2212 struct dma_fence **fence)
2213{
2214 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
2215 uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
2216 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
2217
2218 struct drm_mm_node *mm_node;
2219 unsigned long num_pages;
2220 unsigned int num_loops, num_dw;
2221
2222 struct amdgpu_job *job;
2223 int r;
2224
2225 if (!adev->mman.buffer_funcs_enabled) {
2226 DRM_ERROR("Trying to clear memory with ring turned off.\n");
2227 return -EINVAL;
2228 }
2229
2230 if (bo->tbo.mem.mem_type == TTM_PL_TT) {
2231 r = amdgpu_ttm_alloc_gart(&bo->tbo);
2232 if (r)
2233 return r;
2234 }
2235
2236 num_pages = bo->tbo.num_pages;
2237 mm_node = bo->tbo.mem.mm_node;
2238 num_loops = 0;
2239 while (num_pages) {
2240 uint64_t byte_count = mm_node->size << PAGE_SHIFT;
2241
2242 num_loops += DIV_ROUND_UP_ULL(byte_count, max_bytes);
2243 num_pages -= mm_node->size;
2244 ++mm_node;
2245 }
2246 num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw;
2247
2248 /* for IB padding */
2249 num_dw += 64;
2250
2251 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, AMDGPU_IB_POOL_DELAYED,
2252 &job);
2253 if (r)
2254 return r;
2255
2256 if (resv) {
2257 r = amdgpu_sync_resv(adev, &job->sync, resv,
2258 AMDGPU_SYNC_ALWAYS,
2259 AMDGPU_FENCE_OWNER_UNDEFINED);
2260 if (r) {
2261 DRM_ERROR("sync failed (%d).\n", r);
2262 goto error_free;
2263 }
2264 }
2265
2266 num_pages = bo->tbo.num_pages;
2267 mm_node = bo->tbo.mem.mm_node;
2268
2269 while (num_pages) {
2270 uint64_t byte_count = mm_node->size << PAGE_SHIFT;
2271 uint64_t dst_addr;
2272
2273 dst_addr = amdgpu_mm_node_addr(&bo->tbo, mm_node, &bo->tbo.mem);
2274 while (byte_count) {
2275 uint32_t cur_size_in_bytes = min_t(uint64_t, byte_count,
2276 max_bytes);
2277
2278 amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data,
2279 dst_addr, cur_size_in_bytes);
2280
2281 dst_addr += cur_size_in_bytes;
2282 byte_count -= cur_size_in_bytes;
2283 }
2284
2285 num_pages -= mm_node->size;
2286 ++mm_node;
2287 }
2288
2289 amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2290 WARN_ON(job->ibs[0].length_dw > num_dw);
2291 r = amdgpu_job_submit(job, &adev->mman.entity,
2292 AMDGPU_FENCE_OWNER_UNDEFINED, fence);
2293 if (r)
2294 goto error_free;
2295
2296 return 0;
2297
2298error_free:
2299 amdgpu_job_free(job);
2300 return r;
2301}
2302
2303#if defined(CONFIG_DEBUG_FS)
2304
2305static int amdgpu_mm_dump_table(struct seq_file *m, void *data)
2306{
2307 struct drm_info_node *node = (struct drm_info_node *)m->private;
2308 unsigned ttm_pl = (uintptr_t)node->info_ent->data;
2309 struct drm_device *dev = node->minor->dev;
2310 struct amdgpu_device *adev = dev->dev_private;
2311 struct ttm_mem_type_manager *man = &adev->mman.bdev.man[ttm_pl];
2312 struct drm_printer p = drm_seq_file_printer(m);
2313
2314 man->func->debug(man, &p);
2315 return 0;
2316}
2317
2318static const struct drm_info_list amdgpu_ttm_debugfs_list[] = {
2319 {"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, (void *)TTM_PL_VRAM},
2320 {"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, (void *)TTM_PL_TT},
2321 {"amdgpu_gds_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_GDS},
2322 {"amdgpu_gws_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_GWS},
2323 {"amdgpu_oa_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_OA},
2324 {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
2325#ifdef CONFIG_SWIOTLB
2326 {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
2327#endif
2328};
2329
2330/**
2331 * amdgpu_ttm_vram_read - Linear read access to VRAM
2332 *
2333 * Accesses VRAM via MMIO for debugging purposes.
2334 */
2335static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
2336 size_t size, loff_t *pos)
2337{
2338 struct amdgpu_device *adev = file_inode(f)->i_private;
2339 ssize_t result = 0;
2340
2341 if (size & 0x3 || *pos & 0x3)
2342 return -EINVAL;
2343
2344 if (*pos >= adev->gmc.mc_vram_size)
2345 return -ENXIO;
2346
2347 size = min(size, (size_t)(adev->gmc.mc_vram_size - *pos));
2348 while (size) {
2349 size_t bytes = min(size, AMDGPU_TTM_VRAM_MAX_DW_READ * 4);
2350 uint32_t value[AMDGPU_TTM_VRAM_MAX_DW_READ];
2351
2352 amdgpu_device_vram_access(adev, *pos, value, bytes, false);
2353 if (copy_to_user(buf, value, bytes))
2354 return -EFAULT;
2355
2356 result += bytes;
2357 buf += bytes;
2358 *pos += bytes;
2359 size -= bytes;
2360 }
2361
2362 return result;
2363}
2364
2365/**
2366 * amdgpu_ttm_vram_write - Linear write access to VRAM
2367 *
2368 * Accesses VRAM via MMIO for debugging purposes.
2369 */
2370static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf,
2371 size_t size, loff_t *pos)
2372{
2373 struct amdgpu_device *adev = file_inode(f)->i_private;
2374 ssize_t result = 0;
2375 int r;
2376
2377 if (size & 0x3 || *pos & 0x3)
2378 return -EINVAL;
2379
2380 if (*pos >= adev->gmc.mc_vram_size)
2381 return -ENXIO;
2382
2383 while (size) {
2384 unsigned long flags;
2385 uint32_t value;
2386
2387 if (*pos >= adev->gmc.mc_vram_size)
2388 return result;
2389
2390 r = get_user(value, (uint32_t *)buf);
2391 if (r)
2392 return r;
2393
2394 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
2395 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
2396 WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31);
2397 WREG32_NO_KIQ(mmMM_DATA, value);
2398 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
2399
2400 result += 4;
2401 buf += 4;
2402 *pos += 4;
2403 size -= 4;
2404 }
2405
2406 return result;
2407}
2408
2409static const struct file_operations amdgpu_ttm_vram_fops = {
2410 .owner = THIS_MODULE,
2411 .read = amdgpu_ttm_vram_read,
2412 .write = amdgpu_ttm_vram_write,
2413 .llseek = default_llseek,
2414};
2415
2416#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
2417
2418/**
2419 * amdgpu_ttm_gtt_read - Linear read access to GTT memory
2420 */
2421static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf,
2422 size_t size, loff_t *pos)
2423{
2424 struct amdgpu_device *adev = file_inode(f)->i_private;
2425 ssize_t result = 0;
2426 int r;
2427
2428 while (size) {
2429 loff_t p = *pos / PAGE_SIZE;
2430 unsigned off = *pos & ~PAGE_MASK;
2431 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
2432 struct page *page;
2433 void *ptr;
2434
2435 if (p >= adev->gart.num_cpu_pages)
2436 return result;
2437
2438 page = adev->gart.pages[p];
2439 if (page) {
2440 ptr = kmap(page);
2441 ptr += off;
2442
2443 r = copy_to_user(buf, ptr, cur_size);
2444 kunmap(adev->gart.pages[p]);
2445 } else
2446 r = clear_user(buf, cur_size);
2447
2448 if (r)
2449 return -EFAULT;
2450
2451 result += cur_size;
2452 buf += cur_size;
2453 *pos += cur_size;
2454 size -= cur_size;
2455 }
2456
2457 return result;
2458}
2459
2460static const struct file_operations amdgpu_ttm_gtt_fops = {
2461 .owner = THIS_MODULE,
2462 .read = amdgpu_ttm_gtt_read,
2463 .llseek = default_llseek
2464};
2465
2466#endif
2467
2468/**
2469 * amdgpu_iomem_read - Virtual read access to GPU mapped memory
2470 *
2471 * This function is used to read memory that has been mapped to the
2472 * GPU and the known addresses are not physical addresses but instead
2473 * bus addresses (e.g., what you'd put in an IB or ring buffer).
2474 */
2475static ssize_t amdgpu_iomem_read(struct file *f, char __user *buf,
2476 size_t size, loff_t *pos)
2477{
2478 struct amdgpu_device *adev = file_inode(f)->i_private;
2479 struct iommu_domain *dom;
2480 ssize_t result = 0;
2481 int r;
2482
2483 /* retrieve the IOMMU domain if any for this device */
2484 dom = iommu_get_domain_for_dev(adev->dev);
2485
2486 while (size) {
2487 phys_addr_t addr = *pos & PAGE_MASK;
2488 loff_t off = *pos & ~PAGE_MASK;
2489 size_t bytes = PAGE_SIZE - off;
2490 unsigned long pfn;
2491 struct page *p;
2492 void *ptr;
2493
2494 bytes = bytes < size ? bytes : size;
2495
2496 /* Translate the bus address to a physical address. If
2497 * the domain is NULL it means there is no IOMMU active
2498 * and the address translation is the identity
2499 */
2500 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2501
2502 pfn = addr >> PAGE_SHIFT;
2503 if (!pfn_valid(pfn))
2504 return -EPERM;
2505
2506 p = pfn_to_page(pfn);
2507 if (p->mapping != adev->mman.bdev.dev_mapping)
2508 return -EPERM;
2509
2510 ptr = kmap(p);
2511 r = copy_to_user(buf, ptr + off, bytes);
2512 kunmap(p);
2513 if (r)
2514 return -EFAULT;
2515
2516 size -= bytes;
2517 *pos += bytes;
2518 result += bytes;
2519 }
2520
2521 return result;
2522}
2523
2524/**
2525 * amdgpu_iomem_write - Virtual write access to GPU mapped memory
2526 *
2527 * This function is used to write memory that has been mapped to the
2528 * GPU and the known addresses are not physical addresses but instead
2529 * bus addresses (e.g., what you'd put in an IB or ring buffer).
2530 */
2531static ssize_t amdgpu_iomem_write(struct file *f, const char __user *buf,
2532 size_t size, loff_t *pos)
2533{
2534 struct amdgpu_device *adev = file_inode(f)->i_private;
2535 struct iommu_domain *dom;
2536 ssize_t result = 0;
2537 int r;
2538
2539 dom = iommu_get_domain_for_dev(adev->dev);
2540
2541 while (size) {
2542 phys_addr_t addr = *pos & PAGE_MASK;
2543 loff_t off = *pos & ~PAGE_MASK;
2544 size_t bytes = PAGE_SIZE - off;
2545 unsigned long pfn;
2546 struct page *p;
2547 void *ptr;
2548
2549 bytes = bytes < size ? bytes : size;
2550
2551 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2552
2553 pfn = addr >> PAGE_SHIFT;
2554 if (!pfn_valid(pfn))
2555 return -EPERM;
2556
2557 p = pfn_to_page(pfn);
2558 if (p->mapping != adev->mman.bdev.dev_mapping)
2559 return -EPERM;
2560
2561 ptr = kmap(p);
2562 r = copy_from_user(ptr + off, buf, bytes);
2563 kunmap(p);
2564 if (r)
2565 return -EFAULT;
2566
2567 size -= bytes;
2568 *pos += bytes;
2569 result += bytes;
2570 }
2571
2572 return result;
2573}
2574
2575static const struct file_operations amdgpu_ttm_iomem_fops = {
2576 .owner = THIS_MODULE,
2577 .read = amdgpu_iomem_read,
2578 .write = amdgpu_iomem_write,
2579 .llseek = default_llseek
2580};
2581
2582static const struct {
2583 char *name;
2584 const struct file_operations *fops;
2585 int domain;
2586} ttm_debugfs_entries[] = {
2587 { "amdgpu_vram", &amdgpu_ttm_vram_fops, TTM_PL_VRAM },
2588#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
2589 { "amdgpu_gtt", &amdgpu_ttm_gtt_fops, TTM_PL_TT },
2590#endif
2591 { "amdgpu_iomem", &amdgpu_ttm_iomem_fops, TTM_PL_SYSTEM },
2592};
2593
2594#endif
2595
2596int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
2597{
2598#if defined(CONFIG_DEBUG_FS)
2599 unsigned count;
2600
2601 struct drm_minor *minor = adev->ddev->primary;
2602 struct dentry *ent, *root = minor->debugfs_root;
2603
2604 for (count = 0; count < ARRAY_SIZE(ttm_debugfs_entries); count++) {
2605 ent = debugfs_create_file(
2606 ttm_debugfs_entries[count].name,
2607 S_IFREG | S_IRUGO, root,
2608 adev,
2609 ttm_debugfs_entries[count].fops);
2610 if (IS_ERR(ent))
2611 return PTR_ERR(ent);
2612 if (ttm_debugfs_entries[count].domain == TTM_PL_VRAM)
2613 i_size_write(ent->d_inode, adev->gmc.mc_vram_size);
2614 else if (ttm_debugfs_entries[count].domain == TTM_PL_TT)
2615 i_size_write(ent->d_inode, adev->gmc.gart_size);
2616 adev->mman.debugfs_entries[count] = ent;
2617 }
2618
2619 count = ARRAY_SIZE(amdgpu_ttm_debugfs_list);
2620
2621#ifdef CONFIG_SWIOTLB
2622 if (!(adev->need_swiotlb && swiotlb_nr_tbl()))
2623 --count;
2624#endif
2625
2626 return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count);
2627#else
2628 return 0;
2629#endif
2630}
1/*
2 * Copyright 2009 Jerome Glisse.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 */
26/*
27 * Authors:
28 * Jerome Glisse <glisse@freedesktop.org>
29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
30 * Dave Airlie
31 */
32#include <ttm/ttm_bo_api.h>
33#include <ttm/ttm_bo_driver.h>
34#include <ttm/ttm_placement.h>
35#include <ttm/ttm_module.h>
36#include <ttm/ttm_page_alloc.h>
37#include <drm/drmP.h>
38#include <drm/amdgpu_drm.h>
39#include <linux/seq_file.h>
40#include <linux/slab.h>
41#include <linux/swiotlb.h>
42#include <linux/swap.h>
43#include <linux/pagemap.h>
44#include <linux/debugfs.h>
45#include "amdgpu.h"
46#include "bif/bif_4_1_d.h"
47
48#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
49
50static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev);
51static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev);
52
53
54/*
55 * Global memory.
56 */
57static int amdgpu_ttm_mem_global_init(struct drm_global_reference *ref)
58{
59 return ttm_mem_global_init(ref->object);
60}
61
62static void amdgpu_ttm_mem_global_release(struct drm_global_reference *ref)
63{
64 ttm_mem_global_release(ref->object);
65}
66
67static int amdgpu_ttm_global_init(struct amdgpu_device *adev)
68{
69 struct drm_global_reference *global_ref;
70 struct amdgpu_ring *ring;
71 struct amd_sched_rq *rq;
72 int r;
73
74 adev->mman.mem_global_referenced = false;
75 global_ref = &adev->mman.mem_global_ref;
76 global_ref->global_type = DRM_GLOBAL_TTM_MEM;
77 global_ref->size = sizeof(struct ttm_mem_global);
78 global_ref->init = &amdgpu_ttm_mem_global_init;
79 global_ref->release = &amdgpu_ttm_mem_global_release;
80 r = drm_global_item_ref(global_ref);
81 if (r) {
82 DRM_ERROR("Failed setting up TTM memory accounting "
83 "subsystem.\n");
84 goto error_mem;
85 }
86
87 adev->mman.bo_global_ref.mem_glob =
88 adev->mman.mem_global_ref.object;
89 global_ref = &adev->mman.bo_global_ref.ref;
90 global_ref->global_type = DRM_GLOBAL_TTM_BO;
91 global_ref->size = sizeof(struct ttm_bo_global);
92 global_ref->init = &ttm_bo_global_init;
93 global_ref->release = &ttm_bo_global_release;
94 r = drm_global_item_ref(global_ref);
95 if (r) {
96 DRM_ERROR("Failed setting up TTM BO subsystem.\n");
97 goto error_bo;
98 }
99
100 ring = adev->mman.buffer_funcs_ring;
101 rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL];
102 r = amd_sched_entity_init(&ring->sched, &adev->mman.entity,
103 rq, amdgpu_sched_jobs);
104 if (r) {
105 DRM_ERROR("Failed setting up TTM BO move run queue.\n");
106 goto error_entity;
107 }
108
109 adev->mman.mem_global_referenced = true;
110
111 return 0;
112
113error_entity:
114 drm_global_item_unref(&adev->mman.bo_global_ref.ref);
115error_bo:
116 drm_global_item_unref(&adev->mman.mem_global_ref);
117error_mem:
118 return r;
119}
120
121static void amdgpu_ttm_global_fini(struct amdgpu_device *adev)
122{
123 if (adev->mman.mem_global_referenced) {
124 amd_sched_entity_fini(adev->mman.entity.sched,
125 &adev->mman.entity);
126 drm_global_item_unref(&adev->mman.bo_global_ref.ref);
127 drm_global_item_unref(&adev->mman.mem_global_ref);
128 adev->mman.mem_global_referenced = false;
129 }
130}
131
132static int amdgpu_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
133{
134 return 0;
135}
136
137static int amdgpu_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
138 struct ttm_mem_type_manager *man)
139{
140 struct amdgpu_device *adev;
141
142 adev = amdgpu_ttm_adev(bdev);
143
144 switch (type) {
145 case TTM_PL_SYSTEM:
146 /* System memory */
147 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
148 man->available_caching = TTM_PL_MASK_CACHING;
149 man->default_caching = TTM_PL_FLAG_CACHED;
150 break;
151 case TTM_PL_TT:
152 man->func = &amdgpu_gtt_mgr_func;
153 man->gpu_offset = adev->mc.gtt_start;
154 man->available_caching = TTM_PL_MASK_CACHING;
155 man->default_caching = TTM_PL_FLAG_CACHED;
156 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
157 break;
158 case TTM_PL_VRAM:
159 /* "On-card" video ram */
160 man->func = &amdgpu_vram_mgr_func;
161 man->gpu_offset = adev->mc.vram_start;
162 man->flags = TTM_MEMTYPE_FLAG_FIXED |
163 TTM_MEMTYPE_FLAG_MAPPABLE;
164 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
165 man->default_caching = TTM_PL_FLAG_WC;
166 break;
167 case AMDGPU_PL_GDS:
168 case AMDGPU_PL_GWS:
169 case AMDGPU_PL_OA:
170 /* On-chip GDS memory*/
171 man->func = &ttm_bo_manager_func;
172 man->gpu_offset = 0;
173 man->flags = TTM_MEMTYPE_FLAG_FIXED | TTM_MEMTYPE_FLAG_CMA;
174 man->available_caching = TTM_PL_FLAG_UNCACHED;
175 man->default_caching = TTM_PL_FLAG_UNCACHED;
176 break;
177 default:
178 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
179 return -EINVAL;
180 }
181 return 0;
182}
183
184static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
185 struct ttm_placement *placement)
186{
187 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
188 struct amdgpu_bo *abo;
189 static struct ttm_place placements = {
190 .fpfn = 0,
191 .lpfn = 0,
192 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM
193 };
194 unsigned i;
195
196 if (!amdgpu_ttm_bo_is_amdgpu_bo(bo)) {
197 placement->placement = &placements;
198 placement->busy_placement = &placements;
199 placement->num_placement = 1;
200 placement->num_busy_placement = 1;
201 return;
202 }
203 abo = container_of(bo, struct amdgpu_bo, tbo);
204 switch (bo->mem.mem_type) {
205 case TTM_PL_VRAM:
206 if (adev->mman.buffer_funcs_ring->ready == false) {
207 amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
208 } else {
209 amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT);
210 for (i = 0; i < abo->placement.num_placement; ++i) {
211 if (!(abo->placements[i].flags &
212 TTM_PL_FLAG_TT))
213 continue;
214
215 if (abo->placements[i].lpfn)
216 continue;
217
218 /* set an upper limit to force directly
219 * allocating address space for the BO.
220 */
221 abo->placements[i].lpfn =
222 adev->mc.gtt_size >> PAGE_SHIFT;
223 }
224 }
225 break;
226 case TTM_PL_TT:
227 default:
228 amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
229 }
230 *placement = abo->placement;
231}
232
233static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
234{
235 struct amdgpu_bo *abo = container_of(bo, struct amdgpu_bo, tbo);
236
237 if (amdgpu_ttm_tt_get_usermm(bo->ttm))
238 return -EPERM;
239 return drm_vma_node_verify_access(&abo->gem_base.vma_node,
240 filp->private_data);
241}
242
243static void amdgpu_move_null(struct ttm_buffer_object *bo,
244 struct ttm_mem_reg *new_mem)
245{
246 struct ttm_mem_reg *old_mem = &bo->mem;
247
248 BUG_ON(old_mem->mm_node != NULL);
249 *old_mem = *new_mem;
250 new_mem->mm_node = NULL;
251}
252
253static int amdgpu_mm_node_addr(struct ttm_buffer_object *bo,
254 struct drm_mm_node *mm_node,
255 struct ttm_mem_reg *mem,
256 uint64_t *addr)
257{
258 int r;
259
260 switch (mem->mem_type) {
261 case TTM_PL_TT:
262 r = amdgpu_ttm_bind(bo, mem);
263 if (r)
264 return r;
265
266 case TTM_PL_VRAM:
267 *addr = mm_node->start << PAGE_SHIFT;
268 *addr += bo->bdev->man[mem->mem_type].gpu_offset;
269 break;
270 default:
271 DRM_ERROR("Unknown placement %d\n", mem->mem_type);
272 return -EINVAL;
273 }
274
275 return 0;
276}
277
278static int amdgpu_move_blit(struct ttm_buffer_object *bo,
279 bool evict, bool no_wait_gpu,
280 struct ttm_mem_reg *new_mem,
281 struct ttm_mem_reg *old_mem)
282{
283 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
284 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
285
286 struct drm_mm_node *old_mm, *new_mm;
287 uint64_t old_start, old_size, new_start, new_size;
288 unsigned long num_pages;
289 struct dma_fence *fence = NULL;
290 int r;
291
292 BUILD_BUG_ON((PAGE_SIZE % AMDGPU_GPU_PAGE_SIZE) != 0);
293
294 if (!ring->ready) {
295 DRM_ERROR("Trying to move memory with ring turned off.\n");
296 return -EINVAL;
297 }
298
299 old_mm = old_mem->mm_node;
300 r = amdgpu_mm_node_addr(bo, old_mm, old_mem, &old_start);
301 if (r)
302 return r;
303 old_size = old_mm->size;
304
305
306 new_mm = new_mem->mm_node;
307 r = amdgpu_mm_node_addr(bo, new_mm, new_mem, &new_start);
308 if (r)
309 return r;
310 new_size = new_mm->size;
311
312 num_pages = new_mem->num_pages;
313 while (num_pages) {
314 unsigned long cur_pages = min(old_size, new_size);
315 struct dma_fence *next;
316
317 r = amdgpu_copy_buffer(ring, old_start, new_start,
318 cur_pages * PAGE_SIZE,
319 bo->resv, &next, false);
320 if (r)
321 goto error;
322
323 dma_fence_put(fence);
324 fence = next;
325
326 num_pages -= cur_pages;
327 if (!num_pages)
328 break;
329
330 old_size -= cur_pages;
331 if (!old_size) {
332 r = amdgpu_mm_node_addr(bo, ++old_mm, old_mem,
333 &old_start);
334 if (r)
335 goto error;
336 old_size = old_mm->size;
337 } else {
338 old_start += cur_pages * PAGE_SIZE;
339 }
340
341 new_size -= cur_pages;
342 if (!new_size) {
343 r = amdgpu_mm_node_addr(bo, ++new_mm, new_mem,
344 &new_start);
345 if (r)
346 goto error;
347
348 new_size = new_mm->size;
349 } else {
350 new_start += cur_pages * PAGE_SIZE;
351 }
352 }
353
354 r = ttm_bo_pipeline_move(bo, fence, evict, new_mem);
355 dma_fence_put(fence);
356 return r;
357
358error:
359 if (fence)
360 dma_fence_wait(fence, false);
361 dma_fence_put(fence);
362 return r;
363}
364
365static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo,
366 bool evict, bool interruptible,
367 bool no_wait_gpu,
368 struct ttm_mem_reg *new_mem)
369{
370 struct amdgpu_device *adev;
371 struct ttm_mem_reg *old_mem = &bo->mem;
372 struct ttm_mem_reg tmp_mem;
373 struct ttm_place placements;
374 struct ttm_placement placement;
375 int r;
376
377 adev = amdgpu_ttm_adev(bo->bdev);
378 tmp_mem = *new_mem;
379 tmp_mem.mm_node = NULL;
380 placement.num_placement = 1;
381 placement.placement = &placements;
382 placement.num_busy_placement = 1;
383 placement.busy_placement = &placements;
384 placements.fpfn = 0;
385 placements.lpfn = adev->mc.gtt_size >> PAGE_SHIFT;
386 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
387 r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
388 interruptible, no_wait_gpu);
389 if (unlikely(r)) {
390 return r;
391 }
392
393 r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
394 if (unlikely(r)) {
395 goto out_cleanup;
396 }
397
398 r = ttm_tt_bind(bo->ttm, &tmp_mem);
399 if (unlikely(r)) {
400 goto out_cleanup;
401 }
402 r = amdgpu_move_blit(bo, true, no_wait_gpu, &tmp_mem, old_mem);
403 if (unlikely(r)) {
404 goto out_cleanup;
405 }
406 r = ttm_bo_move_ttm(bo, interruptible, no_wait_gpu, new_mem);
407out_cleanup:
408 ttm_bo_mem_put(bo, &tmp_mem);
409 return r;
410}
411
412static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo,
413 bool evict, bool interruptible,
414 bool no_wait_gpu,
415 struct ttm_mem_reg *new_mem)
416{
417 struct amdgpu_device *adev;
418 struct ttm_mem_reg *old_mem = &bo->mem;
419 struct ttm_mem_reg tmp_mem;
420 struct ttm_placement placement;
421 struct ttm_place placements;
422 int r;
423
424 adev = amdgpu_ttm_adev(bo->bdev);
425 tmp_mem = *new_mem;
426 tmp_mem.mm_node = NULL;
427 placement.num_placement = 1;
428 placement.placement = &placements;
429 placement.num_busy_placement = 1;
430 placement.busy_placement = &placements;
431 placements.fpfn = 0;
432 placements.lpfn = adev->mc.gtt_size >> PAGE_SHIFT;
433 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
434 r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
435 interruptible, no_wait_gpu);
436 if (unlikely(r)) {
437 return r;
438 }
439 r = ttm_bo_move_ttm(bo, interruptible, no_wait_gpu, &tmp_mem);
440 if (unlikely(r)) {
441 goto out_cleanup;
442 }
443 r = amdgpu_move_blit(bo, true, no_wait_gpu, new_mem, old_mem);
444 if (unlikely(r)) {
445 goto out_cleanup;
446 }
447out_cleanup:
448 ttm_bo_mem_put(bo, &tmp_mem);
449 return r;
450}
451
452static int amdgpu_bo_move(struct ttm_buffer_object *bo,
453 bool evict, bool interruptible,
454 bool no_wait_gpu,
455 struct ttm_mem_reg *new_mem)
456{
457 struct amdgpu_device *adev;
458 struct amdgpu_bo *abo;
459 struct ttm_mem_reg *old_mem = &bo->mem;
460 int r;
461
462 /* Can't move a pinned BO */
463 abo = container_of(bo, struct amdgpu_bo, tbo);
464 if (WARN_ON_ONCE(abo->pin_count > 0))
465 return -EINVAL;
466
467 adev = amdgpu_ttm_adev(bo->bdev);
468
469 /* remember the eviction */
470 if (evict)
471 atomic64_inc(&adev->num_evictions);
472
473 if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
474 amdgpu_move_null(bo, new_mem);
475 return 0;
476 }
477 if ((old_mem->mem_type == TTM_PL_TT &&
478 new_mem->mem_type == TTM_PL_SYSTEM) ||
479 (old_mem->mem_type == TTM_PL_SYSTEM &&
480 new_mem->mem_type == TTM_PL_TT)) {
481 /* bind is enough */
482 amdgpu_move_null(bo, new_mem);
483 return 0;
484 }
485 if (adev->mman.buffer_funcs == NULL ||
486 adev->mman.buffer_funcs_ring == NULL ||
487 !adev->mman.buffer_funcs_ring->ready) {
488 /* use memcpy */
489 goto memcpy;
490 }
491
492 if (old_mem->mem_type == TTM_PL_VRAM &&
493 new_mem->mem_type == TTM_PL_SYSTEM) {
494 r = amdgpu_move_vram_ram(bo, evict, interruptible,
495 no_wait_gpu, new_mem);
496 } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
497 new_mem->mem_type == TTM_PL_VRAM) {
498 r = amdgpu_move_ram_vram(bo, evict, interruptible,
499 no_wait_gpu, new_mem);
500 } else {
501 r = amdgpu_move_blit(bo, evict, no_wait_gpu, new_mem, old_mem);
502 }
503
504 if (r) {
505memcpy:
506 r = ttm_bo_move_memcpy(bo, interruptible, no_wait_gpu, new_mem);
507 if (r) {
508 return r;
509 }
510 }
511
512 /* update statistics */
513 atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved);
514 return 0;
515}
516
517static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
518{
519 struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
520 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
521
522 mem->bus.addr = NULL;
523 mem->bus.offset = 0;
524 mem->bus.size = mem->num_pages << PAGE_SHIFT;
525 mem->bus.base = 0;
526 mem->bus.is_iomem = false;
527 if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
528 return -EINVAL;
529 switch (mem->mem_type) {
530 case TTM_PL_SYSTEM:
531 /* system memory */
532 return 0;
533 case TTM_PL_TT:
534 break;
535 case TTM_PL_VRAM:
536 mem->bus.offset = mem->start << PAGE_SHIFT;
537 /* check if it's visible */
538 if ((mem->bus.offset + mem->bus.size) > adev->mc.visible_vram_size)
539 return -EINVAL;
540 mem->bus.base = adev->mc.aper_base;
541 mem->bus.is_iomem = true;
542#ifdef __alpha__
543 /*
544 * Alpha: use bus.addr to hold the ioremap() return,
545 * so we can modify bus.base below.
546 */
547 if (mem->placement & TTM_PL_FLAG_WC)
548 mem->bus.addr =
549 ioremap_wc(mem->bus.base + mem->bus.offset,
550 mem->bus.size);
551 else
552 mem->bus.addr =
553 ioremap_nocache(mem->bus.base + mem->bus.offset,
554 mem->bus.size);
555
556 /*
557 * Alpha: Use just the bus offset plus
558 * the hose/domain memory base for bus.base.
559 * It then can be used to build PTEs for VRAM
560 * access, as done in ttm_bo_vm_fault().
561 */
562 mem->bus.base = (mem->bus.base & 0x0ffffffffUL) +
563 adev->ddev->hose->dense_mem_base;
564#endif
565 break;
566 default:
567 return -EINVAL;
568 }
569 return 0;
570}
571
572static void amdgpu_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
573{
574}
575
576/*
577 * TTM backend functions.
578 */
579struct amdgpu_ttm_gup_task_list {
580 struct list_head list;
581 struct task_struct *task;
582};
583
584struct amdgpu_ttm_tt {
585 struct ttm_dma_tt ttm;
586 struct amdgpu_device *adev;
587 u64 offset;
588 uint64_t userptr;
589 struct mm_struct *usermm;
590 uint32_t userflags;
591 spinlock_t guptasklock;
592 struct list_head guptasks;
593 atomic_t mmu_invalidations;
594 struct list_head list;
595};
596
597int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages)
598{
599 struct amdgpu_ttm_tt *gtt = (void *)ttm;
600 unsigned int flags = 0;
601 unsigned pinned = 0;
602 int r;
603
604 if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY))
605 flags |= FOLL_WRITE;
606
607 if (gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) {
608 /* check that we only use anonymous memory
609 to prevent problems with writeback */
610 unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE;
611 struct vm_area_struct *vma;
612
613 vma = find_vma(gtt->usermm, gtt->userptr);
614 if (!vma || vma->vm_file || vma->vm_end < end)
615 return -EPERM;
616 }
617
618 do {
619 unsigned num_pages = ttm->num_pages - pinned;
620 uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE;
621 struct page **p = pages + pinned;
622 struct amdgpu_ttm_gup_task_list guptask;
623
624 guptask.task = current;
625 spin_lock(>t->guptasklock);
626 list_add(&guptask.list, >t->guptasks);
627 spin_unlock(>t->guptasklock);
628
629 r = get_user_pages(userptr, num_pages, flags, p, NULL);
630
631 spin_lock(>t->guptasklock);
632 list_del(&guptask.list);
633 spin_unlock(>t->guptasklock);
634
635 if (r < 0)
636 goto release_pages;
637
638 pinned += r;
639
640 } while (pinned < ttm->num_pages);
641
642 return 0;
643
644release_pages:
645 release_pages(pages, pinned, 0);
646 return r;
647}
648
649/* prepare the sg table with the user pages */
650static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm)
651{
652 struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
653 struct amdgpu_ttm_tt *gtt = (void *)ttm;
654 unsigned nents;
655 int r;
656
657 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
658 enum dma_data_direction direction = write ?
659 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
660
661 r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
662 ttm->num_pages << PAGE_SHIFT,
663 GFP_KERNEL);
664 if (r)
665 goto release_sg;
666
667 r = -ENOMEM;
668 nents = dma_map_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
669 if (nents != ttm->sg->nents)
670 goto release_sg;
671
672 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
673 gtt->ttm.dma_address, ttm->num_pages);
674
675 return 0;
676
677release_sg:
678 kfree(ttm->sg);
679 return r;
680}
681
682static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
683{
684 struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
685 struct amdgpu_ttm_tt *gtt = (void *)ttm;
686 struct sg_page_iter sg_iter;
687
688 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
689 enum dma_data_direction direction = write ?
690 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
691
692 /* double check that we don't free the table twice */
693 if (!ttm->sg->sgl)
694 return;
695
696 /* free the sg table and pages again */
697 dma_unmap_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
698
699 for_each_sg_page(ttm->sg->sgl, &sg_iter, ttm->sg->nents, 0) {
700 struct page *page = sg_page_iter_page(&sg_iter);
701 if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY))
702 set_page_dirty(page);
703
704 mark_page_accessed(page);
705 put_page(page);
706 }
707
708 sg_free_table(ttm->sg);
709}
710
711static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm,
712 struct ttm_mem_reg *bo_mem)
713{
714 struct amdgpu_ttm_tt *gtt = (void*)ttm;
715 int r;
716
717 if (gtt->userptr) {
718 r = amdgpu_ttm_tt_pin_userptr(ttm);
719 if (r) {
720 DRM_ERROR("failed to pin userptr\n");
721 return r;
722 }
723 }
724 if (!ttm->num_pages) {
725 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
726 ttm->num_pages, bo_mem, ttm);
727 }
728
729 if (bo_mem->mem_type == AMDGPU_PL_GDS ||
730 bo_mem->mem_type == AMDGPU_PL_GWS ||
731 bo_mem->mem_type == AMDGPU_PL_OA)
732 return -EINVAL;
733
734 return 0;
735}
736
737bool amdgpu_ttm_is_bound(struct ttm_tt *ttm)
738{
739 struct amdgpu_ttm_tt *gtt = (void *)ttm;
740
741 return gtt && !list_empty(>t->list);
742}
743
744int amdgpu_ttm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *bo_mem)
745{
746 struct ttm_tt *ttm = bo->ttm;
747 struct amdgpu_ttm_tt *gtt = (void *)bo->ttm;
748 uint32_t flags;
749 int r;
750
751 if (!ttm || amdgpu_ttm_is_bound(ttm))
752 return 0;
753
754 r = amdgpu_gtt_mgr_alloc(&bo->bdev->man[TTM_PL_TT], bo,
755 NULL, bo_mem);
756 if (r) {
757 DRM_ERROR("Failed to allocate GTT address space (%d)\n", r);
758 return r;
759 }
760
761 flags = amdgpu_ttm_tt_pte_flags(gtt->adev, ttm, bo_mem);
762 gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
763 r = amdgpu_gart_bind(gtt->adev, gtt->offset, ttm->num_pages,
764 ttm->pages, gtt->ttm.dma_address, flags);
765
766 if (r) {
767 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
768 ttm->num_pages, gtt->offset);
769 return r;
770 }
771 spin_lock(>t->adev->gtt_list_lock);
772 list_add_tail(>t->list, >t->adev->gtt_list);
773 spin_unlock(>t->adev->gtt_list_lock);
774 return 0;
775}
776
777int amdgpu_ttm_recover_gart(struct amdgpu_device *adev)
778{
779 struct amdgpu_ttm_tt *gtt, *tmp;
780 struct ttm_mem_reg bo_mem;
781 uint32_t flags;
782 int r;
783
784 bo_mem.mem_type = TTM_PL_TT;
785 spin_lock(&adev->gtt_list_lock);
786 list_for_each_entry_safe(gtt, tmp, &adev->gtt_list, list) {
787 flags = amdgpu_ttm_tt_pte_flags(gtt->adev, >t->ttm.ttm, &bo_mem);
788 r = amdgpu_gart_bind(adev, gtt->offset, gtt->ttm.ttm.num_pages,
789 gtt->ttm.ttm.pages, gtt->ttm.dma_address,
790 flags);
791 if (r) {
792 spin_unlock(&adev->gtt_list_lock);
793 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
794 gtt->ttm.ttm.num_pages, gtt->offset);
795 return r;
796 }
797 }
798 spin_unlock(&adev->gtt_list_lock);
799 return 0;
800}
801
802static int amdgpu_ttm_backend_unbind(struct ttm_tt *ttm)
803{
804 struct amdgpu_ttm_tt *gtt = (void *)ttm;
805
806 if (gtt->userptr)
807 amdgpu_ttm_tt_unpin_userptr(ttm);
808
809 if (!amdgpu_ttm_is_bound(ttm))
810 return 0;
811
812 /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
813 if (gtt->adev->gart.ready)
814 amdgpu_gart_unbind(gtt->adev, gtt->offset, ttm->num_pages);
815
816 spin_lock(>t->adev->gtt_list_lock);
817 list_del_init(>t->list);
818 spin_unlock(>t->adev->gtt_list_lock);
819
820 return 0;
821}
822
823static void amdgpu_ttm_backend_destroy(struct ttm_tt *ttm)
824{
825 struct amdgpu_ttm_tt *gtt = (void *)ttm;
826
827 ttm_dma_tt_fini(>t->ttm);
828 kfree(gtt);
829}
830
831static struct ttm_backend_func amdgpu_backend_func = {
832 .bind = &amdgpu_ttm_backend_bind,
833 .unbind = &amdgpu_ttm_backend_unbind,
834 .destroy = &amdgpu_ttm_backend_destroy,
835};
836
837static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_bo_device *bdev,
838 unsigned long size, uint32_t page_flags,
839 struct page *dummy_read_page)
840{
841 struct amdgpu_device *adev;
842 struct amdgpu_ttm_tt *gtt;
843
844 adev = amdgpu_ttm_adev(bdev);
845
846 gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
847 if (gtt == NULL) {
848 return NULL;
849 }
850 gtt->ttm.ttm.func = &amdgpu_backend_func;
851 gtt->adev = adev;
852 if (ttm_dma_tt_init(>t->ttm, bdev, size, page_flags, dummy_read_page)) {
853 kfree(gtt);
854 return NULL;
855 }
856 INIT_LIST_HEAD(>t->list);
857 return >t->ttm.ttm;
858}
859
860static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm)
861{
862 struct amdgpu_device *adev;
863 struct amdgpu_ttm_tt *gtt = (void *)ttm;
864 unsigned i;
865 int r;
866 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
867
868 if (ttm->state != tt_unpopulated)
869 return 0;
870
871 if (gtt && gtt->userptr) {
872 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
873 if (!ttm->sg)
874 return -ENOMEM;
875
876 ttm->page_flags |= TTM_PAGE_FLAG_SG;
877 ttm->state = tt_unbound;
878 return 0;
879 }
880
881 if (slave && ttm->sg) {
882 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
883 gtt->ttm.dma_address, ttm->num_pages);
884 ttm->state = tt_unbound;
885 return 0;
886 }
887
888 adev = amdgpu_ttm_adev(ttm->bdev);
889
890#ifdef CONFIG_SWIOTLB
891 if (swiotlb_nr_tbl()) {
892 return ttm_dma_populate(>t->ttm, adev->dev);
893 }
894#endif
895
896 r = ttm_pool_populate(ttm);
897 if (r) {
898 return r;
899 }
900
901 for (i = 0; i < ttm->num_pages; i++) {
902 gtt->ttm.dma_address[i] = pci_map_page(adev->pdev, ttm->pages[i],
903 0, PAGE_SIZE,
904 PCI_DMA_BIDIRECTIONAL);
905 if (pci_dma_mapping_error(adev->pdev, gtt->ttm.dma_address[i])) {
906 while (i--) {
907 pci_unmap_page(adev->pdev, gtt->ttm.dma_address[i],
908 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
909 gtt->ttm.dma_address[i] = 0;
910 }
911 ttm_pool_unpopulate(ttm);
912 return -EFAULT;
913 }
914 }
915 return 0;
916}
917
918static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm)
919{
920 struct amdgpu_device *adev;
921 struct amdgpu_ttm_tt *gtt = (void *)ttm;
922 unsigned i;
923 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
924
925 if (gtt && gtt->userptr) {
926 kfree(ttm->sg);
927 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
928 return;
929 }
930
931 if (slave)
932 return;
933
934 adev = amdgpu_ttm_adev(ttm->bdev);
935
936#ifdef CONFIG_SWIOTLB
937 if (swiotlb_nr_tbl()) {
938 ttm_dma_unpopulate(>t->ttm, adev->dev);
939 return;
940 }
941#endif
942
943 for (i = 0; i < ttm->num_pages; i++) {
944 if (gtt->ttm.dma_address[i]) {
945 pci_unmap_page(adev->pdev, gtt->ttm.dma_address[i],
946 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
947 }
948 }
949
950 ttm_pool_unpopulate(ttm);
951}
952
953int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
954 uint32_t flags)
955{
956 struct amdgpu_ttm_tt *gtt = (void *)ttm;
957
958 if (gtt == NULL)
959 return -EINVAL;
960
961 gtt->userptr = addr;
962 gtt->usermm = current->mm;
963 gtt->userflags = flags;
964 spin_lock_init(>t->guptasklock);
965 INIT_LIST_HEAD(>t->guptasks);
966 atomic_set(>t->mmu_invalidations, 0);
967
968 return 0;
969}
970
971struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
972{
973 struct amdgpu_ttm_tt *gtt = (void *)ttm;
974
975 if (gtt == NULL)
976 return NULL;
977
978 return gtt->usermm;
979}
980
981bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
982 unsigned long end)
983{
984 struct amdgpu_ttm_tt *gtt = (void *)ttm;
985 struct amdgpu_ttm_gup_task_list *entry;
986 unsigned long size;
987
988 if (gtt == NULL || !gtt->userptr)
989 return false;
990
991 size = (unsigned long)gtt->ttm.ttm.num_pages * PAGE_SIZE;
992 if (gtt->userptr > end || gtt->userptr + size <= start)
993 return false;
994
995 spin_lock(>t->guptasklock);
996 list_for_each_entry(entry, >t->guptasks, list) {
997 if (entry->task == current) {
998 spin_unlock(>t->guptasklock);
999 return false;
1000 }
1001 }
1002 spin_unlock(>t->guptasklock);
1003
1004 atomic_inc(>t->mmu_invalidations);
1005
1006 return true;
1007}
1008
1009bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
1010 int *last_invalidated)
1011{
1012 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1013 int prev_invalidated = *last_invalidated;
1014
1015 *last_invalidated = atomic_read(>t->mmu_invalidations);
1016 return prev_invalidated != *last_invalidated;
1017}
1018
1019bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
1020{
1021 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1022
1023 if (gtt == NULL)
1024 return false;
1025
1026 return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1027}
1028
1029uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
1030 struct ttm_mem_reg *mem)
1031{
1032 uint32_t flags = 0;
1033
1034 if (mem && mem->mem_type != TTM_PL_SYSTEM)
1035 flags |= AMDGPU_PTE_VALID;
1036
1037 if (mem && mem->mem_type == TTM_PL_TT) {
1038 flags |= AMDGPU_PTE_SYSTEM;
1039
1040 if (ttm->caching_state == tt_cached)
1041 flags |= AMDGPU_PTE_SNOOPED;
1042 }
1043
1044 if (adev->asic_type >= CHIP_TONGA)
1045 flags |= AMDGPU_PTE_EXECUTABLE;
1046
1047 flags |= AMDGPU_PTE_READABLE;
1048
1049 if (!amdgpu_ttm_tt_is_readonly(ttm))
1050 flags |= AMDGPU_PTE_WRITEABLE;
1051
1052 return flags;
1053}
1054
1055static void amdgpu_ttm_lru_removal(struct ttm_buffer_object *tbo)
1056{
1057 struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
1058 unsigned i, j;
1059
1060 for (i = 0; i < AMDGPU_TTM_LRU_SIZE; ++i) {
1061 struct amdgpu_mman_lru *lru = &adev->mman.log2_size[i];
1062
1063 for (j = 0; j < TTM_NUM_MEM_TYPES; ++j)
1064 if (&tbo->lru == lru->lru[j])
1065 lru->lru[j] = tbo->lru.prev;
1066
1067 if (&tbo->swap == lru->swap_lru)
1068 lru->swap_lru = tbo->swap.prev;
1069 }
1070}
1071
1072static struct amdgpu_mman_lru *amdgpu_ttm_lru(struct ttm_buffer_object *tbo)
1073{
1074 struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
1075 unsigned log2_size = min(ilog2(tbo->num_pages),
1076 AMDGPU_TTM_LRU_SIZE - 1);
1077
1078 return &adev->mman.log2_size[log2_size];
1079}
1080
1081static struct list_head *amdgpu_ttm_lru_tail(struct ttm_buffer_object *tbo)
1082{
1083 struct amdgpu_mman_lru *lru = amdgpu_ttm_lru(tbo);
1084 struct list_head *res = lru->lru[tbo->mem.mem_type];
1085
1086 lru->lru[tbo->mem.mem_type] = &tbo->lru;
1087 while ((++lru)->lru[tbo->mem.mem_type] == res)
1088 lru->lru[tbo->mem.mem_type] = &tbo->lru;
1089
1090 return res;
1091}
1092
1093static struct list_head *amdgpu_ttm_swap_lru_tail(struct ttm_buffer_object *tbo)
1094{
1095 struct amdgpu_mman_lru *lru = amdgpu_ttm_lru(tbo);
1096 struct list_head *res = lru->swap_lru;
1097
1098 lru->swap_lru = &tbo->swap;
1099 while ((++lru)->swap_lru == res)
1100 lru->swap_lru = &tbo->swap;
1101
1102 return res;
1103}
1104
1105static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
1106 const struct ttm_place *place)
1107{
1108 if (bo->mem.mem_type == TTM_PL_VRAM &&
1109 bo->mem.start == AMDGPU_BO_INVALID_OFFSET) {
1110 unsigned long num_pages = bo->mem.num_pages;
1111 struct drm_mm_node *node = bo->mem.mm_node;
1112
1113 /* Check each drm MM node individually */
1114 while (num_pages) {
1115 if (place->fpfn < (node->start + node->size) &&
1116 !(place->lpfn && place->lpfn <= node->start))
1117 return true;
1118
1119 num_pages -= node->size;
1120 ++node;
1121 }
1122
1123 return false;
1124 }
1125
1126 return ttm_bo_eviction_valuable(bo, place);
1127}
1128
1129static struct ttm_bo_driver amdgpu_bo_driver = {
1130 .ttm_tt_create = &amdgpu_ttm_tt_create,
1131 .ttm_tt_populate = &amdgpu_ttm_tt_populate,
1132 .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
1133 .invalidate_caches = &amdgpu_invalidate_caches,
1134 .init_mem_type = &amdgpu_init_mem_type,
1135 .eviction_valuable = amdgpu_ttm_bo_eviction_valuable,
1136 .evict_flags = &amdgpu_evict_flags,
1137 .move = &amdgpu_bo_move,
1138 .verify_access = &amdgpu_verify_access,
1139 .move_notify = &amdgpu_bo_move_notify,
1140 .fault_reserve_notify = &amdgpu_bo_fault_reserve_notify,
1141 .io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
1142 .io_mem_free = &amdgpu_ttm_io_mem_free,
1143 .lru_removal = &amdgpu_ttm_lru_removal,
1144 .lru_tail = &amdgpu_ttm_lru_tail,
1145 .swap_lru_tail = &amdgpu_ttm_swap_lru_tail,
1146};
1147
1148int amdgpu_ttm_init(struct amdgpu_device *adev)
1149{
1150 unsigned i, j;
1151 int r;
1152
1153 r = amdgpu_ttm_global_init(adev);
1154 if (r) {
1155 return r;
1156 }
1157 /* No others user of address space so set it to 0 */
1158 r = ttm_bo_device_init(&adev->mman.bdev,
1159 adev->mman.bo_global_ref.ref.object,
1160 &amdgpu_bo_driver,
1161 adev->ddev->anon_inode->i_mapping,
1162 DRM_FILE_PAGE_OFFSET,
1163 adev->need_dma32);
1164 if (r) {
1165 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
1166 return r;
1167 }
1168
1169 for (i = 0; i < AMDGPU_TTM_LRU_SIZE; ++i) {
1170 struct amdgpu_mman_lru *lru = &adev->mman.log2_size[i];
1171
1172 for (j = 0; j < TTM_NUM_MEM_TYPES; ++j)
1173 lru->lru[j] = &adev->mman.bdev.man[j].lru;
1174 lru->swap_lru = &adev->mman.bdev.glob->swap_lru;
1175 }
1176
1177 for (j = 0; j < TTM_NUM_MEM_TYPES; ++j)
1178 adev->mman.guard.lru[j] = NULL;
1179 adev->mman.guard.swap_lru = NULL;
1180
1181 adev->mman.initialized = true;
1182 r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_VRAM,
1183 adev->mc.real_vram_size >> PAGE_SHIFT);
1184 if (r) {
1185 DRM_ERROR("Failed initializing VRAM heap.\n");
1186 return r;
1187 }
1188 /* Change the size here instead of the init above so only lpfn is affected */
1189 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
1190
1191 r = amdgpu_bo_create(adev, 256 * 1024, PAGE_SIZE, true,
1192 AMDGPU_GEM_DOMAIN_VRAM,
1193 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
1194 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
1195 NULL, NULL, &adev->stollen_vga_memory);
1196 if (r) {
1197 return r;
1198 }
1199 r = amdgpu_bo_reserve(adev->stollen_vga_memory, false);
1200 if (r)
1201 return r;
1202 r = amdgpu_bo_pin(adev->stollen_vga_memory, AMDGPU_GEM_DOMAIN_VRAM, NULL);
1203 amdgpu_bo_unreserve(adev->stollen_vga_memory);
1204 if (r) {
1205 amdgpu_bo_unref(&adev->stollen_vga_memory);
1206 return r;
1207 }
1208 DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
1209 (unsigned) (adev->mc.real_vram_size / (1024 * 1024)));
1210 r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_TT,
1211 adev->mc.gtt_size >> PAGE_SHIFT);
1212 if (r) {
1213 DRM_ERROR("Failed initializing GTT heap.\n");
1214 return r;
1215 }
1216 DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
1217 (unsigned)(adev->mc.gtt_size / (1024 * 1024)));
1218
1219 adev->gds.mem.total_size = adev->gds.mem.total_size << AMDGPU_GDS_SHIFT;
1220 adev->gds.mem.gfx_partition_size = adev->gds.mem.gfx_partition_size << AMDGPU_GDS_SHIFT;
1221 adev->gds.mem.cs_partition_size = adev->gds.mem.cs_partition_size << AMDGPU_GDS_SHIFT;
1222 adev->gds.gws.total_size = adev->gds.gws.total_size << AMDGPU_GWS_SHIFT;
1223 adev->gds.gws.gfx_partition_size = adev->gds.gws.gfx_partition_size << AMDGPU_GWS_SHIFT;
1224 adev->gds.gws.cs_partition_size = adev->gds.gws.cs_partition_size << AMDGPU_GWS_SHIFT;
1225 adev->gds.oa.total_size = adev->gds.oa.total_size << AMDGPU_OA_SHIFT;
1226 adev->gds.oa.gfx_partition_size = adev->gds.oa.gfx_partition_size << AMDGPU_OA_SHIFT;
1227 adev->gds.oa.cs_partition_size = adev->gds.oa.cs_partition_size << AMDGPU_OA_SHIFT;
1228 /* GDS Memory */
1229 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GDS,
1230 adev->gds.mem.total_size >> PAGE_SHIFT);
1231 if (r) {
1232 DRM_ERROR("Failed initializing GDS heap.\n");
1233 return r;
1234 }
1235
1236 /* GWS */
1237 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GWS,
1238 adev->gds.gws.total_size >> PAGE_SHIFT);
1239 if (r) {
1240 DRM_ERROR("Failed initializing gws heap.\n");
1241 return r;
1242 }
1243
1244 /* OA */
1245 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_OA,
1246 adev->gds.oa.total_size >> PAGE_SHIFT);
1247 if (r) {
1248 DRM_ERROR("Failed initializing oa heap.\n");
1249 return r;
1250 }
1251
1252 r = amdgpu_ttm_debugfs_init(adev);
1253 if (r) {
1254 DRM_ERROR("Failed to init debugfs\n");
1255 return r;
1256 }
1257 return 0;
1258}
1259
1260void amdgpu_ttm_fini(struct amdgpu_device *adev)
1261{
1262 int r;
1263
1264 if (!adev->mman.initialized)
1265 return;
1266 amdgpu_ttm_debugfs_fini(adev);
1267 if (adev->stollen_vga_memory) {
1268 r = amdgpu_bo_reserve(adev->stollen_vga_memory, false);
1269 if (r == 0) {
1270 amdgpu_bo_unpin(adev->stollen_vga_memory);
1271 amdgpu_bo_unreserve(adev->stollen_vga_memory);
1272 }
1273 amdgpu_bo_unref(&adev->stollen_vga_memory);
1274 }
1275 ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_VRAM);
1276 ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_TT);
1277 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GDS);
1278 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GWS);
1279 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_OA);
1280 ttm_bo_device_release(&adev->mman.bdev);
1281 amdgpu_gart_fini(adev);
1282 amdgpu_ttm_global_fini(adev);
1283 adev->mman.initialized = false;
1284 DRM_INFO("amdgpu: ttm finalized\n");
1285}
1286
1287/* this should only be called at bootup or when userspace
1288 * isn't running */
1289void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size)
1290{
1291 struct ttm_mem_type_manager *man;
1292
1293 if (!adev->mman.initialized)
1294 return;
1295
1296 man = &adev->mman.bdev.man[TTM_PL_VRAM];
1297 /* this just adjusts TTM size idea, which sets lpfn to the correct value */
1298 man->size = size >> PAGE_SHIFT;
1299}
1300
1301int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma)
1302{
1303 struct drm_file *file_priv;
1304 struct amdgpu_device *adev;
1305
1306 if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET))
1307 return -EINVAL;
1308
1309 file_priv = filp->private_data;
1310 adev = file_priv->minor->dev->dev_private;
1311 if (adev == NULL)
1312 return -EINVAL;
1313
1314 return ttm_bo_mmap(filp, vma, &adev->mman.bdev);
1315}
1316
1317int amdgpu_copy_buffer(struct amdgpu_ring *ring,
1318 uint64_t src_offset,
1319 uint64_t dst_offset,
1320 uint32_t byte_count,
1321 struct reservation_object *resv,
1322 struct dma_fence **fence, bool direct_submit)
1323{
1324 struct amdgpu_device *adev = ring->adev;
1325 struct amdgpu_job *job;
1326
1327 uint32_t max_bytes;
1328 unsigned num_loops, num_dw;
1329 unsigned i;
1330 int r;
1331
1332 max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
1333 num_loops = DIV_ROUND_UP(byte_count, max_bytes);
1334 num_dw = num_loops * adev->mman.buffer_funcs->copy_num_dw;
1335
1336 /* for IB padding */
1337 while (num_dw & 0x7)
1338 num_dw++;
1339
1340 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
1341 if (r)
1342 return r;
1343
1344 if (resv) {
1345 r = amdgpu_sync_resv(adev, &job->sync, resv,
1346 AMDGPU_FENCE_OWNER_UNDEFINED);
1347 if (r) {
1348 DRM_ERROR("sync failed (%d).\n", r);
1349 goto error_free;
1350 }
1351 }
1352
1353 for (i = 0; i < num_loops; i++) {
1354 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
1355
1356 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
1357 dst_offset, cur_size_in_bytes);
1358
1359 src_offset += cur_size_in_bytes;
1360 dst_offset += cur_size_in_bytes;
1361 byte_count -= cur_size_in_bytes;
1362 }
1363
1364 amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1365 WARN_ON(job->ibs[0].length_dw > num_dw);
1366 if (direct_submit) {
1367 r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs,
1368 NULL, NULL, fence);
1369 job->fence = dma_fence_get(*fence);
1370 if (r)
1371 DRM_ERROR("Error scheduling IBs (%d)\n", r);
1372 amdgpu_job_free(job);
1373 } else {
1374 r = amdgpu_job_submit(job, ring, &adev->mman.entity,
1375 AMDGPU_FENCE_OWNER_UNDEFINED, fence);
1376 if (r)
1377 goto error_free;
1378 }
1379
1380 return r;
1381
1382error_free:
1383 amdgpu_job_free(job);
1384 return r;
1385}
1386
1387int amdgpu_fill_buffer(struct amdgpu_bo *bo,
1388 uint32_t src_data,
1389 struct reservation_object *resv,
1390 struct dma_fence **fence)
1391{
1392 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
1393 uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
1394 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
1395
1396 struct drm_mm_node *mm_node;
1397 unsigned long num_pages;
1398 unsigned int num_loops, num_dw;
1399
1400 struct amdgpu_job *job;
1401 int r;
1402
1403 if (!ring->ready) {
1404 DRM_ERROR("Trying to clear memory with ring turned off.\n");
1405 return -EINVAL;
1406 }
1407
1408 num_pages = bo->tbo.num_pages;
1409 mm_node = bo->tbo.mem.mm_node;
1410 num_loops = 0;
1411 while (num_pages) {
1412 uint32_t byte_count = mm_node->size << PAGE_SHIFT;
1413
1414 num_loops += DIV_ROUND_UP(byte_count, max_bytes);
1415 num_pages -= mm_node->size;
1416 ++mm_node;
1417 }
1418 num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw;
1419
1420 /* for IB padding */
1421 num_dw += 64;
1422
1423 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
1424 if (r)
1425 return r;
1426
1427 if (resv) {
1428 r = amdgpu_sync_resv(adev, &job->sync, resv,
1429 AMDGPU_FENCE_OWNER_UNDEFINED);
1430 if (r) {
1431 DRM_ERROR("sync failed (%d).\n", r);
1432 goto error_free;
1433 }
1434 }
1435
1436 num_pages = bo->tbo.num_pages;
1437 mm_node = bo->tbo.mem.mm_node;
1438
1439 while (num_pages) {
1440 uint32_t byte_count = mm_node->size << PAGE_SHIFT;
1441 uint64_t dst_addr;
1442
1443 r = amdgpu_mm_node_addr(&bo->tbo, mm_node,
1444 &bo->tbo.mem, &dst_addr);
1445 if (r)
1446 return r;
1447
1448 while (byte_count) {
1449 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
1450
1451 amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data,
1452 dst_addr, cur_size_in_bytes);
1453
1454 dst_addr += cur_size_in_bytes;
1455 byte_count -= cur_size_in_bytes;
1456 }
1457
1458 num_pages -= mm_node->size;
1459 ++mm_node;
1460 }
1461
1462 amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1463 WARN_ON(job->ibs[0].length_dw > num_dw);
1464 r = amdgpu_job_submit(job, ring, &adev->mman.entity,
1465 AMDGPU_FENCE_OWNER_UNDEFINED, fence);
1466 if (r)
1467 goto error_free;
1468
1469 return 0;
1470
1471error_free:
1472 amdgpu_job_free(job);
1473 return r;
1474}
1475
1476#if defined(CONFIG_DEBUG_FS)
1477
1478static int amdgpu_mm_dump_table(struct seq_file *m, void *data)
1479{
1480 struct drm_info_node *node = (struct drm_info_node *)m->private;
1481 unsigned ttm_pl = *(int *)node->info_ent->data;
1482 struct drm_device *dev = node->minor->dev;
1483 struct amdgpu_device *adev = dev->dev_private;
1484 struct drm_mm *mm = (struct drm_mm *)adev->mman.bdev.man[ttm_pl].priv;
1485 int ret;
1486 struct ttm_bo_global *glob = adev->mman.bdev.glob;
1487
1488 spin_lock(&glob->lru_lock);
1489 ret = drm_mm_dump_table(m, mm);
1490 spin_unlock(&glob->lru_lock);
1491 if (ttm_pl == TTM_PL_VRAM)
1492 seq_printf(m, "man size:%llu pages, ram usage:%lluMB, vis usage:%lluMB\n",
1493 adev->mman.bdev.man[ttm_pl].size,
1494 (u64)atomic64_read(&adev->vram_usage) >> 20,
1495 (u64)atomic64_read(&adev->vram_vis_usage) >> 20);
1496 return ret;
1497}
1498
1499static int ttm_pl_vram = TTM_PL_VRAM;
1500static int ttm_pl_tt = TTM_PL_TT;
1501
1502static const struct drm_info_list amdgpu_ttm_debugfs_list[] = {
1503 {"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, &ttm_pl_vram},
1504 {"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, &ttm_pl_tt},
1505 {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
1506#ifdef CONFIG_SWIOTLB
1507 {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
1508#endif
1509};
1510
1511static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
1512 size_t size, loff_t *pos)
1513{
1514 struct amdgpu_device *adev = file_inode(f)->i_private;
1515 ssize_t result = 0;
1516 int r;
1517
1518 if (size & 0x3 || *pos & 0x3)
1519 return -EINVAL;
1520
1521 while (size) {
1522 unsigned long flags;
1523 uint32_t value;
1524
1525 if (*pos >= adev->mc.mc_vram_size)
1526 return result;
1527
1528 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1529 WREG32(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
1530 WREG32(mmMM_INDEX_HI, *pos >> 31);
1531 value = RREG32(mmMM_DATA);
1532 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1533
1534 r = put_user(value, (uint32_t *)buf);
1535 if (r)
1536 return r;
1537
1538 result += 4;
1539 buf += 4;
1540 *pos += 4;
1541 size -= 4;
1542 }
1543
1544 return result;
1545}
1546
1547static const struct file_operations amdgpu_ttm_vram_fops = {
1548 .owner = THIS_MODULE,
1549 .read = amdgpu_ttm_vram_read,
1550 .llseek = default_llseek
1551};
1552
1553#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
1554
1555static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf,
1556 size_t size, loff_t *pos)
1557{
1558 struct amdgpu_device *adev = file_inode(f)->i_private;
1559 ssize_t result = 0;
1560 int r;
1561
1562 while (size) {
1563 loff_t p = *pos / PAGE_SIZE;
1564 unsigned off = *pos & ~PAGE_MASK;
1565 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
1566 struct page *page;
1567 void *ptr;
1568
1569 if (p >= adev->gart.num_cpu_pages)
1570 return result;
1571
1572 page = adev->gart.pages[p];
1573 if (page) {
1574 ptr = kmap(page);
1575 ptr += off;
1576
1577 r = copy_to_user(buf, ptr, cur_size);
1578 kunmap(adev->gart.pages[p]);
1579 } else
1580 r = clear_user(buf, cur_size);
1581
1582 if (r)
1583 return -EFAULT;
1584
1585 result += cur_size;
1586 buf += cur_size;
1587 *pos += cur_size;
1588 size -= cur_size;
1589 }
1590
1591 return result;
1592}
1593
1594static const struct file_operations amdgpu_ttm_gtt_fops = {
1595 .owner = THIS_MODULE,
1596 .read = amdgpu_ttm_gtt_read,
1597 .llseek = default_llseek
1598};
1599
1600#endif
1601
1602#endif
1603
1604static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
1605{
1606#if defined(CONFIG_DEBUG_FS)
1607 unsigned count;
1608
1609 struct drm_minor *minor = adev->ddev->primary;
1610 struct dentry *ent, *root = minor->debugfs_root;
1611
1612 ent = debugfs_create_file("amdgpu_vram", S_IFREG | S_IRUGO, root,
1613 adev, &amdgpu_ttm_vram_fops);
1614 if (IS_ERR(ent))
1615 return PTR_ERR(ent);
1616 i_size_write(ent->d_inode, adev->mc.mc_vram_size);
1617 adev->mman.vram = ent;
1618
1619#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
1620 ent = debugfs_create_file("amdgpu_gtt", S_IFREG | S_IRUGO, root,
1621 adev, &amdgpu_ttm_gtt_fops);
1622 if (IS_ERR(ent))
1623 return PTR_ERR(ent);
1624 i_size_write(ent->d_inode, adev->mc.gtt_size);
1625 adev->mman.gtt = ent;
1626
1627#endif
1628 count = ARRAY_SIZE(amdgpu_ttm_debugfs_list);
1629
1630#ifdef CONFIG_SWIOTLB
1631 if (!swiotlb_nr_tbl())
1632 --count;
1633#endif
1634
1635 return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count);
1636#else
1637
1638 return 0;
1639#endif
1640}
1641
1642static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev)
1643{
1644#if defined(CONFIG_DEBUG_FS)
1645
1646 debugfs_remove(adev->mman.vram);
1647 adev->mman.vram = NULL;
1648
1649#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
1650 debugfs_remove(adev->mman.gtt);
1651 adev->mman.gtt = NULL;
1652#endif
1653
1654#endif
1655}