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1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28
29#include <linux/pci.h>
30#include <linux/vmalloc.h>
31
32#include <drm/amdgpu_drm.h>
33#ifdef CONFIG_X86
34#include <asm/set_memory.h>
35#endif
36#include "amdgpu.h"
37
38/*
39 * GART
40 * The GART (Graphics Aperture Remapping Table) is an aperture
41 * in the GPU's address space. System pages can be mapped into
42 * the aperture and look like contiguous pages from the GPU's
43 * perspective. A page table maps the pages in the aperture
44 * to the actual backing pages in system memory.
45 *
46 * Radeon GPUs support both an internal GART, as described above,
47 * and AGP. AGP works similarly, but the GART table is configured
48 * and maintained by the northbridge rather than the driver.
49 * Radeon hw has a separate AGP aperture that is programmed to
50 * point to the AGP aperture provided by the northbridge and the
51 * requests are passed through to the northbridge aperture.
52 * Both AGP and internal GART can be used at the same time, however
53 * that is not currently supported by the driver.
54 *
55 * This file handles the common internal GART management.
56 */
57
58/*
59 * Common GART table functions.
60 */
61
62/**
63 * amdgpu_dummy_page_init - init dummy page used by the driver
64 *
65 * @adev: amdgpu_device pointer
66 *
67 * Allocate the dummy page used by the driver (all asics).
68 * This dummy page is used by the driver as a filler for gart entries
69 * when pages are taken out of the GART
70 * Returns 0 on sucess, -ENOMEM on failure.
71 */
72static int amdgpu_gart_dummy_page_init(struct amdgpu_device *adev)
73{
74 struct page *dummy_page = ttm_bo_glob.dummy_read_page;
75
76 if (adev->dummy_page_addr)
77 return 0;
78 adev->dummy_page_addr = pci_map_page(adev->pdev, dummy_page, 0,
79 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
80 if (pci_dma_mapping_error(adev->pdev, adev->dummy_page_addr)) {
81 dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n");
82 adev->dummy_page_addr = 0;
83 return -ENOMEM;
84 }
85 return 0;
86}
87
88/**
89 * amdgpu_dummy_page_fini - free dummy page used by the driver
90 *
91 * @adev: amdgpu_device pointer
92 *
93 * Frees the dummy page used by the driver (all asics).
94 */
95static void amdgpu_gart_dummy_page_fini(struct amdgpu_device *adev)
96{
97 if (!adev->dummy_page_addr)
98 return;
99 pci_unmap_page(adev->pdev, adev->dummy_page_addr,
100 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
101 adev->dummy_page_addr = 0;
102}
103
104/**
105 * amdgpu_gart_table_vram_alloc - allocate vram for gart page table
106 *
107 * @adev: amdgpu_device pointer
108 *
109 * Allocate video memory for GART page table
110 * (pcie r4xx, r5xx+). These asics require the
111 * gart table to be in video memory.
112 * Returns 0 for success, error for failure.
113 */
114int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev)
115{
116 int r;
117
118 if (adev->gart.bo == NULL) {
119 struct amdgpu_bo_param bp;
120
121 memset(&bp, 0, sizeof(bp));
122 bp.size = adev->gart.table_size;
123 bp.byte_align = PAGE_SIZE;
124 bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
125 bp.flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
126 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
127 bp.type = ttm_bo_type_kernel;
128 bp.resv = NULL;
129 r = amdgpu_bo_create(adev, &bp, &adev->gart.bo);
130 if (r) {
131 return r;
132 }
133 }
134 return 0;
135}
136
137/**
138 * amdgpu_gart_table_vram_pin - pin gart page table in vram
139 *
140 * @adev: amdgpu_device pointer
141 *
142 * Pin the GART page table in vram so it will not be moved
143 * by the memory manager (pcie r4xx, r5xx+). These asics require the
144 * gart table to be in video memory.
145 * Returns 0 for success, error for failure.
146 */
147int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev)
148{
149 int r;
150
151 r = amdgpu_bo_reserve(adev->gart.bo, false);
152 if (unlikely(r != 0))
153 return r;
154 r = amdgpu_bo_pin(adev->gart.bo, AMDGPU_GEM_DOMAIN_VRAM);
155 if (r) {
156 amdgpu_bo_unreserve(adev->gart.bo);
157 return r;
158 }
159 r = amdgpu_bo_kmap(adev->gart.bo, &adev->gart.ptr);
160 if (r)
161 amdgpu_bo_unpin(adev->gart.bo);
162 amdgpu_bo_unreserve(adev->gart.bo);
163 return r;
164}
165
166/**
167 * amdgpu_gart_table_vram_unpin - unpin gart page table in vram
168 *
169 * @adev: amdgpu_device pointer
170 *
171 * Unpin the GART page table in vram (pcie r4xx, r5xx+).
172 * These asics require the gart table to be in video memory.
173 */
174void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev)
175{
176 int r;
177
178 if (adev->gart.bo == NULL) {
179 return;
180 }
181 r = amdgpu_bo_reserve(adev->gart.bo, true);
182 if (likely(r == 0)) {
183 amdgpu_bo_kunmap(adev->gart.bo);
184 amdgpu_bo_unpin(adev->gart.bo);
185 amdgpu_bo_unreserve(adev->gart.bo);
186 adev->gart.ptr = NULL;
187 }
188}
189
190/**
191 * amdgpu_gart_table_vram_free - free gart page table vram
192 *
193 * @adev: amdgpu_device pointer
194 *
195 * Free the video memory used for the GART page table
196 * (pcie r4xx, r5xx+). These asics require the gart table to
197 * be in video memory.
198 */
199void amdgpu_gart_table_vram_free(struct amdgpu_device *adev)
200{
201 if (adev->gart.bo == NULL) {
202 return;
203 }
204 amdgpu_bo_unref(&adev->gart.bo);
205}
206
207/*
208 * Common gart functions.
209 */
210/**
211 * amdgpu_gart_unbind - unbind pages from the gart page table
212 *
213 * @adev: amdgpu_device pointer
214 * @offset: offset into the GPU's gart aperture
215 * @pages: number of pages to unbind
216 *
217 * Unbinds the requested pages from the gart page table and
218 * replaces them with the dummy page (all asics).
219 * Returns 0 for success, -EINVAL for failure.
220 */
221int amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset,
222 int pages)
223{
224 unsigned t;
225 unsigned p;
226 int i, j;
227 u64 page_base;
228 /* Starting from VEGA10, system bit must be 0 to mean invalid. */
229 uint64_t flags = 0;
230
231 if (!adev->gart.ready) {
232 WARN(1, "trying to unbind memory from uninitialized GART !\n");
233 return -EINVAL;
234 }
235
236 t = offset / AMDGPU_GPU_PAGE_SIZE;
237 p = t / AMDGPU_GPU_PAGES_IN_CPU_PAGE;
238 for (i = 0; i < pages; i++, p++) {
239#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
240 adev->gart.pages[p] = NULL;
241#endif
242 page_base = adev->dummy_page_addr;
243 if (!adev->gart.ptr)
244 continue;
245
246 for (j = 0; j < AMDGPU_GPU_PAGES_IN_CPU_PAGE; j++, t++) {
247 amdgpu_gmc_set_pte_pde(adev, adev->gart.ptr,
248 t, page_base, flags);
249 page_base += AMDGPU_GPU_PAGE_SIZE;
250 }
251 }
252 mb();
253 amdgpu_asic_flush_hdp(adev, NULL);
254 for (i = 0; i < adev->num_vmhubs; i++)
255 amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0);
256
257 return 0;
258}
259
260/**
261 * amdgpu_gart_map - map dma_addresses into GART entries
262 *
263 * @adev: amdgpu_device pointer
264 * @offset: offset into the GPU's gart aperture
265 * @pages: number of pages to bind
266 * @dma_addr: DMA addresses of pages
267 * @flags: page table entry flags
268 * @dst: CPU address of the gart table
269 *
270 * Map the dma_addresses into GART entries (all asics).
271 * Returns 0 for success, -EINVAL for failure.
272 */
273int amdgpu_gart_map(struct amdgpu_device *adev, uint64_t offset,
274 int pages, dma_addr_t *dma_addr, uint64_t flags,
275 void *dst)
276{
277 uint64_t page_base;
278 unsigned i, j, t;
279
280 if (!adev->gart.ready) {
281 WARN(1, "trying to bind memory to uninitialized GART !\n");
282 return -EINVAL;
283 }
284
285 t = offset / AMDGPU_GPU_PAGE_SIZE;
286
287 for (i = 0; i < pages; i++) {
288 page_base = dma_addr[i];
289 for (j = 0; j < AMDGPU_GPU_PAGES_IN_CPU_PAGE; j++, t++) {
290 amdgpu_gmc_set_pte_pde(adev, dst, t, page_base, flags);
291 page_base += AMDGPU_GPU_PAGE_SIZE;
292 }
293 }
294 return 0;
295}
296
297/**
298 * amdgpu_gart_bind - bind pages into the gart page table
299 *
300 * @adev: amdgpu_device pointer
301 * @offset: offset into the GPU's gart aperture
302 * @pages: number of pages to bind
303 * @pagelist: pages to bind
304 * @dma_addr: DMA addresses of pages
305 * @flags: page table entry flags
306 *
307 * Binds the requested pages to the gart page table
308 * (all asics).
309 * Returns 0 for success, -EINVAL for failure.
310 */
311int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset,
312 int pages, struct page **pagelist, dma_addr_t *dma_addr,
313 uint64_t flags)
314{
315#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
316 unsigned t,p;
317#endif
318 int r, i;
319
320 if (!adev->gart.ready) {
321 WARN(1, "trying to bind memory to uninitialized GART !\n");
322 return -EINVAL;
323 }
324
325#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
326 t = offset / AMDGPU_GPU_PAGE_SIZE;
327 p = t / AMDGPU_GPU_PAGES_IN_CPU_PAGE;
328 for (i = 0; i < pages; i++, p++)
329 adev->gart.pages[p] = pagelist ? pagelist[i] : NULL;
330#endif
331
332 if (!adev->gart.ptr)
333 return 0;
334
335 r = amdgpu_gart_map(adev, offset, pages, dma_addr, flags,
336 adev->gart.ptr);
337 if (r)
338 return r;
339
340 mb();
341 amdgpu_asic_flush_hdp(adev, NULL);
342 for (i = 0; i < adev->num_vmhubs; i++)
343 amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0);
344 return 0;
345}
346
347/**
348 * amdgpu_gart_init - init the driver info for managing the gart
349 *
350 * @adev: amdgpu_device pointer
351 *
352 * Allocate the dummy page and init the gart driver info (all asics).
353 * Returns 0 for success, error for failure.
354 */
355int amdgpu_gart_init(struct amdgpu_device *adev)
356{
357 int r;
358
359 if (adev->dummy_page_addr)
360 return 0;
361
362 /* We need PAGE_SIZE >= AMDGPU_GPU_PAGE_SIZE */
363 if (PAGE_SIZE < AMDGPU_GPU_PAGE_SIZE) {
364 DRM_ERROR("Page size is smaller than GPU page size!\n");
365 return -EINVAL;
366 }
367 r = amdgpu_gart_dummy_page_init(adev);
368 if (r)
369 return r;
370 /* Compute table size */
371 adev->gart.num_cpu_pages = adev->gmc.gart_size / PAGE_SIZE;
372 adev->gart.num_gpu_pages = adev->gmc.gart_size / AMDGPU_GPU_PAGE_SIZE;
373 DRM_INFO("GART: num cpu pages %u, num gpu pages %u\n",
374 adev->gart.num_cpu_pages, adev->gart.num_gpu_pages);
375
376#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
377 /* Allocate pages table */
378 adev->gart.pages = vzalloc(array_size(sizeof(void *),
379 adev->gart.num_cpu_pages));
380 if (adev->gart.pages == NULL)
381 return -ENOMEM;
382#endif
383
384 return 0;
385}
386
387/**
388 * amdgpu_gart_fini - tear down the driver info for managing the gart
389 *
390 * @adev: amdgpu_device pointer
391 *
392 * Tear down the gart driver info and free the dummy page (all asics).
393 */
394void amdgpu_gart_fini(struct amdgpu_device *adev)
395{
396#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
397 vfree(adev->gart.pages);
398 adev->gart.pages = NULL;
399#endif
400 amdgpu_gart_dummy_page_fini(adev);
401}
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include <drm/drmP.h>
29#include <drm/amdgpu_drm.h>
30#include "amdgpu.h"
31
32/*
33 * GART
34 * The GART (Graphics Aperture Remapping Table) is an aperture
35 * in the GPU's address space. System pages can be mapped into
36 * the aperture and look like contiguous pages from the GPU's
37 * perspective. A page table maps the pages in the aperture
38 * to the actual backing pages in system memory.
39 *
40 * Radeon GPUs support both an internal GART, as described above,
41 * and AGP. AGP works similarly, but the GART table is configured
42 * and maintained by the northbridge rather than the driver.
43 * Radeon hw has a separate AGP aperture that is programmed to
44 * point to the AGP aperture provided by the northbridge and the
45 * requests are passed through to the northbridge aperture.
46 * Both AGP and internal GART can be used at the same time, however
47 * that is not currently supported by the driver.
48 *
49 * This file handles the common internal GART management.
50 */
51
52/*
53 * Common GART table functions.
54 */
55/**
56 * amdgpu_gart_table_ram_alloc - allocate system ram for gart page table
57 *
58 * @adev: amdgpu_device pointer
59 *
60 * Allocate system memory for GART page table
61 * (r1xx-r3xx, non-pcie r4xx, rs400). These asics require the
62 * gart table to be in system memory.
63 * Returns 0 for success, -ENOMEM for failure.
64 */
65int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev)
66{
67 void *ptr;
68
69 ptr = pci_alloc_consistent(adev->pdev, adev->gart.table_size,
70 &adev->gart.table_addr);
71 if (ptr == NULL) {
72 return -ENOMEM;
73 }
74#ifdef CONFIG_X86
75 if (0) {
76 set_memory_uc((unsigned long)ptr,
77 adev->gart.table_size >> PAGE_SHIFT);
78 }
79#endif
80 adev->gart.ptr = ptr;
81 memset((void *)adev->gart.ptr, 0, adev->gart.table_size);
82 return 0;
83}
84
85/**
86 * amdgpu_gart_table_ram_free - free system ram for gart page table
87 *
88 * @adev: amdgpu_device pointer
89 *
90 * Free system memory for GART page table
91 * (r1xx-r3xx, non-pcie r4xx, rs400). These asics require the
92 * gart table to be in system memory.
93 */
94void amdgpu_gart_table_ram_free(struct amdgpu_device *adev)
95{
96 if (adev->gart.ptr == NULL) {
97 return;
98 }
99#ifdef CONFIG_X86
100 if (0) {
101 set_memory_wb((unsigned long)adev->gart.ptr,
102 adev->gart.table_size >> PAGE_SHIFT);
103 }
104#endif
105 pci_free_consistent(adev->pdev, adev->gart.table_size,
106 (void *)adev->gart.ptr,
107 adev->gart.table_addr);
108 adev->gart.ptr = NULL;
109 adev->gart.table_addr = 0;
110}
111
112/**
113 * amdgpu_gart_table_vram_alloc - allocate vram for gart page table
114 *
115 * @adev: amdgpu_device pointer
116 *
117 * Allocate video memory for GART page table
118 * (pcie r4xx, r5xx+). These asics require the
119 * gart table to be in video memory.
120 * Returns 0 for success, error for failure.
121 */
122int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev)
123{
124 int r;
125
126 if (adev->gart.robj == NULL) {
127 r = amdgpu_bo_create(adev, adev->gart.table_size,
128 PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM,
129 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
130 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
131 NULL, NULL, &adev->gart.robj);
132 if (r) {
133 return r;
134 }
135 }
136 return 0;
137}
138
139/**
140 * amdgpu_gart_table_vram_pin - pin gart page table in vram
141 *
142 * @adev: amdgpu_device pointer
143 *
144 * Pin the GART page table in vram so it will not be moved
145 * by the memory manager (pcie r4xx, r5xx+). These asics require the
146 * gart table to be in video memory.
147 * Returns 0 for success, error for failure.
148 */
149int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev)
150{
151 uint64_t gpu_addr;
152 int r;
153
154 r = amdgpu_bo_reserve(adev->gart.robj, false);
155 if (unlikely(r != 0))
156 return r;
157 r = amdgpu_bo_pin(adev->gart.robj,
158 AMDGPU_GEM_DOMAIN_VRAM, &gpu_addr);
159 if (r) {
160 amdgpu_bo_unreserve(adev->gart.robj);
161 return r;
162 }
163 r = amdgpu_bo_kmap(adev->gart.robj, &adev->gart.ptr);
164 if (r)
165 amdgpu_bo_unpin(adev->gart.robj);
166 amdgpu_bo_unreserve(adev->gart.robj);
167 adev->gart.table_addr = gpu_addr;
168 return r;
169}
170
171/**
172 * amdgpu_gart_table_vram_unpin - unpin gart page table in vram
173 *
174 * @adev: amdgpu_device pointer
175 *
176 * Unpin the GART page table in vram (pcie r4xx, r5xx+).
177 * These asics require the gart table to be in video memory.
178 */
179void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev)
180{
181 int r;
182
183 if (adev->gart.robj == NULL) {
184 return;
185 }
186 r = amdgpu_bo_reserve(adev->gart.robj, false);
187 if (likely(r == 0)) {
188 amdgpu_bo_kunmap(adev->gart.robj);
189 amdgpu_bo_unpin(adev->gart.robj);
190 amdgpu_bo_unreserve(adev->gart.robj);
191 adev->gart.ptr = NULL;
192 }
193}
194
195/**
196 * amdgpu_gart_table_vram_free - free gart page table vram
197 *
198 * @adev: amdgpu_device pointer
199 *
200 * Free the video memory used for the GART page table
201 * (pcie r4xx, r5xx+). These asics require the gart table to
202 * be in video memory.
203 */
204void amdgpu_gart_table_vram_free(struct amdgpu_device *adev)
205{
206 if (adev->gart.robj == NULL) {
207 return;
208 }
209 amdgpu_bo_unref(&adev->gart.robj);
210}
211
212/*
213 * Common gart functions.
214 */
215/**
216 * amdgpu_gart_unbind - unbind pages from the gart page table
217 *
218 * @adev: amdgpu_device pointer
219 * @offset: offset into the GPU's gart aperture
220 * @pages: number of pages to unbind
221 *
222 * Unbinds the requested pages from the gart page table and
223 * replaces them with the dummy page (all asics).
224 */
225void amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset,
226 int pages)
227{
228 unsigned t;
229 unsigned p;
230 int i, j;
231 u64 page_base;
232 uint32_t flags = AMDGPU_PTE_SYSTEM;
233
234 if (!adev->gart.ready) {
235 WARN(1, "trying to unbind memory from uninitialized GART !\n");
236 return;
237 }
238
239 t = offset / AMDGPU_GPU_PAGE_SIZE;
240 p = t / (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE);
241 for (i = 0; i < pages; i++, p++) {
242#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
243 adev->gart.pages[p] = NULL;
244#endif
245 page_base = adev->dummy_page.addr;
246 if (!adev->gart.ptr)
247 continue;
248
249 for (j = 0; j < (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE); j++, t++) {
250 amdgpu_gart_set_pte_pde(adev, adev->gart.ptr,
251 t, page_base, flags);
252 page_base += AMDGPU_GPU_PAGE_SIZE;
253 }
254 }
255 mb();
256 amdgpu_gart_flush_gpu_tlb(adev, 0);
257}
258
259/**
260 * amdgpu_gart_bind - bind pages into the gart page table
261 *
262 * @adev: amdgpu_device pointer
263 * @offset: offset into the GPU's gart aperture
264 * @pages: number of pages to bind
265 * @pagelist: pages to bind
266 * @dma_addr: DMA addresses of pages
267 *
268 * Binds the requested pages to the gart page table
269 * (all asics).
270 * Returns 0 for success, -EINVAL for failure.
271 */
272int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset,
273 int pages, struct page **pagelist, dma_addr_t *dma_addr,
274 uint32_t flags)
275{
276 unsigned t;
277 unsigned p;
278 uint64_t page_base;
279 int i, j;
280
281 if (!adev->gart.ready) {
282 WARN(1, "trying to bind memory to uninitialized GART !\n");
283 return -EINVAL;
284 }
285
286 t = offset / AMDGPU_GPU_PAGE_SIZE;
287 p = t / (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE);
288
289 for (i = 0; i < pages; i++, p++) {
290#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
291 adev->gart.pages[p] = pagelist[i];
292#endif
293 if (adev->gart.ptr) {
294 page_base = dma_addr[i];
295 for (j = 0; j < (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE); j++, t++) {
296 amdgpu_gart_set_pte_pde(adev, adev->gart.ptr, t, page_base, flags);
297 page_base += AMDGPU_GPU_PAGE_SIZE;
298 }
299 }
300 }
301 mb();
302 amdgpu_gart_flush_gpu_tlb(adev, 0);
303 return 0;
304}
305
306/**
307 * amdgpu_gart_init - init the driver info for managing the gart
308 *
309 * @adev: amdgpu_device pointer
310 *
311 * Allocate the dummy page and init the gart driver info (all asics).
312 * Returns 0 for success, error for failure.
313 */
314int amdgpu_gart_init(struct amdgpu_device *adev)
315{
316 int r;
317
318 if (adev->dummy_page.page)
319 return 0;
320
321 /* We need PAGE_SIZE >= AMDGPU_GPU_PAGE_SIZE */
322 if (PAGE_SIZE < AMDGPU_GPU_PAGE_SIZE) {
323 DRM_ERROR("Page size is smaller than GPU page size!\n");
324 return -EINVAL;
325 }
326 r = amdgpu_dummy_page_init(adev);
327 if (r)
328 return r;
329 /* Compute table size */
330 adev->gart.num_cpu_pages = adev->mc.gtt_size / PAGE_SIZE;
331 adev->gart.num_gpu_pages = adev->mc.gtt_size / AMDGPU_GPU_PAGE_SIZE;
332 DRM_INFO("GART: num cpu pages %u, num gpu pages %u\n",
333 adev->gart.num_cpu_pages, adev->gart.num_gpu_pages);
334
335#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
336 /* Allocate pages table */
337 adev->gart.pages = vzalloc(sizeof(void *) * adev->gart.num_cpu_pages);
338 if (adev->gart.pages == NULL) {
339 amdgpu_gart_fini(adev);
340 return -ENOMEM;
341 }
342#endif
343
344 return 0;
345}
346
347/**
348 * amdgpu_gart_fini - tear down the driver info for managing the gart
349 *
350 * @adev: amdgpu_device pointer
351 *
352 * Tear down the gart driver info and free the dummy page (all asics).
353 */
354void amdgpu_gart_fini(struct amdgpu_device *adev)
355{
356 if (adev->gart.ready) {
357 /* unbind pages */
358 amdgpu_gart_unbind(adev, 0, adev->gart.num_cpu_pages);
359 }
360 adev->gart.ready = false;
361#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
362 vfree(adev->gart.pages);
363 adev->gart.pages = NULL;
364#endif
365 amdgpu_dummy_page_fini(adev);
366}