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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd.
4 * Author: Lin Huang <hl@rock-chips.com>
5 */
6
7#include <linux/arm-smccc.h>
8#include <linux/clk.h>
9#include <linux/delay.h>
10#include <linux/devfreq.h>
11#include <linux/devfreq-event.h>
12#include <linux/interrupt.h>
13#include <linux/mfd/syscon.h>
14#include <linux/module.h>
15#include <linux/of.h>
16#include <linux/platform_device.h>
17#include <linux/pm_opp.h>
18#include <linux/regmap.h>
19#include <linux/regulator/consumer.h>
20#include <linux/rwsem.h>
21#include <linux/suspend.h>
22
23#include <soc/rockchip/rk3399_grf.h>
24#include <soc/rockchip/rockchip_sip.h>
25
26struct dram_timing {
27 unsigned int ddr3_speed_bin;
28 unsigned int pd_idle;
29 unsigned int sr_idle;
30 unsigned int sr_mc_gate_idle;
31 unsigned int srpd_lite_idle;
32 unsigned int standby_idle;
33 unsigned int auto_pd_dis_freq;
34 unsigned int dram_dll_dis_freq;
35 unsigned int phy_dll_dis_freq;
36 unsigned int ddr3_odt_dis_freq;
37 unsigned int ddr3_drv;
38 unsigned int ddr3_odt;
39 unsigned int phy_ddr3_ca_drv;
40 unsigned int phy_ddr3_dq_drv;
41 unsigned int phy_ddr3_odt;
42 unsigned int lpddr3_odt_dis_freq;
43 unsigned int lpddr3_drv;
44 unsigned int lpddr3_odt;
45 unsigned int phy_lpddr3_ca_drv;
46 unsigned int phy_lpddr3_dq_drv;
47 unsigned int phy_lpddr3_odt;
48 unsigned int lpddr4_odt_dis_freq;
49 unsigned int lpddr4_drv;
50 unsigned int lpddr4_dq_odt;
51 unsigned int lpddr4_ca_odt;
52 unsigned int phy_lpddr4_ca_drv;
53 unsigned int phy_lpddr4_ck_cs_drv;
54 unsigned int phy_lpddr4_dq_drv;
55 unsigned int phy_lpddr4_odt;
56};
57
58struct rk3399_dmcfreq {
59 struct device *dev;
60 struct devfreq *devfreq;
61 struct devfreq_simple_ondemand_data ondemand_data;
62 struct clk *dmc_clk;
63 struct devfreq_event_dev *edev;
64 struct mutex lock;
65 struct dram_timing timing;
66 struct regulator *vdd_center;
67 struct regmap *regmap_pmu;
68 unsigned long rate, target_rate;
69 unsigned long volt, target_volt;
70 unsigned int odt_dis_freq;
71 int odt_pd_arg0, odt_pd_arg1;
72};
73
74static int rk3399_dmcfreq_target(struct device *dev, unsigned long *freq,
75 u32 flags)
76{
77 struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
78 struct dev_pm_opp *opp;
79 unsigned long old_clk_rate = dmcfreq->rate;
80 unsigned long target_volt, target_rate;
81 struct arm_smccc_res res;
82 bool odt_enable = false;
83 int err;
84
85 opp = devfreq_recommended_opp(dev, freq, flags);
86 if (IS_ERR(opp))
87 return PTR_ERR(opp);
88
89 target_rate = dev_pm_opp_get_freq(opp);
90 target_volt = dev_pm_opp_get_voltage(opp);
91 dev_pm_opp_put(opp);
92
93 if (dmcfreq->rate == target_rate)
94 return 0;
95
96 mutex_lock(&dmcfreq->lock);
97
98 if (dmcfreq->regmap_pmu) {
99 if (target_rate >= dmcfreq->odt_dis_freq)
100 odt_enable = true;
101
102 /*
103 * This makes a SMC call to the TF-A to set the DDR PD
104 * (power-down) timings and to enable or disable the
105 * ODT (on-die termination) resistors.
106 */
107 arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, dmcfreq->odt_pd_arg0,
108 dmcfreq->odt_pd_arg1,
109 ROCKCHIP_SIP_CONFIG_DRAM_SET_ODT_PD,
110 odt_enable, 0, 0, 0, &res);
111 }
112
113 /*
114 * If frequency scaling from low to high, adjust voltage first.
115 * If frequency scaling from high to low, adjust frequency first.
116 */
117 if (old_clk_rate < target_rate) {
118 err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,
119 target_volt);
120 if (err) {
121 dev_err(dev, "Cannot set voltage %lu uV\n",
122 target_volt);
123 goto out;
124 }
125 }
126
127 err = clk_set_rate(dmcfreq->dmc_clk, target_rate);
128 if (err) {
129 dev_err(dev, "Cannot set frequency %lu (%d)\n", target_rate,
130 err);
131 regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt,
132 dmcfreq->volt);
133 goto out;
134 }
135
136 /*
137 * Check the dpll rate,
138 * There only two result we will get,
139 * 1. Ddr frequency scaling fail, we still get the old rate.
140 * 2. Ddr frequency scaling sucessful, we get the rate we set.
141 */
142 dmcfreq->rate = clk_get_rate(dmcfreq->dmc_clk);
143
144 /* If get the incorrect rate, set voltage to old value. */
145 if (dmcfreq->rate != target_rate) {
146 dev_err(dev, "Got wrong frequency, Request %lu, Current %lu\n",
147 target_rate, dmcfreq->rate);
148 regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt,
149 dmcfreq->volt);
150 goto out;
151 } else if (old_clk_rate > target_rate)
152 err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,
153 target_volt);
154 if (err)
155 dev_err(dev, "Cannot set voltage %lu uV\n", target_volt);
156
157 dmcfreq->rate = target_rate;
158 dmcfreq->volt = target_volt;
159
160out:
161 mutex_unlock(&dmcfreq->lock);
162 return err;
163}
164
165static int rk3399_dmcfreq_get_dev_status(struct device *dev,
166 struct devfreq_dev_status *stat)
167{
168 struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
169 struct devfreq_event_data edata;
170 int ret = 0;
171
172 ret = devfreq_event_get_event(dmcfreq->edev, &edata);
173 if (ret < 0)
174 return ret;
175
176 stat->current_frequency = dmcfreq->rate;
177 stat->busy_time = edata.load_count;
178 stat->total_time = edata.total_count;
179
180 return ret;
181}
182
183static int rk3399_dmcfreq_get_cur_freq(struct device *dev, unsigned long *freq)
184{
185 struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
186
187 *freq = dmcfreq->rate;
188
189 return 0;
190}
191
192static struct devfreq_dev_profile rk3399_devfreq_dmc_profile = {
193 .polling_ms = 200,
194 .target = rk3399_dmcfreq_target,
195 .get_dev_status = rk3399_dmcfreq_get_dev_status,
196 .get_cur_freq = rk3399_dmcfreq_get_cur_freq,
197};
198
199static __maybe_unused int rk3399_dmcfreq_suspend(struct device *dev)
200{
201 struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
202 int ret = 0;
203
204 ret = devfreq_event_disable_edev(dmcfreq->edev);
205 if (ret < 0) {
206 dev_err(dev, "failed to disable the devfreq-event devices\n");
207 return ret;
208 }
209
210 ret = devfreq_suspend_device(dmcfreq->devfreq);
211 if (ret < 0) {
212 dev_err(dev, "failed to suspend the devfreq devices\n");
213 return ret;
214 }
215
216 return 0;
217}
218
219static __maybe_unused int rk3399_dmcfreq_resume(struct device *dev)
220{
221 struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
222 int ret = 0;
223
224 ret = devfreq_event_enable_edev(dmcfreq->edev);
225 if (ret < 0) {
226 dev_err(dev, "failed to enable the devfreq-event devices\n");
227 return ret;
228 }
229
230 ret = devfreq_resume_device(dmcfreq->devfreq);
231 if (ret < 0) {
232 dev_err(dev, "failed to resume the devfreq devices\n");
233 return ret;
234 }
235 return ret;
236}
237
238static SIMPLE_DEV_PM_OPS(rk3399_dmcfreq_pm, rk3399_dmcfreq_suspend,
239 rk3399_dmcfreq_resume);
240
241static int of_get_ddr_timings(struct dram_timing *timing,
242 struct device_node *np)
243{
244 int ret = 0;
245
246 ret = of_property_read_u32(np, "rockchip,ddr3_speed_bin",
247 &timing->ddr3_speed_bin);
248 ret |= of_property_read_u32(np, "rockchip,pd_idle",
249 &timing->pd_idle);
250 ret |= of_property_read_u32(np, "rockchip,sr_idle",
251 &timing->sr_idle);
252 ret |= of_property_read_u32(np, "rockchip,sr_mc_gate_idle",
253 &timing->sr_mc_gate_idle);
254 ret |= of_property_read_u32(np, "rockchip,srpd_lite_idle",
255 &timing->srpd_lite_idle);
256 ret |= of_property_read_u32(np, "rockchip,standby_idle",
257 &timing->standby_idle);
258 ret |= of_property_read_u32(np, "rockchip,auto_pd_dis_freq",
259 &timing->auto_pd_dis_freq);
260 ret |= of_property_read_u32(np, "rockchip,dram_dll_dis_freq",
261 &timing->dram_dll_dis_freq);
262 ret |= of_property_read_u32(np, "rockchip,phy_dll_dis_freq",
263 &timing->phy_dll_dis_freq);
264 ret |= of_property_read_u32(np, "rockchip,ddr3_odt_dis_freq",
265 &timing->ddr3_odt_dis_freq);
266 ret |= of_property_read_u32(np, "rockchip,ddr3_drv",
267 &timing->ddr3_drv);
268 ret |= of_property_read_u32(np, "rockchip,ddr3_odt",
269 &timing->ddr3_odt);
270 ret |= of_property_read_u32(np, "rockchip,phy_ddr3_ca_drv",
271 &timing->phy_ddr3_ca_drv);
272 ret |= of_property_read_u32(np, "rockchip,phy_ddr3_dq_drv",
273 &timing->phy_ddr3_dq_drv);
274 ret |= of_property_read_u32(np, "rockchip,phy_ddr3_odt",
275 &timing->phy_ddr3_odt);
276 ret |= of_property_read_u32(np, "rockchip,lpddr3_odt_dis_freq",
277 &timing->lpddr3_odt_dis_freq);
278 ret |= of_property_read_u32(np, "rockchip,lpddr3_drv",
279 &timing->lpddr3_drv);
280 ret |= of_property_read_u32(np, "rockchip,lpddr3_odt",
281 &timing->lpddr3_odt);
282 ret |= of_property_read_u32(np, "rockchip,phy_lpddr3_ca_drv",
283 &timing->phy_lpddr3_ca_drv);
284 ret |= of_property_read_u32(np, "rockchip,phy_lpddr3_dq_drv",
285 &timing->phy_lpddr3_dq_drv);
286 ret |= of_property_read_u32(np, "rockchip,phy_lpddr3_odt",
287 &timing->phy_lpddr3_odt);
288 ret |= of_property_read_u32(np, "rockchip,lpddr4_odt_dis_freq",
289 &timing->lpddr4_odt_dis_freq);
290 ret |= of_property_read_u32(np, "rockchip,lpddr4_drv",
291 &timing->lpddr4_drv);
292 ret |= of_property_read_u32(np, "rockchip,lpddr4_dq_odt",
293 &timing->lpddr4_dq_odt);
294 ret |= of_property_read_u32(np, "rockchip,lpddr4_ca_odt",
295 &timing->lpddr4_ca_odt);
296 ret |= of_property_read_u32(np, "rockchip,phy_lpddr4_ca_drv",
297 &timing->phy_lpddr4_ca_drv);
298 ret |= of_property_read_u32(np, "rockchip,phy_lpddr4_ck_cs_drv",
299 &timing->phy_lpddr4_ck_cs_drv);
300 ret |= of_property_read_u32(np, "rockchip,phy_lpddr4_dq_drv",
301 &timing->phy_lpddr4_dq_drv);
302 ret |= of_property_read_u32(np, "rockchip,phy_lpddr4_odt",
303 &timing->phy_lpddr4_odt);
304
305 return ret;
306}
307
308static int rk3399_dmcfreq_probe(struct platform_device *pdev)
309{
310 struct arm_smccc_res res;
311 struct device *dev = &pdev->dev;
312 struct device_node *np = pdev->dev.of_node, *node;
313 struct rk3399_dmcfreq *data;
314 int ret, index, size;
315 uint32_t *timing;
316 struct dev_pm_opp *opp;
317 u32 ddr_type;
318 u32 val;
319
320 data = devm_kzalloc(dev, sizeof(struct rk3399_dmcfreq), GFP_KERNEL);
321 if (!data)
322 return -ENOMEM;
323
324 mutex_init(&data->lock);
325
326 data->vdd_center = devm_regulator_get(dev, "center");
327 if (IS_ERR(data->vdd_center)) {
328 if (PTR_ERR(data->vdd_center) == -EPROBE_DEFER)
329 return -EPROBE_DEFER;
330
331 dev_err(dev, "Cannot get the regulator \"center\"\n");
332 return PTR_ERR(data->vdd_center);
333 }
334
335 data->dmc_clk = devm_clk_get(dev, "dmc_clk");
336 if (IS_ERR(data->dmc_clk)) {
337 if (PTR_ERR(data->dmc_clk) == -EPROBE_DEFER)
338 return -EPROBE_DEFER;
339
340 dev_err(dev, "Cannot get the clk dmc_clk\n");
341 return PTR_ERR(data->dmc_clk);
342 }
343
344 data->edev = devfreq_event_get_edev_by_phandle(dev, 0);
345 if (IS_ERR(data->edev))
346 return -EPROBE_DEFER;
347
348 ret = devfreq_event_enable_edev(data->edev);
349 if (ret < 0) {
350 dev_err(dev, "failed to enable devfreq-event devices\n");
351 return ret;
352 }
353
354 /*
355 * Get dram timing and pass it to arm trust firmware,
356 * the dram driver in arm trust firmware will get these
357 * timing and to do dram initial.
358 */
359 if (!of_get_ddr_timings(&data->timing, np)) {
360 timing = &data->timing.ddr3_speed_bin;
361 size = sizeof(struct dram_timing) / 4;
362 for (index = 0; index < size; index++) {
363 arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, *timing++, index,
364 ROCKCHIP_SIP_CONFIG_DRAM_SET_PARAM,
365 0, 0, 0, 0, &res);
366 if (res.a0) {
367 dev_err(dev, "Failed to set dram param: %ld\n",
368 res.a0);
369 ret = -EINVAL;
370 goto err_edev;
371 }
372 }
373 }
374
375 node = of_parse_phandle(np, "rockchip,pmu", 0);
376 if (!node)
377 goto no_pmu;
378
379 data->regmap_pmu = syscon_node_to_regmap(node);
380 of_node_put(node);
381 if (IS_ERR(data->regmap_pmu)) {
382 ret = PTR_ERR(data->regmap_pmu);
383 goto err_edev;
384 }
385
386 regmap_read(data->regmap_pmu, RK3399_PMUGRF_OS_REG2, &val);
387 ddr_type = (val >> RK3399_PMUGRF_DDRTYPE_SHIFT) &
388 RK3399_PMUGRF_DDRTYPE_MASK;
389
390 switch (ddr_type) {
391 case RK3399_PMUGRF_DDRTYPE_DDR3:
392 data->odt_dis_freq = data->timing.ddr3_odt_dis_freq;
393 break;
394 case RK3399_PMUGRF_DDRTYPE_LPDDR3:
395 data->odt_dis_freq = data->timing.lpddr3_odt_dis_freq;
396 break;
397 case RK3399_PMUGRF_DDRTYPE_LPDDR4:
398 data->odt_dis_freq = data->timing.lpddr4_odt_dis_freq;
399 break;
400 default:
401 ret = -EINVAL;
402 goto err_edev;
403 };
404
405no_pmu:
406 arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, 0, 0,
407 ROCKCHIP_SIP_CONFIG_DRAM_INIT,
408 0, 0, 0, 0, &res);
409
410 /*
411 * In TF-A there is a platform SIP call to set the PD (power-down)
412 * timings and to enable or disable the ODT (on-die termination).
413 * This call needs three arguments as follows:
414 *
415 * arg0:
416 * bit[0-7] : sr_idle
417 * bit[8-15] : sr_mc_gate_idle
418 * bit[16-31] : standby idle
419 * arg1:
420 * bit[0-11] : pd_idle
421 * bit[16-27] : srpd_lite_idle
422 * arg2:
423 * bit[0] : odt enable
424 */
425 data->odt_pd_arg0 = (data->timing.sr_idle & 0xff) |
426 ((data->timing.sr_mc_gate_idle & 0xff) << 8) |
427 ((data->timing.standby_idle & 0xffff) << 16);
428 data->odt_pd_arg1 = (data->timing.pd_idle & 0xfff) |
429 ((data->timing.srpd_lite_idle & 0xfff) << 16);
430
431 /*
432 * We add a devfreq driver to our parent since it has a device tree node
433 * with operating points.
434 */
435 if (dev_pm_opp_of_add_table(dev)) {
436 dev_err(dev, "Invalid operating-points in device tree.\n");
437 ret = -EINVAL;
438 goto err_edev;
439 }
440
441 of_property_read_u32(np, "upthreshold",
442 &data->ondemand_data.upthreshold);
443 of_property_read_u32(np, "downdifferential",
444 &data->ondemand_data.downdifferential);
445
446 data->rate = clk_get_rate(data->dmc_clk);
447
448 opp = devfreq_recommended_opp(dev, &data->rate, 0);
449 if (IS_ERR(opp)) {
450 ret = PTR_ERR(opp);
451 goto err_free_opp;
452 }
453
454 data->rate = dev_pm_opp_get_freq(opp);
455 data->volt = dev_pm_opp_get_voltage(opp);
456 dev_pm_opp_put(opp);
457
458 rk3399_devfreq_dmc_profile.initial_freq = data->rate;
459
460 data->devfreq = devm_devfreq_add_device(dev,
461 &rk3399_devfreq_dmc_profile,
462 DEVFREQ_GOV_SIMPLE_ONDEMAND,
463 &data->ondemand_data);
464 if (IS_ERR(data->devfreq)) {
465 ret = PTR_ERR(data->devfreq);
466 goto err_free_opp;
467 }
468
469 devm_devfreq_register_opp_notifier(dev, data->devfreq);
470
471 data->dev = dev;
472 platform_set_drvdata(pdev, data);
473
474 return 0;
475
476err_free_opp:
477 dev_pm_opp_of_remove_table(&pdev->dev);
478err_edev:
479 devfreq_event_disable_edev(data->edev);
480
481 return ret;
482}
483
484static int rk3399_dmcfreq_remove(struct platform_device *pdev)
485{
486 struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(&pdev->dev);
487
488 /*
489 * Before remove the opp table we need to unregister the opp notifier.
490 */
491 devm_devfreq_unregister_opp_notifier(dmcfreq->dev, dmcfreq->devfreq);
492 dev_pm_opp_of_remove_table(dmcfreq->dev);
493
494 return 0;
495}
496
497static const struct of_device_id rk3399dmc_devfreq_of_match[] = {
498 { .compatible = "rockchip,rk3399-dmc" },
499 { },
500};
501MODULE_DEVICE_TABLE(of, rk3399dmc_devfreq_of_match);
502
503static struct platform_driver rk3399_dmcfreq_driver = {
504 .probe = rk3399_dmcfreq_probe,
505 .remove = rk3399_dmcfreq_remove,
506 .driver = {
507 .name = "rk3399-dmc-freq",
508 .pm = &rk3399_dmcfreq_pm,
509 .of_match_table = rk3399dmc_devfreq_of_match,
510 },
511};
512module_platform_driver(rk3399_dmcfreq_driver);
513
514MODULE_LICENSE("GPL v2");
515MODULE_AUTHOR("Lin Huang <hl@rock-chips.com>");
516MODULE_DESCRIPTION("RK3399 dmcfreq driver with devfreq framework");
1/*
2 * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd.
3 * Author: Lin Huang <hl@rock-chips.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 */
14
15#include <linux/arm-smccc.h>
16#include <linux/clk.h>
17#include <linux/delay.h>
18#include <linux/devfreq.h>
19#include <linux/devfreq-event.h>
20#include <linux/interrupt.h>
21#include <linux/module.h>
22#include <linux/of.h>
23#include <linux/platform_device.h>
24#include <linux/pm_opp.h>
25#include <linux/regulator/consumer.h>
26#include <linux/rwsem.h>
27#include <linux/suspend.h>
28
29#include <soc/rockchip/rockchip_sip.h>
30
31struct dram_timing {
32 unsigned int ddr3_speed_bin;
33 unsigned int pd_idle;
34 unsigned int sr_idle;
35 unsigned int sr_mc_gate_idle;
36 unsigned int srpd_lite_idle;
37 unsigned int standby_idle;
38 unsigned int auto_pd_dis_freq;
39 unsigned int dram_dll_dis_freq;
40 unsigned int phy_dll_dis_freq;
41 unsigned int ddr3_odt_dis_freq;
42 unsigned int ddr3_drv;
43 unsigned int ddr3_odt;
44 unsigned int phy_ddr3_ca_drv;
45 unsigned int phy_ddr3_dq_drv;
46 unsigned int phy_ddr3_odt;
47 unsigned int lpddr3_odt_dis_freq;
48 unsigned int lpddr3_drv;
49 unsigned int lpddr3_odt;
50 unsigned int phy_lpddr3_ca_drv;
51 unsigned int phy_lpddr3_dq_drv;
52 unsigned int phy_lpddr3_odt;
53 unsigned int lpddr4_odt_dis_freq;
54 unsigned int lpddr4_drv;
55 unsigned int lpddr4_dq_odt;
56 unsigned int lpddr4_ca_odt;
57 unsigned int phy_lpddr4_ca_drv;
58 unsigned int phy_lpddr4_ck_cs_drv;
59 unsigned int phy_lpddr4_dq_drv;
60 unsigned int phy_lpddr4_odt;
61};
62
63struct rk3399_dmcfreq {
64 struct device *dev;
65 struct devfreq *devfreq;
66 struct devfreq_simple_ondemand_data ondemand_data;
67 struct clk *dmc_clk;
68 struct devfreq_event_dev *edev;
69 struct mutex lock;
70 struct dram_timing timing;
71
72 /*
73 * DDR Converser of Frequency (DCF) is used to implement DDR frequency
74 * conversion without the participation of CPU, we will implement and
75 * control it in arm trust firmware.
76 */
77 wait_queue_head_t wait_dcf_queue;
78 int irq;
79 int wait_dcf_flag;
80 struct regulator *vdd_center;
81 unsigned long rate, target_rate;
82 unsigned long volt, target_volt;
83};
84
85static int rk3399_dmcfreq_target(struct device *dev, unsigned long *freq,
86 u32 flags)
87{
88 struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
89 struct dev_pm_opp *opp;
90 unsigned long old_clk_rate = dmcfreq->rate;
91 unsigned long target_volt, target_rate;
92 int err;
93
94 rcu_read_lock();
95 opp = devfreq_recommended_opp(dev, freq, flags);
96 if (IS_ERR(opp)) {
97 rcu_read_unlock();
98 return PTR_ERR(opp);
99 }
100
101 target_rate = dev_pm_opp_get_freq(opp);
102 target_volt = dev_pm_opp_get_voltage(opp);
103
104 rcu_read_unlock();
105
106 if (dmcfreq->rate == target_rate)
107 return 0;
108
109 mutex_lock(&dmcfreq->lock);
110
111 /*
112 * If frequency scaling from low to high, adjust voltage first.
113 * If frequency scaling from high to low, adjust frequency first.
114 */
115 if (old_clk_rate < target_rate) {
116 err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,
117 target_volt);
118 if (err) {
119 dev_err(dev, "Cannot to set voltage %lu uV\n",
120 target_volt);
121 goto out;
122 }
123 }
124 dmcfreq->wait_dcf_flag = 1;
125
126 err = clk_set_rate(dmcfreq->dmc_clk, target_rate);
127 if (err) {
128 dev_err(dev, "Cannot to set frequency %lu (%d)\n",
129 target_rate, err);
130 regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt,
131 dmcfreq->volt);
132 goto out;
133 }
134
135 /*
136 * Wait until bcf irq happen, it means freq scaling finish in
137 * arm trust firmware, use 100ms as timeout time.
138 */
139 if (!wait_event_timeout(dmcfreq->wait_dcf_queue,
140 !dmcfreq->wait_dcf_flag, HZ / 10))
141 dev_warn(dev, "Timeout waiting for dcf interrupt\n");
142
143 /*
144 * Check the dpll rate,
145 * There only two result we will get,
146 * 1. Ddr frequency scaling fail, we still get the old rate.
147 * 2. Ddr frequency scaling sucessful, we get the rate we set.
148 */
149 dmcfreq->rate = clk_get_rate(dmcfreq->dmc_clk);
150
151 /* If get the incorrect rate, set voltage to old value. */
152 if (dmcfreq->rate != target_rate) {
153 dev_err(dev, "Get wrong ddr frequency, Request frequency %lu,\
154 Current frequency %lu\n", target_rate, dmcfreq->rate);
155 regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt,
156 dmcfreq->volt);
157 goto out;
158 } else if (old_clk_rate > target_rate)
159 err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,
160 target_volt);
161 if (err)
162 dev_err(dev, "Cannot to set vol %lu uV\n", target_volt);
163
164 dmcfreq->rate = target_rate;
165 dmcfreq->volt = target_volt;
166
167out:
168 mutex_unlock(&dmcfreq->lock);
169 return err;
170}
171
172static int rk3399_dmcfreq_get_dev_status(struct device *dev,
173 struct devfreq_dev_status *stat)
174{
175 struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
176 struct devfreq_event_data edata;
177 int ret = 0;
178
179 ret = devfreq_event_get_event(dmcfreq->edev, &edata);
180 if (ret < 0)
181 return ret;
182
183 stat->current_frequency = dmcfreq->rate;
184 stat->busy_time = edata.load_count;
185 stat->total_time = edata.total_count;
186
187 return ret;
188}
189
190static int rk3399_dmcfreq_get_cur_freq(struct device *dev, unsigned long *freq)
191{
192 struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
193
194 *freq = dmcfreq->rate;
195
196 return 0;
197}
198
199static struct devfreq_dev_profile rk3399_devfreq_dmc_profile = {
200 .polling_ms = 200,
201 .target = rk3399_dmcfreq_target,
202 .get_dev_status = rk3399_dmcfreq_get_dev_status,
203 .get_cur_freq = rk3399_dmcfreq_get_cur_freq,
204};
205
206static __maybe_unused int rk3399_dmcfreq_suspend(struct device *dev)
207{
208 struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
209 int ret = 0;
210
211 ret = devfreq_event_disable_edev(dmcfreq->edev);
212 if (ret < 0) {
213 dev_err(dev, "failed to disable the devfreq-event devices\n");
214 return ret;
215 }
216
217 ret = devfreq_suspend_device(dmcfreq->devfreq);
218 if (ret < 0) {
219 dev_err(dev, "failed to suspend the devfreq devices\n");
220 return ret;
221 }
222
223 return 0;
224}
225
226static __maybe_unused int rk3399_dmcfreq_resume(struct device *dev)
227{
228 struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
229 int ret = 0;
230
231 ret = devfreq_event_enable_edev(dmcfreq->edev);
232 if (ret < 0) {
233 dev_err(dev, "failed to enable the devfreq-event devices\n");
234 return ret;
235 }
236
237 ret = devfreq_resume_device(dmcfreq->devfreq);
238 if (ret < 0) {
239 dev_err(dev, "failed to resume the devfreq devices\n");
240 return ret;
241 }
242 return ret;
243}
244
245static SIMPLE_DEV_PM_OPS(rk3399_dmcfreq_pm, rk3399_dmcfreq_suspend,
246 rk3399_dmcfreq_resume);
247
248static irqreturn_t rk3399_dmc_irq(int irq, void *dev_id)
249{
250 struct rk3399_dmcfreq *dmcfreq = dev_id;
251 struct arm_smccc_res res;
252
253 dmcfreq->wait_dcf_flag = 0;
254 wake_up(&dmcfreq->wait_dcf_queue);
255
256 /* Clear the DCF interrupt */
257 arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, 0, 0,
258 ROCKCHIP_SIP_CONFIG_DRAM_CLR_IRQ,
259 0, 0, 0, 0, &res);
260
261 return IRQ_HANDLED;
262}
263
264static int of_get_ddr_timings(struct dram_timing *timing,
265 struct device_node *np)
266{
267 int ret = 0;
268
269 ret = of_property_read_u32(np, "rockchip,ddr3_speed_bin",
270 &timing->ddr3_speed_bin);
271 ret |= of_property_read_u32(np, "rockchip,pd_idle",
272 &timing->pd_idle);
273 ret |= of_property_read_u32(np, "rockchip,sr_idle",
274 &timing->sr_idle);
275 ret |= of_property_read_u32(np, "rockchip,sr_mc_gate_idle",
276 &timing->sr_mc_gate_idle);
277 ret |= of_property_read_u32(np, "rockchip,srpd_lite_idle",
278 &timing->srpd_lite_idle);
279 ret |= of_property_read_u32(np, "rockchip,standby_idle",
280 &timing->standby_idle);
281 ret |= of_property_read_u32(np, "rockchip,auto_pd_dis_freq",
282 &timing->auto_pd_dis_freq);
283 ret |= of_property_read_u32(np, "rockchip,dram_dll_dis_freq",
284 &timing->dram_dll_dis_freq);
285 ret |= of_property_read_u32(np, "rockchip,phy_dll_dis_freq",
286 &timing->phy_dll_dis_freq);
287 ret |= of_property_read_u32(np, "rockchip,ddr3_odt_dis_freq",
288 &timing->ddr3_odt_dis_freq);
289 ret |= of_property_read_u32(np, "rockchip,ddr3_drv",
290 &timing->ddr3_drv);
291 ret |= of_property_read_u32(np, "rockchip,ddr3_odt",
292 &timing->ddr3_odt);
293 ret |= of_property_read_u32(np, "rockchip,phy_ddr3_ca_drv",
294 &timing->phy_ddr3_ca_drv);
295 ret |= of_property_read_u32(np, "rockchip,phy_ddr3_dq_drv",
296 &timing->phy_ddr3_dq_drv);
297 ret |= of_property_read_u32(np, "rockchip,phy_ddr3_odt",
298 &timing->phy_ddr3_odt);
299 ret |= of_property_read_u32(np, "rockchip,lpddr3_odt_dis_freq",
300 &timing->lpddr3_odt_dis_freq);
301 ret |= of_property_read_u32(np, "rockchip,lpddr3_drv",
302 &timing->lpddr3_drv);
303 ret |= of_property_read_u32(np, "rockchip,lpddr3_odt",
304 &timing->lpddr3_odt);
305 ret |= of_property_read_u32(np, "rockchip,phy_lpddr3_ca_drv",
306 &timing->phy_lpddr3_ca_drv);
307 ret |= of_property_read_u32(np, "rockchip,phy_lpddr3_dq_drv",
308 &timing->phy_lpddr3_dq_drv);
309 ret |= of_property_read_u32(np, "rockchip,phy_lpddr3_odt",
310 &timing->phy_lpddr3_odt);
311 ret |= of_property_read_u32(np, "rockchip,lpddr4_odt_dis_freq",
312 &timing->lpddr4_odt_dis_freq);
313 ret |= of_property_read_u32(np, "rockchip,lpddr4_drv",
314 &timing->lpddr4_drv);
315 ret |= of_property_read_u32(np, "rockchip,lpddr4_dq_odt",
316 &timing->lpddr4_dq_odt);
317 ret |= of_property_read_u32(np, "rockchip,lpddr4_ca_odt",
318 &timing->lpddr4_ca_odt);
319 ret |= of_property_read_u32(np, "rockchip,phy_lpddr4_ca_drv",
320 &timing->phy_lpddr4_ca_drv);
321 ret |= of_property_read_u32(np, "rockchip,phy_lpddr4_ck_cs_drv",
322 &timing->phy_lpddr4_ck_cs_drv);
323 ret |= of_property_read_u32(np, "rockchip,phy_lpddr4_dq_drv",
324 &timing->phy_lpddr4_dq_drv);
325 ret |= of_property_read_u32(np, "rockchip,phy_lpddr4_odt",
326 &timing->phy_lpddr4_odt);
327
328 return ret;
329}
330
331static int rk3399_dmcfreq_probe(struct platform_device *pdev)
332{
333 struct arm_smccc_res res;
334 struct device *dev = &pdev->dev;
335 struct device_node *np = pdev->dev.of_node;
336 struct rk3399_dmcfreq *data;
337 int ret, irq, index, size;
338 uint32_t *timing;
339 struct dev_pm_opp *opp;
340
341 irq = platform_get_irq(pdev, 0);
342 if (irq < 0) {
343 dev_err(&pdev->dev, "Cannot get the dmc interrupt resource\n");
344 return -EINVAL;
345 }
346 data = devm_kzalloc(dev, sizeof(struct rk3399_dmcfreq), GFP_KERNEL);
347 if (!data)
348 return -ENOMEM;
349
350 mutex_init(&data->lock);
351
352 data->vdd_center = devm_regulator_get(dev, "center");
353 if (IS_ERR(data->vdd_center)) {
354 dev_err(dev, "Cannot get the regulator \"center\"\n");
355 return PTR_ERR(data->vdd_center);
356 }
357
358 data->dmc_clk = devm_clk_get(dev, "dmc_clk");
359 if (IS_ERR(data->dmc_clk)) {
360 dev_err(dev, "Cannot get the clk dmc_clk\n");
361 return PTR_ERR(data->dmc_clk);
362 };
363
364 data->irq = irq;
365 ret = devm_request_irq(dev, irq, rk3399_dmc_irq, 0,
366 dev_name(dev), data);
367 if (ret) {
368 dev_err(dev, "Failed to request dmc irq: %d\n", ret);
369 return ret;
370 }
371
372 init_waitqueue_head(&data->wait_dcf_queue);
373 data->wait_dcf_flag = 0;
374
375 data->edev = devfreq_event_get_edev_by_phandle(dev, 0);
376 if (IS_ERR(data->edev))
377 return -EPROBE_DEFER;
378
379 ret = devfreq_event_enable_edev(data->edev);
380 if (ret < 0) {
381 dev_err(dev, "failed to enable devfreq-event devices\n");
382 return ret;
383 }
384
385 /*
386 * Get dram timing and pass it to arm trust firmware,
387 * the dram drvier in arm trust firmware will get these
388 * timing and to do dram initial.
389 */
390 if (!of_get_ddr_timings(&data->timing, np)) {
391 timing = &data->timing.ddr3_speed_bin;
392 size = sizeof(struct dram_timing) / 4;
393 for (index = 0; index < size; index++) {
394 arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, *timing++, index,
395 ROCKCHIP_SIP_CONFIG_DRAM_SET_PARAM,
396 0, 0, 0, 0, &res);
397 if (res.a0) {
398 dev_err(dev, "Failed to set dram param: %ld\n",
399 res.a0);
400 return -EINVAL;
401 }
402 }
403 }
404
405 arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, 0, 0,
406 ROCKCHIP_SIP_CONFIG_DRAM_INIT,
407 0, 0, 0, 0, &res);
408
409 /*
410 * We add a devfreq driver to our parent since it has a device tree node
411 * with operating points.
412 */
413 if (dev_pm_opp_of_add_table(dev)) {
414 dev_err(dev, "Invalid operating-points in device tree.\n");
415 return -EINVAL;
416 }
417
418 of_property_read_u32(np, "upthreshold",
419 &data->ondemand_data.upthreshold);
420 of_property_read_u32(np, "downdifferential",
421 &data->ondemand_data.downdifferential);
422
423 data->rate = clk_get_rate(data->dmc_clk);
424
425 rcu_read_lock();
426 opp = devfreq_recommended_opp(dev, &data->rate, 0);
427 if (IS_ERR(opp)) {
428 rcu_read_unlock();
429 return PTR_ERR(opp);
430 }
431 data->rate = dev_pm_opp_get_freq(opp);
432 data->volt = dev_pm_opp_get_voltage(opp);
433 rcu_read_unlock();
434
435 rk3399_devfreq_dmc_profile.initial_freq = data->rate;
436
437 data->devfreq = devm_devfreq_add_device(dev,
438 &rk3399_devfreq_dmc_profile,
439 "simple_ondemand",
440 &data->ondemand_data);
441 if (IS_ERR(data->devfreq))
442 return PTR_ERR(data->devfreq);
443 devm_devfreq_register_opp_notifier(dev, data->devfreq);
444
445 data->dev = dev;
446 platform_set_drvdata(pdev, data);
447
448 return 0;
449}
450
451static const struct of_device_id rk3399dmc_devfreq_of_match[] = {
452 { .compatible = "rockchip,rk3399-dmc" },
453 { },
454};
455MODULE_DEVICE_TABLE(of, rk3399dmc_devfreq_of_match);
456
457static struct platform_driver rk3399_dmcfreq_driver = {
458 .probe = rk3399_dmcfreq_probe,
459 .driver = {
460 .name = "rk3399-dmc-freq",
461 .pm = &rk3399_dmcfreq_pm,
462 .of_match_table = rk3399dmc_devfreq_of_match,
463 },
464};
465module_platform_driver(rk3399_dmcfreq_driver);
466
467MODULE_LICENSE("GPL v2");
468MODULE_AUTHOR("Lin Huang <hl@rock-chips.com>");
469MODULE_DESCRIPTION("RK3399 dmcfreq driver with devfreq framework");