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1/*
2 * Resource Director Technology(RDT)
3 * - Cache Allocation code.
4 *
5 * Copyright (C) 2016 Intel Corporation
6 *
7 * Authors:
8 * Fenghua Yu <fenghua.yu@intel.com>
9 * Tony Luck <tony.luck@intel.com>
10 * Vikas Shivappa <vikas.shivappa@intel.com>
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms and conditions of the GNU General Public License,
14 * version 2, as published by the Free Software Foundation.
15 *
16 * This program is distributed in the hope it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * More information about RDT be found in the Intel (R) x86 Architecture
22 * Software Developer Manual June 2016, volume 3, section 17.17.
23 */
24
25#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
26
27#include <linux/slab.h>
28#include <linux/err.h>
29#include <linux/cacheinfo.h>
30#include <linux/cpuhotplug.h>
31
32#include <asm/intel-family.h>
33#include <asm/intel_rdt.h>
34
35/* Mutex to protect rdtgroup access. */
36DEFINE_MUTEX(rdtgroup_mutex);
37
38DEFINE_PER_CPU_READ_MOSTLY(int, cpu_closid);
39
40#define domain_init(id) LIST_HEAD_INIT(rdt_resources_all[id].domains)
41
42struct rdt_resource rdt_resources_all[] = {
43 {
44 .name = "L3",
45 .domains = domain_init(RDT_RESOURCE_L3),
46 .msr_base = IA32_L3_CBM_BASE,
47 .min_cbm_bits = 1,
48 .cache_level = 3,
49 .cbm_idx_multi = 1,
50 .cbm_idx_offset = 0
51 },
52 {
53 .name = "L3DATA",
54 .domains = domain_init(RDT_RESOURCE_L3DATA),
55 .msr_base = IA32_L3_CBM_BASE,
56 .min_cbm_bits = 1,
57 .cache_level = 3,
58 .cbm_idx_multi = 2,
59 .cbm_idx_offset = 0
60 },
61 {
62 .name = "L3CODE",
63 .domains = domain_init(RDT_RESOURCE_L3CODE),
64 .msr_base = IA32_L3_CBM_BASE,
65 .min_cbm_bits = 1,
66 .cache_level = 3,
67 .cbm_idx_multi = 2,
68 .cbm_idx_offset = 1
69 },
70 {
71 .name = "L2",
72 .domains = domain_init(RDT_RESOURCE_L2),
73 .msr_base = IA32_L2_CBM_BASE,
74 .min_cbm_bits = 1,
75 .cache_level = 2,
76 .cbm_idx_multi = 1,
77 .cbm_idx_offset = 0
78 },
79};
80
81static int cbm_idx(struct rdt_resource *r, int closid)
82{
83 return closid * r->cbm_idx_multi + r->cbm_idx_offset;
84}
85
86/*
87 * cache_alloc_hsw_probe() - Have to probe for Intel haswell server CPUs
88 * as they do not have CPUID enumeration support for Cache allocation.
89 * The check for Vendor/Family/Model is not enough to guarantee that
90 * the MSRs won't #GP fault because only the following SKUs support
91 * CAT:
92 * Intel(R) Xeon(R) CPU E5-2658 v3 @ 2.20GHz
93 * Intel(R) Xeon(R) CPU E5-2648L v3 @ 1.80GHz
94 * Intel(R) Xeon(R) CPU E5-2628L v3 @ 2.00GHz
95 * Intel(R) Xeon(R) CPU E5-2618L v3 @ 2.30GHz
96 * Intel(R) Xeon(R) CPU E5-2608L v3 @ 2.00GHz
97 * Intel(R) Xeon(R) CPU E5-2658A v3 @ 2.20GHz
98 *
99 * Probe by trying to write the first of the L3 cach mask registers
100 * and checking that the bits stick. Max CLOSids is always 4 and max cbm length
101 * is always 20 on hsw server parts. The minimum cache bitmask length
102 * allowed for HSW server is always 2 bits. Hardcode all of them.
103 */
104static inline bool cache_alloc_hsw_probe(void)
105{
106 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
107 boot_cpu_data.x86 == 6 &&
108 boot_cpu_data.x86_model == INTEL_FAM6_HASWELL_X) {
109 struct rdt_resource *r = &rdt_resources_all[RDT_RESOURCE_L3];
110 u32 l, h, max_cbm = BIT_MASK(20) - 1;
111
112 if (wrmsr_safe(IA32_L3_CBM_BASE, max_cbm, 0))
113 return false;
114 rdmsr(IA32_L3_CBM_BASE, l, h);
115
116 /* If all the bits were set in MSR, return success */
117 if (l != max_cbm)
118 return false;
119
120 r->num_closid = 4;
121 r->cbm_len = 20;
122 r->max_cbm = max_cbm;
123 r->min_cbm_bits = 2;
124 r->capable = true;
125 r->enabled = true;
126
127 return true;
128 }
129
130 return false;
131}
132
133static void rdt_get_config(int idx, struct rdt_resource *r)
134{
135 union cpuid_0x10_1_eax eax;
136 union cpuid_0x10_1_edx edx;
137 u32 ebx, ecx;
138
139 cpuid_count(0x00000010, idx, &eax.full, &ebx, &ecx, &edx.full);
140 r->num_closid = edx.split.cos_max + 1;
141 r->cbm_len = eax.split.cbm_len + 1;
142 r->max_cbm = BIT_MASK(eax.split.cbm_len + 1) - 1;
143 r->capable = true;
144 r->enabled = true;
145}
146
147static void rdt_get_cdp_l3_config(int type)
148{
149 struct rdt_resource *r_l3 = &rdt_resources_all[RDT_RESOURCE_L3];
150 struct rdt_resource *r = &rdt_resources_all[type];
151
152 r->num_closid = r_l3->num_closid / 2;
153 r->cbm_len = r_l3->cbm_len;
154 r->max_cbm = r_l3->max_cbm;
155 r->capable = true;
156 /*
157 * By default, CDP is disabled. CDP can be enabled by mount parameter
158 * "cdp" during resctrl file system mount time.
159 */
160 r->enabled = false;
161}
162
163static inline bool get_rdt_resources(void)
164{
165 bool ret = false;
166
167 if (cache_alloc_hsw_probe())
168 return true;
169
170 if (!boot_cpu_has(X86_FEATURE_RDT_A))
171 return false;
172
173 if (boot_cpu_has(X86_FEATURE_CAT_L3)) {
174 rdt_get_config(1, &rdt_resources_all[RDT_RESOURCE_L3]);
175 if (boot_cpu_has(X86_FEATURE_CDP_L3)) {
176 rdt_get_cdp_l3_config(RDT_RESOURCE_L3DATA);
177 rdt_get_cdp_l3_config(RDT_RESOURCE_L3CODE);
178 }
179 ret = true;
180 }
181 if (boot_cpu_has(X86_FEATURE_CAT_L2)) {
182 /* CPUID 0x10.2 fields are same format at 0x10.1 */
183 rdt_get_config(2, &rdt_resources_all[RDT_RESOURCE_L2]);
184 ret = true;
185 }
186
187 return ret;
188}
189
190static int get_cache_id(int cpu, int level)
191{
192 struct cpu_cacheinfo *ci = get_cpu_cacheinfo(cpu);
193 int i;
194
195 for (i = 0; i < ci->num_leaves; i++) {
196 if (ci->info_list[i].level == level)
197 return ci->info_list[i].id;
198 }
199
200 return -1;
201}
202
203void rdt_cbm_update(void *arg)
204{
205 struct msr_param *m = (struct msr_param *)arg;
206 struct rdt_resource *r = m->res;
207 int i, cpu = smp_processor_id();
208 struct rdt_domain *d;
209
210 list_for_each_entry(d, &r->domains, list) {
211 /* Find the domain that contains this CPU */
212 if (cpumask_test_cpu(cpu, &d->cpu_mask))
213 goto found;
214 }
215 pr_info_once("cpu %d not found in any domain for resource %s\n",
216 cpu, r->name);
217
218 return;
219
220found:
221 for (i = m->low; i < m->high; i++) {
222 int idx = cbm_idx(r, i);
223
224 wrmsrl(r->msr_base + idx, d->cbm[i]);
225 }
226}
227
228/*
229 * rdt_find_domain - Find a domain in a resource that matches input resource id
230 *
231 * Search resource r's domain list to find the resource id. If the resource
232 * id is found in a domain, return the domain. Otherwise, if requested by
233 * caller, return the first domain whose id is bigger than the input id.
234 * The domain list is sorted by id in ascending order.
235 */
236static struct rdt_domain *rdt_find_domain(struct rdt_resource *r, int id,
237 struct list_head **pos)
238{
239 struct rdt_domain *d;
240 struct list_head *l;
241
242 if (id < 0)
243 return ERR_PTR(id);
244
245 list_for_each(l, &r->domains) {
246 d = list_entry(l, struct rdt_domain, list);
247 /* When id is found, return its domain. */
248 if (id == d->id)
249 return d;
250 /* Stop searching when finding id's position in sorted list. */
251 if (id < d->id)
252 break;
253 }
254
255 if (pos)
256 *pos = l;
257
258 return NULL;
259}
260
261/*
262 * domain_add_cpu - Add a cpu to a resource's domain list.
263 *
264 * If an existing domain in the resource r's domain list matches the cpu's
265 * resource id, add the cpu in the domain.
266 *
267 * Otherwise, a new domain is allocated and inserted into the right position
268 * in the domain list sorted by id in ascending order.
269 *
270 * The order in the domain list is visible to users when we print entries
271 * in the schemata file and schemata input is validated to have the same order
272 * as this list.
273 */
274static void domain_add_cpu(int cpu, struct rdt_resource *r)
275{
276 int i, id = get_cache_id(cpu, r->cache_level);
277 struct list_head *add_pos = NULL;
278 struct rdt_domain *d;
279
280 d = rdt_find_domain(r, id, &add_pos);
281 if (IS_ERR(d)) {
282 pr_warn("Could't find cache id for cpu %d\n", cpu);
283 return;
284 }
285
286 if (d) {
287 cpumask_set_cpu(cpu, &d->cpu_mask);
288 return;
289 }
290
291 d = kzalloc_node(sizeof(*d), GFP_KERNEL, cpu_to_node(cpu));
292 if (!d)
293 return;
294
295 d->id = id;
296
297 d->cbm = kmalloc_array(r->num_closid, sizeof(*d->cbm), GFP_KERNEL);
298 if (!d->cbm) {
299 kfree(d);
300 return;
301 }
302
303 for (i = 0; i < r->num_closid; i++) {
304 int idx = cbm_idx(r, i);
305
306 d->cbm[i] = r->max_cbm;
307 wrmsrl(r->msr_base + idx, d->cbm[i]);
308 }
309
310 cpumask_set_cpu(cpu, &d->cpu_mask);
311 list_add_tail(&d->list, add_pos);
312 r->num_domains++;
313}
314
315static void domain_remove_cpu(int cpu, struct rdt_resource *r)
316{
317 int id = get_cache_id(cpu, r->cache_level);
318 struct rdt_domain *d;
319
320 d = rdt_find_domain(r, id, NULL);
321 if (IS_ERR_OR_NULL(d)) {
322 pr_warn("Could't find cache id for cpu %d\n", cpu);
323 return;
324 }
325
326 cpumask_clear_cpu(cpu, &d->cpu_mask);
327 if (cpumask_empty(&d->cpu_mask)) {
328 r->num_domains--;
329 kfree(d->cbm);
330 list_del(&d->list);
331 kfree(d);
332 }
333}
334
335static void clear_closid(int cpu)
336{
337 struct intel_pqr_state *state = this_cpu_ptr(&pqr_state);
338
339 per_cpu(cpu_closid, cpu) = 0;
340 state->closid = 0;
341 wrmsr(MSR_IA32_PQR_ASSOC, state->rmid, 0);
342}
343
344static int intel_rdt_online_cpu(unsigned int cpu)
345{
346 struct rdt_resource *r;
347
348 mutex_lock(&rdtgroup_mutex);
349 for_each_capable_rdt_resource(r)
350 domain_add_cpu(cpu, r);
351 /* The cpu is set in default rdtgroup after online. */
352 cpumask_set_cpu(cpu, &rdtgroup_default.cpu_mask);
353 clear_closid(cpu);
354 mutex_unlock(&rdtgroup_mutex);
355
356 return 0;
357}
358
359static int intel_rdt_offline_cpu(unsigned int cpu)
360{
361 struct rdtgroup *rdtgrp;
362 struct rdt_resource *r;
363
364 mutex_lock(&rdtgroup_mutex);
365 for_each_capable_rdt_resource(r)
366 domain_remove_cpu(cpu, r);
367 list_for_each_entry(rdtgrp, &rdt_all_groups, rdtgroup_list) {
368 if (cpumask_test_and_clear_cpu(cpu, &rdtgrp->cpu_mask))
369 break;
370 }
371 clear_closid(cpu);
372 mutex_unlock(&rdtgroup_mutex);
373
374 return 0;
375}
376
377static int __init intel_rdt_late_init(void)
378{
379 struct rdt_resource *r;
380 int state, ret;
381
382 if (!get_rdt_resources())
383 return -ENODEV;
384
385 state = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN,
386 "x86/rdt/cat:online:",
387 intel_rdt_online_cpu, intel_rdt_offline_cpu);
388 if (state < 0)
389 return state;
390
391 ret = rdtgroup_init();
392 if (ret) {
393 cpuhp_remove_state(state);
394 return ret;
395 }
396
397 for_each_capable_rdt_resource(r)
398 pr_info("Intel RDT %s allocation detected\n", r->name);
399
400 return 0;
401}
402
403late_initcall(intel_rdt_late_init);