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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2010 Google, Inc.
4 * Copyright (C) 2013 NVIDIA Corporation
5 *
6 * Author:
7 * Erik Gilling <konkers@google.com>
8 * Benoit Goby <benoit@android.com>
9 * Venu Byravarasu <vbyravarasu@nvidia.com>
10 */
11
12#include <linux/delay.h>
13#include <linux/err.h>
14#include <linux/export.h>
15#include <linux/gpio/consumer.h>
16#include <linux/iopoll.h>
17#include <linux/module.h>
18#include <linux/of.h>
19#include <linux/of_device.h>
20#include <linux/platform_device.h>
21#include <linux/resource.h>
22#include <linux/slab.h>
23#include <linux/spinlock.h>
24
25#include <linux/regulator/consumer.h>
26
27#include <linux/usb/ehci_def.h>
28#include <linux/usb/of.h>
29#include <linux/usb/tegra_usb_phy.h>
30#include <linux/usb/ulpi.h>
31
32#define ULPI_VIEWPORT 0x170
33
34/* PORTSC PTS/PHCD bits, Tegra20 only */
35#define TEGRA_USB_PORTSC1 0x184
36#define TEGRA_USB_PORTSC1_PTS(x) (((x) & 0x3) << 30)
37#define TEGRA_USB_PORTSC1_PHCD BIT(23)
38
39/* HOSTPC1 PTS/PHCD bits, Tegra30 and above */
40#define TEGRA_USB_HOSTPC1_DEVLC 0x1b4
41#define TEGRA_USB_HOSTPC1_DEVLC_PTS(x) (((x) & 0x7) << 29)
42#define TEGRA_USB_HOSTPC1_DEVLC_PHCD BIT(22)
43
44/* Bits of PORTSC1, which will get cleared by writing 1 into them */
45#define TEGRA_PORTSC1_RWC_BITS (PORT_CSC | PORT_PEC | PORT_OCC)
46
47#define USB_SUSP_CTRL 0x400
48#define USB_WAKE_ON_CNNT_EN_DEV BIT(3)
49#define USB_WAKE_ON_DISCON_EN_DEV BIT(4)
50#define USB_SUSP_CLR BIT(5)
51#define USB_PHY_CLK_VALID BIT(7)
52#define UTMIP_RESET BIT(11)
53#define UHSIC_RESET BIT(11)
54#define UTMIP_PHY_ENABLE BIT(12)
55#define ULPI_PHY_ENABLE BIT(13)
56#define USB_SUSP_SET BIT(14)
57#define USB_WAKEUP_DEBOUNCE_COUNT(x) (((x) & 0x7) << 16)
58
59#define USB1_LEGACY_CTRL 0x410
60#define USB1_NO_LEGACY_MODE BIT(0)
61#define USB1_VBUS_SENSE_CTL_MASK (3 << 1)
62#define USB1_VBUS_SENSE_CTL_VBUS_WAKEUP (0 << 1)
63#define USB1_VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP \
64 (1 << 1)
65#define USB1_VBUS_SENSE_CTL_AB_SESS_VLD (2 << 1)
66#define USB1_VBUS_SENSE_CTL_A_SESS_VLD (3 << 1)
67
68#define ULPI_TIMING_CTRL_0 0x424
69#define ULPI_OUTPUT_PINMUX_BYP BIT(10)
70#define ULPI_CLKOUT_PINMUX_BYP BIT(11)
71
72#define ULPI_TIMING_CTRL_1 0x428
73#define ULPI_DATA_TRIMMER_LOAD BIT(0)
74#define ULPI_DATA_TRIMMER_SEL(x) (((x) & 0x7) << 1)
75#define ULPI_STPDIRNXT_TRIMMER_LOAD BIT(16)
76#define ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17)
77#define ULPI_DIR_TRIMMER_LOAD BIT(24)
78#define ULPI_DIR_TRIMMER_SEL(x) (((x) & 0x7) << 25)
79
80#define UTMIP_PLL_CFG1 0x804
81#define UTMIP_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
82#define UTMIP_PLLU_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27)
83
84#define UTMIP_XCVR_CFG0 0x808
85#define UTMIP_XCVR_SETUP(x) (((x) & 0xf) << 0)
86#define UTMIP_XCVR_SETUP_MSB(x) ((((x) & 0x70) >> 4) << 22)
87#define UTMIP_XCVR_LSRSLEW(x) (((x) & 0x3) << 8)
88#define UTMIP_XCVR_LSFSLEW(x) (((x) & 0x3) << 10)
89#define UTMIP_FORCE_PD_POWERDOWN BIT(14)
90#define UTMIP_FORCE_PD2_POWERDOWN BIT(16)
91#define UTMIP_FORCE_PDZI_POWERDOWN BIT(18)
92#define UTMIP_XCVR_LSBIAS_SEL BIT(21)
93#define UTMIP_XCVR_HSSLEW(x) (((x) & 0x3) << 4)
94#define UTMIP_XCVR_HSSLEW_MSB(x) ((((x) & 0x1fc) >> 2) << 25)
95
96#define UTMIP_BIAS_CFG0 0x80c
97#define UTMIP_OTGPD BIT(11)
98#define UTMIP_BIASPD BIT(10)
99#define UTMIP_HSSQUELCH_LEVEL(x) (((x) & 0x3) << 0)
100#define UTMIP_HSDISCON_LEVEL(x) (((x) & 0x3) << 2)
101#define UTMIP_HSDISCON_LEVEL_MSB(x) ((((x) & 0x4) >> 2) << 24)
102
103#define UTMIP_HSRX_CFG0 0x810
104#define UTMIP_ELASTIC_LIMIT(x) (((x) & 0x1f) << 10)
105#define UTMIP_IDLE_WAIT(x) (((x) & 0x1f) << 15)
106
107#define UTMIP_HSRX_CFG1 0x814
108#define UTMIP_HS_SYNC_START_DLY(x) (((x) & 0x1f) << 1)
109
110#define UTMIP_TX_CFG0 0x820
111#define UTMIP_FS_PREABMLE_J BIT(19)
112#define UTMIP_HS_DISCON_DISABLE BIT(8)
113
114#define UTMIP_MISC_CFG0 0x824
115#define UTMIP_DPDM_OBSERVE BIT(26)
116#define UTMIP_DPDM_OBSERVE_SEL(x) (((x) & 0xf) << 27)
117#define UTMIP_DPDM_OBSERVE_SEL_FS_J UTMIP_DPDM_OBSERVE_SEL(0xf)
118#define UTMIP_DPDM_OBSERVE_SEL_FS_K UTMIP_DPDM_OBSERVE_SEL(0xe)
119#define UTMIP_DPDM_OBSERVE_SEL_FS_SE1 UTMIP_DPDM_OBSERVE_SEL(0xd)
120#define UTMIP_DPDM_OBSERVE_SEL_FS_SE0 UTMIP_DPDM_OBSERVE_SEL(0xc)
121#define UTMIP_SUSPEND_EXIT_ON_EDGE BIT(22)
122
123#define UTMIP_MISC_CFG1 0x828
124#define UTMIP_PLL_ACTIVE_DLY_COUNT(x) (((x) & 0x1f) << 18)
125#define UTMIP_PLLU_STABLE_COUNT(x) (((x) & 0xfff) << 6)
126
127#define UTMIP_DEBOUNCE_CFG0 0x82c
128#define UTMIP_BIAS_DEBOUNCE_A(x) (((x) & 0xffff) << 0)
129
130#define UTMIP_BAT_CHRG_CFG0 0x830
131#define UTMIP_PD_CHRG BIT(0)
132
133#define UTMIP_SPARE_CFG0 0x834
134#define FUSE_SETUP_SEL BIT(3)
135
136#define UTMIP_XCVR_CFG1 0x838
137#define UTMIP_FORCE_PDDISC_POWERDOWN BIT(0)
138#define UTMIP_FORCE_PDCHRP_POWERDOWN BIT(2)
139#define UTMIP_FORCE_PDDR_POWERDOWN BIT(4)
140#define UTMIP_XCVR_TERM_RANGE_ADJ(x) (((x) & 0xf) << 18)
141
142#define UTMIP_BIAS_CFG1 0x83c
143#define UTMIP_BIAS_PDTRK_COUNT(x) (((x) & 0x1f) << 3)
144
145/* For Tegra30 and above only, the address is different in Tegra20 */
146#define USB_USBMODE 0x1f8
147#define USB_USBMODE_MASK (3 << 0)
148#define USB_USBMODE_HOST (3 << 0)
149#define USB_USBMODE_DEVICE (2 << 0)
150
151static DEFINE_SPINLOCK(utmip_pad_lock);
152static unsigned int utmip_pad_count;
153
154struct tegra_xtal_freq {
155 unsigned int freq;
156 u8 enable_delay;
157 u8 stable_count;
158 u8 active_delay;
159 u8 xtal_freq_count;
160 u16 debounce;
161};
162
163static const struct tegra_xtal_freq tegra_freq_table[] = {
164 {
165 .freq = 12000000,
166 .enable_delay = 0x02,
167 .stable_count = 0x2F,
168 .active_delay = 0x04,
169 .xtal_freq_count = 0x76,
170 .debounce = 0x7530,
171 },
172 {
173 .freq = 13000000,
174 .enable_delay = 0x02,
175 .stable_count = 0x33,
176 .active_delay = 0x05,
177 .xtal_freq_count = 0x7F,
178 .debounce = 0x7EF4,
179 },
180 {
181 .freq = 19200000,
182 .enable_delay = 0x03,
183 .stable_count = 0x4B,
184 .active_delay = 0x06,
185 .xtal_freq_count = 0xBB,
186 .debounce = 0xBB80,
187 },
188 {
189 .freq = 26000000,
190 .enable_delay = 0x04,
191 .stable_count = 0x66,
192 .active_delay = 0x09,
193 .xtal_freq_count = 0xFE,
194 .debounce = 0xFDE8,
195 },
196};
197
198static inline struct tegra_usb_phy *to_tegra_usb_phy(struct usb_phy *u_phy)
199{
200 return container_of(u_phy, struct tegra_usb_phy, u_phy);
201}
202
203static void set_pts(struct tegra_usb_phy *phy, u8 pts_val)
204{
205 void __iomem *base = phy->regs;
206 u32 val;
207
208 if (phy->soc_config->has_hostpc) {
209 val = readl_relaxed(base + TEGRA_USB_HOSTPC1_DEVLC);
210 val &= ~TEGRA_USB_HOSTPC1_DEVLC_PTS(~0);
211 val |= TEGRA_USB_HOSTPC1_DEVLC_PTS(pts_val);
212 writel_relaxed(val, base + TEGRA_USB_HOSTPC1_DEVLC);
213 } else {
214 val = readl_relaxed(base + TEGRA_USB_PORTSC1);
215 val &= ~TEGRA_PORTSC1_RWC_BITS;
216 val &= ~TEGRA_USB_PORTSC1_PTS(~0);
217 val |= TEGRA_USB_PORTSC1_PTS(pts_val);
218 writel_relaxed(val, base + TEGRA_USB_PORTSC1);
219 }
220}
221
222static void set_phcd(struct tegra_usb_phy *phy, bool enable)
223{
224 void __iomem *base = phy->regs;
225 u32 val;
226
227 if (phy->soc_config->has_hostpc) {
228 val = readl_relaxed(base + TEGRA_USB_HOSTPC1_DEVLC);
229 if (enable)
230 val |= TEGRA_USB_HOSTPC1_DEVLC_PHCD;
231 else
232 val &= ~TEGRA_USB_HOSTPC1_DEVLC_PHCD;
233 writel_relaxed(val, base + TEGRA_USB_HOSTPC1_DEVLC);
234 } else {
235 val = readl_relaxed(base + TEGRA_USB_PORTSC1) & ~PORT_RWC_BITS;
236 if (enable)
237 val |= TEGRA_USB_PORTSC1_PHCD;
238 else
239 val &= ~TEGRA_USB_PORTSC1_PHCD;
240 writel_relaxed(val, base + TEGRA_USB_PORTSC1);
241 }
242}
243
244static int utmip_pad_open(struct tegra_usb_phy *phy)
245{
246 int ret;
247
248 ret = clk_prepare_enable(phy->pad_clk);
249 if (ret) {
250 dev_err(phy->u_phy.dev,
251 "Failed to enable UTMI-pads clock: %d\n", ret);
252 return ret;
253 }
254
255 spin_lock(&utmip_pad_lock);
256
257 ret = reset_control_deassert(phy->pad_rst);
258 if (ret) {
259 dev_err(phy->u_phy.dev,
260 "Failed to initialize UTMI-pads reset: %d\n", ret);
261 goto unlock;
262 }
263
264 ret = reset_control_assert(phy->pad_rst);
265 if (ret) {
266 dev_err(phy->u_phy.dev,
267 "Failed to assert UTMI-pads reset: %d\n", ret);
268 goto unlock;
269 }
270
271 udelay(1);
272
273 ret = reset_control_deassert(phy->pad_rst);
274 if (ret)
275 dev_err(phy->u_phy.dev,
276 "Failed to deassert UTMI-pads reset: %d\n", ret);
277unlock:
278 spin_unlock(&utmip_pad_lock);
279
280 clk_disable_unprepare(phy->pad_clk);
281
282 return ret;
283}
284
285static int utmip_pad_close(struct tegra_usb_phy *phy)
286{
287 int ret;
288
289 ret = clk_prepare_enable(phy->pad_clk);
290 if (ret) {
291 dev_err(phy->u_phy.dev,
292 "Failed to enable UTMI-pads clock: %d\n", ret);
293 return ret;
294 }
295
296 ret = reset_control_assert(phy->pad_rst);
297 if (ret)
298 dev_err(phy->u_phy.dev,
299 "Failed to assert UTMI-pads reset: %d\n", ret);
300
301 udelay(1);
302
303 clk_disable_unprepare(phy->pad_clk);
304
305 return ret;
306}
307
308static int utmip_pad_power_on(struct tegra_usb_phy *phy)
309{
310 struct tegra_utmip_config *config = phy->config;
311 void __iomem *base = phy->pad_regs;
312 u32 val;
313 int err;
314
315 err = clk_prepare_enable(phy->pad_clk);
316 if (err)
317 return err;
318
319 spin_lock(&utmip_pad_lock);
320
321 if (utmip_pad_count++ == 0) {
322 val = readl_relaxed(base + UTMIP_BIAS_CFG0);
323 val &= ~(UTMIP_OTGPD | UTMIP_BIASPD);
324
325 if (phy->soc_config->requires_extra_tuning_parameters) {
326 val &= ~(UTMIP_HSSQUELCH_LEVEL(~0) |
327 UTMIP_HSDISCON_LEVEL(~0) |
328 UTMIP_HSDISCON_LEVEL_MSB(~0));
329
330 val |= UTMIP_HSSQUELCH_LEVEL(config->hssquelch_level);
331 val |= UTMIP_HSDISCON_LEVEL(config->hsdiscon_level);
332 val |= UTMIP_HSDISCON_LEVEL_MSB(config->hsdiscon_level);
333 }
334 writel_relaxed(val, base + UTMIP_BIAS_CFG0);
335 }
336
337 spin_unlock(&utmip_pad_lock);
338
339 clk_disable_unprepare(phy->pad_clk);
340
341 return 0;
342}
343
344static int utmip_pad_power_off(struct tegra_usb_phy *phy)
345{
346 void __iomem *base = phy->pad_regs;
347 u32 val;
348 int ret;
349
350 ret = clk_prepare_enable(phy->pad_clk);
351 if (ret)
352 return ret;
353
354 spin_lock(&utmip_pad_lock);
355
356 if (!utmip_pad_count) {
357 dev_err(phy->u_phy.dev, "UTMIP pad already powered off\n");
358 ret = -EINVAL;
359 goto ulock;
360 }
361
362 if (--utmip_pad_count == 0) {
363 val = readl_relaxed(base + UTMIP_BIAS_CFG0);
364 val |= UTMIP_OTGPD | UTMIP_BIASPD;
365 writel_relaxed(val, base + UTMIP_BIAS_CFG0);
366 }
367ulock:
368 spin_unlock(&utmip_pad_lock);
369
370 clk_disable_unprepare(phy->pad_clk);
371
372 return ret;
373}
374
375static int utmi_wait_register(void __iomem *reg, u32 mask, u32 result)
376{
377 u32 tmp;
378
379 return readl_relaxed_poll_timeout(reg, tmp, (tmp & mask) == result,
380 2000, 6000);
381}
382
383static void utmi_phy_clk_disable(struct tegra_usb_phy *phy)
384{
385 void __iomem *base = phy->regs;
386 u32 val;
387
388 /*
389 * The USB driver may have already initiated the phy clock
390 * disable so wait to see if the clock turns off and if not
391 * then proceed with gating the clock.
392 */
393 if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, 0) == 0)
394 return;
395
396 if (phy->is_legacy_phy) {
397 val = readl_relaxed(base + USB_SUSP_CTRL);
398 val |= USB_SUSP_SET;
399 writel_relaxed(val, base + USB_SUSP_CTRL);
400
401 usleep_range(10, 100);
402
403 val = readl_relaxed(base + USB_SUSP_CTRL);
404 val &= ~USB_SUSP_SET;
405 writel_relaxed(val, base + USB_SUSP_CTRL);
406 } else {
407 set_phcd(phy, true);
408 }
409
410 if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, 0))
411 dev_err(phy->u_phy.dev,
412 "Timeout waiting for PHY to stabilize on disable\n");
413}
414
415static void utmi_phy_clk_enable(struct tegra_usb_phy *phy)
416{
417 void __iomem *base = phy->regs;
418 u32 val;
419
420 /*
421 * The USB driver may have already initiated the phy clock
422 * enable so wait to see if the clock turns on and if not
423 * then proceed with ungating the clock.
424 */
425 if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
426 USB_PHY_CLK_VALID) == 0)
427 return;
428
429 if (phy->is_legacy_phy) {
430 val = readl_relaxed(base + USB_SUSP_CTRL);
431 val |= USB_SUSP_CLR;
432 writel_relaxed(val, base + USB_SUSP_CTRL);
433
434 usleep_range(10, 100);
435
436 val = readl_relaxed(base + USB_SUSP_CTRL);
437 val &= ~USB_SUSP_CLR;
438 writel_relaxed(val, base + USB_SUSP_CTRL);
439 } else {
440 set_phcd(phy, false);
441 }
442
443 if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
444 USB_PHY_CLK_VALID))
445 dev_err(phy->u_phy.dev,
446 "Timeout waiting for PHY to stabilize on enable\n");
447}
448
449static int utmi_phy_power_on(struct tegra_usb_phy *phy)
450{
451 struct tegra_utmip_config *config = phy->config;
452 void __iomem *base = phy->regs;
453 u32 val;
454 int err;
455
456 val = readl_relaxed(base + USB_SUSP_CTRL);
457 val |= UTMIP_RESET;
458 writel_relaxed(val, base + USB_SUSP_CTRL);
459
460 if (phy->is_legacy_phy) {
461 val = readl_relaxed(base + USB1_LEGACY_CTRL);
462 val |= USB1_NO_LEGACY_MODE;
463 writel_relaxed(val, base + USB1_LEGACY_CTRL);
464 }
465
466 val = readl_relaxed(base + UTMIP_TX_CFG0);
467 val |= UTMIP_FS_PREABMLE_J;
468 writel_relaxed(val, base + UTMIP_TX_CFG0);
469
470 val = readl_relaxed(base + UTMIP_HSRX_CFG0);
471 val &= ~(UTMIP_IDLE_WAIT(~0) | UTMIP_ELASTIC_LIMIT(~0));
472 val |= UTMIP_IDLE_WAIT(config->idle_wait_delay);
473 val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit);
474 writel_relaxed(val, base + UTMIP_HSRX_CFG0);
475
476 val = readl_relaxed(base + UTMIP_HSRX_CFG1);
477 val &= ~UTMIP_HS_SYNC_START_DLY(~0);
478 val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay);
479 writel_relaxed(val, base + UTMIP_HSRX_CFG1);
480
481 val = readl_relaxed(base + UTMIP_DEBOUNCE_CFG0);
482 val &= ~UTMIP_BIAS_DEBOUNCE_A(~0);
483 val |= UTMIP_BIAS_DEBOUNCE_A(phy->freq->debounce);
484 writel_relaxed(val, base + UTMIP_DEBOUNCE_CFG0);
485
486 val = readl_relaxed(base + UTMIP_MISC_CFG0);
487 val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE;
488 writel_relaxed(val, base + UTMIP_MISC_CFG0);
489
490 if (!phy->soc_config->utmi_pll_config_in_car_module) {
491 val = readl_relaxed(base + UTMIP_MISC_CFG1);
492 val &= ~(UTMIP_PLL_ACTIVE_DLY_COUNT(~0) |
493 UTMIP_PLLU_STABLE_COUNT(~0));
494 val |= UTMIP_PLL_ACTIVE_DLY_COUNT(phy->freq->active_delay) |
495 UTMIP_PLLU_STABLE_COUNT(phy->freq->stable_count);
496 writel_relaxed(val, base + UTMIP_MISC_CFG1);
497
498 val = readl_relaxed(base + UTMIP_PLL_CFG1);
499 val &= ~(UTMIP_XTAL_FREQ_COUNT(~0) |
500 UTMIP_PLLU_ENABLE_DLY_COUNT(~0));
501 val |= UTMIP_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count) |
502 UTMIP_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay);
503 writel_relaxed(val, base + UTMIP_PLL_CFG1);
504 }
505
506 if (phy->mode == USB_DR_MODE_PERIPHERAL) {
507 val = readl_relaxed(base + USB_SUSP_CTRL);
508 val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV);
509 writel_relaxed(val, base + USB_SUSP_CTRL);
510
511 val = readl_relaxed(base + UTMIP_BAT_CHRG_CFG0);
512 val &= ~UTMIP_PD_CHRG;
513 writel_relaxed(val, base + UTMIP_BAT_CHRG_CFG0);
514 } else {
515 val = readl_relaxed(base + UTMIP_BAT_CHRG_CFG0);
516 val |= UTMIP_PD_CHRG;
517 writel_relaxed(val, base + UTMIP_BAT_CHRG_CFG0);
518 }
519
520 err = utmip_pad_power_on(phy);
521 if (err)
522 return err;
523
524 val = readl_relaxed(base + UTMIP_XCVR_CFG0);
525 val &= ~(UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
526 UTMIP_FORCE_PDZI_POWERDOWN | UTMIP_XCVR_LSBIAS_SEL |
527 UTMIP_XCVR_SETUP(~0) | UTMIP_XCVR_SETUP_MSB(~0) |
528 UTMIP_XCVR_LSFSLEW(~0) | UTMIP_XCVR_LSRSLEW(~0));
529
530 if (!config->xcvr_setup_use_fuses) {
531 val |= UTMIP_XCVR_SETUP(config->xcvr_setup);
532 val |= UTMIP_XCVR_SETUP_MSB(config->xcvr_setup);
533 }
534 val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew);
535 val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew);
536
537 if (phy->soc_config->requires_extra_tuning_parameters) {
538 val &= ~(UTMIP_XCVR_HSSLEW(~0) | UTMIP_XCVR_HSSLEW_MSB(~0));
539 val |= UTMIP_XCVR_HSSLEW(config->xcvr_hsslew);
540 val |= UTMIP_XCVR_HSSLEW_MSB(config->xcvr_hsslew);
541 }
542 writel_relaxed(val, base + UTMIP_XCVR_CFG0);
543
544 val = readl_relaxed(base + UTMIP_XCVR_CFG1);
545 val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
546 UTMIP_FORCE_PDDR_POWERDOWN | UTMIP_XCVR_TERM_RANGE_ADJ(~0));
547 val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj);
548 writel_relaxed(val, base + UTMIP_XCVR_CFG1);
549
550 val = readl_relaxed(base + UTMIP_BIAS_CFG1);
551 val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
552 val |= UTMIP_BIAS_PDTRK_COUNT(0x5);
553 writel_relaxed(val, base + UTMIP_BIAS_CFG1);
554
555 val = readl_relaxed(base + UTMIP_SPARE_CFG0);
556 if (config->xcvr_setup_use_fuses)
557 val |= FUSE_SETUP_SEL;
558 else
559 val &= ~FUSE_SETUP_SEL;
560 writel_relaxed(val, base + UTMIP_SPARE_CFG0);
561
562 if (!phy->is_legacy_phy) {
563 val = readl_relaxed(base + USB_SUSP_CTRL);
564 val |= UTMIP_PHY_ENABLE;
565 writel_relaxed(val, base + USB_SUSP_CTRL);
566 }
567
568 val = readl_relaxed(base + USB_SUSP_CTRL);
569 val &= ~UTMIP_RESET;
570 writel_relaxed(val, base + USB_SUSP_CTRL);
571
572 if (phy->is_legacy_phy) {
573 val = readl_relaxed(base + USB1_LEGACY_CTRL);
574 val &= ~USB1_VBUS_SENSE_CTL_MASK;
575 val |= USB1_VBUS_SENSE_CTL_A_SESS_VLD;
576 writel_relaxed(val, base + USB1_LEGACY_CTRL);
577
578 val = readl_relaxed(base + USB_SUSP_CTRL);
579 val &= ~USB_SUSP_SET;
580 writel_relaxed(val, base + USB_SUSP_CTRL);
581 }
582
583 utmi_phy_clk_enable(phy);
584
585 if (phy->soc_config->requires_usbmode_setup) {
586 val = readl_relaxed(base + USB_USBMODE);
587 val &= ~USB_USBMODE_MASK;
588 if (phy->mode == USB_DR_MODE_HOST)
589 val |= USB_USBMODE_HOST;
590 else
591 val |= USB_USBMODE_DEVICE;
592 writel_relaxed(val, base + USB_USBMODE);
593 }
594
595 if (!phy->is_legacy_phy)
596 set_pts(phy, 0);
597
598 return 0;
599}
600
601static int utmi_phy_power_off(struct tegra_usb_phy *phy)
602{
603 void __iomem *base = phy->regs;
604 u32 val;
605
606 utmi_phy_clk_disable(phy);
607
608 if (phy->mode == USB_DR_MODE_PERIPHERAL) {
609 val = readl_relaxed(base + USB_SUSP_CTRL);
610 val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0);
611 val |= USB_WAKE_ON_CNNT_EN_DEV | USB_WAKEUP_DEBOUNCE_COUNT(5);
612 writel_relaxed(val, base + USB_SUSP_CTRL);
613 }
614
615 val = readl_relaxed(base + USB_SUSP_CTRL);
616 val |= UTMIP_RESET;
617 writel_relaxed(val, base + USB_SUSP_CTRL);
618
619 val = readl_relaxed(base + UTMIP_BAT_CHRG_CFG0);
620 val |= UTMIP_PD_CHRG;
621 writel_relaxed(val, base + UTMIP_BAT_CHRG_CFG0);
622
623 val = readl_relaxed(base + UTMIP_XCVR_CFG0);
624 val |= UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
625 UTMIP_FORCE_PDZI_POWERDOWN;
626 writel_relaxed(val, base + UTMIP_XCVR_CFG0);
627
628 val = readl_relaxed(base + UTMIP_XCVR_CFG1);
629 val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
630 UTMIP_FORCE_PDDR_POWERDOWN;
631 writel_relaxed(val, base + UTMIP_XCVR_CFG1);
632
633 return utmip_pad_power_off(phy);
634}
635
636static void utmi_phy_preresume(struct tegra_usb_phy *phy)
637{
638 void __iomem *base = phy->regs;
639 u32 val;
640
641 val = readl_relaxed(base + UTMIP_TX_CFG0);
642 val |= UTMIP_HS_DISCON_DISABLE;
643 writel_relaxed(val, base + UTMIP_TX_CFG0);
644}
645
646static void utmi_phy_postresume(struct tegra_usb_phy *phy)
647{
648 void __iomem *base = phy->regs;
649 u32 val;
650
651 val = readl_relaxed(base + UTMIP_TX_CFG0);
652 val &= ~UTMIP_HS_DISCON_DISABLE;
653 writel_relaxed(val, base + UTMIP_TX_CFG0);
654}
655
656static void utmi_phy_restore_start(struct tegra_usb_phy *phy,
657 enum tegra_usb_phy_port_speed port_speed)
658{
659 void __iomem *base = phy->regs;
660 u32 val;
661
662 val = readl_relaxed(base + UTMIP_MISC_CFG0);
663 val &= ~UTMIP_DPDM_OBSERVE_SEL(~0);
664 if (port_speed == TEGRA_USB_PHY_PORT_SPEED_LOW)
665 val |= UTMIP_DPDM_OBSERVE_SEL_FS_K;
666 else
667 val |= UTMIP_DPDM_OBSERVE_SEL_FS_J;
668 writel_relaxed(val, base + UTMIP_MISC_CFG0);
669 usleep_range(1, 10);
670
671 val = readl_relaxed(base + UTMIP_MISC_CFG0);
672 val |= UTMIP_DPDM_OBSERVE;
673 writel_relaxed(val, base + UTMIP_MISC_CFG0);
674 usleep_range(10, 100);
675}
676
677static void utmi_phy_restore_end(struct tegra_usb_phy *phy)
678{
679 void __iomem *base = phy->regs;
680 u32 val;
681
682 val = readl_relaxed(base + UTMIP_MISC_CFG0);
683 val &= ~UTMIP_DPDM_OBSERVE;
684 writel_relaxed(val, base + UTMIP_MISC_CFG0);
685 usleep_range(10, 100);
686}
687
688static int ulpi_phy_power_on(struct tegra_usb_phy *phy)
689{
690 void __iomem *base = phy->regs;
691 u32 val;
692 int err;
693
694 gpiod_set_value_cansleep(phy->reset_gpio, 1);
695
696 err = clk_prepare_enable(phy->clk);
697 if (err)
698 return err;
699
700 usleep_range(5000, 6000);
701
702 gpiod_set_value_cansleep(phy->reset_gpio, 0);
703
704 usleep_range(1000, 2000);
705
706 val = readl_relaxed(base + USB_SUSP_CTRL);
707 val |= UHSIC_RESET;
708 writel_relaxed(val, base + USB_SUSP_CTRL);
709
710 val = readl_relaxed(base + ULPI_TIMING_CTRL_0);
711 val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP;
712 writel_relaxed(val, base + ULPI_TIMING_CTRL_0);
713
714 val = readl_relaxed(base + USB_SUSP_CTRL);
715 val |= ULPI_PHY_ENABLE;
716 writel_relaxed(val, base + USB_SUSP_CTRL);
717
718 val = 0;
719 writel_relaxed(val, base + ULPI_TIMING_CTRL_1);
720
721 val |= ULPI_DATA_TRIMMER_SEL(4);
722 val |= ULPI_STPDIRNXT_TRIMMER_SEL(4);
723 val |= ULPI_DIR_TRIMMER_SEL(4);
724 writel_relaxed(val, base + ULPI_TIMING_CTRL_1);
725 usleep_range(10, 100);
726
727 val |= ULPI_DATA_TRIMMER_LOAD;
728 val |= ULPI_STPDIRNXT_TRIMMER_LOAD;
729 val |= ULPI_DIR_TRIMMER_LOAD;
730 writel_relaxed(val, base + ULPI_TIMING_CTRL_1);
731
732 /* Fix VbusInvalid due to floating VBUS */
733 err = usb_phy_io_write(phy->ulpi, 0x40, 0x08);
734 if (err) {
735 dev_err(phy->u_phy.dev, "ULPI write failed: %d\n", err);
736 goto disable_clk;
737 }
738
739 err = usb_phy_io_write(phy->ulpi, 0x80, 0x0B);
740 if (err) {
741 dev_err(phy->u_phy.dev, "ULPI write failed: %d\n", err);
742 goto disable_clk;
743 }
744
745 val = readl_relaxed(base + USB_SUSP_CTRL);
746 val |= USB_SUSP_CLR;
747 writel_relaxed(val, base + USB_SUSP_CTRL);
748 usleep_range(100, 1000);
749
750 val = readl_relaxed(base + USB_SUSP_CTRL);
751 val &= ~USB_SUSP_CLR;
752 writel_relaxed(val, base + USB_SUSP_CTRL);
753
754 return 0;
755
756disable_clk:
757 clk_disable_unprepare(phy->clk);
758
759 return err;
760}
761
762static int ulpi_phy_power_off(struct tegra_usb_phy *phy)
763{
764 gpiod_set_value_cansleep(phy->reset_gpio, 1);
765 usleep_range(5000, 6000);
766 clk_disable_unprepare(phy->clk);
767
768 return 0;
769}
770
771static int tegra_usb_phy_power_on(struct tegra_usb_phy *phy)
772{
773 int err;
774
775 if (phy->powered_on)
776 return 0;
777
778 if (phy->is_ulpi_phy)
779 err = ulpi_phy_power_on(phy);
780 else
781 err = utmi_phy_power_on(phy);
782 if (err)
783 return err;
784
785 phy->powered_on = true;
786
787 return 0;
788}
789
790static int tegra_usb_phy_power_off(struct tegra_usb_phy *phy)
791{
792 int err;
793
794 if (!phy->powered_on)
795 return 0;
796
797 if (phy->is_ulpi_phy)
798 err = ulpi_phy_power_off(phy);
799 else
800 err = utmi_phy_power_off(phy);
801 if (err)
802 return err;
803
804 phy->powered_on = false;
805
806 return 0;
807}
808
809static void tegra_usb_phy_shutdown(struct usb_phy *u_phy)
810{
811 struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy);
812
813 if (WARN_ON(!phy->freq))
814 return;
815
816 tegra_usb_phy_power_off(phy);
817
818 if (!phy->is_ulpi_phy)
819 utmip_pad_close(phy);
820
821 regulator_disable(phy->vbus);
822 clk_disable_unprepare(phy->pll_u);
823
824 phy->freq = NULL;
825}
826
827static int tegra_usb_phy_set_suspend(struct usb_phy *u_phy, int suspend)
828{
829 struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy);
830
831 if (WARN_ON(!phy->freq))
832 return -EINVAL;
833
834 if (suspend)
835 return tegra_usb_phy_power_off(phy);
836 else
837 return tegra_usb_phy_power_on(phy);
838}
839
840static int tegra_usb_phy_init(struct usb_phy *u_phy)
841{
842 struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy);
843 unsigned long parent_rate;
844 unsigned int i;
845 int err;
846
847 if (WARN_ON(phy->freq))
848 return 0;
849
850 err = clk_prepare_enable(phy->pll_u);
851 if (err)
852 return err;
853
854 parent_rate = clk_get_rate(clk_get_parent(phy->pll_u));
855 for (i = 0; i < ARRAY_SIZE(tegra_freq_table); i++) {
856 if (tegra_freq_table[i].freq == parent_rate) {
857 phy->freq = &tegra_freq_table[i];
858 break;
859 }
860 }
861 if (!phy->freq) {
862 dev_err(phy->u_phy.dev, "Invalid pll_u parent rate %ld\n",
863 parent_rate);
864 err = -EINVAL;
865 goto disable_clk;
866 }
867
868 err = regulator_enable(phy->vbus);
869 if (err) {
870 dev_err(phy->u_phy.dev,
871 "Failed to enable USB VBUS regulator: %d\n", err);
872 goto disable_clk;
873 }
874
875 if (!phy->is_ulpi_phy) {
876 err = utmip_pad_open(phy);
877 if (err)
878 goto disable_vbus;
879 }
880
881 err = tegra_usb_phy_power_on(phy);
882 if (err)
883 goto close_phy;
884
885 return 0;
886
887close_phy:
888 if (!phy->is_ulpi_phy)
889 utmip_pad_close(phy);
890
891disable_vbus:
892 regulator_disable(phy->vbus);
893
894disable_clk:
895 clk_disable_unprepare(phy->pll_u);
896
897 phy->freq = NULL;
898
899 return err;
900}
901
902void tegra_usb_phy_preresume(struct usb_phy *u_phy)
903{
904 struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy);
905
906 if (!phy->is_ulpi_phy)
907 utmi_phy_preresume(phy);
908}
909EXPORT_SYMBOL_GPL(tegra_usb_phy_preresume);
910
911void tegra_usb_phy_postresume(struct usb_phy *u_phy)
912{
913 struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy);
914
915 if (!phy->is_ulpi_phy)
916 utmi_phy_postresume(phy);
917}
918EXPORT_SYMBOL_GPL(tegra_usb_phy_postresume);
919
920void tegra_ehci_phy_restore_start(struct usb_phy *u_phy,
921 enum tegra_usb_phy_port_speed port_speed)
922{
923 struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy);
924
925 if (!phy->is_ulpi_phy)
926 utmi_phy_restore_start(phy, port_speed);
927}
928EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_start);
929
930void tegra_ehci_phy_restore_end(struct usb_phy *u_phy)
931{
932 struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy);
933
934 if (!phy->is_ulpi_phy)
935 utmi_phy_restore_end(phy);
936}
937EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_end);
938
939static int read_utmi_param(struct platform_device *pdev, const char *param,
940 u8 *dest)
941{
942 u32 value;
943 int err;
944
945 err = of_property_read_u32(pdev->dev.of_node, param, &value);
946 if (err)
947 dev_err(&pdev->dev,
948 "Failed to read USB UTMI parameter %s: %d\n",
949 param, err);
950 else
951 *dest = value;
952
953 return err;
954}
955
956static int utmi_phy_probe(struct tegra_usb_phy *tegra_phy,
957 struct platform_device *pdev)
958{
959 struct tegra_utmip_config *config;
960 struct resource *res;
961 int err;
962
963 tegra_phy->is_ulpi_phy = false;
964
965 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
966 if (!res) {
967 dev_err(&pdev->dev, "Failed to get UTMI pad regs\n");
968 return -ENXIO;
969 }
970
971 /*
972 * Note that UTMI pad registers are shared by all PHYs, therefore
973 * devm_platform_ioremap_resource() can't be used here.
974 */
975 tegra_phy->pad_regs = devm_ioremap(&pdev->dev, res->start,
976 resource_size(res));
977 if (!tegra_phy->pad_regs) {
978 dev_err(&pdev->dev, "Failed to remap UTMI pad regs\n");
979 return -ENOMEM;
980 }
981
982 tegra_phy->config = devm_kzalloc(&pdev->dev, sizeof(*config),
983 GFP_KERNEL);
984 if (!tegra_phy->config)
985 return -ENOMEM;
986
987 config = tegra_phy->config;
988
989 err = read_utmi_param(pdev, "nvidia,hssync-start-delay",
990 &config->hssync_start_delay);
991 if (err)
992 return err;
993
994 err = read_utmi_param(pdev, "nvidia,elastic-limit",
995 &config->elastic_limit);
996 if (err)
997 return err;
998
999 err = read_utmi_param(pdev, "nvidia,idle-wait-delay",
1000 &config->idle_wait_delay);
1001 if (err)
1002 return err;
1003
1004 err = read_utmi_param(pdev, "nvidia,term-range-adj",
1005 &config->term_range_adj);
1006 if (err)
1007 return err;
1008
1009 err = read_utmi_param(pdev, "nvidia,xcvr-lsfslew",
1010 &config->xcvr_lsfslew);
1011 if (err)
1012 return err;
1013
1014 err = read_utmi_param(pdev, "nvidia,xcvr-lsrslew",
1015 &config->xcvr_lsrslew);
1016 if (err)
1017 return err;
1018
1019 if (tegra_phy->soc_config->requires_extra_tuning_parameters) {
1020 err = read_utmi_param(pdev, "nvidia,xcvr-hsslew",
1021 &config->xcvr_hsslew);
1022 if (err)
1023 return err;
1024
1025 err = read_utmi_param(pdev, "nvidia,hssquelch-level",
1026 &config->hssquelch_level);
1027 if (err)
1028 return err;
1029
1030 err = read_utmi_param(pdev, "nvidia,hsdiscon-level",
1031 &config->hsdiscon_level);
1032 if (err)
1033 return err;
1034 }
1035
1036 config->xcvr_setup_use_fuses = of_property_read_bool(
1037 pdev->dev.of_node, "nvidia,xcvr-setup-use-fuses");
1038
1039 if (!config->xcvr_setup_use_fuses) {
1040 err = read_utmi_param(pdev, "nvidia,xcvr-setup",
1041 &config->xcvr_setup);
1042 if (err)
1043 return err;
1044 }
1045
1046 return 0;
1047}
1048
1049static const struct tegra_phy_soc_config tegra20_soc_config = {
1050 .utmi_pll_config_in_car_module = false,
1051 .has_hostpc = false,
1052 .requires_usbmode_setup = false,
1053 .requires_extra_tuning_parameters = false,
1054};
1055
1056static const struct tegra_phy_soc_config tegra30_soc_config = {
1057 .utmi_pll_config_in_car_module = true,
1058 .has_hostpc = true,
1059 .requires_usbmode_setup = true,
1060 .requires_extra_tuning_parameters = true,
1061};
1062
1063static const struct of_device_id tegra_usb_phy_id_table[] = {
1064 { .compatible = "nvidia,tegra30-usb-phy", .data = &tegra30_soc_config },
1065 { .compatible = "nvidia,tegra20-usb-phy", .data = &tegra20_soc_config },
1066 { },
1067};
1068MODULE_DEVICE_TABLE(of, tegra_usb_phy_id_table);
1069
1070static int tegra_usb_phy_probe(struct platform_device *pdev)
1071{
1072 struct device_node *np = pdev->dev.of_node;
1073 struct tegra_usb_phy *tegra_phy;
1074 enum usb_phy_interface phy_type;
1075 struct reset_control *reset;
1076 struct gpio_desc *gpiod;
1077 struct resource *res;
1078 struct usb_phy *phy;
1079 int err;
1080
1081 tegra_phy = devm_kzalloc(&pdev->dev, sizeof(*tegra_phy), GFP_KERNEL);
1082 if (!tegra_phy)
1083 return -ENOMEM;
1084
1085 tegra_phy->soc_config = of_device_get_match_data(&pdev->dev);
1086
1087 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1088 if (!res) {
1089 dev_err(&pdev->dev, "Failed to get I/O memory\n");
1090 return -ENXIO;
1091 }
1092
1093 /*
1094 * Note that PHY and USB controller are using shared registers,
1095 * therefore devm_platform_ioremap_resource() can't be used here.
1096 */
1097 tegra_phy->regs = devm_ioremap(&pdev->dev, res->start,
1098 resource_size(res));
1099 if (!tegra_phy->regs) {
1100 dev_err(&pdev->dev, "Failed to remap I/O memory\n");
1101 return -ENOMEM;
1102 }
1103
1104 tegra_phy->is_legacy_phy =
1105 of_property_read_bool(np, "nvidia,has-legacy-mode");
1106
1107 if (of_find_property(np, "dr_mode", NULL))
1108 tegra_phy->mode = usb_get_dr_mode(&pdev->dev);
1109 else
1110 tegra_phy->mode = USB_DR_MODE_HOST;
1111
1112 if (tegra_phy->mode == USB_DR_MODE_UNKNOWN) {
1113 dev_err(&pdev->dev, "dr_mode is invalid\n");
1114 return -EINVAL;
1115 }
1116
1117 /* On some boards, the VBUS regulator doesn't need to be controlled */
1118 tegra_phy->vbus = devm_regulator_get(&pdev->dev, "vbus");
1119 if (IS_ERR(tegra_phy->vbus))
1120 return PTR_ERR(tegra_phy->vbus);
1121
1122 tegra_phy->pll_u = devm_clk_get(&pdev->dev, "pll_u");
1123 err = PTR_ERR_OR_ZERO(tegra_phy->pll_u);
1124 if (err) {
1125 dev_err(&pdev->dev, "Failed to get pll_u clock: %d\n", err);
1126 return err;
1127 }
1128
1129 phy_type = of_usb_get_phy_mode(np);
1130 switch (phy_type) {
1131 case USBPHY_INTERFACE_MODE_UTMI:
1132 err = utmi_phy_probe(tegra_phy, pdev);
1133 if (err)
1134 return err;
1135
1136 tegra_phy->pad_clk = devm_clk_get(&pdev->dev, "utmi-pads");
1137 err = PTR_ERR_OR_ZERO(tegra_phy->pad_clk);
1138 if (err) {
1139 dev_err(&pdev->dev,
1140 "Failed to get UTMIP pad clock: %d\n", err);
1141 return err;
1142 }
1143
1144 reset = devm_reset_control_get_optional_shared(&pdev->dev,
1145 "utmi-pads");
1146 err = PTR_ERR_OR_ZERO(reset);
1147 if (err) {
1148 dev_err(&pdev->dev,
1149 "Failed to get UTMI-pads reset: %d\n", err);
1150 return err;
1151 }
1152 tegra_phy->pad_rst = reset;
1153 break;
1154
1155 case USBPHY_INTERFACE_MODE_ULPI:
1156 tegra_phy->is_ulpi_phy = true;
1157
1158 tegra_phy->clk = devm_clk_get(&pdev->dev, "ulpi-link");
1159 err = PTR_ERR_OR_ZERO(tegra_phy->clk);
1160 if (err) {
1161 dev_err(&pdev->dev,
1162 "Failed to get ULPI clock: %d\n", err);
1163 return err;
1164 }
1165
1166 gpiod = devm_gpiod_get_from_of_node(&pdev->dev, np,
1167 "nvidia,phy-reset-gpio",
1168 0, GPIOD_OUT_HIGH,
1169 "ulpi_phy_reset_b");
1170 err = PTR_ERR_OR_ZERO(gpiod);
1171 if (err) {
1172 dev_err(&pdev->dev,
1173 "Request failed for reset GPIO: %d\n", err);
1174 return err;
1175 }
1176 tegra_phy->reset_gpio = gpiod;
1177
1178 phy = devm_otg_ulpi_create(&pdev->dev,
1179 &ulpi_viewport_access_ops, 0);
1180 if (!phy) {
1181 dev_err(&pdev->dev, "Failed to create ULPI OTG\n");
1182 return -ENOMEM;
1183 }
1184
1185 tegra_phy->ulpi = phy;
1186 tegra_phy->ulpi->io_priv = tegra_phy->regs + ULPI_VIEWPORT;
1187 break;
1188
1189 default:
1190 dev_err(&pdev->dev, "phy_type %u is invalid or unsupported\n",
1191 phy_type);
1192 return -EINVAL;
1193 }
1194
1195 tegra_phy->u_phy.dev = &pdev->dev;
1196 tegra_phy->u_phy.init = tegra_usb_phy_init;
1197 tegra_phy->u_phy.shutdown = tegra_usb_phy_shutdown;
1198 tegra_phy->u_phy.set_suspend = tegra_usb_phy_set_suspend;
1199
1200 platform_set_drvdata(pdev, tegra_phy);
1201
1202 return usb_add_phy_dev(&tegra_phy->u_phy);
1203}
1204
1205static int tegra_usb_phy_remove(struct platform_device *pdev)
1206{
1207 struct tegra_usb_phy *tegra_phy = platform_get_drvdata(pdev);
1208
1209 usb_remove_phy(&tegra_phy->u_phy);
1210
1211 return 0;
1212}
1213
1214static struct platform_driver tegra_usb_phy_driver = {
1215 .probe = tegra_usb_phy_probe,
1216 .remove = tegra_usb_phy_remove,
1217 .driver = {
1218 .name = "tegra-phy",
1219 .of_match_table = tegra_usb_phy_id_table,
1220 },
1221};
1222module_platform_driver(tegra_usb_phy_driver);
1223
1224MODULE_DESCRIPTION("Tegra USB PHY driver");
1225MODULE_LICENSE("GPL v2");
1/*
2 * Copyright (C) 2010 Google, Inc.
3 * Copyright (C) 2013 NVIDIA Corporation
4 *
5 * Author:
6 * Erik Gilling <konkers@google.com>
7 * Benoit Goby <benoit@android.com>
8 * Venu Byravarasu <vbyravarasu@nvidia.com>
9 *
10 * This software is licensed under the terms of the GNU General Public
11 * License version 2, as published by the Free Software Foundation, and
12 * may be copied, distributed, and modified under those terms.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 */
20
21#include <linux/resource.h>
22#include <linux/delay.h>
23#include <linux/slab.h>
24#include <linux/err.h>
25#include <linux/export.h>
26#include <linux/module.h>
27#include <linux/platform_device.h>
28#include <linux/io.h>
29#include <linux/gpio.h>
30#include <linux/of.h>
31#include <linux/of_device.h>
32#include <linux/of_gpio.h>
33#include <linux/usb/otg.h>
34#include <linux/usb/ulpi.h>
35#include <linux/usb/of.h>
36#include <linux/usb/ehci_def.h>
37#include <linux/usb/tegra_usb_phy.h>
38#include <linux/regulator/consumer.h>
39
40#define ULPI_VIEWPORT 0x170
41
42/* PORTSC PTS/PHCD bits, Tegra20 only */
43#define TEGRA_USB_PORTSC1 0x184
44#define TEGRA_USB_PORTSC1_PTS(x) (((x) & 0x3) << 30)
45#define TEGRA_USB_PORTSC1_PHCD (1 << 23)
46
47/* HOSTPC1 PTS/PHCD bits, Tegra30 and above */
48#define TEGRA_USB_HOSTPC1_DEVLC 0x1b4
49#define TEGRA_USB_HOSTPC1_DEVLC_PTS(x) (((x) & 0x7) << 29)
50#define TEGRA_USB_HOSTPC1_DEVLC_PHCD (1 << 22)
51
52/* Bits of PORTSC1, which will get cleared by writing 1 into them */
53#define TEGRA_PORTSC1_RWC_BITS (PORT_CSC | PORT_PEC | PORT_OCC)
54
55#define USB_SUSP_CTRL 0x400
56#define USB_WAKE_ON_CNNT_EN_DEV (1 << 3)
57#define USB_WAKE_ON_DISCON_EN_DEV (1 << 4)
58#define USB_SUSP_CLR (1 << 5)
59#define USB_PHY_CLK_VALID (1 << 7)
60#define UTMIP_RESET (1 << 11)
61#define UHSIC_RESET (1 << 11)
62#define UTMIP_PHY_ENABLE (1 << 12)
63#define ULPI_PHY_ENABLE (1 << 13)
64#define USB_SUSP_SET (1 << 14)
65#define USB_WAKEUP_DEBOUNCE_COUNT(x) (((x) & 0x7) << 16)
66
67#define USB1_LEGACY_CTRL 0x410
68#define USB1_NO_LEGACY_MODE (1 << 0)
69#define USB1_VBUS_SENSE_CTL_MASK (3 << 1)
70#define USB1_VBUS_SENSE_CTL_VBUS_WAKEUP (0 << 1)
71#define USB1_VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP \
72 (1 << 1)
73#define USB1_VBUS_SENSE_CTL_AB_SESS_VLD (2 << 1)
74#define USB1_VBUS_SENSE_CTL_A_SESS_VLD (3 << 1)
75
76#define ULPI_TIMING_CTRL_0 0x424
77#define ULPI_OUTPUT_PINMUX_BYP (1 << 10)
78#define ULPI_CLKOUT_PINMUX_BYP (1 << 11)
79
80#define ULPI_TIMING_CTRL_1 0x428
81#define ULPI_DATA_TRIMMER_LOAD (1 << 0)
82#define ULPI_DATA_TRIMMER_SEL(x) (((x) & 0x7) << 1)
83#define ULPI_STPDIRNXT_TRIMMER_LOAD (1 << 16)
84#define ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17)
85#define ULPI_DIR_TRIMMER_LOAD (1 << 24)
86#define ULPI_DIR_TRIMMER_SEL(x) (((x) & 0x7) << 25)
87
88#define UTMIP_PLL_CFG1 0x804
89#define UTMIP_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
90#define UTMIP_PLLU_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27)
91
92#define UTMIP_XCVR_CFG0 0x808
93#define UTMIP_XCVR_SETUP(x) (((x) & 0xf) << 0)
94#define UTMIP_XCVR_SETUP_MSB(x) ((((x) & 0x70) >> 4) << 22)
95#define UTMIP_XCVR_LSRSLEW(x) (((x) & 0x3) << 8)
96#define UTMIP_XCVR_LSFSLEW(x) (((x) & 0x3) << 10)
97#define UTMIP_FORCE_PD_POWERDOWN (1 << 14)
98#define UTMIP_FORCE_PD2_POWERDOWN (1 << 16)
99#define UTMIP_FORCE_PDZI_POWERDOWN (1 << 18)
100#define UTMIP_XCVR_LSBIAS_SEL (1 << 21)
101#define UTMIP_XCVR_HSSLEW(x) (((x) & 0x3) << 4)
102#define UTMIP_XCVR_HSSLEW_MSB(x) ((((x) & 0x1fc) >> 2) << 25)
103
104#define UTMIP_BIAS_CFG0 0x80c
105#define UTMIP_OTGPD (1 << 11)
106#define UTMIP_BIASPD (1 << 10)
107#define UTMIP_HSSQUELCH_LEVEL(x) (((x) & 0x3) << 0)
108#define UTMIP_HSDISCON_LEVEL(x) (((x) & 0x3) << 2)
109#define UTMIP_HSDISCON_LEVEL_MSB(x) ((((x) & 0x4) >> 2) << 24)
110
111#define UTMIP_HSRX_CFG0 0x810
112#define UTMIP_ELASTIC_LIMIT(x) (((x) & 0x1f) << 10)
113#define UTMIP_IDLE_WAIT(x) (((x) & 0x1f) << 15)
114
115#define UTMIP_HSRX_CFG1 0x814
116#define UTMIP_HS_SYNC_START_DLY(x) (((x) & 0x1f) << 1)
117
118#define UTMIP_TX_CFG0 0x820
119#define UTMIP_FS_PREABMLE_J (1 << 19)
120#define UTMIP_HS_DISCON_DISABLE (1 << 8)
121
122#define UTMIP_MISC_CFG0 0x824
123#define UTMIP_DPDM_OBSERVE (1 << 26)
124#define UTMIP_DPDM_OBSERVE_SEL(x) (((x) & 0xf) << 27)
125#define UTMIP_DPDM_OBSERVE_SEL_FS_J UTMIP_DPDM_OBSERVE_SEL(0xf)
126#define UTMIP_DPDM_OBSERVE_SEL_FS_K UTMIP_DPDM_OBSERVE_SEL(0xe)
127#define UTMIP_DPDM_OBSERVE_SEL_FS_SE1 UTMIP_DPDM_OBSERVE_SEL(0xd)
128#define UTMIP_DPDM_OBSERVE_SEL_FS_SE0 UTMIP_DPDM_OBSERVE_SEL(0xc)
129#define UTMIP_SUSPEND_EXIT_ON_EDGE (1 << 22)
130
131#define UTMIP_MISC_CFG1 0x828
132#define UTMIP_PLL_ACTIVE_DLY_COUNT(x) (((x) & 0x1f) << 18)
133#define UTMIP_PLLU_STABLE_COUNT(x) (((x) & 0xfff) << 6)
134
135#define UTMIP_DEBOUNCE_CFG0 0x82c
136#define UTMIP_BIAS_DEBOUNCE_A(x) (((x) & 0xffff) << 0)
137
138#define UTMIP_BAT_CHRG_CFG0 0x830
139#define UTMIP_PD_CHRG (1 << 0)
140
141#define UTMIP_SPARE_CFG0 0x834
142#define FUSE_SETUP_SEL (1 << 3)
143
144#define UTMIP_XCVR_CFG1 0x838
145#define UTMIP_FORCE_PDDISC_POWERDOWN (1 << 0)
146#define UTMIP_FORCE_PDCHRP_POWERDOWN (1 << 2)
147#define UTMIP_FORCE_PDDR_POWERDOWN (1 << 4)
148#define UTMIP_XCVR_TERM_RANGE_ADJ(x) (((x) & 0xf) << 18)
149
150#define UTMIP_BIAS_CFG1 0x83c
151#define UTMIP_BIAS_PDTRK_COUNT(x) (((x) & 0x1f) << 3)
152
153/* For Tegra30 and above only, the address is different in Tegra20 */
154#define USB_USBMODE 0x1f8
155#define USB_USBMODE_MASK (3 << 0)
156#define USB_USBMODE_HOST (3 << 0)
157#define USB_USBMODE_DEVICE (2 << 0)
158
159static DEFINE_SPINLOCK(utmip_pad_lock);
160static int utmip_pad_count;
161
162struct tegra_xtal_freq {
163 int freq;
164 u8 enable_delay;
165 u8 stable_count;
166 u8 active_delay;
167 u8 xtal_freq_count;
168 u16 debounce;
169};
170
171static const struct tegra_xtal_freq tegra_freq_table[] = {
172 {
173 .freq = 12000000,
174 .enable_delay = 0x02,
175 .stable_count = 0x2F,
176 .active_delay = 0x04,
177 .xtal_freq_count = 0x76,
178 .debounce = 0x7530,
179 },
180 {
181 .freq = 13000000,
182 .enable_delay = 0x02,
183 .stable_count = 0x33,
184 .active_delay = 0x05,
185 .xtal_freq_count = 0x7F,
186 .debounce = 0x7EF4,
187 },
188 {
189 .freq = 19200000,
190 .enable_delay = 0x03,
191 .stable_count = 0x4B,
192 .active_delay = 0x06,
193 .xtal_freq_count = 0xBB,
194 .debounce = 0xBB80,
195 },
196 {
197 .freq = 26000000,
198 .enable_delay = 0x04,
199 .stable_count = 0x66,
200 .active_delay = 0x09,
201 .xtal_freq_count = 0xFE,
202 .debounce = 0xFDE8,
203 },
204};
205
206static void set_pts(struct tegra_usb_phy *phy, u8 pts_val)
207{
208 void __iomem *base = phy->regs;
209 unsigned long val;
210
211 if (phy->soc_config->has_hostpc) {
212 val = readl(base + TEGRA_USB_HOSTPC1_DEVLC);
213 val &= ~TEGRA_USB_HOSTPC1_DEVLC_PTS(~0);
214 val |= TEGRA_USB_HOSTPC1_DEVLC_PTS(pts_val);
215 writel(val, base + TEGRA_USB_HOSTPC1_DEVLC);
216 } else {
217 val = readl(base + TEGRA_USB_PORTSC1) & ~TEGRA_PORTSC1_RWC_BITS;
218 val &= ~TEGRA_USB_PORTSC1_PTS(~0);
219 val |= TEGRA_USB_PORTSC1_PTS(pts_val);
220 writel(val, base + TEGRA_USB_PORTSC1);
221 }
222}
223
224static void set_phcd(struct tegra_usb_phy *phy, bool enable)
225{
226 void __iomem *base = phy->regs;
227 unsigned long val;
228
229 if (phy->soc_config->has_hostpc) {
230 val = readl(base + TEGRA_USB_HOSTPC1_DEVLC);
231 if (enable)
232 val |= TEGRA_USB_HOSTPC1_DEVLC_PHCD;
233 else
234 val &= ~TEGRA_USB_HOSTPC1_DEVLC_PHCD;
235 writel(val, base + TEGRA_USB_HOSTPC1_DEVLC);
236 } else {
237 val = readl(base + TEGRA_USB_PORTSC1) & ~PORT_RWC_BITS;
238 if (enable)
239 val |= TEGRA_USB_PORTSC1_PHCD;
240 else
241 val &= ~TEGRA_USB_PORTSC1_PHCD;
242 writel(val, base + TEGRA_USB_PORTSC1);
243 }
244}
245
246static int utmip_pad_open(struct tegra_usb_phy *phy)
247{
248 phy->pad_clk = devm_clk_get(phy->u_phy.dev, "utmi-pads");
249 if (IS_ERR(phy->pad_clk)) {
250 pr_err("%s: can't get utmip pad clock\n", __func__);
251 return PTR_ERR(phy->pad_clk);
252 }
253
254 return 0;
255}
256
257static void utmip_pad_power_on(struct tegra_usb_phy *phy)
258{
259 unsigned long val, flags;
260 void __iomem *base = phy->pad_regs;
261 struct tegra_utmip_config *config = phy->config;
262
263 clk_prepare_enable(phy->pad_clk);
264
265 spin_lock_irqsave(&utmip_pad_lock, flags);
266
267 if (utmip_pad_count++ == 0) {
268 val = readl(base + UTMIP_BIAS_CFG0);
269 val &= ~(UTMIP_OTGPD | UTMIP_BIASPD);
270
271 if (phy->soc_config->requires_extra_tuning_parameters) {
272 val &= ~(UTMIP_HSSQUELCH_LEVEL(~0) |
273 UTMIP_HSDISCON_LEVEL(~0) |
274 UTMIP_HSDISCON_LEVEL_MSB(~0));
275
276 val |= UTMIP_HSSQUELCH_LEVEL(config->hssquelch_level);
277 val |= UTMIP_HSDISCON_LEVEL(config->hsdiscon_level);
278 val |= UTMIP_HSDISCON_LEVEL_MSB(config->hsdiscon_level);
279 }
280 writel(val, base + UTMIP_BIAS_CFG0);
281 }
282
283 spin_unlock_irqrestore(&utmip_pad_lock, flags);
284
285 clk_disable_unprepare(phy->pad_clk);
286}
287
288static int utmip_pad_power_off(struct tegra_usb_phy *phy)
289{
290 unsigned long val, flags;
291 void __iomem *base = phy->pad_regs;
292
293 if (!utmip_pad_count) {
294 pr_err("%s: utmip pad already powered off\n", __func__);
295 return -EINVAL;
296 }
297
298 clk_prepare_enable(phy->pad_clk);
299
300 spin_lock_irqsave(&utmip_pad_lock, flags);
301
302 if (--utmip_pad_count == 0) {
303 val = readl(base + UTMIP_BIAS_CFG0);
304 val |= UTMIP_OTGPD | UTMIP_BIASPD;
305 writel(val, base + UTMIP_BIAS_CFG0);
306 }
307
308 spin_unlock_irqrestore(&utmip_pad_lock, flags);
309
310 clk_disable_unprepare(phy->pad_clk);
311
312 return 0;
313}
314
315static int utmi_wait_register(void __iomem *reg, u32 mask, u32 result)
316{
317 unsigned long timeout = 2000;
318 do {
319 if ((readl(reg) & mask) == result)
320 return 0;
321 udelay(1);
322 timeout--;
323 } while (timeout);
324 return -1;
325}
326
327static void utmi_phy_clk_disable(struct tegra_usb_phy *phy)
328{
329 unsigned long val;
330 void __iomem *base = phy->regs;
331
332 if (phy->is_legacy_phy) {
333 val = readl(base + USB_SUSP_CTRL);
334 val |= USB_SUSP_SET;
335 writel(val, base + USB_SUSP_CTRL);
336
337 udelay(10);
338
339 val = readl(base + USB_SUSP_CTRL);
340 val &= ~USB_SUSP_SET;
341 writel(val, base + USB_SUSP_CTRL);
342 } else
343 set_phcd(phy, true);
344
345 if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, 0) < 0)
346 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
347}
348
349static void utmi_phy_clk_enable(struct tegra_usb_phy *phy)
350{
351 unsigned long val;
352 void __iomem *base = phy->regs;
353
354 if (phy->is_legacy_phy) {
355 val = readl(base + USB_SUSP_CTRL);
356 val |= USB_SUSP_CLR;
357 writel(val, base + USB_SUSP_CTRL);
358
359 udelay(10);
360
361 val = readl(base + USB_SUSP_CTRL);
362 val &= ~USB_SUSP_CLR;
363 writel(val, base + USB_SUSP_CTRL);
364 } else
365 set_phcd(phy, false);
366
367 if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
368 USB_PHY_CLK_VALID))
369 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
370}
371
372static int utmi_phy_power_on(struct tegra_usb_phy *phy)
373{
374 unsigned long val;
375 void __iomem *base = phy->regs;
376 struct tegra_utmip_config *config = phy->config;
377
378 val = readl(base + USB_SUSP_CTRL);
379 val |= UTMIP_RESET;
380 writel(val, base + USB_SUSP_CTRL);
381
382 if (phy->is_legacy_phy) {
383 val = readl(base + USB1_LEGACY_CTRL);
384 val |= USB1_NO_LEGACY_MODE;
385 writel(val, base + USB1_LEGACY_CTRL);
386 }
387
388 val = readl(base + UTMIP_TX_CFG0);
389 val |= UTMIP_FS_PREABMLE_J;
390 writel(val, base + UTMIP_TX_CFG0);
391
392 val = readl(base + UTMIP_HSRX_CFG0);
393 val &= ~(UTMIP_IDLE_WAIT(~0) | UTMIP_ELASTIC_LIMIT(~0));
394 val |= UTMIP_IDLE_WAIT(config->idle_wait_delay);
395 val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit);
396 writel(val, base + UTMIP_HSRX_CFG0);
397
398 val = readl(base + UTMIP_HSRX_CFG1);
399 val &= ~UTMIP_HS_SYNC_START_DLY(~0);
400 val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay);
401 writel(val, base + UTMIP_HSRX_CFG1);
402
403 val = readl(base + UTMIP_DEBOUNCE_CFG0);
404 val &= ~UTMIP_BIAS_DEBOUNCE_A(~0);
405 val |= UTMIP_BIAS_DEBOUNCE_A(phy->freq->debounce);
406 writel(val, base + UTMIP_DEBOUNCE_CFG0);
407
408 val = readl(base + UTMIP_MISC_CFG0);
409 val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE;
410 writel(val, base + UTMIP_MISC_CFG0);
411
412 if (!phy->soc_config->utmi_pll_config_in_car_module) {
413 val = readl(base + UTMIP_MISC_CFG1);
414 val &= ~(UTMIP_PLL_ACTIVE_DLY_COUNT(~0) |
415 UTMIP_PLLU_STABLE_COUNT(~0));
416 val |= UTMIP_PLL_ACTIVE_DLY_COUNT(phy->freq->active_delay) |
417 UTMIP_PLLU_STABLE_COUNT(phy->freq->stable_count);
418 writel(val, base + UTMIP_MISC_CFG1);
419
420 val = readl(base + UTMIP_PLL_CFG1);
421 val &= ~(UTMIP_XTAL_FREQ_COUNT(~0) |
422 UTMIP_PLLU_ENABLE_DLY_COUNT(~0));
423 val |= UTMIP_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count) |
424 UTMIP_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay);
425 writel(val, base + UTMIP_PLL_CFG1);
426 }
427
428 if (phy->mode == USB_DR_MODE_PERIPHERAL) {
429 val = readl(base + USB_SUSP_CTRL);
430 val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV);
431 writel(val, base + USB_SUSP_CTRL);
432
433 val = readl(base + UTMIP_BAT_CHRG_CFG0);
434 val &= ~UTMIP_PD_CHRG;
435 writel(val, base + UTMIP_BAT_CHRG_CFG0);
436 } else {
437 val = readl(base + UTMIP_BAT_CHRG_CFG0);
438 val |= UTMIP_PD_CHRG;
439 writel(val, base + UTMIP_BAT_CHRG_CFG0);
440 }
441
442 utmip_pad_power_on(phy);
443
444 val = readl(base + UTMIP_XCVR_CFG0);
445 val &= ~(UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
446 UTMIP_FORCE_PDZI_POWERDOWN | UTMIP_XCVR_LSBIAS_SEL |
447 UTMIP_XCVR_SETUP(~0) | UTMIP_XCVR_SETUP_MSB(~0) |
448 UTMIP_XCVR_LSFSLEW(~0) | UTMIP_XCVR_LSRSLEW(~0));
449
450 if (!config->xcvr_setup_use_fuses) {
451 val |= UTMIP_XCVR_SETUP(config->xcvr_setup);
452 val |= UTMIP_XCVR_SETUP_MSB(config->xcvr_setup);
453 }
454 val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew);
455 val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew);
456
457 if (phy->soc_config->requires_extra_tuning_parameters) {
458 val &= ~(UTMIP_XCVR_HSSLEW(~0) | UTMIP_XCVR_HSSLEW_MSB(~0));
459 val |= UTMIP_XCVR_HSSLEW(config->xcvr_hsslew);
460 val |= UTMIP_XCVR_HSSLEW_MSB(config->xcvr_hsslew);
461 }
462 writel(val, base + UTMIP_XCVR_CFG0);
463
464 val = readl(base + UTMIP_XCVR_CFG1);
465 val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
466 UTMIP_FORCE_PDDR_POWERDOWN | UTMIP_XCVR_TERM_RANGE_ADJ(~0));
467 val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj);
468 writel(val, base + UTMIP_XCVR_CFG1);
469
470 val = readl(base + UTMIP_BIAS_CFG1);
471 val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
472 val |= UTMIP_BIAS_PDTRK_COUNT(0x5);
473 writel(val, base + UTMIP_BIAS_CFG1);
474
475 val = readl(base + UTMIP_SPARE_CFG0);
476 if (config->xcvr_setup_use_fuses)
477 val |= FUSE_SETUP_SEL;
478 else
479 val &= ~FUSE_SETUP_SEL;
480 writel(val, base + UTMIP_SPARE_CFG0);
481
482 if (!phy->is_legacy_phy) {
483 val = readl(base + USB_SUSP_CTRL);
484 val |= UTMIP_PHY_ENABLE;
485 writel(val, base + USB_SUSP_CTRL);
486 }
487
488 val = readl(base + USB_SUSP_CTRL);
489 val &= ~UTMIP_RESET;
490 writel(val, base + USB_SUSP_CTRL);
491
492 if (phy->is_legacy_phy) {
493 val = readl(base + USB1_LEGACY_CTRL);
494 val &= ~USB1_VBUS_SENSE_CTL_MASK;
495 val |= USB1_VBUS_SENSE_CTL_A_SESS_VLD;
496 writel(val, base + USB1_LEGACY_CTRL);
497
498 val = readl(base + USB_SUSP_CTRL);
499 val &= ~USB_SUSP_SET;
500 writel(val, base + USB_SUSP_CTRL);
501 }
502
503 utmi_phy_clk_enable(phy);
504
505 if (phy->soc_config->requires_usbmode_setup) {
506 val = readl(base + USB_USBMODE);
507 val &= ~USB_USBMODE_MASK;
508 if (phy->mode == USB_DR_MODE_HOST)
509 val |= USB_USBMODE_HOST;
510 else
511 val |= USB_USBMODE_DEVICE;
512 writel(val, base + USB_USBMODE);
513 }
514
515 if (!phy->is_legacy_phy)
516 set_pts(phy, 0);
517
518 return 0;
519}
520
521static int utmi_phy_power_off(struct tegra_usb_phy *phy)
522{
523 unsigned long val;
524 void __iomem *base = phy->regs;
525
526 utmi_phy_clk_disable(phy);
527
528 if (phy->mode == USB_DR_MODE_PERIPHERAL) {
529 val = readl(base + USB_SUSP_CTRL);
530 val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0);
531 val |= USB_WAKE_ON_CNNT_EN_DEV | USB_WAKEUP_DEBOUNCE_COUNT(5);
532 writel(val, base + USB_SUSP_CTRL);
533 }
534
535 val = readl(base + USB_SUSP_CTRL);
536 val |= UTMIP_RESET;
537 writel(val, base + USB_SUSP_CTRL);
538
539 val = readl(base + UTMIP_BAT_CHRG_CFG0);
540 val |= UTMIP_PD_CHRG;
541 writel(val, base + UTMIP_BAT_CHRG_CFG0);
542
543 val = readl(base + UTMIP_XCVR_CFG0);
544 val |= UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
545 UTMIP_FORCE_PDZI_POWERDOWN;
546 writel(val, base + UTMIP_XCVR_CFG0);
547
548 val = readl(base + UTMIP_XCVR_CFG1);
549 val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
550 UTMIP_FORCE_PDDR_POWERDOWN;
551 writel(val, base + UTMIP_XCVR_CFG1);
552
553 return utmip_pad_power_off(phy);
554}
555
556static void utmi_phy_preresume(struct tegra_usb_phy *phy)
557{
558 unsigned long val;
559 void __iomem *base = phy->regs;
560
561 val = readl(base + UTMIP_TX_CFG0);
562 val |= UTMIP_HS_DISCON_DISABLE;
563 writel(val, base + UTMIP_TX_CFG0);
564}
565
566static void utmi_phy_postresume(struct tegra_usb_phy *phy)
567{
568 unsigned long val;
569 void __iomem *base = phy->regs;
570
571 val = readl(base + UTMIP_TX_CFG0);
572 val &= ~UTMIP_HS_DISCON_DISABLE;
573 writel(val, base + UTMIP_TX_CFG0);
574}
575
576static void utmi_phy_restore_start(struct tegra_usb_phy *phy,
577 enum tegra_usb_phy_port_speed port_speed)
578{
579 unsigned long val;
580 void __iomem *base = phy->regs;
581
582 val = readl(base + UTMIP_MISC_CFG0);
583 val &= ~UTMIP_DPDM_OBSERVE_SEL(~0);
584 if (port_speed == TEGRA_USB_PHY_PORT_SPEED_LOW)
585 val |= UTMIP_DPDM_OBSERVE_SEL_FS_K;
586 else
587 val |= UTMIP_DPDM_OBSERVE_SEL_FS_J;
588 writel(val, base + UTMIP_MISC_CFG0);
589 udelay(1);
590
591 val = readl(base + UTMIP_MISC_CFG0);
592 val |= UTMIP_DPDM_OBSERVE;
593 writel(val, base + UTMIP_MISC_CFG0);
594 udelay(10);
595}
596
597static void utmi_phy_restore_end(struct tegra_usb_phy *phy)
598{
599 unsigned long val;
600 void __iomem *base = phy->regs;
601
602 val = readl(base + UTMIP_MISC_CFG0);
603 val &= ~UTMIP_DPDM_OBSERVE;
604 writel(val, base + UTMIP_MISC_CFG0);
605 udelay(10);
606}
607
608static int ulpi_phy_power_on(struct tegra_usb_phy *phy)
609{
610 int ret;
611 unsigned long val;
612 void __iomem *base = phy->regs;
613
614 ret = gpio_direction_output(phy->reset_gpio, 0);
615 if (ret < 0) {
616 dev_err(phy->u_phy.dev, "gpio %d not set to 0\n",
617 phy->reset_gpio);
618 return ret;
619 }
620 msleep(5);
621 ret = gpio_direction_output(phy->reset_gpio, 1);
622 if (ret < 0) {
623 dev_err(phy->u_phy.dev, "gpio %d not set to 1\n",
624 phy->reset_gpio);
625 return ret;
626 }
627
628 clk_prepare_enable(phy->clk);
629 msleep(1);
630
631 val = readl(base + USB_SUSP_CTRL);
632 val |= UHSIC_RESET;
633 writel(val, base + USB_SUSP_CTRL);
634
635 val = readl(base + ULPI_TIMING_CTRL_0);
636 val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP;
637 writel(val, base + ULPI_TIMING_CTRL_0);
638
639 val = readl(base + USB_SUSP_CTRL);
640 val |= ULPI_PHY_ENABLE;
641 writel(val, base + USB_SUSP_CTRL);
642
643 val = 0;
644 writel(val, base + ULPI_TIMING_CTRL_1);
645
646 val |= ULPI_DATA_TRIMMER_SEL(4);
647 val |= ULPI_STPDIRNXT_TRIMMER_SEL(4);
648 val |= ULPI_DIR_TRIMMER_SEL(4);
649 writel(val, base + ULPI_TIMING_CTRL_1);
650 udelay(10);
651
652 val |= ULPI_DATA_TRIMMER_LOAD;
653 val |= ULPI_STPDIRNXT_TRIMMER_LOAD;
654 val |= ULPI_DIR_TRIMMER_LOAD;
655 writel(val, base + ULPI_TIMING_CTRL_1);
656
657 /* Fix VbusInvalid due to floating VBUS */
658 ret = usb_phy_io_write(phy->ulpi, 0x40, 0x08);
659 if (ret) {
660 pr_err("%s: ulpi write failed\n", __func__);
661 return ret;
662 }
663
664 ret = usb_phy_io_write(phy->ulpi, 0x80, 0x0B);
665 if (ret) {
666 pr_err("%s: ulpi write failed\n", __func__);
667 return ret;
668 }
669
670 val = readl(base + USB_SUSP_CTRL);
671 val |= USB_SUSP_CLR;
672 writel(val, base + USB_SUSP_CTRL);
673 udelay(100);
674
675 val = readl(base + USB_SUSP_CTRL);
676 val &= ~USB_SUSP_CLR;
677 writel(val, base + USB_SUSP_CTRL);
678
679 return 0;
680}
681
682static int ulpi_phy_power_off(struct tegra_usb_phy *phy)
683{
684 clk_disable(phy->clk);
685 return gpio_direction_output(phy->reset_gpio, 0);
686}
687
688static void tegra_usb_phy_close(struct tegra_usb_phy *phy)
689{
690 if (!IS_ERR(phy->vbus))
691 regulator_disable(phy->vbus);
692
693 clk_disable_unprepare(phy->pll_u);
694}
695
696static int tegra_usb_phy_power_on(struct tegra_usb_phy *phy)
697{
698 if (phy->is_ulpi_phy)
699 return ulpi_phy_power_on(phy);
700 else
701 return utmi_phy_power_on(phy);
702}
703
704static int tegra_usb_phy_power_off(struct tegra_usb_phy *phy)
705{
706 if (phy->is_ulpi_phy)
707 return ulpi_phy_power_off(phy);
708 else
709 return utmi_phy_power_off(phy);
710}
711
712static int tegra_usb_phy_suspend(struct usb_phy *x, int suspend)
713{
714 struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
715 if (suspend)
716 return tegra_usb_phy_power_off(phy);
717 else
718 return tegra_usb_phy_power_on(phy);
719}
720
721static int ulpi_open(struct tegra_usb_phy *phy)
722{
723 int err;
724
725 phy->clk = devm_clk_get(phy->u_phy.dev, "ulpi-link");
726 if (IS_ERR(phy->clk)) {
727 pr_err("%s: can't get ulpi clock\n", __func__);
728 return PTR_ERR(phy->clk);
729 }
730
731 err = devm_gpio_request(phy->u_phy.dev, phy->reset_gpio,
732 "ulpi_phy_reset_b");
733 if (err < 0) {
734 dev_err(phy->u_phy.dev, "request failed for gpio: %d\n",
735 phy->reset_gpio);
736 return err;
737 }
738
739 err = gpio_direction_output(phy->reset_gpio, 0);
740 if (err < 0) {
741 dev_err(phy->u_phy.dev, "gpio %d direction not set to output\n",
742 phy->reset_gpio);
743 return err;
744 }
745
746 phy->ulpi = otg_ulpi_create(&ulpi_viewport_access_ops, 0);
747 if (!phy->ulpi) {
748 dev_err(phy->u_phy.dev, "otg_ulpi_create returned NULL\n");
749 err = -ENOMEM;
750 return err;
751 }
752
753 phy->ulpi->io_priv = phy->regs + ULPI_VIEWPORT;
754 return 0;
755}
756
757static int tegra_usb_phy_init(struct tegra_usb_phy *phy)
758{
759 unsigned long parent_rate;
760 int i;
761 int err;
762
763 phy->pll_u = devm_clk_get(phy->u_phy.dev, "pll_u");
764 if (IS_ERR(phy->pll_u)) {
765 pr_err("Can't get pll_u clock\n");
766 return PTR_ERR(phy->pll_u);
767 }
768
769 err = clk_prepare_enable(phy->pll_u);
770 if (err)
771 return err;
772
773 parent_rate = clk_get_rate(clk_get_parent(phy->pll_u));
774 for (i = 0; i < ARRAY_SIZE(tegra_freq_table); i++) {
775 if (tegra_freq_table[i].freq == parent_rate) {
776 phy->freq = &tegra_freq_table[i];
777 break;
778 }
779 }
780 if (!phy->freq) {
781 pr_err("invalid pll_u parent rate %ld\n", parent_rate);
782 err = -EINVAL;
783 goto fail;
784 }
785
786 if (!IS_ERR(phy->vbus)) {
787 err = regulator_enable(phy->vbus);
788 if (err) {
789 dev_err(phy->u_phy.dev,
790 "failed to enable usb vbus regulator: %d\n",
791 err);
792 goto fail;
793 }
794 }
795
796 if (phy->is_ulpi_phy)
797 err = ulpi_open(phy);
798 else
799 err = utmip_pad_open(phy);
800 if (err < 0)
801 goto fail;
802
803 return 0;
804
805fail:
806 clk_disable_unprepare(phy->pll_u);
807 return err;
808}
809
810void tegra_usb_phy_preresume(struct usb_phy *x)
811{
812 struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
813
814 if (!phy->is_ulpi_phy)
815 utmi_phy_preresume(phy);
816}
817EXPORT_SYMBOL_GPL(tegra_usb_phy_preresume);
818
819void tegra_usb_phy_postresume(struct usb_phy *x)
820{
821 struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
822
823 if (!phy->is_ulpi_phy)
824 utmi_phy_postresume(phy);
825}
826EXPORT_SYMBOL_GPL(tegra_usb_phy_postresume);
827
828void tegra_ehci_phy_restore_start(struct usb_phy *x,
829 enum tegra_usb_phy_port_speed port_speed)
830{
831 struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
832
833 if (!phy->is_ulpi_phy)
834 utmi_phy_restore_start(phy, port_speed);
835}
836EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_start);
837
838void tegra_ehci_phy_restore_end(struct usb_phy *x)
839{
840 struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
841
842 if (!phy->is_ulpi_phy)
843 utmi_phy_restore_end(phy);
844}
845EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_end);
846
847static int read_utmi_param(struct platform_device *pdev, const char *param,
848 u8 *dest)
849{
850 u32 value;
851 int err = of_property_read_u32(pdev->dev.of_node, param, &value);
852 *dest = (u8)value;
853 if (err < 0)
854 dev_err(&pdev->dev, "Failed to read USB UTMI parameter %s: %d\n",
855 param, err);
856 return err;
857}
858
859static int utmi_phy_probe(struct tegra_usb_phy *tegra_phy,
860 struct platform_device *pdev)
861{
862 struct resource *res;
863 int err;
864 struct tegra_utmip_config *config;
865
866 tegra_phy->is_ulpi_phy = false;
867
868 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
869 if (!res) {
870 dev_err(&pdev->dev, "Failed to get UTMI Pad regs\n");
871 return -ENXIO;
872 }
873
874 tegra_phy->pad_regs = devm_ioremap(&pdev->dev, res->start,
875 resource_size(res));
876 if (!tegra_phy->pad_regs) {
877 dev_err(&pdev->dev, "Failed to remap UTMI Pad regs\n");
878 return -ENOMEM;
879 }
880
881 tegra_phy->config = devm_kzalloc(&pdev->dev, sizeof(*config),
882 GFP_KERNEL);
883 if (!tegra_phy->config)
884 return -ENOMEM;
885
886 config = tegra_phy->config;
887
888 err = read_utmi_param(pdev, "nvidia,hssync-start-delay",
889 &config->hssync_start_delay);
890 if (err < 0)
891 return err;
892
893 err = read_utmi_param(pdev, "nvidia,elastic-limit",
894 &config->elastic_limit);
895 if (err < 0)
896 return err;
897
898 err = read_utmi_param(pdev, "nvidia,idle-wait-delay",
899 &config->idle_wait_delay);
900 if (err < 0)
901 return err;
902
903 err = read_utmi_param(pdev, "nvidia,term-range-adj",
904 &config->term_range_adj);
905 if (err < 0)
906 return err;
907
908 err = read_utmi_param(pdev, "nvidia,xcvr-lsfslew",
909 &config->xcvr_lsfslew);
910 if (err < 0)
911 return err;
912
913 err = read_utmi_param(pdev, "nvidia,xcvr-lsrslew",
914 &config->xcvr_lsrslew);
915 if (err < 0)
916 return err;
917
918 if (tegra_phy->soc_config->requires_extra_tuning_parameters) {
919 err = read_utmi_param(pdev, "nvidia,xcvr-hsslew",
920 &config->xcvr_hsslew);
921 if (err < 0)
922 return err;
923
924 err = read_utmi_param(pdev, "nvidia,hssquelch-level",
925 &config->hssquelch_level);
926 if (err < 0)
927 return err;
928
929 err = read_utmi_param(pdev, "nvidia,hsdiscon-level",
930 &config->hsdiscon_level);
931 if (err < 0)
932 return err;
933 }
934
935 config->xcvr_setup_use_fuses = of_property_read_bool(
936 pdev->dev.of_node, "nvidia,xcvr-setup-use-fuses");
937
938 if (!config->xcvr_setup_use_fuses) {
939 err = read_utmi_param(pdev, "nvidia,xcvr-setup",
940 &config->xcvr_setup);
941 if (err < 0)
942 return err;
943 }
944
945 return 0;
946}
947
948static const struct tegra_phy_soc_config tegra20_soc_config = {
949 .utmi_pll_config_in_car_module = false,
950 .has_hostpc = false,
951 .requires_usbmode_setup = false,
952 .requires_extra_tuning_parameters = false,
953};
954
955static const struct tegra_phy_soc_config tegra30_soc_config = {
956 .utmi_pll_config_in_car_module = true,
957 .has_hostpc = true,
958 .requires_usbmode_setup = true,
959 .requires_extra_tuning_parameters = true,
960};
961
962static const struct of_device_id tegra_usb_phy_id_table[] = {
963 { .compatible = "nvidia,tegra30-usb-phy", .data = &tegra30_soc_config },
964 { .compatible = "nvidia,tegra20-usb-phy", .data = &tegra20_soc_config },
965 { },
966};
967MODULE_DEVICE_TABLE(of, tegra_usb_phy_id_table);
968
969static int tegra_usb_phy_probe(struct platform_device *pdev)
970{
971 const struct of_device_id *match;
972 struct resource *res;
973 struct tegra_usb_phy *tegra_phy = NULL;
974 struct device_node *np = pdev->dev.of_node;
975 enum usb_phy_interface phy_type;
976 int err;
977
978 tegra_phy = devm_kzalloc(&pdev->dev, sizeof(*tegra_phy), GFP_KERNEL);
979 if (!tegra_phy)
980 return -ENOMEM;
981
982 match = of_match_device(tegra_usb_phy_id_table, &pdev->dev);
983 if (!match) {
984 dev_err(&pdev->dev, "Error: No device match found\n");
985 return -ENODEV;
986 }
987 tegra_phy->soc_config = match->data;
988
989 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
990 if (!res) {
991 dev_err(&pdev->dev, "Failed to get I/O memory\n");
992 return -ENXIO;
993 }
994
995 tegra_phy->regs = devm_ioremap(&pdev->dev, res->start,
996 resource_size(res));
997 if (!tegra_phy->regs) {
998 dev_err(&pdev->dev, "Failed to remap I/O memory\n");
999 return -ENOMEM;
1000 }
1001
1002 tegra_phy->is_legacy_phy =
1003 of_property_read_bool(np, "nvidia,has-legacy-mode");
1004
1005 phy_type = of_usb_get_phy_mode(np);
1006 switch (phy_type) {
1007 case USBPHY_INTERFACE_MODE_UTMI:
1008 err = utmi_phy_probe(tegra_phy, pdev);
1009 if (err < 0)
1010 return err;
1011 break;
1012
1013 case USBPHY_INTERFACE_MODE_ULPI:
1014 tegra_phy->is_ulpi_phy = true;
1015
1016 tegra_phy->reset_gpio =
1017 of_get_named_gpio(np, "nvidia,phy-reset-gpio", 0);
1018 if (!gpio_is_valid(tegra_phy->reset_gpio)) {
1019 dev_err(&pdev->dev, "invalid gpio: %d\n",
1020 tegra_phy->reset_gpio);
1021 return tegra_phy->reset_gpio;
1022 }
1023 tegra_phy->config = NULL;
1024 break;
1025
1026 default:
1027 dev_err(&pdev->dev, "phy_type is invalid or unsupported\n");
1028 return -EINVAL;
1029 }
1030
1031 if (of_find_property(np, "dr_mode", NULL))
1032 tegra_phy->mode = usb_get_dr_mode(&pdev->dev);
1033 else
1034 tegra_phy->mode = USB_DR_MODE_HOST;
1035
1036 if (tegra_phy->mode == USB_DR_MODE_UNKNOWN) {
1037 dev_err(&pdev->dev, "dr_mode is invalid\n");
1038 return -EINVAL;
1039 }
1040
1041 /* On some boards, the VBUS regulator doesn't need to be controlled */
1042 if (of_find_property(np, "vbus-supply", NULL)) {
1043 tegra_phy->vbus = devm_regulator_get(&pdev->dev, "vbus");
1044 if (IS_ERR(tegra_phy->vbus))
1045 return PTR_ERR(tegra_phy->vbus);
1046 } else {
1047 dev_notice(&pdev->dev, "no vbus regulator");
1048 tegra_phy->vbus = ERR_PTR(-ENODEV);
1049 }
1050
1051 tegra_phy->u_phy.dev = &pdev->dev;
1052 err = tegra_usb_phy_init(tegra_phy);
1053 if (err < 0)
1054 return err;
1055
1056 tegra_phy->u_phy.set_suspend = tegra_usb_phy_suspend;
1057
1058 platform_set_drvdata(pdev, tegra_phy);
1059
1060 err = usb_add_phy_dev(&tegra_phy->u_phy);
1061 if (err < 0) {
1062 tegra_usb_phy_close(tegra_phy);
1063 return err;
1064 }
1065
1066 return 0;
1067}
1068
1069static int tegra_usb_phy_remove(struct platform_device *pdev)
1070{
1071 struct tegra_usb_phy *tegra_phy = platform_get_drvdata(pdev);
1072
1073 usb_remove_phy(&tegra_phy->u_phy);
1074 tegra_usb_phy_close(tegra_phy);
1075
1076 return 0;
1077}
1078
1079static struct platform_driver tegra_usb_phy_driver = {
1080 .probe = tegra_usb_phy_probe,
1081 .remove = tegra_usb_phy_remove,
1082 .driver = {
1083 .name = "tegra-phy",
1084 .of_match_table = tegra_usb_phy_id_table,
1085 },
1086};
1087module_platform_driver(tegra_usb_phy_driver);
1088
1089MODULE_DESCRIPTION("Tegra USB PHY driver");
1090MODULE_LICENSE("GPL v2");