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1// SPDX-License-Identifier: GPL-2.0-only
2/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
3 */
4#include <linux/of.h>
5#include <linux/module.h>
6#include <linux/init.h>
7#include <linux/rtc.h>
8#include <linux/platform_device.h>
9#include <linux/pm.h>
10#include <linux/regmap.h>
11#include <linux/slab.h>
12#include <linux/spinlock.h>
13
14/* RTC Register offsets from RTC CTRL REG */
15#define PM8XXX_ALARM_CTRL_OFFSET 0x01
16#define PM8XXX_RTC_WRITE_OFFSET 0x02
17#define PM8XXX_RTC_READ_OFFSET 0x06
18#define PM8XXX_ALARM_RW_OFFSET 0x0A
19
20/* RTC_CTRL register bit fields */
21#define PM8xxx_RTC_ENABLE BIT(7)
22#define PM8xxx_RTC_ALARM_CLEAR BIT(0)
23
24#define NUM_8_BIT_RTC_REGS 0x4
25
26/**
27 * struct pm8xxx_rtc_regs - describe RTC registers per PMIC versions
28 * @ctrl: base address of control register
29 * @write: base address of write register
30 * @read: base address of read register
31 * @alarm_ctrl: base address of alarm control register
32 * @alarm_ctrl2: base address of alarm control2 register
33 * @alarm_rw: base address of alarm read-write register
34 * @alarm_en: alarm enable mask
35 */
36struct pm8xxx_rtc_regs {
37 unsigned int ctrl;
38 unsigned int write;
39 unsigned int read;
40 unsigned int alarm_ctrl;
41 unsigned int alarm_ctrl2;
42 unsigned int alarm_rw;
43 unsigned int alarm_en;
44};
45
46/**
47 * struct pm8xxx_rtc - rtc driver internal structure
48 * @rtc: rtc device for this driver.
49 * @regmap: regmap used to access RTC registers
50 * @allow_set_time: indicates whether writing to the RTC is allowed
51 * @rtc_alarm_irq: rtc alarm irq number.
52 * @regs: rtc registers description.
53 * @rtc_dev: device structure.
54 * @ctrl_reg_lock: spinlock protecting access to ctrl_reg.
55 */
56struct pm8xxx_rtc {
57 struct rtc_device *rtc;
58 struct regmap *regmap;
59 bool allow_set_time;
60 int rtc_alarm_irq;
61 const struct pm8xxx_rtc_regs *regs;
62 struct device *rtc_dev;
63 spinlock_t ctrl_reg_lock;
64};
65
66/*
67 * Steps to write the RTC registers.
68 * 1. Disable alarm if enabled.
69 * 2. Disable rtc if enabled.
70 * 3. Write 0x00 to LSB.
71 * 4. Write Byte[1], Byte[2], Byte[3] then Byte[0].
72 * 5. Enable rtc if disabled in step 2.
73 * 6. Enable alarm if disabled in step 1.
74 */
75static int pm8xxx_rtc_set_time(struct device *dev, struct rtc_time *tm)
76{
77 int rc, i;
78 unsigned long secs, irq_flags;
79 u8 value[NUM_8_BIT_RTC_REGS], alarm_enabled = 0, rtc_disabled = 0;
80 unsigned int ctrl_reg, rtc_ctrl_reg;
81 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
82 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
83
84 if (!rtc_dd->allow_set_time)
85 return -EACCES;
86
87 secs = rtc_tm_to_time64(tm);
88
89 dev_dbg(dev, "Seconds value to be written to RTC = %lu\n", secs);
90
91 for (i = 0; i < NUM_8_BIT_RTC_REGS; i++) {
92 value[i] = secs & 0xFF;
93 secs >>= 8;
94 }
95
96 spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
97
98 rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
99 if (rc)
100 goto rtc_rw_fail;
101
102 if (ctrl_reg & regs->alarm_en) {
103 alarm_enabled = 1;
104 ctrl_reg &= ~regs->alarm_en;
105 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
106 if (rc) {
107 dev_err(dev, "Write to RTC Alarm control register failed\n");
108 goto rtc_rw_fail;
109 }
110 }
111
112 /* Disable RTC H/w before writing on RTC register */
113 rc = regmap_read(rtc_dd->regmap, regs->ctrl, &rtc_ctrl_reg);
114 if (rc)
115 goto rtc_rw_fail;
116
117 if (rtc_ctrl_reg & PM8xxx_RTC_ENABLE) {
118 rtc_disabled = 1;
119 rtc_ctrl_reg &= ~PM8xxx_RTC_ENABLE;
120 rc = regmap_write(rtc_dd->regmap, regs->ctrl, rtc_ctrl_reg);
121 if (rc) {
122 dev_err(dev, "Write to RTC control register failed\n");
123 goto rtc_rw_fail;
124 }
125 }
126
127 /* Write 0 to Byte[0] */
128 rc = regmap_write(rtc_dd->regmap, regs->write, 0);
129 if (rc) {
130 dev_err(dev, "Write to RTC write data register failed\n");
131 goto rtc_rw_fail;
132 }
133
134 /* Write Byte[1], Byte[2], Byte[3] */
135 rc = regmap_bulk_write(rtc_dd->regmap, regs->write + 1,
136 &value[1], sizeof(value) - 1);
137 if (rc) {
138 dev_err(dev, "Write to RTC write data register failed\n");
139 goto rtc_rw_fail;
140 }
141
142 /* Write Byte[0] */
143 rc = regmap_write(rtc_dd->regmap, regs->write, value[0]);
144 if (rc) {
145 dev_err(dev, "Write to RTC write data register failed\n");
146 goto rtc_rw_fail;
147 }
148
149 /* Enable RTC H/w after writing on RTC register */
150 if (rtc_disabled) {
151 rtc_ctrl_reg |= PM8xxx_RTC_ENABLE;
152 rc = regmap_write(rtc_dd->regmap, regs->ctrl, rtc_ctrl_reg);
153 if (rc) {
154 dev_err(dev, "Write to RTC control register failed\n");
155 goto rtc_rw_fail;
156 }
157 }
158
159 if (alarm_enabled) {
160 ctrl_reg |= regs->alarm_en;
161 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
162 if (rc) {
163 dev_err(dev, "Write to RTC Alarm control register failed\n");
164 goto rtc_rw_fail;
165 }
166 }
167
168rtc_rw_fail:
169 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
170
171 return rc;
172}
173
174static int pm8xxx_rtc_read_time(struct device *dev, struct rtc_time *tm)
175{
176 int rc;
177 u8 value[NUM_8_BIT_RTC_REGS];
178 unsigned long secs;
179 unsigned int reg;
180 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
181 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
182
183 rc = regmap_bulk_read(rtc_dd->regmap, regs->read, value, sizeof(value));
184 if (rc) {
185 dev_err(dev, "RTC read data register failed\n");
186 return rc;
187 }
188
189 /*
190 * Read the LSB again and check if there has been a carry over.
191 * If there is, redo the read operation.
192 */
193 rc = regmap_read(rtc_dd->regmap, regs->read, ®);
194 if (rc < 0) {
195 dev_err(dev, "RTC read data register failed\n");
196 return rc;
197 }
198
199 if (unlikely(reg < value[0])) {
200 rc = regmap_bulk_read(rtc_dd->regmap, regs->read,
201 value, sizeof(value));
202 if (rc) {
203 dev_err(dev, "RTC read data register failed\n");
204 return rc;
205 }
206 }
207
208 secs = value[0] | (value[1] << 8) | (value[2] << 16) |
209 ((unsigned long)value[3] << 24);
210
211 rtc_time64_to_tm(secs, tm);
212
213 dev_dbg(dev, "secs = %lu, h:m:s == %ptRt, y-m-d = %ptRdr\n", secs, tm, tm);
214
215 return 0;
216}
217
218static int pm8xxx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
219{
220 int rc, i;
221 u8 value[NUM_8_BIT_RTC_REGS];
222 unsigned int ctrl_reg;
223 unsigned long secs, irq_flags;
224 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
225 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
226
227 secs = rtc_tm_to_time64(&alarm->time);
228
229 for (i = 0; i < NUM_8_BIT_RTC_REGS; i++) {
230 value[i] = secs & 0xFF;
231 secs >>= 8;
232 }
233
234 spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
235
236 rc = regmap_bulk_write(rtc_dd->regmap, regs->alarm_rw, value,
237 sizeof(value));
238 if (rc) {
239 dev_err(dev, "Write to RTC ALARM register failed\n");
240 goto rtc_rw_fail;
241 }
242
243 rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
244 if (rc)
245 goto rtc_rw_fail;
246
247 if (alarm->enabled)
248 ctrl_reg |= regs->alarm_en;
249 else
250 ctrl_reg &= ~regs->alarm_en;
251
252 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
253 if (rc) {
254 dev_err(dev, "Write to RTC alarm control register failed\n");
255 goto rtc_rw_fail;
256 }
257
258 dev_dbg(dev, "Alarm Set for h:m:s=%ptRt, y-m-d=%ptRdr\n",
259 &alarm->time, &alarm->time);
260rtc_rw_fail:
261 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
262 return rc;
263}
264
265static int pm8xxx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
266{
267 int rc;
268 u8 value[NUM_8_BIT_RTC_REGS];
269 unsigned long secs;
270 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
271 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
272
273 rc = regmap_bulk_read(rtc_dd->regmap, regs->alarm_rw, value,
274 sizeof(value));
275 if (rc) {
276 dev_err(dev, "RTC alarm time read failed\n");
277 return rc;
278 }
279
280 secs = value[0] | (value[1] << 8) | (value[2] << 16) |
281 ((unsigned long)value[3] << 24);
282
283 rtc_time64_to_tm(secs, &alarm->time);
284
285 dev_dbg(dev, "Alarm set for - h:m:s=%ptRt, y-m-d=%ptRdr\n",
286 &alarm->time, &alarm->time);
287
288 return 0;
289}
290
291static int pm8xxx_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
292{
293 int rc;
294 unsigned long irq_flags;
295 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
296 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
297 unsigned int ctrl_reg;
298 u8 value[NUM_8_BIT_RTC_REGS] = {0};
299
300 spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
301
302 rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
303 if (rc)
304 goto rtc_rw_fail;
305
306 if (enable)
307 ctrl_reg |= regs->alarm_en;
308 else
309 ctrl_reg &= ~regs->alarm_en;
310
311 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
312 if (rc) {
313 dev_err(dev, "Write to RTC control register failed\n");
314 goto rtc_rw_fail;
315 }
316
317 /* Clear Alarm register */
318 if (!enable) {
319 rc = regmap_bulk_write(rtc_dd->regmap, regs->alarm_rw, value,
320 sizeof(value));
321 if (rc) {
322 dev_err(dev, "Clear RTC ALARM register failed\n");
323 goto rtc_rw_fail;
324 }
325 }
326
327rtc_rw_fail:
328 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
329 return rc;
330}
331
332static const struct rtc_class_ops pm8xxx_rtc_ops = {
333 .read_time = pm8xxx_rtc_read_time,
334 .set_time = pm8xxx_rtc_set_time,
335 .set_alarm = pm8xxx_rtc_set_alarm,
336 .read_alarm = pm8xxx_rtc_read_alarm,
337 .alarm_irq_enable = pm8xxx_rtc_alarm_irq_enable,
338};
339
340static irqreturn_t pm8xxx_alarm_trigger(int irq, void *dev_id)
341{
342 struct pm8xxx_rtc *rtc_dd = dev_id;
343 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
344 unsigned int ctrl_reg;
345 int rc;
346 unsigned long irq_flags;
347
348 rtc_update_irq(rtc_dd->rtc, 1, RTC_IRQF | RTC_AF);
349
350 spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
351
352 /* Clear the alarm enable bit */
353 rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
354 if (rc) {
355 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
356 goto rtc_alarm_handled;
357 }
358
359 ctrl_reg &= ~regs->alarm_en;
360
361 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
362 if (rc) {
363 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
364 dev_err(rtc_dd->rtc_dev,
365 "Write to alarm control register failed\n");
366 goto rtc_alarm_handled;
367 }
368
369 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
370
371 /* Clear RTC alarm register */
372 rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl2, &ctrl_reg);
373 if (rc) {
374 dev_err(rtc_dd->rtc_dev,
375 "RTC Alarm control2 register read failed\n");
376 goto rtc_alarm_handled;
377 }
378
379 ctrl_reg |= PM8xxx_RTC_ALARM_CLEAR;
380 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl2, ctrl_reg);
381 if (rc)
382 dev_err(rtc_dd->rtc_dev,
383 "Write to RTC Alarm control2 register failed\n");
384
385rtc_alarm_handled:
386 return IRQ_HANDLED;
387}
388
389static int pm8xxx_rtc_enable(struct pm8xxx_rtc *rtc_dd)
390{
391 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
392 unsigned int ctrl_reg;
393 int rc;
394
395 /* Check if the RTC is on, else turn it on */
396 rc = regmap_read(rtc_dd->regmap, regs->ctrl, &ctrl_reg);
397 if (rc)
398 return rc;
399
400 if (!(ctrl_reg & PM8xxx_RTC_ENABLE)) {
401 ctrl_reg |= PM8xxx_RTC_ENABLE;
402 rc = regmap_write(rtc_dd->regmap, regs->ctrl, ctrl_reg);
403 if (rc)
404 return rc;
405 }
406
407 return 0;
408}
409
410static const struct pm8xxx_rtc_regs pm8921_regs = {
411 .ctrl = 0x11d,
412 .write = 0x11f,
413 .read = 0x123,
414 .alarm_rw = 0x127,
415 .alarm_ctrl = 0x11d,
416 .alarm_ctrl2 = 0x11e,
417 .alarm_en = BIT(1),
418};
419
420static const struct pm8xxx_rtc_regs pm8058_regs = {
421 .ctrl = 0x1e8,
422 .write = 0x1ea,
423 .read = 0x1ee,
424 .alarm_rw = 0x1f2,
425 .alarm_ctrl = 0x1e8,
426 .alarm_ctrl2 = 0x1e9,
427 .alarm_en = BIT(1),
428};
429
430static const struct pm8xxx_rtc_regs pm8941_regs = {
431 .ctrl = 0x6046,
432 .write = 0x6040,
433 .read = 0x6048,
434 .alarm_rw = 0x6140,
435 .alarm_ctrl = 0x6146,
436 .alarm_ctrl2 = 0x6148,
437 .alarm_en = BIT(7),
438};
439
440/*
441 * Hardcoded RTC bases until IORESOURCE_REG mapping is figured out
442 */
443static const struct of_device_id pm8xxx_id_table[] = {
444 { .compatible = "qcom,pm8921-rtc", .data = &pm8921_regs },
445 { .compatible = "qcom,pm8018-rtc", .data = &pm8921_regs },
446 { .compatible = "qcom,pm8058-rtc", .data = &pm8058_regs },
447 { .compatible = "qcom,pm8941-rtc", .data = &pm8941_regs },
448 { },
449};
450MODULE_DEVICE_TABLE(of, pm8xxx_id_table);
451
452static int pm8xxx_rtc_probe(struct platform_device *pdev)
453{
454 int rc;
455 struct pm8xxx_rtc *rtc_dd;
456 const struct of_device_id *match;
457
458 match = of_match_node(pm8xxx_id_table, pdev->dev.of_node);
459 if (!match)
460 return -ENXIO;
461
462 rtc_dd = devm_kzalloc(&pdev->dev, sizeof(*rtc_dd), GFP_KERNEL);
463 if (rtc_dd == NULL)
464 return -ENOMEM;
465
466 /* Initialise spinlock to protect RTC control register */
467 spin_lock_init(&rtc_dd->ctrl_reg_lock);
468
469 rtc_dd->regmap = dev_get_regmap(pdev->dev.parent, NULL);
470 if (!rtc_dd->regmap) {
471 dev_err(&pdev->dev, "Parent regmap unavailable.\n");
472 return -ENXIO;
473 }
474
475 rtc_dd->rtc_alarm_irq = platform_get_irq(pdev, 0);
476 if (rtc_dd->rtc_alarm_irq < 0)
477 return -ENXIO;
478
479 rtc_dd->allow_set_time = of_property_read_bool(pdev->dev.of_node,
480 "allow-set-time");
481
482 rtc_dd->regs = match->data;
483 rtc_dd->rtc_dev = &pdev->dev;
484
485 rc = pm8xxx_rtc_enable(rtc_dd);
486 if (rc)
487 return rc;
488
489 platform_set_drvdata(pdev, rtc_dd);
490
491 device_init_wakeup(&pdev->dev, 1);
492
493 /* Register the RTC device */
494 rtc_dd->rtc = devm_rtc_allocate_device(&pdev->dev);
495 if (IS_ERR(rtc_dd->rtc))
496 return PTR_ERR(rtc_dd->rtc);
497
498 rtc_dd->rtc->ops = &pm8xxx_rtc_ops;
499 rtc_dd->rtc->range_max = U32_MAX;
500
501 /* Request the alarm IRQ */
502 rc = devm_request_any_context_irq(&pdev->dev, rtc_dd->rtc_alarm_irq,
503 pm8xxx_alarm_trigger,
504 IRQF_TRIGGER_RISING,
505 "pm8xxx_rtc_alarm", rtc_dd);
506 if (rc < 0) {
507 dev_err(&pdev->dev, "Request IRQ failed (%d)\n", rc);
508 return rc;
509 }
510
511 return rtc_register_device(rtc_dd->rtc);
512}
513
514#ifdef CONFIG_PM_SLEEP
515static int pm8xxx_rtc_resume(struct device *dev)
516{
517 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
518
519 if (device_may_wakeup(dev))
520 disable_irq_wake(rtc_dd->rtc_alarm_irq);
521
522 return 0;
523}
524
525static int pm8xxx_rtc_suspend(struct device *dev)
526{
527 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
528
529 if (device_may_wakeup(dev))
530 enable_irq_wake(rtc_dd->rtc_alarm_irq);
531
532 return 0;
533}
534#endif
535
536static SIMPLE_DEV_PM_OPS(pm8xxx_rtc_pm_ops,
537 pm8xxx_rtc_suspend,
538 pm8xxx_rtc_resume);
539
540static struct platform_driver pm8xxx_rtc_driver = {
541 .probe = pm8xxx_rtc_probe,
542 .driver = {
543 .name = "rtc-pm8xxx",
544 .pm = &pm8xxx_rtc_pm_ops,
545 .of_match_table = pm8xxx_id_table,
546 },
547};
548
549module_platform_driver(pm8xxx_rtc_driver);
550
551MODULE_ALIAS("platform:rtc-pm8xxx");
552MODULE_DESCRIPTION("PMIC8xxx RTC driver");
553MODULE_LICENSE("GPL v2");
554MODULE_AUTHOR("Anirudh Ghayal <aghayal@codeaurora.org>");
1/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12#include <linux/of.h>
13#include <linux/module.h>
14#include <linux/init.h>
15#include <linux/rtc.h>
16#include <linux/platform_device.h>
17#include <linux/pm.h>
18#include <linux/regmap.h>
19#include <linux/slab.h>
20#include <linux/spinlock.h>
21
22/* RTC Register offsets from RTC CTRL REG */
23#define PM8XXX_ALARM_CTRL_OFFSET 0x01
24#define PM8XXX_RTC_WRITE_OFFSET 0x02
25#define PM8XXX_RTC_READ_OFFSET 0x06
26#define PM8XXX_ALARM_RW_OFFSET 0x0A
27
28/* RTC_CTRL register bit fields */
29#define PM8xxx_RTC_ENABLE BIT(7)
30#define PM8xxx_RTC_ALARM_CLEAR BIT(0)
31
32#define NUM_8_BIT_RTC_REGS 0x4
33
34/**
35 * struct pm8xxx_rtc_regs - describe RTC registers per PMIC versions
36 * @ctrl: base address of control register
37 * @write: base address of write register
38 * @read: base address of read register
39 * @alarm_ctrl: base address of alarm control register
40 * @alarm_ctrl2: base address of alarm control2 register
41 * @alarm_rw: base address of alarm read-write register
42 * @alarm_en: alarm enable mask
43 */
44struct pm8xxx_rtc_regs {
45 unsigned int ctrl;
46 unsigned int write;
47 unsigned int read;
48 unsigned int alarm_ctrl;
49 unsigned int alarm_ctrl2;
50 unsigned int alarm_rw;
51 unsigned int alarm_en;
52};
53
54/**
55 * struct pm8xxx_rtc - rtc driver internal structure
56 * @rtc: rtc device for this driver.
57 * @regmap: regmap used to access RTC registers
58 * @allow_set_time: indicates whether writing to the RTC is allowed
59 * @rtc_alarm_irq: rtc alarm irq number.
60 * @ctrl_reg: rtc control register.
61 * @rtc_dev: device structure.
62 * @ctrl_reg_lock: spinlock protecting access to ctrl_reg.
63 */
64struct pm8xxx_rtc {
65 struct rtc_device *rtc;
66 struct regmap *regmap;
67 bool allow_set_time;
68 int rtc_alarm_irq;
69 const struct pm8xxx_rtc_regs *regs;
70 struct device *rtc_dev;
71 spinlock_t ctrl_reg_lock;
72};
73
74/*
75 * Steps to write the RTC registers.
76 * 1. Disable alarm if enabled.
77 * 2. Write 0x00 to LSB.
78 * 3. Write Byte[1], Byte[2], Byte[3] then Byte[0].
79 * 4. Enable alarm if disabled in step 1.
80 */
81static int pm8xxx_rtc_set_time(struct device *dev, struct rtc_time *tm)
82{
83 int rc, i;
84 unsigned long secs, irq_flags;
85 u8 value[NUM_8_BIT_RTC_REGS], alarm_enabled = 0;
86 unsigned int ctrl_reg;
87 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
88 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
89
90 if (!rtc_dd->allow_set_time)
91 return -EACCES;
92
93 rtc_tm_to_time(tm, &secs);
94
95 for (i = 0; i < NUM_8_BIT_RTC_REGS; i++) {
96 value[i] = secs & 0xFF;
97 secs >>= 8;
98 }
99
100 dev_dbg(dev, "Seconds value to be written to RTC = %lu\n", secs);
101
102 spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
103
104 rc = regmap_read(rtc_dd->regmap, regs->ctrl, &ctrl_reg);
105 if (rc)
106 goto rtc_rw_fail;
107
108 if (ctrl_reg & regs->alarm_en) {
109 alarm_enabled = 1;
110 ctrl_reg &= ~regs->alarm_en;
111 rc = regmap_write(rtc_dd->regmap, regs->ctrl, ctrl_reg);
112 if (rc) {
113 dev_err(dev, "Write to RTC control register failed\n");
114 goto rtc_rw_fail;
115 }
116 }
117
118 /* Write 0 to Byte[0] */
119 rc = regmap_write(rtc_dd->regmap, regs->write, 0);
120 if (rc) {
121 dev_err(dev, "Write to RTC write data register failed\n");
122 goto rtc_rw_fail;
123 }
124
125 /* Write Byte[1], Byte[2], Byte[3] */
126 rc = regmap_bulk_write(rtc_dd->regmap, regs->write + 1,
127 &value[1], sizeof(value) - 1);
128 if (rc) {
129 dev_err(dev, "Write to RTC write data register failed\n");
130 goto rtc_rw_fail;
131 }
132
133 /* Write Byte[0] */
134 rc = regmap_write(rtc_dd->regmap, regs->write, value[0]);
135 if (rc) {
136 dev_err(dev, "Write to RTC write data register failed\n");
137 goto rtc_rw_fail;
138 }
139
140 if (alarm_enabled) {
141 ctrl_reg |= regs->alarm_en;
142 rc = regmap_write(rtc_dd->regmap, regs->ctrl, ctrl_reg);
143 if (rc) {
144 dev_err(dev, "Write to RTC control register failed\n");
145 goto rtc_rw_fail;
146 }
147 }
148
149rtc_rw_fail:
150 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
151
152 return rc;
153}
154
155static int pm8xxx_rtc_read_time(struct device *dev, struct rtc_time *tm)
156{
157 int rc;
158 u8 value[NUM_8_BIT_RTC_REGS];
159 unsigned long secs;
160 unsigned int reg;
161 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
162 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
163
164 rc = regmap_bulk_read(rtc_dd->regmap, regs->read, value, sizeof(value));
165 if (rc) {
166 dev_err(dev, "RTC read data register failed\n");
167 return rc;
168 }
169
170 /*
171 * Read the LSB again and check if there has been a carry over.
172 * If there is, redo the read operation.
173 */
174 rc = regmap_read(rtc_dd->regmap, regs->read, ®);
175 if (rc < 0) {
176 dev_err(dev, "RTC read data register failed\n");
177 return rc;
178 }
179
180 if (unlikely(reg < value[0])) {
181 rc = regmap_bulk_read(rtc_dd->regmap, regs->read,
182 value, sizeof(value));
183 if (rc) {
184 dev_err(dev, "RTC read data register failed\n");
185 return rc;
186 }
187 }
188
189 secs = value[0] | (value[1] << 8) | (value[2] << 16) | (value[3] << 24);
190
191 rtc_time_to_tm(secs, tm);
192
193 rc = rtc_valid_tm(tm);
194 if (rc < 0) {
195 dev_err(dev, "Invalid time read from RTC\n");
196 return rc;
197 }
198
199 dev_dbg(dev, "secs = %lu, h:m:s == %d:%d:%d, d/m/y = %d/%d/%d\n",
200 secs, tm->tm_hour, tm->tm_min, tm->tm_sec,
201 tm->tm_mday, tm->tm_mon, tm->tm_year);
202
203 return 0;
204}
205
206static int pm8xxx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
207{
208 int rc, i;
209 u8 value[NUM_8_BIT_RTC_REGS];
210 unsigned int ctrl_reg;
211 unsigned long secs, irq_flags;
212 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
213 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
214
215 rtc_tm_to_time(&alarm->time, &secs);
216
217 for (i = 0; i < NUM_8_BIT_RTC_REGS; i++) {
218 value[i] = secs & 0xFF;
219 secs >>= 8;
220 }
221
222 spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
223
224 rc = regmap_bulk_write(rtc_dd->regmap, regs->alarm_rw, value,
225 sizeof(value));
226 if (rc) {
227 dev_err(dev, "Write to RTC ALARM register failed\n");
228 goto rtc_rw_fail;
229 }
230
231 rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
232 if (rc)
233 goto rtc_rw_fail;
234
235 if (alarm->enabled)
236 ctrl_reg |= regs->alarm_en;
237 else
238 ctrl_reg &= ~regs->alarm_en;
239
240 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
241 if (rc) {
242 dev_err(dev, "Write to RTC alarm control register failed\n");
243 goto rtc_rw_fail;
244 }
245
246 dev_dbg(dev, "Alarm Set for h:r:s=%d:%d:%d, d/m/y=%d/%d/%d\n",
247 alarm->time.tm_hour, alarm->time.tm_min,
248 alarm->time.tm_sec, alarm->time.tm_mday,
249 alarm->time.tm_mon, alarm->time.tm_year);
250rtc_rw_fail:
251 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
252 return rc;
253}
254
255static int pm8xxx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
256{
257 int rc;
258 u8 value[NUM_8_BIT_RTC_REGS];
259 unsigned long secs;
260 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
261 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
262
263 rc = regmap_bulk_read(rtc_dd->regmap, regs->alarm_rw, value,
264 sizeof(value));
265 if (rc) {
266 dev_err(dev, "RTC alarm time read failed\n");
267 return rc;
268 }
269
270 secs = value[0] | (value[1] << 8) | (value[2] << 16) | (value[3] << 24);
271
272 rtc_time_to_tm(secs, &alarm->time);
273
274 rc = rtc_valid_tm(&alarm->time);
275 if (rc < 0) {
276 dev_err(dev, "Invalid alarm time read from RTC\n");
277 return rc;
278 }
279
280 dev_dbg(dev, "Alarm set for - h:r:s=%d:%d:%d, d/m/y=%d/%d/%d\n",
281 alarm->time.tm_hour, alarm->time.tm_min,
282 alarm->time.tm_sec, alarm->time.tm_mday,
283 alarm->time.tm_mon, alarm->time.tm_year);
284
285 return 0;
286}
287
288static int pm8xxx_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
289{
290 int rc;
291 unsigned long irq_flags;
292 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
293 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
294 unsigned int ctrl_reg;
295
296 spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
297
298 rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
299 if (rc)
300 goto rtc_rw_fail;
301
302 if (enable)
303 ctrl_reg |= regs->alarm_en;
304 else
305 ctrl_reg &= ~regs->alarm_en;
306
307 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
308 if (rc) {
309 dev_err(dev, "Write to RTC control register failed\n");
310 goto rtc_rw_fail;
311 }
312
313rtc_rw_fail:
314 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
315 return rc;
316}
317
318static const struct rtc_class_ops pm8xxx_rtc_ops = {
319 .read_time = pm8xxx_rtc_read_time,
320 .set_time = pm8xxx_rtc_set_time,
321 .set_alarm = pm8xxx_rtc_set_alarm,
322 .read_alarm = pm8xxx_rtc_read_alarm,
323 .alarm_irq_enable = pm8xxx_rtc_alarm_irq_enable,
324};
325
326static irqreturn_t pm8xxx_alarm_trigger(int irq, void *dev_id)
327{
328 struct pm8xxx_rtc *rtc_dd = dev_id;
329 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
330 unsigned int ctrl_reg;
331 int rc;
332 unsigned long irq_flags;
333
334 rtc_update_irq(rtc_dd->rtc, 1, RTC_IRQF | RTC_AF);
335
336 spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
337
338 /* Clear the alarm enable bit */
339 rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
340 if (rc) {
341 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
342 goto rtc_alarm_handled;
343 }
344
345 ctrl_reg &= ~regs->alarm_en;
346
347 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
348 if (rc) {
349 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
350 dev_err(rtc_dd->rtc_dev,
351 "Write to alarm control register failed\n");
352 goto rtc_alarm_handled;
353 }
354
355 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
356
357 /* Clear RTC alarm register */
358 rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl2, &ctrl_reg);
359 if (rc) {
360 dev_err(rtc_dd->rtc_dev,
361 "RTC Alarm control2 register read failed\n");
362 goto rtc_alarm_handled;
363 }
364
365 ctrl_reg |= PM8xxx_RTC_ALARM_CLEAR;
366 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl2, ctrl_reg);
367 if (rc)
368 dev_err(rtc_dd->rtc_dev,
369 "Write to RTC Alarm control2 register failed\n");
370
371rtc_alarm_handled:
372 return IRQ_HANDLED;
373}
374
375static int pm8xxx_rtc_enable(struct pm8xxx_rtc *rtc_dd)
376{
377 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
378 unsigned int ctrl_reg;
379 int rc;
380
381 /* Check if the RTC is on, else turn it on */
382 rc = regmap_read(rtc_dd->regmap, regs->ctrl, &ctrl_reg);
383 if (rc)
384 return rc;
385
386 if (!(ctrl_reg & PM8xxx_RTC_ENABLE)) {
387 ctrl_reg |= PM8xxx_RTC_ENABLE;
388 rc = regmap_write(rtc_dd->regmap, regs->ctrl, ctrl_reg);
389 if (rc)
390 return rc;
391 }
392
393 return 0;
394}
395
396static const struct pm8xxx_rtc_regs pm8921_regs = {
397 .ctrl = 0x11d,
398 .write = 0x11f,
399 .read = 0x123,
400 .alarm_rw = 0x127,
401 .alarm_ctrl = 0x11d,
402 .alarm_ctrl2 = 0x11e,
403 .alarm_en = BIT(1),
404};
405
406static const struct pm8xxx_rtc_regs pm8058_regs = {
407 .ctrl = 0x1e8,
408 .write = 0x1ea,
409 .read = 0x1ee,
410 .alarm_rw = 0x1f2,
411 .alarm_ctrl = 0x1e8,
412 .alarm_ctrl2 = 0x1e9,
413 .alarm_en = BIT(1),
414};
415
416static const struct pm8xxx_rtc_regs pm8941_regs = {
417 .ctrl = 0x6046,
418 .write = 0x6040,
419 .read = 0x6048,
420 .alarm_rw = 0x6140,
421 .alarm_ctrl = 0x6146,
422 .alarm_ctrl2 = 0x6148,
423 .alarm_en = BIT(7),
424};
425
426/*
427 * Hardcoded RTC bases until IORESOURCE_REG mapping is figured out
428 */
429static const struct of_device_id pm8xxx_id_table[] = {
430 { .compatible = "qcom,pm8921-rtc", .data = &pm8921_regs },
431 { .compatible = "qcom,pm8018-rtc", .data = &pm8921_regs },
432 { .compatible = "qcom,pm8058-rtc", .data = &pm8058_regs },
433 { .compatible = "qcom,pm8941-rtc", .data = &pm8941_regs },
434 { },
435};
436MODULE_DEVICE_TABLE(of, pm8xxx_id_table);
437
438static int pm8xxx_rtc_probe(struct platform_device *pdev)
439{
440 int rc;
441 struct pm8xxx_rtc *rtc_dd;
442 const struct of_device_id *match;
443
444 match = of_match_node(pm8xxx_id_table, pdev->dev.of_node);
445 if (!match)
446 return -ENXIO;
447
448 rtc_dd = devm_kzalloc(&pdev->dev, sizeof(*rtc_dd), GFP_KERNEL);
449 if (rtc_dd == NULL)
450 return -ENOMEM;
451
452 /* Initialise spinlock to protect RTC control register */
453 spin_lock_init(&rtc_dd->ctrl_reg_lock);
454
455 rtc_dd->regmap = dev_get_regmap(pdev->dev.parent, NULL);
456 if (!rtc_dd->regmap) {
457 dev_err(&pdev->dev, "Parent regmap unavailable.\n");
458 return -ENXIO;
459 }
460
461 rtc_dd->rtc_alarm_irq = platform_get_irq(pdev, 0);
462 if (rtc_dd->rtc_alarm_irq < 0) {
463 dev_err(&pdev->dev, "Alarm IRQ resource absent!\n");
464 return -ENXIO;
465 }
466
467 rtc_dd->allow_set_time = of_property_read_bool(pdev->dev.of_node,
468 "allow-set-time");
469
470 rtc_dd->regs = match->data;
471 rtc_dd->rtc_dev = &pdev->dev;
472
473 rc = pm8xxx_rtc_enable(rtc_dd);
474 if (rc)
475 return rc;
476
477 platform_set_drvdata(pdev, rtc_dd);
478
479 device_init_wakeup(&pdev->dev, 1);
480
481 /* Register the RTC device */
482 rtc_dd->rtc = devm_rtc_device_register(&pdev->dev, "pm8xxx_rtc",
483 &pm8xxx_rtc_ops, THIS_MODULE);
484 if (IS_ERR(rtc_dd->rtc)) {
485 dev_err(&pdev->dev, "%s: RTC registration failed (%ld)\n",
486 __func__, PTR_ERR(rtc_dd->rtc));
487 return PTR_ERR(rtc_dd->rtc);
488 }
489
490 /* Request the alarm IRQ */
491 rc = devm_request_any_context_irq(&pdev->dev, rtc_dd->rtc_alarm_irq,
492 pm8xxx_alarm_trigger,
493 IRQF_TRIGGER_RISING,
494 "pm8xxx_rtc_alarm", rtc_dd);
495 if (rc < 0) {
496 dev_err(&pdev->dev, "Request IRQ failed (%d)\n", rc);
497 return rc;
498 }
499
500 dev_dbg(&pdev->dev, "Probe success !!\n");
501
502 return 0;
503}
504
505#ifdef CONFIG_PM_SLEEP
506static int pm8xxx_rtc_resume(struct device *dev)
507{
508 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
509
510 if (device_may_wakeup(dev))
511 disable_irq_wake(rtc_dd->rtc_alarm_irq);
512
513 return 0;
514}
515
516static int pm8xxx_rtc_suspend(struct device *dev)
517{
518 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
519
520 if (device_may_wakeup(dev))
521 enable_irq_wake(rtc_dd->rtc_alarm_irq);
522
523 return 0;
524}
525#endif
526
527static SIMPLE_DEV_PM_OPS(pm8xxx_rtc_pm_ops,
528 pm8xxx_rtc_suspend,
529 pm8xxx_rtc_resume);
530
531static struct platform_driver pm8xxx_rtc_driver = {
532 .probe = pm8xxx_rtc_probe,
533 .driver = {
534 .name = "rtc-pm8xxx",
535 .pm = &pm8xxx_rtc_pm_ops,
536 .of_match_table = pm8xxx_id_table,
537 },
538};
539
540module_platform_driver(pm8xxx_rtc_driver);
541
542MODULE_ALIAS("platform:rtc-pm8xxx");
543MODULE_DESCRIPTION("PMIC8xxx RTC driver");
544MODULE_LICENSE("GPL v2");
545MODULE_AUTHOR("Anirudh Ghayal <aghayal@codeaurora.org>");