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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * ECAP PWM driver
4 *
5 * Copyright (C) 2012 Texas Instruments, Inc. - https://www.ti.com/
6 */
7
8#include <linux/module.h>
9#include <linux/platform_device.h>
10#include <linux/io.h>
11#include <linux/err.h>
12#include <linux/clk.h>
13#include <linux/pm_runtime.h>
14#include <linux/pwm.h>
15#include <linux/of_device.h>
16
17/* ECAP registers and bits definitions */
18#define CAP1 0x08
19#define CAP2 0x0C
20#define CAP3 0x10
21#define CAP4 0x14
22#define ECCTL2 0x2A
23#define ECCTL2_APWM_POL_LOW BIT(10)
24#define ECCTL2_APWM_MODE BIT(9)
25#define ECCTL2_SYNC_SEL_DISA (BIT(7) | BIT(6))
26#define ECCTL2_TSCTR_FREERUN BIT(4)
27
28struct ecap_context {
29 u32 cap3;
30 u32 cap4;
31 u16 ecctl2;
32};
33
34struct ecap_pwm_chip {
35 struct pwm_chip chip;
36 unsigned int clk_rate;
37 void __iomem *mmio_base;
38 struct ecap_context ctx;
39};
40
41static inline struct ecap_pwm_chip *to_ecap_pwm_chip(struct pwm_chip *chip)
42{
43 return container_of(chip, struct ecap_pwm_chip, chip);
44}
45
46/*
47 * period_ns = 10^9 * period_cycles / PWM_CLK_RATE
48 * duty_ns = 10^9 * duty_cycles / PWM_CLK_RATE
49 */
50static int ecap_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
51 int duty_ns, int period_ns)
52{
53 struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);
54 u32 period_cycles, duty_cycles;
55 unsigned long long c;
56 u16 value;
57
58 if (period_ns > NSEC_PER_SEC)
59 return -ERANGE;
60
61 c = pc->clk_rate;
62 c = c * period_ns;
63 do_div(c, NSEC_PER_SEC);
64 period_cycles = (u32)c;
65
66 if (period_cycles < 1) {
67 period_cycles = 1;
68 duty_cycles = 1;
69 } else {
70 c = pc->clk_rate;
71 c = c * duty_ns;
72 do_div(c, NSEC_PER_SEC);
73 duty_cycles = (u32)c;
74 }
75
76 pm_runtime_get_sync(pc->chip.dev);
77
78 value = readw(pc->mmio_base + ECCTL2);
79
80 /* Configure APWM mode & disable sync option */
81 value |= ECCTL2_APWM_MODE | ECCTL2_SYNC_SEL_DISA;
82
83 writew(value, pc->mmio_base + ECCTL2);
84
85 if (!pwm_is_enabled(pwm)) {
86 /* Update active registers if not running */
87 writel(duty_cycles, pc->mmio_base + CAP2);
88 writel(period_cycles, pc->mmio_base + CAP1);
89 } else {
90 /*
91 * Update shadow registers to configure period and
92 * compare values. This helps current PWM period to
93 * complete on reconfiguring
94 */
95 writel(duty_cycles, pc->mmio_base + CAP4);
96 writel(period_cycles, pc->mmio_base + CAP3);
97 }
98
99 if (!pwm_is_enabled(pwm)) {
100 value = readw(pc->mmio_base + ECCTL2);
101 /* Disable APWM mode to put APWM output Low */
102 value &= ~ECCTL2_APWM_MODE;
103 writew(value, pc->mmio_base + ECCTL2);
104 }
105
106 pm_runtime_put_sync(pc->chip.dev);
107
108 return 0;
109}
110
111static int ecap_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm,
112 enum pwm_polarity polarity)
113{
114 struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);
115 u16 value;
116
117 pm_runtime_get_sync(pc->chip.dev);
118
119 value = readw(pc->mmio_base + ECCTL2);
120
121 if (polarity == PWM_POLARITY_INVERSED)
122 /* Duty cycle defines LOW period of PWM */
123 value |= ECCTL2_APWM_POL_LOW;
124 else
125 /* Duty cycle defines HIGH period of PWM */
126 value &= ~ECCTL2_APWM_POL_LOW;
127
128 writew(value, pc->mmio_base + ECCTL2);
129
130 pm_runtime_put_sync(pc->chip.dev);
131
132 return 0;
133}
134
135static int ecap_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
136{
137 struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);
138 u16 value;
139
140 /* Leave clock enabled on enabling PWM */
141 pm_runtime_get_sync(pc->chip.dev);
142
143 /*
144 * Enable 'Free run Time stamp counter mode' to start counter
145 * and 'APWM mode' to enable APWM output
146 */
147 value = readw(pc->mmio_base + ECCTL2);
148 value |= ECCTL2_TSCTR_FREERUN | ECCTL2_APWM_MODE;
149 writew(value, pc->mmio_base + ECCTL2);
150
151 return 0;
152}
153
154static void ecap_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
155{
156 struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);
157 u16 value;
158
159 /*
160 * Disable 'Free run Time stamp counter mode' to stop counter
161 * and 'APWM mode' to put APWM output to low
162 */
163 value = readw(pc->mmio_base + ECCTL2);
164 value &= ~(ECCTL2_TSCTR_FREERUN | ECCTL2_APWM_MODE);
165 writew(value, pc->mmio_base + ECCTL2);
166
167 /* Disable clock on PWM disable */
168 pm_runtime_put_sync(pc->chip.dev);
169}
170
171static void ecap_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
172{
173 if (pwm_is_enabled(pwm)) {
174 dev_warn(chip->dev, "Removing PWM device without disabling\n");
175 pm_runtime_put_sync(chip->dev);
176 }
177}
178
179static const struct pwm_ops ecap_pwm_ops = {
180 .free = ecap_pwm_free,
181 .config = ecap_pwm_config,
182 .set_polarity = ecap_pwm_set_polarity,
183 .enable = ecap_pwm_enable,
184 .disable = ecap_pwm_disable,
185 .owner = THIS_MODULE,
186};
187
188static const struct of_device_id ecap_of_match[] = {
189 { .compatible = "ti,am3352-ecap" },
190 { .compatible = "ti,am33xx-ecap" },
191 {},
192};
193MODULE_DEVICE_TABLE(of, ecap_of_match);
194
195static int ecap_pwm_probe(struct platform_device *pdev)
196{
197 struct device_node *np = pdev->dev.of_node;
198 struct ecap_pwm_chip *pc;
199 struct resource *r;
200 struct clk *clk;
201 int ret;
202
203 pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
204 if (!pc)
205 return -ENOMEM;
206
207 clk = devm_clk_get(&pdev->dev, "fck");
208 if (IS_ERR(clk)) {
209 if (of_device_is_compatible(np, "ti,am33xx-ecap")) {
210 dev_warn(&pdev->dev, "Binding is obsolete.\n");
211 clk = devm_clk_get(pdev->dev.parent, "fck");
212 }
213 }
214
215 if (IS_ERR(clk)) {
216 dev_err(&pdev->dev, "failed to get clock\n");
217 return PTR_ERR(clk);
218 }
219
220 pc->clk_rate = clk_get_rate(clk);
221 if (!pc->clk_rate) {
222 dev_err(&pdev->dev, "failed to get clock rate\n");
223 return -EINVAL;
224 }
225
226 pc->chip.dev = &pdev->dev;
227 pc->chip.ops = &ecap_pwm_ops;
228 pc->chip.of_xlate = of_pwm_xlate_with_flags;
229 pc->chip.of_pwm_n_cells = 3;
230 pc->chip.base = -1;
231 pc->chip.npwm = 1;
232
233 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
234 pc->mmio_base = devm_ioremap_resource(&pdev->dev, r);
235 if (IS_ERR(pc->mmio_base))
236 return PTR_ERR(pc->mmio_base);
237
238 ret = pwmchip_add(&pc->chip);
239 if (ret < 0) {
240 dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
241 return ret;
242 }
243
244 platform_set_drvdata(pdev, pc);
245 pm_runtime_enable(&pdev->dev);
246
247 return 0;
248}
249
250static int ecap_pwm_remove(struct platform_device *pdev)
251{
252 struct ecap_pwm_chip *pc = platform_get_drvdata(pdev);
253
254 pm_runtime_disable(&pdev->dev);
255
256 return pwmchip_remove(&pc->chip);
257}
258
259#ifdef CONFIG_PM_SLEEP
260static void ecap_pwm_save_context(struct ecap_pwm_chip *pc)
261{
262 pm_runtime_get_sync(pc->chip.dev);
263 pc->ctx.ecctl2 = readw(pc->mmio_base + ECCTL2);
264 pc->ctx.cap4 = readl(pc->mmio_base + CAP4);
265 pc->ctx.cap3 = readl(pc->mmio_base + CAP3);
266 pm_runtime_put_sync(pc->chip.dev);
267}
268
269static void ecap_pwm_restore_context(struct ecap_pwm_chip *pc)
270{
271 writel(pc->ctx.cap3, pc->mmio_base + CAP3);
272 writel(pc->ctx.cap4, pc->mmio_base + CAP4);
273 writew(pc->ctx.ecctl2, pc->mmio_base + ECCTL2);
274}
275
276static int ecap_pwm_suspend(struct device *dev)
277{
278 struct ecap_pwm_chip *pc = dev_get_drvdata(dev);
279 struct pwm_device *pwm = pc->chip.pwms;
280
281 ecap_pwm_save_context(pc);
282
283 /* Disable explicitly if PWM is running */
284 if (pwm_is_enabled(pwm))
285 pm_runtime_put_sync(dev);
286
287 return 0;
288}
289
290static int ecap_pwm_resume(struct device *dev)
291{
292 struct ecap_pwm_chip *pc = dev_get_drvdata(dev);
293 struct pwm_device *pwm = pc->chip.pwms;
294
295 /* Enable explicitly if PWM was running */
296 if (pwm_is_enabled(pwm))
297 pm_runtime_get_sync(dev);
298
299 ecap_pwm_restore_context(pc);
300 return 0;
301}
302#endif
303
304static SIMPLE_DEV_PM_OPS(ecap_pwm_pm_ops, ecap_pwm_suspend, ecap_pwm_resume);
305
306static struct platform_driver ecap_pwm_driver = {
307 .driver = {
308 .name = "ecap",
309 .of_match_table = ecap_of_match,
310 .pm = &ecap_pwm_pm_ops,
311 },
312 .probe = ecap_pwm_probe,
313 .remove = ecap_pwm_remove,
314};
315module_platform_driver(ecap_pwm_driver);
316
317MODULE_DESCRIPTION("ECAP PWM driver");
318MODULE_AUTHOR("Texas Instruments");
319MODULE_LICENSE("GPL");
1/*
2 * ECAP PWM driver
3 *
4 * Copyright (C) 2012 Texas Instruments, Inc. - http://www.ti.com/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 */
20
21#include <linux/module.h>
22#include <linux/platform_device.h>
23#include <linux/io.h>
24#include <linux/err.h>
25#include <linux/clk.h>
26#include <linux/pm_runtime.h>
27#include <linux/pwm.h>
28#include <linux/of_device.h>
29
30/* ECAP registers and bits definitions */
31#define CAP1 0x08
32#define CAP2 0x0C
33#define CAP3 0x10
34#define CAP4 0x14
35#define ECCTL2 0x2A
36#define ECCTL2_APWM_POL_LOW BIT(10)
37#define ECCTL2_APWM_MODE BIT(9)
38#define ECCTL2_SYNC_SEL_DISA (BIT(7) | BIT(6))
39#define ECCTL2_TSCTR_FREERUN BIT(4)
40
41struct ecap_context {
42 u32 cap3;
43 u32 cap4;
44 u16 ecctl2;
45};
46
47struct ecap_pwm_chip {
48 struct pwm_chip chip;
49 unsigned int clk_rate;
50 void __iomem *mmio_base;
51 struct ecap_context ctx;
52};
53
54static inline struct ecap_pwm_chip *to_ecap_pwm_chip(struct pwm_chip *chip)
55{
56 return container_of(chip, struct ecap_pwm_chip, chip);
57}
58
59/*
60 * period_ns = 10^9 * period_cycles / PWM_CLK_RATE
61 * duty_ns = 10^9 * duty_cycles / PWM_CLK_RATE
62 */
63static int ecap_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
64 int duty_ns, int period_ns)
65{
66 struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);
67 unsigned long long c;
68 unsigned long period_cycles, duty_cycles;
69 unsigned int reg_val;
70
71 if (period_ns > NSEC_PER_SEC)
72 return -ERANGE;
73
74 c = pc->clk_rate;
75 c = c * period_ns;
76 do_div(c, NSEC_PER_SEC);
77 period_cycles = (unsigned long)c;
78
79 if (period_cycles < 1) {
80 period_cycles = 1;
81 duty_cycles = 1;
82 } else {
83 c = pc->clk_rate;
84 c = c * duty_ns;
85 do_div(c, NSEC_PER_SEC);
86 duty_cycles = (unsigned long)c;
87 }
88
89 pm_runtime_get_sync(pc->chip.dev);
90
91 reg_val = readw(pc->mmio_base + ECCTL2);
92
93 /* Configure APWM mode & disable sync option */
94 reg_val |= ECCTL2_APWM_MODE | ECCTL2_SYNC_SEL_DISA;
95
96 writew(reg_val, pc->mmio_base + ECCTL2);
97
98 if (!pwm_is_enabled(pwm)) {
99 /* Update active registers if not running */
100 writel(duty_cycles, pc->mmio_base + CAP2);
101 writel(period_cycles, pc->mmio_base + CAP1);
102 } else {
103 /*
104 * Update shadow registers to configure period and
105 * compare values. This helps current PWM period to
106 * complete on reconfiguring
107 */
108 writel(duty_cycles, pc->mmio_base + CAP4);
109 writel(period_cycles, pc->mmio_base + CAP3);
110 }
111
112 if (!pwm_is_enabled(pwm)) {
113 reg_val = readw(pc->mmio_base + ECCTL2);
114 /* Disable APWM mode to put APWM output Low */
115 reg_val &= ~ECCTL2_APWM_MODE;
116 writew(reg_val, pc->mmio_base + ECCTL2);
117 }
118
119 pm_runtime_put_sync(pc->chip.dev);
120 return 0;
121}
122
123static int ecap_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm,
124 enum pwm_polarity polarity)
125{
126 struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);
127 unsigned short reg_val;
128
129 pm_runtime_get_sync(pc->chip.dev);
130 reg_val = readw(pc->mmio_base + ECCTL2);
131 if (polarity == PWM_POLARITY_INVERSED)
132 /* Duty cycle defines LOW period of PWM */
133 reg_val |= ECCTL2_APWM_POL_LOW;
134 else
135 /* Duty cycle defines HIGH period of PWM */
136 reg_val &= ~ECCTL2_APWM_POL_LOW;
137
138 writew(reg_val, pc->mmio_base + ECCTL2);
139 pm_runtime_put_sync(pc->chip.dev);
140 return 0;
141}
142
143static int ecap_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
144{
145 struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);
146 unsigned int reg_val;
147
148 /* Leave clock enabled on enabling PWM */
149 pm_runtime_get_sync(pc->chip.dev);
150
151 /*
152 * Enable 'Free run Time stamp counter mode' to start counter
153 * and 'APWM mode' to enable APWM output
154 */
155 reg_val = readw(pc->mmio_base + ECCTL2);
156 reg_val |= ECCTL2_TSCTR_FREERUN | ECCTL2_APWM_MODE;
157 writew(reg_val, pc->mmio_base + ECCTL2);
158 return 0;
159}
160
161static void ecap_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
162{
163 struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);
164 unsigned int reg_val;
165
166 /*
167 * Disable 'Free run Time stamp counter mode' to stop counter
168 * and 'APWM mode' to put APWM output to low
169 */
170 reg_val = readw(pc->mmio_base + ECCTL2);
171 reg_val &= ~(ECCTL2_TSCTR_FREERUN | ECCTL2_APWM_MODE);
172 writew(reg_val, pc->mmio_base + ECCTL2);
173
174 /* Disable clock on PWM disable */
175 pm_runtime_put_sync(pc->chip.dev);
176}
177
178static void ecap_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
179{
180 if (pwm_is_enabled(pwm)) {
181 dev_warn(chip->dev, "Removing PWM device without disabling\n");
182 pm_runtime_put_sync(chip->dev);
183 }
184}
185
186static const struct pwm_ops ecap_pwm_ops = {
187 .free = ecap_pwm_free,
188 .config = ecap_pwm_config,
189 .set_polarity = ecap_pwm_set_polarity,
190 .enable = ecap_pwm_enable,
191 .disable = ecap_pwm_disable,
192 .owner = THIS_MODULE,
193};
194
195static const struct of_device_id ecap_of_match[] = {
196 { .compatible = "ti,am3352-ecap" },
197 { .compatible = "ti,am33xx-ecap" },
198 {},
199};
200MODULE_DEVICE_TABLE(of, ecap_of_match);
201
202static int ecap_pwm_probe(struct platform_device *pdev)
203{
204 struct device_node *np = pdev->dev.of_node;
205 int ret;
206 struct resource *r;
207 struct clk *clk;
208 struct ecap_pwm_chip *pc;
209
210 pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
211 if (!pc)
212 return -ENOMEM;
213
214 clk = devm_clk_get(&pdev->dev, "fck");
215 if (IS_ERR(clk)) {
216 if (of_device_is_compatible(np, "ti,am33xx-ecap")) {
217 dev_warn(&pdev->dev, "Binding is obsolete.\n");
218 clk = devm_clk_get(pdev->dev.parent, "fck");
219 }
220 }
221
222 if (IS_ERR(clk)) {
223 dev_err(&pdev->dev, "failed to get clock\n");
224 return PTR_ERR(clk);
225 }
226
227 pc->clk_rate = clk_get_rate(clk);
228 if (!pc->clk_rate) {
229 dev_err(&pdev->dev, "failed to get clock rate\n");
230 return -EINVAL;
231 }
232
233 pc->chip.dev = &pdev->dev;
234 pc->chip.ops = &ecap_pwm_ops;
235 pc->chip.of_xlate = of_pwm_xlate_with_flags;
236 pc->chip.of_pwm_n_cells = 3;
237 pc->chip.base = -1;
238 pc->chip.npwm = 1;
239
240 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
241 pc->mmio_base = devm_ioremap_resource(&pdev->dev, r);
242 if (IS_ERR(pc->mmio_base))
243 return PTR_ERR(pc->mmio_base);
244
245 ret = pwmchip_add(&pc->chip);
246 if (ret < 0) {
247 dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
248 return ret;
249 }
250
251 pm_runtime_enable(&pdev->dev);
252
253 platform_set_drvdata(pdev, pc);
254 return 0;
255}
256
257static int ecap_pwm_remove(struct platform_device *pdev)
258{
259 struct ecap_pwm_chip *pc = platform_get_drvdata(pdev);
260
261 pm_runtime_disable(&pdev->dev);
262 return pwmchip_remove(&pc->chip);
263}
264
265#ifdef CONFIG_PM_SLEEP
266static void ecap_pwm_save_context(struct ecap_pwm_chip *pc)
267{
268 pm_runtime_get_sync(pc->chip.dev);
269 pc->ctx.ecctl2 = readw(pc->mmio_base + ECCTL2);
270 pc->ctx.cap4 = readl(pc->mmio_base + CAP4);
271 pc->ctx.cap3 = readl(pc->mmio_base + CAP3);
272 pm_runtime_put_sync(pc->chip.dev);
273}
274
275static void ecap_pwm_restore_context(struct ecap_pwm_chip *pc)
276{
277 writel(pc->ctx.cap3, pc->mmio_base + CAP3);
278 writel(pc->ctx.cap4, pc->mmio_base + CAP4);
279 writew(pc->ctx.ecctl2, pc->mmio_base + ECCTL2);
280}
281
282static int ecap_pwm_suspend(struct device *dev)
283{
284 struct ecap_pwm_chip *pc = dev_get_drvdata(dev);
285 struct pwm_device *pwm = pc->chip.pwms;
286
287 ecap_pwm_save_context(pc);
288
289 /* Disable explicitly if PWM is running */
290 if (pwm_is_enabled(pwm))
291 pm_runtime_put_sync(dev);
292
293 return 0;
294}
295
296static int ecap_pwm_resume(struct device *dev)
297{
298 struct ecap_pwm_chip *pc = dev_get_drvdata(dev);
299 struct pwm_device *pwm = pc->chip.pwms;
300
301 /* Enable explicitly if PWM was running */
302 if (pwm_is_enabled(pwm))
303 pm_runtime_get_sync(dev);
304
305 ecap_pwm_restore_context(pc);
306 return 0;
307}
308#endif
309
310static SIMPLE_DEV_PM_OPS(ecap_pwm_pm_ops, ecap_pwm_suspend, ecap_pwm_resume);
311
312static struct platform_driver ecap_pwm_driver = {
313 .driver = {
314 .name = "ecap",
315 .of_match_table = ecap_of_match,
316 .pm = &ecap_pwm_pm_ops,
317 },
318 .probe = ecap_pwm_probe,
319 .remove = ecap_pwm_remove,
320};
321
322module_platform_driver(ecap_pwm_driver);
323
324MODULE_DESCRIPTION("ECAP PWM driver");
325MODULE_AUTHOR("Texas Instruments");
326MODULE_LICENSE("GPL");