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1/* SPDX-License-Identifier: GPL-2.0 */
2/* Copyright (c) 2018, Intel Corporation. */
3
4#ifndef _ICE_ADMINQ_CMD_H_
5#define _ICE_ADMINQ_CMD_H_
6
7/* This header file defines the Admin Queue commands, error codes and
8 * descriptor format. It is shared between Firmware and Software.
9 */
10
11#define ICE_MAX_VSI 768
12#define ICE_AQC_TOPO_MAX_LEVEL_NUM 0x9
13#define ICE_AQ_SET_MAC_FRAME_SIZE_MAX 9728
14
15struct ice_aqc_generic {
16 __le32 param0;
17 __le32 param1;
18 __le32 addr_high;
19 __le32 addr_low;
20};
21
22/* Get version (direct 0x0001) */
23struct ice_aqc_get_ver {
24 __le32 rom_ver;
25 __le32 fw_build;
26 u8 fw_branch;
27 u8 fw_major;
28 u8 fw_minor;
29 u8 fw_patch;
30 u8 api_branch;
31 u8 api_major;
32 u8 api_minor;
33 u8 api_patch;
34};
35
36/* Send driver version (indirect 0x0002) */
37struct ice_aqc_driver_ver {
38 u8 major_ver;
39 u8 minor_ver;
40 u8 build_ver;
41 u8 subbuild_ver;
42 u8 reserved[4];
43 __le32 addr_high;
44 __le32 addr_low;
45};
46
47/* Queue Shutdown (direct 0x0003) */
48struct ice_aqc_q_shutdown {
49 u8 driver_unloading;
50#define ICE_AQC_DRIVER_UNLOADING BIT(0)
51 u8 reserved[15];
52};
53
54/* Request resource ownership (direct 0x0008)
55 * Release resource ownership (direct 0x0009)
56 */
57struct ice_aqc_req_res {
58 __le16 res_id;
59#define ICE_AQC_RES_ID_NVM 1
60#define ICE_AQC_RES_ID_SDP 2
61#define ICE_AQC_RES_ID_CHNG_LOCK 3
62#define ICE_AQC_RES_ID_GLBL_LOCK 4
63 __le16 access_type;
64#define ICE_AQC_RES_ACCESS_READ 1
65#define ICE_AQC_RES_ACCESS_WRITE 2
66
67 /* Upon successful completion, FW writes this value and driver is
68 * expected to release resource before timeout. This value is provided
69 * in milliseconds.
70 */
71 __le32 timeout;
72#define ICE_AQ_RES_NVM_READ_DFLT_TIMEOUT_MS 3000
73#define ICE_AQ_RES_NVM_WRITE_DFLT_TIMEOUT_MS 180000
74#define ICE_AQ_RES_CHNG_LOCK_DFLT_TIMEOUT_MS 1000
75#define ICE_AQ_RES_GLBL_LOCK_DFLT_TIMEOUT_MS 3000
76 /* For SDP: pin ID of the SDP */
77 __le32 res_number;
78 /* Status is only used for ICE_AQC_RES_ID_GLBL_LOCK */
79 __le16 status;
80#define ICE_AQ_RES_GLBL_SUCCESS 0
81#define ICE_AQ_RES_GLBL_IN_PROG 1
82#define ICE_AQ_RES_GLBL_DONE 2
83 u8 reserved[2];
84};
85
86/* Get function capabilities (indirect 0x000A)
87 * Get device capabilities (indirect 0x000B)
88 */
89struct ice_aqc_list_caps {
90 u8 cmd_flags;
91 u8 pf_index;
92 u8 reserved[2];
93 __le32 count;
94 __le32 addr_high;
95 __le32 addr_low;
96};
97
98/* Device/Function buffer entry, repeated per reported capability */
99struct ice_aqc_list_caps_elem {
100 __le16 cap;
101#define ICE_AQC_CAPS_VALID_FUNCTIONS 0x0005
102#define ICE_AQC_CAPS_SRIOV 0x0012
103#define ICE_AQC_CAPS_VF 0x0013
104#define ICE_AQC_CAPS_VSI 0x0017
105#define ICE_AQC_CAPS_DCB 0x0018
106#define ICE_AQC_CAPS_RSS 0x0040
107#define ICE_AQC_CAPS_RXQS 0x0041
108#define ICE_AQC_CAPS_TXQS 0x0042
109#define ICE_AQC_CAPS_MSIX 0x0043
110#define ICE_AQC_CAPS_FD 0x0045
111#define ICE_AQC_CAPS_MAX_MTU 0x0047
112#define ICE_AQC_CAPS_NVM_VER 0x0048
113#define ICE_AQC_CAPS_PENDING_NVM_VER 0x0049
114#define ICE_AQC_CAPS_OROM_VER 0x004A
115#define ICE_AQC_CAPS_PENDING_OROM_VER 0x004B
116#define ICE_AQC_CAPS_NET_VER 0x004C
117#define ICE_AQC_CAPS_PENDING_NET_VER 0x004D
118#define ICE_AQC_CAPS_NVM_MGMT 0x0080
119
120 u8 major_ver;
121 u8 minor_ver;
122 /* Number of resources described by this capability */
123 __le32 number;
124 /* Only meaningful for some types of resources */
125 __le32 logical_id;
126 /* Only meaningful for some types of resources */
127 __le32 phys_id;
128 __le64 rsvd1;
129 __le64 rsvd2;
130};
131
132/* Manage MAC address, read command - indirect (0x0107)
133 * This struct is also used for the response
134 */
135struct ice_aqc_manage_mac_read {
136 __le16 flags; /* Zeroed by device driver */
137#define ICE_AQC_MAN_MAC_LAN_ADDR_VALID BIT(4)
138#define ICE_AQC_MAN_MAC_SAN_ADDR_VALID BIT(5)
139#define ICE_AQC_MAN_MAC_PORT_ADDR_VALID BIT(6)
140#define ICE_AQC_MAN_MAC_WOL_ADDR_VALID BIT(7)
141#define ICE_AQC_MAN_MAC_READ_S 4
142#define ICE_AQC_MAN_MAC_READ_M (0xF << ICE_AQC_MAN_MAC_READ_S)
143 u8 rsvd[2];
144 u8 num_addr; /* Used in response */
145 u8 rsvd1[3];
146 __le32 addr_high;
147 __le32 addr_low;
148};
149
150/* Response buffer format for manage MAC read command */
151struct ice_aqc_manage_mac_read_resp {
152 u8 lport_num;
153 u8 addr_type;
154#define ICE_AQC_MAN_MAC_ADDR_TYPE_LAN 0
155#define ICE_AQC_MAN_MAC_ADDR_TYPE_WOL 1
156 u8 mac_addr[ETH_ALEN];
157};
158
159/* Manage MAC address, write command - direct (0x0108) */
160struct ice_aqc_manage_mac_write {
161 u8 rsvd;
162 u8 flags;
163#define ICE_AQC_MAN_MAC_WR_MC_MAG_EN BIT(0)
164#define ICE_AQC_MAN_MAC_WR_WOL_LAA_PFR_KEEP BIT(1)
165#define ICE_AQC_MAN_MAC_WR_S 6
166#define ICE_AQC_MAN_MAC_WR_M ICE_M(3, ICE_AQC_MAN_MAC_WR_S)
167#define ICE_AQC_MAN_MAC_UPDATE_LAA 0
168#define ICE_AQC_MAN_MAC_UPDATE_LAA_WOL BIT(ICE_AQC_MAN_MAC_WR_S)
169 /* byte stream in network order */
170 u8 mac_addr[ETH_ALEN];
171 __le32 addr_high;
172 __le32 addr_low;
173};
174
175/* Clear PXE Command and response (direct 0x0110) */
176struct ice_aqc_clear_pxe {
177 u8 rx_cnt;
178#define ICE_AQC_CLEAR_PXE_RX_CNT 0x2
179 u8 reserved[15];
180};
181
182/* Get switch configuration (0x0200) */
183struct ice_aqc_get_sw_cfg {
184 /* Reserved for command and copy of request flags for response */
185 __le16 flags;
186 /* First desc in case of command and next_elem in case of response
187 * In case of response, if it is not zero, means all the configuration
188 * was not returned and new command shall be sent with this value in
189 * the 'first desc' field
190 */
191 __le16 element;
192 /* Reserved for command, only used for response */
193 __le16 num_elems;
194 __le16 rsvd;
195 __le32 addr_high;
196 __le32 addr_low;
197};
198
199/* Each entry in the response buffer is of the following type: */
200struct ice_aqc_get_sw_cfg_resp_elem {
201 /* VSI/Port Number */
202 __le16 vsi_port_num;
203#define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S 0
204#define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_M \
205 (0x3FF << ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S)
206#define ICE_AQC_GET_SW_CONF_RESP_TYPE_S 14
207#define ICE_AQC_GET_SW_CONF_RESP_TYPE_M (0x3 << ICE_AQC_GET_SW_CONF_RESP_TYPE_S)
208#define ICE_AQC_GET_SW_CONF_RESP_PHYS_PORT 0
209#define ICE_AQC_GET_SW_CONF_RESP_VIRT_PORT 1
210#define ICE_AQC_GET_SW_CONF_RESP_VSI 2
211
212 /* SWID VSI/Port belongs to */
213 __le16 swid;
214
215 /* Bit 14..0 : PF/VF number VSI belongs to
216 * Bit 15 : VF indication bit
217 */
218 __le16 pf_vf_num;
219#define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S 0
220#define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_M \
221 (0x7FFF << ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S)
222#define ICE_AQC_GET_SW_CONF_RESP_IS_VF BIT(15)
223};
224
225/* These resource type defines are used for all switch resource
226 * commands where a resource type is required, such as:
227 * Get Resource Allocation command (indirect 0x0204)
228 * Allocate Resources command (indirect 0x0208)
229 * Free Resources command (indirect 0x0209)
230 * Get Allocated Resource Descriptors Command (indirect 0x020A)
231 */
232#define ICE_AQC_RES_TYPE_VSI_LIST_REP 0x03
233#define ICE_AQC_RES_TYPE_VSI_LIST_PRUNE 0x04
234#define ICE_AQC_RES_TYPE_FDIR_COUNTER_BLOCK 0x21
235#define ICE_AQC_RES_TYPE_FDIR_GUARANTEED_ENTRIES 0x22
236#define ICE_AQC_RES_TYPE_FDIR_SHARED_ENTRIES 0x23
237#define ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID 0x58
238#define ICE_AQC_RES_TYPE_FD_PROF_BLDR_TCAM 0x59
239#define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID 0x60
240#define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_TCAM 0x61
241
242#define ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM BIT(12)
243#define ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX BIT(13)
244
245#define ICE_AQC_RES_TYPE_FLAG_DEDICATED 0x00
246
247#define ICE_AQC_RES_TYPE_S 0
248#define ICE_AQC_RES_TYPE_M (0x07F << ICE_AQC_RES_TYPE_S)
249
250/* Allocate Resources command (indirect 0x0208)
251 * Free Resources command (indirect 0x0209)
252 */
253struct ice_aqc_alloc_free_res_cmd {
254 __le16 num_entries; /* Number of Resource entries */
255 u8 reserved[6];
256 __le32 addr_high;
257 __le32 addr_low;
258};
259
260/* Resource descriptor */
261struct ice_aqc_res_elem {
262 union {
263 __le16 sw_resp;
264 __le16 flu_resp;
265 } e;
266};
267
268/* Buffer for Allocate/Free Resources commands */
269struct ice_aqc_alloc_free_res_elem {
270 __le16 res_type; /* Types defined above cmd 0x0204 */
271#define ICE_AQC_RES_TYPE_SHARED_S 7
272#define ICE_AQC_RES_TYPE_SHARED_M (0x1 << ICE_AQC_RES_TYPE_SHARED_S)
273#define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S 8
274#define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_M \
275 (0xF << ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S)
276 __le16 num_elems;
277 struct ice_aqc_res_elem elem[];
278};
279
280/* Add VSI (indirect 0x0210)
281 * Update VSI (indirect 0x0211)
282 * Get VSI (indirect 0x0212)
283 * Free VSI (indirect 0x0213)
284 */
285struct ice_aqc_add_get_update_free_vsi {
286 __le16 vsi_num;
287#define ICE_AQ_VSI_NUM_S 0
288#define ICE_AQ_VSI_NUM_M (0x03FF << ICE_AQ_VSI_NUM_S)
289#define ICE_AQ_VSI_IS_VALID BIT(15)
290 __le16 cmd_flags;
291#define ICE_AQ_VSI_KEEP_ALLOC 0x1
292 u8 vf_id;
293 u8 reserved;
294 __le16 vsi_flags;
295#define ICE_AQ_VSI_TYPE_S 0
296#define ICE_AQ_VSI_TYPE_M (0x3 << ICE_AQ_VSI_TYPE_S)
297#define ICE_AQ_VSI_TYPE_VF 0x0
298#define ICE_AQ_VSI_TYPE_VMDQ2 0x1
299#define ICE_AQ_VSI_TYPE_PF 0x2
300#define ICE_AQ_VSI_TYPE_EMP_MNG 0x3
301 __le32 addr_high;
302 __le32 addr_low;
303};
304
305/* Response descriptor for:
306 * Add VSI (indirect 0x0210)
307 * Update VSI (indirect 0x0211)
308 * Free VSI (indirect 0x0213)
309 */
310struct ice_aqc_add_update_free_vsi_resp {
311 __le16 vsi_num;
312 __le16 ext_status;
313 __le16 vsi_used;
314 __le16 vsi_free;
315 __le32 addr_high;
316 __le32 addr_low;
317};
318
319struct ice_aqc_vsi_props {
320 __le16 valid_sections;
321#define ICE_AQ_VSI_PROP_SW_VALID BIT(0)
322#define ICE_AQ_VSI_PROP_SECURITY_VALID BIT(1)
323#define ICE_AQ_VSI_PROP_VLAN_VALID BIT(2)
324#define ICE_AQ_VSI_PROP_OUTER_TAG_VALID BIT(3)
325#define ICE_AQ_VSI_PROP_INGRESS_UP_VALID BIT(4)
326#define ICE_AQ_VSI_PROP_EGRESS_UP_VALID BIT(5)
327#define ICE_AQ_VSI_PROP_RXQ_MAP_VALID BIT(6)
328#define ICE_AQ_VSI_PROP_Q_OPT_VALID BIT(7)
329#define ICE_AQ_VSI_PROP_OUTER_UP_VALID BIT(8)
330#define ICE_AQ_VSI_PROP_FLOW_DIR_VALID BIT(11)
331#define ICE_AQ_VSI_PROP_PASID_VALID BIT(12)
332 /* switch section */
333 u8 sw_id;
334 u8 sw_flags;
335#define ICE_AQ_VSI_SW_FLAG_ALLOW_LB BIT(5)
336#define ICE_AQ_VSI_SW_FLAG_LOCAL_LB BIT(6)
337#define ICE_AQ_VSI_SW_FLAG_SRC_PRUNE BIT(7)
338 u8 sw_flags2;
339#define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S 0
340#define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_M \
341 (0xF << ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S)
342#define ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA BIT(0)
343#define ICE_AQ_VSI_SW_FLAG_LAN_ENA BIT(4)
344 u8 veb_stat_id;
345#define ICE_AQ_VSI_SW_VEB_STAT_ID_S 0
346#define ICE_AQ_VSI_SW_VEB_STAT_ID_M (0x1F << ICE_AQ_VSI_SW_VEB_STAT_ID_S)
347#define ICE_AQ_VSI_SW_VEB_STAT_ID_VALID BIT(5)
348 /* security section */
349 u8 sec_flags;
350#define ICE_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD BIT(0)
351#define ICE_AQ_VSI_SEC_FLAG_ENA_MAC_ANTI_SPOOF BIT(2)
352#define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S 4
353#define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_M (0xF << ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S)
354#define ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA BIT(0)
355 u8 sec_reserved;
356 /* VLAN section */
357 __le16 pvid; /* VLANS include priority bits */
358 u8 pvlan_reserved[2];
359 u8 vlan_flags;
360#define ICE_AQ_VSI_VLAN_MODE_S 0
361#define ICE_AQ_VSI_VLAN_MODE_M (0x3 << ICE_AQ_VSI_VLAN_MODE_S)
362#define ICE_AQ_VSI_VLAN_MODE_UNTAGGED 0x1
363#define ICE_AQ_VSI_VLAN_MODE_TAGGED 0x2
364#define ICE_AQ_VSI_VLAN_MODE_ALL 0x3
365#define ICE_AQ_VSI_PVLAN_INSERT_PVID BIT(2)
366#define ICE_AQ_VSI_VLAN_EMOD_S 3
367#define ICE_AQ_VSI_VLAN_EMOD_M (0x3 << ICE_AQ_VSI_VLAN_EMOD_S)
368#define ICE_AQ_VSI_VLAN_EMOD_STR_BOTH (0x0 << ICE_AQ_VSI_VLAN_EMOD_S)
369#define ICE_AQ_VSI_VLAN_EMOD_STR_UP (0x1 << ICE_AQ_VSI_VLAN_EMOD_S)
370#define ICE_AQ_VSI_VLAN_EMOD_STR (0x2 << ICE_AQ_VSI_VLAN_EMOD_S)
371#define ICE_AQ_VSI_VLAN_EMOD_NOTHING (0x3 << ICE_AQ_VSI_VLAN_EMOD_S)
372 u8 pvlan_reserved2[3];
373 /* ingress egress up sections */
374 __le32 ingress_table; /* bitmap, 3 bits per up */
375#define ICE_AQ_VSI_UP_TABLE_UP0_S 0
376#define ICE_AQ_VSI_UP_TABLE_UP0_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP0_S)
377#define ICE_AQ_VSI_UP_TABLE_UP1_S 3
378#define ICE_AQ_VSI_UP_TABLE_UP1_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP1_S)
379#define ICE_AQ_VSI_UP_TABLE_UP2_S 6
380#define ICE_AQ_VSI_UP_TABLE_UP2_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP2_S)
381#define ICE_AQ_VSI_UP_TABLE_UP3_S 9
382#define ICE_AQ_VSI_UP_TABLE_UP3_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP3_S)
383#define ICE_AQ_VSI_UP_TABLE_UP4_S 12
384#define ICE_AQ_VSI_UP_TABLE_UP4_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP4_S)
385#define ICE_AQ_VSI_UP_TABLE_UP5_S 15
386#define ICE_AQ_VSI_UP_TABLE_UP5_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP5_S)
387#define ICE_AQ_VSI_UP_TABLE_UP6_S 18
388#define ICE_AQ_VSI_UP_TABLE_UP6_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP6_S)
389#define ICE_AQ_VSI_UP_TABLE_UP7_S 21
390#define ICE_AQ_VSI_UP_TABLE_UP7_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP7_S)
391 __le32 egress_table; /* same defines as for ingress table */
392 /* outer tags section */
393 __le16 outer_tag;
394 u8 outer_tag_flags;
395#define ICE_AQ_VSI_OUTER_TAG_MODE_S 0
396#define ICE_AQ_VSI_OUTER_TAG_MODE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_MODE_S)
397#define ICE_AQ_VSI_OUTER_TAG_NOTHING 0x0
398#define ICE_AQ_VSI_OUTER_TAG_REMOVE 0x1
399#define ICE_AQ_VSI_OUTER_TAG_COPY 0x2
400#define ICE_AQ_VSI_OUTER_TAG_TYPE_S 2
401#define ICE_AQ_VSI_OUTER_TAG_TYPE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_TYPE_S)
402#define ICE_AQ_VSI_OUTER_TAG_NONE 0x0
403#define ICE_AQ_VSI_OUTER_TAG_STAG 0x1
404#define ICE_AQ_VSI_OUTER_TAG_VLAN_8100 0x2
405#define ICE_AQ_VSI_OUTER_TAG_VLAN_9100 0x3
406#define ICE_AQ_VSI_OUTER_TAG_INSERT BIT(4)
407#define ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST BIT(6)
408 u8 outer_tag_reserved;
409 /* queue mapping section */
410 __le16 mapping_flags;
411#define ICE_AQ_VSI_Q_MAP_CONTIG 0x0
412#define ICE_AQ_VSI_Q_MAP_NONCONTIG BIT(0)
413 __le16 q_mapping[16];
414#define ICE_AQ_VSI_Q_S 0
415#define ICE_AQ_VSI_Q_M (0x7FF << ICE_AQ_VSI_Q_S)
416 __le16 tc_mapping[8];
417#define ICE_AQ_VSI_TC_Q_OFFSET_S 0
418#define ICE_AQ_VSI_TC_Q_OFFSET_M (0x7FF << ICE_AQ_VSI_TC_Q_OFFSET_S)
419#define ICE_AQ_VSI_TC_Q_NUM_S 11
420#define ICE_AQ_VSI_TC_Q_NUM_M (0xF << ICE_AQ_VSI_TC_Q_NUM_S)
421 /* queueing option section */
422 u8 q_opt_rss;
423#define ICE_AQ_VSI_Q_OPT_RSS_LUT_S 0
424#define ICE_AQ_VSI_Q_OPT_RSS_LUT_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_LUT_S)
425#define ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI 0x0
426#define ICE_AQ_VSI_Q_OPT_RSS_LUT_PF 0x2
427#define ICE_AQ_VSI_Q_OPT_RSS_LUT_GBL 0x3
428#define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S 2
429#define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_M (0xF << ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S)
430#define ICE_AQ_VSI_Q_OPT_RSS_HASH_S 6
431#define ICE_AQ_VSI_Q_OPT_RSS_HASH_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
432#define ICE_AQ_VSI_Q_OPT_RSS_TPLZ (0x0 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
433#define ICE_AQ_VSI_Q_OPT_RSS_SYM_TPLZ (0x1 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
434#define ICE_AQ_VSI_Q_OPT_RSS_XOR (0x2 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
435#define ICE_AQ_VSI_Q_OPT_RSS_JHASH (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
436 u8 q_opt_tc;
437#define ICE_AQ_VSI_Q_OPT_TC_OVR_S 0
438#define ICE_AQ_VSI_Q_OPT_TC_OVR_M (0x1F << ICE_AQ_VSI_Q_OPT_TC_OVR_S)
439#define ICE_AQ_VSI_Q_OPT_PROF_TC_OVR BIT(7)
440 u8 q_opt_flags;
441#define ICE_AQ_VSI_Q_OPT_PE_FLTR_EN BIT(0)
442 u8 q_opt_reserved[3];
443 /* outer up section */
444 __le32 outer_up_table; /* same structure and defines as ingress tbl */
445 /* section 10 */
446 __le16 sect_10_reserved;
447 /* flow director section */
448 __le16 fd_options;
449#define ICE_AQ_VSI_FD_ENABLE BIT(0)
450#define ICE_AQ_VSI_FD_TX_AUTO_ENABLE BIT(1)
451#define ICE_AQ_VSI_FD_PROG_ENABLE BIT(3)
452 __le16 max_fd_fltr_dedicated;
453 __le16 max_fd_fltr_shared;
454 __le16 fd_def_q;
455#define ICE_AQ_VSI_FD_DEF_Q_S 0
456#define ICE_AQ_VSI_FD_DEF_Q_M (0x7FF << ICE_AQ_VSI_FD_DEF_Q_S)
457#define ICE_AQ_VSI_FD_DEF_GRP_S 12
458#define ICE_AQ_VSI_FD_DEF_GRP_M (0x7 << ICE_AQ_VSI_FD_DEF_GRP_S)
459 __le16 fd_report_opt;
460#define ICE_AQ_VSI_FD_REPORT_Q_S 0
461#define ICE_AQ_VSI_FD_REPORT_Q_M (0x7FF << ICE_AQ_VSI_FD_REPORT_Q_S)
462#define ICE_AQ_VSI_FD_DEF_PRIORITY_S 12
463#define ICE_AQ_VSI_FD_DEF_PRIORITY_M (0x7 << ICE_AQ_VSI_FD_DEF_PRIORITY_S)
464#define ICE_AQ_VSI_FD_DEF_DROP BIT(15)
465 /* PASID section */
466 __le32 pasid_id;
467#define ICE_AQ_VSI_PASID_ID_S 0
468#define ICE_AQ_VSI_PASID_ID_M (0xFFFFF << ICE_AQ_VSI_PASID_ID_S)
469#define ICE_AQ_VSI_PASID_ID_VALID BIT(31)
470 u8 reserved[24];
471};
472
473#define ICE_MAX_NUM_RECIPES 64
474
475/* Add/Update/Remove/Get switch rules (indirect 0x02A0, 0x02A1, 0x02A2, 0x02A3)
476 */
477struct ice_aqc_sw_rules {
478 /* ops: add switch rules, referring the number of rules.
479 * ops: update switch rules, referring the number of filters
480 * ops: remove switch rules, referring the entry index.
481 * ops: get switch rules, referring to the number of filters.
482 */
483 __le16 num_rules_fltr_entry_index;
484 u8 reserved[6];
485 __le32 addr_high;
486 __le32 addr_low;
487};
488
489/* Add/Update/Get/Remove lookup Rx/Tx command/response entry
490 * This structures describes the lookup rules and associated actions. "index"
491 * is returned as part of a response to a successful Add command, and can be
492 * used to identify the rule for Update/Get/Remove commands.
493 */
494struct ice_sw_rule_lkup_rx_tx {
495 __le16 recipe_id;
496#define ICE_SW_RECIPE_LOGICAL_PORT_FWD 10
497 /* Source port for LOOKUP_RX and source VSI in case of LOOKUP_TX */
498 __le16 src;
499 __le32 act;
500
501 /* Bit 0:1 - Action type */
502#define ICE_SINGLE_ACT_TYPE_S 0x00
503#define ICE_SINGLE_ACT_TYPE_M (0x3 << ICE_SINGLE_ACT_TYPE_S)
504
505 /* Bit 2 - Loop back enable
506 * Bit 3 - LAN enable
507 */
508#define ICE_SINGLE_ACT_LB_ENABLE BIT(2)
509#define ICE_SINGLE_ACT_LAN_ENABLE BIT(3)
510
511 /* Action type = 0 - Forward to VSI or VSI list */
512#define ICE_SINGLE_ACT_VSI_FORWARDING 0x0
513
514#define ICE_SINGLE_ACT_VSI_ID_S 4
515#define ICE_SINGLE_ACT_VSI_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_ID_S)
516#define ICE_SINGLE_ACT_VSI_LIST_ID_S 4
517#define ICE_SINGLE_ACT_VSI_LIST_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_LIST_ID_S)
518 /* This bit needs to be set if action is forward to VSI list */
519#define ICE_SINGLE_ACT_VSI_LIST BIT(14)
520#define ICE_SINGLE_ACT_VALID_BIT BIT(17)
521#define ICE_SINGLE_ACT_DROP BIT(18)
522
523 /* Action type = 1 - Forward to Queue of Queue group */
524#define ICE_SINGLE_ACT_TO_Q 0x1
525#define ICE_SINGLE_ACT_Q_INDEX_S 4
526#define ICE_SINGLE_ACT_Q_INDEX_M (0x7FF << ICE_SINGLE_ACT_Q_INDEX_S)
527#define ICE_SINGLE_ACT_Q_REGION_S 15
528#define ICE_SINGLE_ACT_Q_REGION_M (0x7 << ICE_SINGLE_ACT_Q_REGION_S)
529#define ICE_SINGLE_ACT_Q_PRIORITY BIT(18)
530
531 /* Action type = 2 - Prune */
532#define ICE_SINGLE_ACT_PRUNE 0x2
533#define ICE_SINGLE_ACT_EGRESS BIT(15)
534#define ICE_SINGLE_ACT_INGRESS BIT(16)
535#define ICE_SINGLE_ACT_PRUNET BIT(17)
536 /* Bit 18 should be set to 0 for this action */
537
538 /* Action type = 2 - Pointer */
539#define ICE_SINGLE_ACT_PTR 0x2
540#define ICE_SINGLE_ACT_PTR_VAL_S 4
541#define ICE_SINGLE_ACT_PTR_VAL_M (0x1FFF << ICE_SINGLE_ACT_PTR_VAL_S)
542 /* Bit 18 should be set to 1 */
543#define ICE_SINGLE_ACT_PTR_BIT BIT(18)
544
545 /* Action type = 3 - Other actions. Last two bits
546 * are other action identifier
547 */
548#define ICE_SINGLE_ACT_OTHER_ACTS 0x3
549#define ICE_SINGLE_OTHER_ACT_IDENTIFIER_S 17
550#define ICE_SINGLE_OTHER_ACT_IDENTIFIER_M \
551 (0x3 << ICE_SINGLE_OTHER_ACT_IDENTIFIER_S)
552
553 /* Bit 17:18 - Defines other actions */
554 /* Other action = 0 - Mirror VSI */
555#define ICE_SINGLE_OTHER_ACT_MIRROR 0
556#define ICE_SINGLE_ACT_MIRROR_VSI_ID_S 4
557#define ICE_SINGLE_ACT_MIRROR_VSI_ID_M \
558 (0x3FF << ICE_SINGLE_ACT_MIRROR_VSI_ID_S)
559
560 /* Other action = 3 - Set Stat count */
561#define ICE_SINGLE_OTHER_ACT_STAT_COUNT 3
562#define ICE_SINGLE_ACT_STAT_COUNT_INDEX_S 4
563#define ICE_SINGLE_ACT_STAT_COUNT_INDEX_M \
564 (0x7F << ICE_SINGLE_ACT_STAT_COUNT_INDEX_S)
565
566 __le16 index; /* The index of the rule in the lookup table */
567 /* Length and values of the header to be matched per recipe or
568 * lookup-type
569 */
570 __le16 hdr_len;
571 u8 hdr[];
572};
573
574/* Add/Update/Remove large action command/response entry
575 * "index" is returned as part of a response to a successful Add command, and
576 * can be used to identify the action for Update/Get/Remove commands.
577 */
578struct ice_sw_rule_lg_act {
579 __le16 index; /* Index in large action table */
580 __le16 size;
581 /* Max number of large actions */
582#define ICE_MAX_LG_ACT 4
583 /* Bit 0:1 - Action type */
584#define ICE_LG_ACT_TYPE_S 0
585#define ICE_LG_ACT_TYPE_M (0x7 << ICE_LG_ACT_TYPE_S)
586
587 /* Action type = 0 - Forward to VSI or VSI list */
588#define ICE_LG_ACT_VSI_FORWARDING 0
589#define ICE_LG_ACT_VSI_ID_S 3
590#define ICE_LG_ACT_VSI_ID_M (0x3FF << ICE_LG_ACT_VSI_ID_S)
591#define ICE_LG_ACT_VSI_LIST_ID_S 3
592#define ICE_LG_ACT_VSI_LIST_ID_M (0x3FF << ICE_LG_ACT_VSI_LIST_ID_S)
593 /* This bit needs to be set if action is forward to VSI list */
594#define ICE_LG_ACT_VSI_LIST BIT(13)
595
596#define ICE_LG_ACT_VALID_BIT BIT(16)
597
598 /* Action type = 1 - Forward to Queue of Queue group */
599#define ICE_LG_ACT_TO_Q 0x1
600#define ICE_LG_ACT_Q_INDEX_S 3
601#define ICE_LG_ACT_Q_INDEX_M (0x7FF << ICE_LG_ACT_Q_INDEX_S)
602#define ICE_LG_ACT_Q_REGION_S 14
603#define ICE_LG_ACT_Q_REGION_M (0x7 << ICE_LG_ACT_Q_REGION_S)
604#define ICE_LG_ACT_Q_PRIORITY_SET BIT(17)
605
606 /* Action type = 2 - Prune */
607#define ICE_LG_ACT_PRUNE 0x2
608#define ICE_LG_ACT_EGRESS BIT(14)
609#define ICE_LG_ACT_INGRESS BIT(15)
610#define ICE_LG_ACT_PRUNET BIT(16)
611
612 /* Action type = 3 - Mirror VSI */
613#define ICE_LG_OTHER_ACT_MIRROR 0x3
614#define ICE_LG_ACT_MIRROR_VSI_ID_S 3
615#define ICE_LG_ACT_MIRROR_VSI_ID_M (0x3FF << ICE_LG_ACT_MIRROR_VSI_ID_S)
616
617 /* Action type = 5 - Generic Value */
618#define ICE_LG_ACT_GENERIC 0x5
619#define ICE_LG_ACT_GENERIC_VALUE_S 3
620#define ICE_LG_ACT_GENERIC_VALUE_M (0xFFFF << ICE_LG_ACT_GENERIC_VALUE_S)
621#define ICE_LG_ACT_GENERIC_OFFSET_S 19
622#define ICE_LG_ACT_GENERIC_OFFSET_M (0x7 << ICE_LG_ACT_GENERIC_OFFSET_S)
623#define ICE_LG_ACT_GENERIC_PRIORITY_S 22
624#define ICE_LG_ACT_GENERIC_PRIORITY_M (0x7 << ICE_LG_ACT_GENERIC_PRIORITY_S)
625#define ICE_LG_ACT_GENERIC_OFF_RX_DESC_PROF_IDX 7
626
627 /* Action = 7 - Set Stat count */
628#define ICE_LG_ACT_STAT_COUNT 0x7
629#define ICE_LG_ACT_STAT_COUNT_S 3
630#define ICE_LG_ACT_STAT_COUNT_M (0x7F << ICE_LG_ACT_STAT_COUNT_S)
631 __le32 act[]; /* array of size for actions */
632};
633
634/* Add/Update/Remove VSI list command/response entry
635 * "index" is returned as part of a response to a successful Add command, and
636 * can be used to identify the VSI list for Update/Get/Remove commands.
637 */
638struct ice_sw_rule_vsi_list {
639 __le16 index; /* Index of VSI/Prune list */
640 __le16 number_vsi;
641 __le16 vsi[]; /* Array of number_vsi VSI numbers */
642};
643
644/* Query VSI list command/response entry */
645struct ice_sw_rule_vsi_list_query {
646 __le16 index;
647 DECLARE_BITMAP(vsi_list, ICE_MAX_VSI);
648} __packed;
649
650/* Add switch rule response:
651 * Content of return buffer is same as the input buffer. The status field and
652 * LUT index are updated as part of the response
653 */
654struct ice_aqc_sw_rules_elem {
655 __le16 type; /* Switch rule type, one of T_... */
656#define ICE_AQC_SW_RULES_T_LKUP_RX 0x0
657#define ICE_AQC_SW_RULES_T_LKUP_TX 0x1
658#define ICE_AQC_SW_RULES_T_LG_ACT 0x2
659#define ICE_AQC_SW_RULES_T_VSI_LIST_SET 0x3
660#define ICE_AQC_SW_RULES_T_VSI_LIST_CLEAR 0x4
661#define ICE_AQC_SW_RULES_T_PRUNE_LIST_SET 0x5
662#define ICE_AQC_SW_RULES_T_PRUNE_LIST_CLEAR 0x6
663 __le16 status;
664 union {
665 struct ice_sw_rule_lkup_rx_tx lkup_tx_rx;
666 struct ice_sw_rule_lg_act lg_act;
667 struct ice_sw_rule_vsi_list vsi_list;
668 struct ice_sw_rule_vsi_list_query vsi_list_query;
669 } __packed pdata;
670};
671
672/* Get Default Topology (indirect 0x0400) */
673struct ice_aqc_get_topo {
674 u8 port_num;
675 u8 num_branches;
676 __le16 reserved1;
677 __le32 reserved2;
678 __le32 addr_high;
679 __le32 addr_low;
680};
681
682/* Update TSE (indirect 0x0403)
683 * Get TSE (indirect 0x0404)
684 * Add TSE (indirect 0x0401)
685 * Delete TSE (indirect 0x040F)
686 * Move TSE (indirect 0x0408)
687 * Suspend Nodes (indirect 0x0409)
688 * Resume Nodes (indirect 0x040A)
689 */
690struct ice_aqc_sched_elem_cmd {
691 __le16 num_elem_req; /* Used by commands */
692 __le16 num_elem_resp; /* Used by responses */
693 __le32 reserved;
694 __le32 addr_high;
695 __le32 addr_low;
696};
697
698struct ice_aqc_elem_info_bw {
699 __le16 bw_profile_idx;
700 __le16 bw_alloc;
701};
702
703struct ice_aqc_txsched_elem {
704 u8 elem_type; /* Special field, reserved for some aq calls */
705#define ICE_AQC_ELEM_TYPE_UNDEFINED 0x0
706#define ICE_AQC_ELEM_TYPE_ROOT_PORT 0x1
707#define ICE_AQC_ELEM_TYPE_TC 0x2
708#define ICE_AQC_ELEM_TYPE_SE_GENERIC 0x3
709#define ICE_AQC_ELEM_TYPE_ENTRY_POINT 0x4
710#define ICE_AQC_ELEM_TYPE_LEAF 0x5
711#define ICE_AQC_ELEM_TYPE_SE_PADDED 0x6
712 u8 valid_sections;
713#define ICE_AQC_ELEM_VALID_GENERIC BIT(0)
714#define ICE_AQC_ELEM_VALID_CIR BIT(1)
715#define ICE_AQC_ELEM_VALID_EIR BIT(2)
716#define ICE_AQC_ELEM_VALID_SHARED BIT(3)
717 u8 generic;
718#define ICE_AQC_ELEM_GENERIC_MODE_M 0x1
719#define ICE_AQC_ELEM_GENERIC_PRIO_S 0x1
720#define ICE_AQC_ELEM_GENERIC_PRIO_M (0x7 << ICE_AQC_ELEM_GENERIC_PRIO_S)
721#define ICE_AQC_ELEM_GENERIC_SP_S 0x4
722#define ICE_AQC_ELEM_GENERIC_SP_M (0x1 << ICE_AQC_ELEM_GENERIC_SP_S)
723#define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S 0x5
724#define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_M \
725 (0x3 << ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S)
726 u8 flags; /* Special field, reserved for some aq calls */
727#define ICE_AQC_ELEM_FLAG_SUSPEND_M 0x1
728 struct ice_aqc_elem_info_bw cir_bw;
729 struct ice_aqc_elem_info_bw eir_bw;
730 __le16 srl_id;
731 __le16 reserved2;
732};
733
734struct ice_aqc_txsched_elem_data {
735 __le32 parent_teid;
736 __le32 node_teid;
737 struct ice_aqc_txsched_elem data;
738};
739
740struct ice_aqc_txsched_topo_grp_info_hdr {
741 __le32 parent_teid;
742 __le16 num_elems;
743 __le16 reserved2;
744};
745
746struct ice_aqc_add_elem {
747 struct ice_aqc_txsched_topo_grp_info_hdr hdr;
748 struct ice_aqc_txsched_elem_data generic[];
749};
750
751struct ice_aqc_get_topo_elem {
752 struct ice_aqc_txsched_topo_grp_info_hdr hdr;
753 struct ice_aqc_txsched_elem_data
754 generic[ICE_AQC_TOPO_MAX_LEVEL_NUM];
755};
756
757struct ice_aqc_delete_elem {
758 struct ice_aqc_txsched_topo_grp_info_hdr hdr;
759 __le32 teid[];
760};
761
762/* Query Port ETS (indirect 0x040E)
763 *
764 * This indirect command is used to query port TC node configuration.
765 */
766struct ice_aqc_query_port_ets {
767 __le32 port_teid;
768 __le32 reserved;
769 __le32 addr_high;
770 __le32 addr_low;
771};
772
773struct ice_aqc_port_ets_elem {
774 u8 tc_valid_bits;
775 u8 reserved[3];
776 /* 3 bits for UP per TC 0-7, 4th byte reserved */
777 __le32 up2tc;
778 u8 tc_bw_share[8];
779 __le32 port_eir_prof_id;
780 __le32 port_cir_prof_id;
781 /* 3 bits per Node priority to TC 0-7, 4th byte reserved */
782 __le32 tc_node_prio;
783#define ICE_TC_NODE_PRIO_S 0x4
784 u8 reserved1[4];
785 __le32 tc_node_teid[8]; /* Used for response, reserved in command */
786};
787
788/* Rate limiting profile for
789 * Add RL profile (indirect 0x0410)
790 * Query RL profile (indirect 0x0411)
791 * Remove RL profile (indirect 0x0415)
792 * These indirect commands acts on single or multiple
793 * RL profiles with specified data.
794 */
795struct ice_aqc_rl_profile {
796 __le16 num_profiles;
797 __le16 num_processed; /* Only for response. Reserved in Command. */
798 u8 reserved[4];
799 __le32 addr_high;
800 __le32 addr_low;
801};
802
803struct ice_aqc_rl_profile_elem {
804 u8 level;
805 u8 flags;
806#define ICE_AQC_RL_PROFILE_TYPE_S 0x0
807#define ICE_AQC_RL_PROFILE_TYPE_M (0x3 << ICE_AQC_RL_PROFILE_TYPE_S)
808#define ICE_AQC_RL_PROFILE_TYPE_CIR 0
809#define ICE_AQC_RL_PROFILE_TYPE_EIR 1
810#define ICE_AQC_RL_PROFILE_TYPE_SRL 2
811/* The following flag is used for Query RL Profile Data */
812#define ICE_AQC_RL_PROFILE_INVAL_S 0x7
813#define ICE_AQC_RL_PROFILE_INVAL_M (0x1 << ICE_AQC_RL_PROFILE_INVAL_S)
814
815 __le16 profile_id;
816 __le16 max_burst_size;
817 __le16 rl_multiply;
818 __le16 wake_up_calc;
819 __le16 rl_encode;
820};
821
822/* Query Scheduler Resource Allocation (indirect 0x0412)
823 * This indirect command retrieves the scheduler resources allocated by
824 * EMP Firmware to the given PF.
825 */
826struct ice_aqc_query_txsched_res {
827 u8 reserved[8];
828 __le32 addr_high;
829 __le32 addr_low;
830};
831
832struct ice_aqc_generic_sched_props {
833 __le16 phys_levels;
834 __le16 logical_levels;
835 u8 flattening_bitmap;
836 u8 max_device_cgds;
837 u8 max_pf_cgds;
838 u8 rsvd0;
839 __le16 rdma_qsets;
840 u8 rsvd1[22];
841};
842
843struct ice_aqc_layer_props {
844 u8 logical_layer;
845 u8 chunk_size;
846 __le16 max_device_nodes;
847 __le16 max_pf_nodes;
848 u8 rsvd0[4];
849 __le16 max_sibl_grp_sz;
850 __le16 max_cir_rl_profiles;
851 __le16 max_eir_rl_profiles;
852 __le16 max_srl_profiles;
853 u8 rsvd1[14];
854};
855
856struct ice_aqc_query_txsched_res_resp {
857 struct ice_aqc_generic_sched_props sched_props;
858 struct ice_aqc_layer_props layer_props[ICE_AQC_TOPO_MAX_LEVEL_NUM];
859};
860
861/* Get PHY capabilities (indirect 0x0600) */
862struct ice_aqc_get_phy_caps {
863 u8 lport_num;
864 u8 reserved;
865 __le16 param0;
866 /* 18.0 - Report qualified modules */
867#define ICE_AQC_GET_PHY_RQM BIT(0)
868 /* 18.1 - 18.2 : Report mode
869 * 00b - Report NVM capabilities
870 * 01b - Report topology capabilities
871 * 10b - Report SW configured
872 */
873#define ICE_AQC_REPORT_MODE_S 1
874#define ICE_AQC_REPORT_MODE_M (3 << ICE_AQC_REPORT_MODE_S)
875#define ICE_AQC_REPORT_NVM_CAP 0
876#define ICE_AQC_REPORT_TOPO_CAP BIT(1)
877#define ICE_AQC_REPORT_SW_CFG BIT(2)
878 __le32 reserved1;
879 __le32 addr_high;
880 __le32 addr_low;
881};
882
883/* This is #define of PHY type (Extended):
884 * The first set of defines is for phy_type_low.
885 */
886#define ICE_PHY_TYPE_LOW_100BASE_TX BIT_ULL(0)
887#define ICE_PHY_TYPE_LOW_100M_SGMII BIT_ULL(1)
888#define ICE_PHY_TYPE_LOW_1000BASE_T BIT_ULL(2)
889#define ICE_PHY_TYPE_LOW_1000BASE_SX BIT_ULL(3)
890#define ICE_PHY_TYPE_LOW_1000BASE_LX BIT_ULL(4)
891#define ICE_PHY_TYPE_LOW_1000BASE_KX BIT_ULL(5)
892#define ICE_PHY_TYPE_LOW_1G_SGMII BIT_ULL(6)
893#define ICE_PHY_TYPE_LOW_2500BASE_T BIT_ULL(7)
894#define ICE_PHY_TYPE_LOW_2500BASE_X BIT_ULL(8)
895#define ICE_PHY_TYPE_LOW_2500BASE_KX BIT_ULL(9)
896#define ICE_PHY_TYPE_LOW_5GBASE_T BIT_ULL(10)
897#define ICE_PHY_TYPE_LOW_5GBASE_KR BIT_ULL(11)
898#define ICE_PHY_TYPE_LOW_10GBASE_T BIT_ULL(12)
899#define ICE_PHY_TYPE_LOW_10G_SFI_DA BIT_ULL(13)
900#define ICE_PHY_TYPE_LOW_10GBASE_SR BIT_ULL(14)
901#define ICE_PHY_TYPE_LOW_10GBASE_LR BIT_ULL(15)
902#define ICE_PHY_TYPE_LOW_10GBASE_KR_CR1 BIT_ULL(16)
903#define ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC BIT_ULL(17)
904#define ICE_PHY_TYPE_LOW_10G_SFI_C2C BIT_ULL(18)
905#define ICE_PHY_TYPE_LOW_25GBASE_T BIT_ULL(19)
906#define ICE_PHY_TYPE_LOW_25GBASE_CR BIT_ULL(20)
907#define ICE_PHY_TYPE_LOW_25GBASE_CR_S BIT_ULL(21)
908#define ICE_PHY_TYPE_LOW_25GBASE_CR1 BIT_ULL(22)
909#define ICE_PHY_TYPE_LOW_25GBASE_SR BIT_ULL(23)
910#define ICE_PHY_TYPE_LOW_25GBASE_LR BIT_ULL(24)
911#define ICE_PHY_TYPE_LOW_25GBASE_KR BIT_ULL(25)
912#define ICE_PHY_TYPE_LOW_25GBASE_KR_S BIT_ULL(26)
913#define ICE_PHY_TYPE_LOW_25GBASE_KR1 BIT_ULL(27)
914#define ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC BIT_ULL(28)
915#define ICE_PHY_TYPE_LOW_25G_AUI_C2C BIT_ULL(29)
916#define ICE_PHY_TYPE_LOW_40GBASE_CR4 BIT_ULL(30)
917#define ICE_PHY_TYPE_LOW_40GBASE_SR4 BIT_ULL(31)
918#define ICE_PHY_TYPE_LOW_40GBASE_LR4 BIT_ULL(32)
919#define ICE_PHY_TYPE_LOW_40GBASE_KR4 BIT_ULL(33)
920#define ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC BIT_ULL(34)
921#define ICE_PHY_TYPE_LOW_40G_XLAUI BIT_ULL(35)
922#define ICE_PHY_TYPE_LOW_50GBASE_CR2 BIT_ULL(36)
923#define ICE_PHY_TYPE_LOW_50GBASE_SR2 BIT_ULL(37)
924#define ICE_PHY_TYPE_LOW_50GBASE_LR2 BIT_ULL(38)
925#define ICE_PHY_TYPE_LOW_50GBASE_KR2 BIT_ULL(39)
926#define ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC BIT_ULL(40)
927#define ICE_PHY_TYPE_LOW_50G_LAUI2 BIT_ULL(41)
928#define ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC BIT_ULL(42)
929#define ICE_PHY_TYPE_LOW_50G_AUI2 BIT_ULL(43)
930#define ICE_PHY_TYPE_LOW_50GBASE_CP BIT_ULL(44)
931#define ICE_PHY_TYPE_LOW_50GBASE_SR BIT_ULL(45)
932#define ICE_PHY_TYPE_LOW_50GBASE_FR BIT_ULL(46)
933#define ICE_PHY_TYPE_LOW_50GBASE_LR BIT_ULL(47)
934#define ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4 BIT_ULL(48)
935#define ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC BIT_ULL(49)
936#define ICE_PHY_TYPE_LOW_50G_AUI1 BIT_ULL(50)
937#define ICE_PHY_TYPE_LOW_100GBASE_CR4 BIT_ULL(51)
938#define ICE_PHY_TYPE_LOW_100GBASE_SR4 BIT_ULL(52)
939#define ICE_PHY_TYPE_LOW_100GBASE_LR4 BIT_ULL(53)
940#define ICE_PHY_TYPE_LOW_100GBASE_KR4 BIT_ULL(54)
941#define ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC BIT_ULL(55)
942#define ICE_PHY_TYPE_LOW_100G_CAUI4 BIT_ULL(56)
943#define ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC BIT_ULL(57)
944#define ICE_PHY_TYPE_LOW_100G_AUI4 BIT_ULL(58)
945#define ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4 BIT_ULL(59)
946#define ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4 BIT_ULL(60)
947#define ICE_PHY_TYPE_LOW_100GBASE_CP2 BIT_ULL(61)
948#define ICE_PHY_TYPE_LOW_100GBASE_SR2 BIT_ULL(62)
949#define ICE_PHY_TYPE_LOW_100GBASE_DR BIT_ULL(63)
950#define ICE_PHY_TYPE_LOW_MAX_INDEX 63
951/* The second set of defines is for phy_type_high. */
952#define ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4 BIT_ULL(0)
953#define ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC BIT_ULL(1)
954#define ICE_PHY_TYPE_HIGH_100G_CAUI2 BIT_ULL(2)
955#define ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC BIT_ULL(3)
956#define ICE_PHY_TYPE_HIGH_100G_AUI2 BIT_ULL(4)
957#define ICE_PHY_TYPE_HIGH_MAX_INDEX 5
958
959struct ice_aqc_get_phy_caps_data {
960 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
961 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */
962 u8 caps;
963#define ICE_AQC_PHY_EN_TX_LINK_PAUSE BIT(0)
964#define ICE_AQC_PHY_EN_RX_LINK_PAUSE BIT(1)
965#define ICE_AQC_PHY_LOW_POWER_MODE BIT(2)
966#define ICE_AQC_PHY_EN_LINK BIT(3)
967#define ICE_AQC_PHY_AN_MODE BIT(4)
968#define ICE_AQC_GET_PHY_EN_MOD_QUAL BIT(5)
969#define ICE_AQC_PHY_EN_AUTO_FEC BIT(7)
970#define ICE_AQC_PHY_CAPS_MASK ICE_M(0xff, 0)
971 u8 low_power_ctrl_an;
972#define ICE_AQC_PHY_EN_D3COLD_LOW_POWER_AUTONEG BIT(0)
973#define ICE_AQC_PHY_AN_EN_CLAUSE28 BIT(1)
974#define ICE_AQC_PHY_AN_EN_CLAUSE73 BIT(2)
975#define ICE_AQC_PHY_AN_EN_CLAUSE37 BIT(3)
976 __le16 eee_cap;
977#define ICE_AQC_PHY_EEE_EN_100BASE_TX BIT(0)
978#define ICE_AQC_PHY_EEE_EN_1000BASE_T BIT(1)
979#define ICE_AQC_PHY_EEE_EN_10GBASE_T BIT(2)
980#define ICE_AQC_PHY_EEE_EN_1000BASE_KX BIT(3)
981#define ICE_AQC_PHY_EEE_EN_10GBASE_KR BIT(4)
982#define ICE_AQC_PHY_EEE_EN_25GBASE_KR BIT(5)
983#define ICE_AQC_PHY_EEE_EN_40GBASE_KR4 BIT(6)
984 __le16 eeer_value;
985 u8 phy_id_oui[4]; /* PHY/Module ID connected on the port */
986 u8 phy_fw_ver[8];
987 u8 link_fec_options;
988#define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN BIT(0)
989#define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ BIT(1)
990#define ICE_AQC_PHY_FEC_25G_RS_528_REQ BIT(2)
991#define ICE_AQC_PHY_FEC_25G_KR_REQ BIT(3)
992#define ICE_AQC_PHY_FEC_25G_RS_544_REQ BIT(4)
993#define ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN BIT(6)
994#define ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN BIT(7)
995#define ICE_AQC_PHY_FEC_MASK ICE_M(0xdf, 0)
996 u8 module_compliance_enforcement;
997#define ICE_AQC_MOD_ENFORCE_STRICT_MODE BIT(0)
998 u8 extended_compliance_code;
999#define ICE_MODULE_TYPE_TOTAL_BYTE 3
1000 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE];
1001#define ICE_AQC_MOD_TYPE_BYTE0_SFP_PLUS 0xA0
1002#define ICE_AQC_MOD_TYPE_BYTE0_QSFP_PLUS 0x80
1003#define ICE_AQC_MOD_TYPE_IDENT 1
1004#define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE BIT(0)
1005#define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE BIT(1)
1006#define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_SR BIT(4)
1007#define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LR BIT(5)
1008#define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LRM BIT(6)
1009#define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_ER BIT(7)
1010#define ICE_AQC_MOD_TYPE_BYTE2_SFP_PLUS 0xA0
1011#define ICE_AQC_MOD_TYPE_BYTE2_QSFP_PLUS 0x86
1012 u8 qualified_module_count;
1013 u8 rsvd2[7]; /* Bytes 47:41 reserved */
1014#define ICE_AQC_QUAL_MOD_COUNT_MAX 16
1015 struct {
1016 u8 v_oui[3];
1017 u8 rsvd3;
1018 u8 v_part[16];
1019 __le32 v_rev;
1020 __le64 rsvd4;
1021 } qual_modules[ICE_AQC_QUAL_MOD_COUNT_MAX];
1022};
1023
1024/* Set PHY capabilities (direct 0x0601)
1025 * NOTE: This command must be followed by setup link and restart auto-neg
1026 */
1027struct ice_aqc_set_phy_cfg {
1028 u8 lport_num;
1029 u8 reserved[7];
1030 __le32 addr_high;
1031 __le32 addr_low;
1032};
1033
1034/* Set PHY config command data structure */
1035struct ice_aqc_set_phy_cfg_data {
1036 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
1037 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */
1038 u8 caps;
1039#define ICE_AQ_PHY_ENA_VALID_MASK ICE_M(0xef, 0)
1040#define ICE_AQ_PHY_ENA_TX_PAUSE_ABILITY BIT(0)
1041#define ICE_AQ_PHY_ENA_RX_PAUSE_ABILITY BIT(1)
1042#define ICE_AQ_PHY_ENA_LOW_POWER BIT(2)
1043#define ICE_AQ_PHY_ENA_LINK BIT(3)
1044#define ICE_AQ_PHY_ENA_AUTO_LINK_UPDT BIT(5)
1045#define ICE_AQ_PHY_ENA_LESM BIT(6)
1046#define ICE_AQ_PHY_ENA_AUTO_FEC BIT(7)
1047 u8 low_power_ctrl_an;
1048 __le16 eee_cap; /* Value from ice_aqc_get_phy_caps */
1049 __le16 eeer_value;
1050 u8 link_fec_opt; /* Use defines from ice_aqc_get_phy_caps */
1051 u8 module_compliance_enforcement;
1052};
1053
1054/* Set MAC Config command data structure (direct 0x0603) */
1055struct ice_aqc_set_mac_cfg {
1056 __le16 max_frame_size;
1057 u8 params;
1058#define ICE_AQ_SET_MAC_PACE_S 3
1059#define ICE_AQ_SET_MAC_PACE_M (0xF << ICE_AQ_SET_MAC_PACE_S)
1060#define ICE_AQ_SET_MAC_PACE_TYPE_M BIT(7)
1061#define ICE_AQ_SET_MAC_PACE_TYPE_RATE 0
1062#define ICE_AQ_SET_MAC_PACE_TYPE_FIXED ICE_AQ_SET_MAC_PACE_TYPE_M
1063 u8 tx_tmr_priority;
1064 __le16 tx_tmr_value;
1065 __le16 fc_refresh_threshold;
1066 u8 drop_opts;
1067#define ICE_AQ_SET_MAC_AUTO_DROP_MASK BIT(0)
1068#define ICE_AQ_SET_MAC_AUTO_DROP_NONE 0
1069#define ICE_AQ_SET_MAC_AUTO_DROP_BLOCKING_PKTS BIT(0)
1070 u8 reserved[7];
1071};
1072
1073/* Restart AN command data structure (direct 0x0605)
1074 * Also used for response, with only the lport_num field present.
1075 */
1076struct ice_aqc_restart_an {
1077 u8 lport_num;
1078 u8 reserved;
1079 u8 cmd_flags;
1080#define ICE_AQC_RESTART_AN_LINK_RESTART BIT(1)
1081#define ICE_AQC_RESTART_AN_LINK_ENABLE BIT(2)
1082 u8 reserved2[13];
1083};
1084
1085/* Get link status (indirect 0x0607), also used for Link Status Event */
1086struct ice_aqc_get_link_status {
1087 u8 lport_num;
1088 u8 reserved;
1089 __le16 cmd_flags;
1090#define ICE_AQ_LSE_M 0x3
1091#define ICE_AQ_LSE_NOP 0x0
1092#define ICE_AQ_LSE_DIS 0x2
1093#define ICE_AQ_LSE_ENA 0x3
1094 /* only response uses this flag */
1095#define ICE_AQ_LSE_IS_ENABLED 0x1
1096 __le32 reserved2;
1097 __le32 addr_high;
1098 __le32 addr_low;
1099};
1100
1101/* Get link status response data structure, also used for Link Status Event */
1102struct ice_aqc_get_link_status_data {
1103 u8 topo_media_conflict;
1104#define ICE_AQ_LINK_TOPO_CONFLICT BIT(0)
1105#define ICE_AQ_LINK_MEDIA_CONFLICT BIT(1)
1106#define ICE_AQ_LINK_TOPO_CORRUPT BIT(2)
1107#define ICE_AQ_LINK_TOPO_UNREACH_PRT BIT(4)
1108#define ICE_AQ_LINK_TOPO_UNDRUTIL_PRT BIT(5)
1109#define ICE_AQ_LINK_TOPO_UNDRUTIL_MEDIA BIT(6)
1110#define ICE_AQ_LINK_TOPO_UNSUPP_MEDIA BIT(7)
1111 u8 reserved1;
1112 u8 link_info;
1113#define ICE_AQ_LINK_UP BIT(0) /* Link Status */
1114#define ICE_AQ_LINK_FAULT BIT(1)
1115#define ICE_AQ_LINK_FAULT_TX BIT(2)
1116#define ICE_AQ_LINK_FAULT_RX BIT(3)
1117#define ICE_AQ_LINK_FAULT_REMOTE BIT(4)
1118#define ICE_AQ_LINK_UP_PORT BIT(5) /* External Port Link Status */
1119#define ICE_AQ_MEDIA_AVAILABLE BIT(6)
1120#define ICE_AQ_SIGNAL_DETECT BIT(7)
1121 u8 an_info;
1122#define ICE_AQ_AN_COMPLETED BIT(0)
1123#define ICE_AQ_LP_AN_ABILITY BIT(1)
1124#define ICE_AQ_PD_FAULT BIT(2) /* Parallel Detection Fault */
1125#define ICE_AQ_FEC_EN BIT(3)
1126#define ICE_AQ_PHY_LOW_POWER BIT(4) /* Low Power State */
1127#define ICE_AQ_LINK_PAUSE_TX BIT(5)
1128#define ICE_AQ_LINK_PAUSE_RX BIT(6)
1129#define ICE_AQ_QUALIFIED_MODULE BIT(7)
1130 u8 ext_info;
1131#define ICE_AQ_LINK_PHY_TEMP_ALARM BIT(0)
1132#define ICE_AQ_LINK_EXCESSIVE_ERRORS BIT(1) /* Excessive Link Errors */
1133 /* Port Tx Suspended */
1134#define ICE_AQ_LINK_TX_S 2
1135#define ICE_AQ_LINK_TX_M (0x03 << ICE_AQ_LINK_TX_S)
1136#define ICE_AQ_LINK_TX_ACTIVE 0
1137#define ICE_AQ_LINK_TX_DRAINED 1
1138#define ICE_AQ_LINK_TX_FLUSHED 3
1139 u8 reserved2;
1140 __le16 max_frame_size;
1141 u8 cfg;
1142#define ICE_AQ_LINK_25G_KR_FEC_EN BIT(0)
1143#define ICE_AQ_LINK_25G_RS_528_FEC_EN BIT(1)
1144#define ICE_AQ_LINK_25G_RS_544_FEC_EN BIT(2)
1145#define ICE_AQ_FEC_MASK ICE_M(0x7, 0)
1146 /* Pacing Config */
1147#define ICE_AQ_CFG_PACING_S 3
1148#define ICE_AQ_CFG_PACING_M (0xF << ICE_AQ_CFG_PACING_S)
1149#define ICE_AQ_CFG_PACING_TYPE_M BIT(7)
1150#define ICE_AQ_CFG_PACING_TYPE_AVG 0
1151#define ICE_AQ_CFG_PACING_TYPE_FIXED ICE_AQ_CFG_PACING_TYPE_M
1152 /* External Device Power Ability */
1153 u8 power_desc;
1154#define ICE_AQ_PWR_CLASS_M 0x3
1155#define ICE_AQ_LINK_PWR_BASET_LOW_HIGH 0
1156#define ICE_AQ_LINK_PWR_BASET_HIGH 1
1157#define ICE_AQ_LINK_PWR_QSFP_CLASS_1 0
1158#define ICE_AQ_LINK_PWR_QSFP_CLASS_2 1
1159#define ICE_AQ_LINK_PWR_QSFP_CLASS_3 2
1160#define ICE_AQ_LINK_PWR_QSFP_CLASS_4 3
1161 __le16 link_speed;
1162#define ICE_AQ_LINK_SPEED_M 0x7FF
1163#define ICE_AQ_LINK_SPEED_10MB BIT(0)
1164#define ICE_AQ_LINK_SPEED_100MB BIT(1)
1165#define ICE_AQ_LINK_SPEED_1000MB BIT(2)
1166#define ICE_AQ_LINK_SPEED_2500MB BIT(3)
1167#define ICE_AQ_LINK_SPEED_5GB BIT(4)
1168#define ICE_AQ_LINK_SPEED_10GB BIT(5)
1169#define ICE_AQ_LINK_SPEED_20GB BIT(6)
1170#define ICE_AQ_LINK_SPEED_25GB BIT(7)
1171#define ICE_AQ_LINK_SPEED_40GB BIT(8)
1172#define ICE_AQ_LINK_SPEED_50GB BIT(9)
1173#define ICE_AQ_LINK_SPEED_100GB BIT(10)
1174#define ICE_AQ_LINK_SPEED_UNKNOWN BIT(15)
1175 __le32 reserved3; /* Aligns next field to 8-byte boundary */
1176 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
1177 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */
1178};
1179
1180/* Set event mask command (direct 0x0613) */
1181struct ice_aqc_set_event_mask {
1182 u8 lport_num;
1183 u8 reserved[7];
1184 __le16 event_mask;
1185#define ICE_AQ_LINK_EVENT_UPDOWN BIT(1)
1186#define ICE_AQ_LINK_EVENT_MEDIA_NA BIT(2)
1187#define ICE_AQ_LINK_EVENT_LINK_FAULT BIT(3)
1188#define ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM BIT(4)
1189#define ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS BIT(5)
1190#define ICE_AQ_LINK_EVENT_SIGNAL_DETECT BIT(6)
1191#define ICE_AQ_LINK_EVENT_AN_COMPLETED BIT(7)
1192#define ICE_AQ_LINK_EVENT_MODULE_QUAL_FAIL BIT(8)
1193#define ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED BIT(9)
1194 u8 reserved1[6];
1195};
1196
1197/* Set MAC Loopback command (direct 0x0620) */
1198struct ice_aqc_set_mac_lb {
1199 u8 lb_mode;
1200#define ICE_AQ_MAC_LB_EN BIT(0)
1201#define ICE_AQ_MAC_LB_OSC_CLK BIT(1)
1202 u8 reserved[15];
1203};
1204
1205struct ice_aqc_link_topo_addr {
1206 u8 lport_num;
1207 u8 lport_num_valid;
1208#define ICE_AQC_LINK_TOPO_PORT_NUM_VALID BIT(0)
1209 u8 node_type_ctx;
1210#define ICE_AQC_LINK_TOPO_NODE_TYPE_S 0
1211#define ICE_AQC_LINK_TOPO_NODE_TYPE_M (0xF << ICE_AQC_LINK_TOPO_NODE_TYPE_S)
1212#define ICE_AQC_LINK_TOPO_NODE_TYPE_PHY 0
1213#define ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL 1
1214#define ICE_AQC_LINK_TOPO_NODE_TYPE_MUX_CTRL 2
1215#define ICE_AQC_LINK_TOPO_NODE_TYPE_LED_CTRL 3
1216#define ICE_AQC_LINK_TOPO_NODE_TYPE_LED 4
1217#define ICE_AQC_LINK_TOPO_NODE_TYPE_THERMAL 5
1218#define ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE 6
1219#define ICE_AQC_LINK_TOPO_NODE_TYPE_MEZZ 7
1220#define ICE_AQC_LINK_TOPO_NODE_TYPE_ID_EEPROM 8
1221#define ICE_AQC_LINK_TOPO_NODE_CTX_S 4
1222#define ICE_AQC_LINK_TOPO_NODE_CTX_M \
1223 (0xF << ICE_AQC_LINK_TOPO_NODE_CTX_S)
1224#define ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL 0
1225#define ICE_AQC_LINK_TOPO_NODE_CTX_BOARD 1
1226#define ICE_AQC_LINK_TOPO_NODE_CTX_PORT 2
1227#define ICE_AQC_LINK_TOPO_NODE_CTX_NODE 3
1228#define ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED 4
1229#define ICE_AQC_LINK_TOPO_NODE_CTX_OVERRIDE 5
1230 u8 index;
1231 __le16 handle;
1232#define ICE_AQC_LINK_TOPO_HANDLE_S 0
1233#define ICE_AQC_LINK_TOPO_HANDLE_M (0x3FF << ICE_AQC_LINK_TOPO_HANDLE_S)
1234/* Used to decode the handle field */
1235#define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_M BIT(9)
1236#define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_LOM BIT(9)
1237#define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_MEZZ 0
1238#define ICE_AQC_LINK_TOPO_HANDLE_NODE_S 0
1239/* In case of a Mezzanine type */
1240#define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_NODE_M \
1241 (0x3F << ICE_AQC_LINK_TOPO_HANDLE_NODE_S)
1242#define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S 6
1243#define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_M (0x7 << ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S)
1244/* In case of a LOM type */
1245#define ICE_AQC_LINK_TOPO_HANDLE_LOM_NODE_M \
1246 (0x1FF << ICE_AQC_LINK_TOPO_HANDLE_NODE_S)
1247};
1248
1249/* Get Link Topology Handle (direct, 0x06E0) */
1250struct ice_aqc_get_link_topo {
1251 struct ice_aqc_link_topo_addr addr;
1252 u8 node_part_num;
1253 u8 rsvd[9];
1254};
1255
1256/* Set Port Identification LED (direct, 0x06E9) */
1257struct ice_aqc_set_port_id_led {
1258 u8 lport_num;
1259 u8 lport_num_valid;
1260 u8 ident_mode;
1261#define ICE_AQC_PORT_IDENT_LED_BLINK BIT(0)
1262#define ICE_AQC_PORT_IDENT_LED_ORIG 0
1263 u8 rsvd[13];
1264};
1265
1266/* Read/Write SFF EEPROM command (indirect 0x06EE) */
1267struct ice_aqc_sff_eeprom {
1268 u8 lport_num;
1269 u8 lport_num_valid;
1270#define ICE_AQC_SFF_PORT_NUM_VALID BIT(0)
1271 __le16 i2c_bus_addr;
1272#define ICE_AQC_SFF_I2CBUS_7BIT_M 0x7F
1273#define ICE_AQC_SFF_I2CBUS_10BIT_M 0x3FF
1274#define ICE_AQC_SFF_I2CBUS_TYPE_M BIT(10)
1275#define ICE_AQC_SFF_I2CBUS_TYPE_7BIT 0
1276#define ICE_AQC_SFF_I2CBUS_TYPE_10BIT ICE_AQC_SFF_I2CBUS_TYPE_M
1277#define ICE_AQC_SFF_SET_EEPROM_PAGE_S 11
1278#define ICE_AQC_SFF_SET_EEPROM_PAGE_M (0x3 << ICE_AQC_SFF_SET_EEPROM_PAGE_S)
1279#define ICE_AQC_SFF_NO_PAGE_CHANGE 0
1280#define ICE_AQC_SFF_SET_23_ON_MISMATCH 1
1281#define ICE_AQC_SFF_SET_22_ON_MISMATCH 2
1282#define ICE_AQC_SFF_IS_WRITE BIT(15)
1283 __le16 i2c_mem_addr;
1284 __le16 eeprom_page;
1285#define ICE_AQC_SFF_EEPROM_BANK_S 0
1286#define ICE_AQC_SFF_EEPROM_BANK_M (0xFF << ICE_AQC_SFF_EEPROM_BANK_S)
1287#define ICE_AQC_SFF_EEPROM_PAGE_S 8
1288#define ICE_AQC_SFF_EEPROM_PAGE_M (0xFF << ICE_AQC_SFF_EEPROM_PAGE_S)
1289 __le32 addr_high;
1290 __le32 addr_low;
1291};
1292
1293/* NVM Read command (indirect 0x0701)
1294 * NVM Erase commands (direct 0x0702)
1295 * NVM Update commands (indirect 0x0703)
1296 */
1297struct ice_aqc_nvm {
1298#define ICE_AQC_NVM_MAX_OFFSET 0xFFFFFF
1299 __le16 offset_low;
1300 u8 offset_high;
1301 u8 cmd_flags;
1302#define ICE_AQC_NVM_LAST_CMD BIT(0)
1303#define ICE_AQC_NVM_PCIR_REQ BIT(0) /* Used by NVM Update reply */
1304#define ICE_AQC_NVM_PRESERVATION_S 1
1305#define ICE_AQC_NVM_PRESERVATION_M (3 << ICE_AQC_NVM_PRESERVATION_S)
1306#define ICE_AQC_NVM_NO_PRESERVATION (0 << ICE_AQC_NVM_PRESERVATION_S)
1307#define ICE_AQC_NVM_PRESERVE_ALL BIT(1)
1308#define ICE_AQC_NVM_FACTORY_DEFAULT (2 << ICE_AQC_NVM_PRESERVATION_S)
1309#define ICE_AQC_NVM_PRESERVE_SELECTED (3 << ICE_AQC_NVM_PRESERVATION_S)
1310#define ICE_AQC_NVM_ACTIV_SEL_NVM BIT(3) /* Write Activate/SR Dump only */
1311#define ICE_AQC_NVM_ACTIV_SEL_OROM BIT(4)
1312#define ICE_AQC_NVM_ACTIV_SEL_NETLIST BIT(5)
1313#define ICE_AQC_NVM_SPECIAL_UPDATE BIT(6)
1314#define ICE_AQC_NVM_REVERT_LAST_ACTIV BIT(6) /* Write Activate only */
1315#define ICE_AQC_NVM_ACTIV_SEL_MASK ICE_M(0x7, 3)
1316#define ICE_AQC_NVM_FLASH_ONLY BIT(7)
1317 __le16 module_typeid;
1318 __le16 length;
1319#define ICE_AQC_NVM_ERASE_LEN 0xFFFF
1320 __le32 addr_high;
1321 __le32 addr_low;
1322};
1323
1324#define ICE_AQC_NVM_START_POINT 0
1325
1326/* NVM Checksum Command (direct, 0x0706) */
1327struct ice_aqc_nvm_checksum {
1328 u8 flags;
1329#define ICE_AQC_NVM_CHECKSUM_VERIFY BIT(0)
1330#define ICE_AQC_NVM_CHECKSUM_RECALC BIT(1)
1331 u8 rsvd;
1332 __le16 checksum; /* Used only by response */
1333#define ICE_AQC_NVM_CHECKSUM_CORRECT 0xBABA
1334 u8 rsvd2[12];
1335};
1336
1337/* The result of netlist NVM read comes in a TLV format. The actual data
1338 * (netlist header) starts from word offset 1 (byte 2). The FW strips
1339 * out the type field from the TLV header so all the netlist fields
1340 * should adjust their offset value by 1 word (2 bytes) in order to map
1341 * their correct location.
1342 */
1343#define ICE_AQC_NVM_LINK_TOPO_NETLIST_MOD_ID 0x11B
1344#define ICE_AQC_NVM_LINK_TOPO_NETLIST_LEN_OFFSET 1
1345#define ICE_AQC_NVM_LINK_TOPO_NETLIST_LEN 2 /* In bytes */
1346#define ICE_AQC_NVM_NETLIST_NODE_COUNT_OFFSET 2
1347#define ICE_AQC_NVM_NETLIST_NODE_COUNT_LEN 2 /* In bytes */
1348#define ICE_AQC_NVM_NETLIST_NODE_COUNT_M ICE_M(0x3FF, 0)
1349#define ICE_AQC_NVM_NETLIST_ID_BLK_START_OFFSET 5
1350#define ICE_AQC_NVM_NETLIST_ID_BLK_LEN 0x30 /* In words */
1351
1352/* netlist ID block field offsets (word offsets) */
1353#define ICE_AQC_NVM_NETLIST_ID_BLK_MAJOR_VER_LOW 2
1354#define ICE_AQC_NVM_NETLIST_ID_BLK_MAJOR_VER_HIGH 3
1355#define ICE_AQC_NVM_NETLIST_ID_BLK_MINOR_VER_LOW 4
1356#define ICE_AQC_NVM_NETLIST_ID_BLK_MINOR_VER_HIGH 5
1357#define ICE_AQC_NVM_NETLIST_ID_BLK_TYPE_LOW 6
1358#define ICE_AQC_NVM_NETLIST_ID_BLK_TYPE_HIGH 7
1359#define ICE_AQC_NVM_NETLIST_ID_BLK_REV_LOW 8
1360#define ICE_AQC_NVM_NETLIST_ID_BLK_REV_HIGH 9
1361#define ICE_AQC_NVM_NETLIST_ID_BLK_SHA_HASH 0xA
1362#define ICE_AQC_NVM_NETLIST_ID_BLK_CUST_VER 0x2F
1363
1364/* Used for NVM Set Package Data command - 0x070A */
1365struct ice_aqc_nvm_pkg_data {
1366 u8 reserved[3];
1367 u8 cmd_flags;
1368#define ICE_AQC_NVM_PKG_DELETE BIT(0) /* used for command call */
1369#define ICE_AQC_NVM_PKG_SKIPPED BIT(0) /* used for command response */
1370
1371 u32 reserved1;
1372 __le32 addr_high;
1373 __le32 addr_low;
1374};
1375
1376/* Used for Pass Component Table command - 0x070B */
1377struct ice_aqc_nvm_pass_comp_tbl {
1378 u8 component_response; /* Response only */
1379#define ICE_AQ_NVM_PASS_COMP_CAN_BE_UPDATED 0x0
1380#define ICE_AQ_NVM_PASS_COMP_CAN_MAY_BE_UPDATEABLE 0x1
1381#define ICE_AQ_NVM_PASS_COMP_CAN_NOT_BE_UPDATED 0x2
1382 u8 component_response_code; /* Response only */
1383#define ICE_AQ_NVM_PASS_COMP_CAN_BE_UPDATED_CODE 0x0
1384#define ICE_AQ_NVM_PASS_COMP_STAMP_IDENTICAL_CODE 0x1
1385#define ICE_AQ_NVM_PASS_COMP_STAMP_LOWER 0x2
1386#define ICE_AQ_NVM_PASS_COMP_INVALID_STAMP_CODE 0x3
1387#define ICE_AQ_NVM_PASS_COMP_CONFLICT_CODE 0x4
1388#define ICE_AQ_NVM_PASS_COMP_PRE_REQ_NOT_MET_CODE 0x5
1389#define ICE_AQ_NVM_PASS_COMP_NOT_SUPPORTED_CODE 0x6
1390#define ICE_AQ_NVM_PASS_COMP_CANNOT_DOWNGRADE_CODE 0x7
1391#define ICE_AQ_NVM_PASS_COMP_INCOMPLETE_IMAGE_CODE 0x8
1392#define ICE_AQ_NVM_PASS_COMP_VER_STR_IDENTICAL_CODE 0xA
1393#define ICE_AQ_NVM_PASS_COMP_VER_STR_LOWER_CODE 0xB
1394 u8 reserved;
1395 u8 transfer_flag;
1396#define ICE_AQ_NVM_PASS_COMP_TBL_START 0x1
1397#define ICE_AQ_NVM_PASS_COMP_TBL_MIDDLE 0x2
1398#define ICE_AQ_NVM_PASS_COMP_TBL_END 0x4
1399#define ICE_AQ_NVM_PASS_COMP_TBL_START_AND_END 0x5
1400 __le32 reserved1;
1401 __le32 addr_high;
1402 __le32 addr_low;
1403};
1404
1405struct ice_aqc_nvm_comp_tbl {
1406 __le16 comp_class;
1407#define NVM_COMP_CLASS_ALL_FW 0x000A
1408
1409 __le16 comp_id;
1410#define NVM_COMP_ID_OROM 0x5
1411#define NVM_COMP_ID_NVM 0x6
1412#define NVM_COMP_ID_NETLIST 0x8
1413
1414 u8 comp_class_idx;
1415#define FWU_COMP_CLASS_IDX_NOT_USE 0x0
1416
1417 __le32 comp_cmp_stamp;
1418 u8 cvs_type;
1419#define NVM_CVS_TYPE_ASCII 0x1
1420
1421 u8 cvs_len;
1422 u8 cvs[]; /* Component Version String */
1423} __packed;
1424
1425/**
1426 * Send to PF command (indirect 0x0801) ID is only used by PF
1427 *
1428 * Send to VF command (indirect 0x0802) ID is only used by PF
1429 *
1430 */
1431struct ice_aqc_pf_vf_msg {
1432 __le32 id;
1433 u32 reserved;
1434 __le32 addr_high;
1435 __le32 addr_low;
1436};
1437
1438/* Get LLDP MIB (indirect 0x0A00)
1439 * Note: This is also used by the LLDP MIB Change Event (0x0A01)
1440 * as the format is the same.
1441 */
1442struct ice_aqc_lldp_get_mib {
1443 u8 type;
1444#define ICE_AQ_LLDP_MIB_TYPE_S 0
1445#define ICE_AQ_LLDP_MIB_TYPE_M (0x3 << ICE_AQ_LLDP_MIB_TYPE_S)
1446#define ICE_AQ_LLDP_MIB_LOCAL 0
1447#define ICE_AQ_LLDP_MIB_REMOTE 1
1448#define ICE_AQ_LLDP_MIB_LOCAL_AND_REMOTE 2
1449#define ICE_AQ_LLDP_BRID_TYPE_S 2
1450#define ICE_AQ_LLDP_BRID_TYPE_M (0x3 << ICE_AQ_LLDP_BRID_TYPE_S)
1451#define ICE_AQ_LLDP_BRID_TYPE_NEAREST_BRID 0
1452#define ICE_AQ_LLDP_BRID_TYPE_NON_TPMR 1
1453/* Tx pause flags in the 0xA01 event use ICE_AQ_LLDP_TX_* */
1454#define ICE_AQ_LLDP_TX_S 0x4
1455#define ICE_AQ_LLDP_TX_M (0x03 << ICE_AQ_LLDP_TX_S)
1456#define ICE_AQ_LLDP_TX_ACTIVE 0
1457#define ICE_AQ_LLDP_TX_SUSPENDED 1
1458#define ICE_AQ_LLDP_TX_FLUSHED 3
1459/* The following bytes are reserved for the Get LLDP MIB command (0x0A00)
1460 * and in the LLDP MIB Change Event (0x0A01). They are valid for the
1461 * Get LLDP MIB (0x0A00) response only.
1462 */
1463 u8 reserved1;
1464 __le16 local_len;
1465 __le16 remote_len;
1466 u8 reserved2[2];
1467 __le32 addr_high;
1468 __le32 addr_low;
1469};
1470
1471/* Configure LLDP MIB Change Event (direct 0x0A01) */
1472/* For MIB Change Event use ice_aqc_lldp_get_mib structure above */
1473struct ice_aqc_lldp_set_mib_change {
1474 u8 command;
1475#define ICE_AQ_LLDP_MIB_UPDATE_ENABLE 0x0
1476#define ICE_AQ_LLDP_MIB_UPDATE_DIS 0x1
1477 u8 reserved[15];
1478};
1479
1480/* Stop LLDP (direct 0x0A05) */
1481struct ice_aqc_lldp_stop {
1482 u8 command;
1483#define ICE_AQ_LLDP_AGENT_STATE_MASK BIT(0)
1484#define ICE_AQ_LLDP_AGENT_STOP 0x0
1485#define ICE_AQ_LLDP_AGENT_SHUTDOWN ICE_AQ_LLDP_AGENT_STATE_MASK
1486#define ICE_AQ_LLDP_AGENT_PERSIST_DIS BIT(1)
1487 u8 reserved[15];
1488};
1489
1490/* Start LLDP (direct 0x0A06) */
1491struct ice_aqc_lldp_start {
1492 u8 command;
1493#define ICE_AQ_LLDP_AGENT_START BIT(0)
1494#define ICE_AQ_LLDP_AGENT_PERSIST_ENA BIT(1)
1495 u8 reserved[15];
1496};
1497
1498/* Get CEE DCBX Oper Config (0x0A07)
1499 * The command uses the generic descriptor struct and
1500 * returns the struct below as an indirect response.
1501 */
1502struct ice_aqc_get_cee_dcb_cfg_resp {
1503 u8 oper_num_tc;
1504 u8 oper_prio_tc[4];
1505 u8 oper_tc_bw[8];
1506 u8 oper_pfc_en;
1507 __le16 oper_app_prio;
1508#define ICE_AQC_CEE_APP_FCOE_S 0
1509#define ICE_AQC_CEE_APP_FCOE_M (0x7 << ICE_AQC_CEE_APP_FCOE_S)
1510#define ICE_AQC_CEE_APP_ISCSI_S 3
1511#define ICE_AQC_CEE_APP_ISCSI_M (0x7 << ICE_AQC_CEE_APP_ISCSI_S)
1512#define ICE_AQC_CEE_APP_FIP_S 8
1513#define ICE_AQC_CEE_APP_FIP_M (0x7 << ICE_AQC_CEE_APP_FIP_S)
1514 __le32 tlv_status;
1515#define ICE_AQC_CEE_PG_STATUS_S 0
1516#define ICE_AQC_CEE_PG_STATUS_M (0x7 << ICE_AQC_CEE_PG_STATUS_S)
1517#define ICE_AQC_CEE_PFC_STATUS_S 3
1518#define ICE_AQC_CEE_PFC_STATUS_M (0x7 << ICE_AQC_CEE_PFC_STATUS_S)
1519#define ICE_AQC_CEE_FCOE_STATUS_S 8
1520#define ICE_AQC_CEE_FCOE_STATUS_M (0x7 << ICE_AQC_CEE_FCOE_STATUS_S)
1521#define ICE_AQC_CEE_ISCSI_STATUS_S 11
1522#define ICE_AQC_CEE_ISCSI_STATUS_M (0x7 << ICE_AQC_CEE_ISCSI_STATUS_S)
1523#define ICE_AQC_CEE_FIP_STATUS_S 16
1524#define ICE_AQC_CEE_FIP_STATUS_M (0x7 << ICE_AQC_CEE_FIP_STATUS_S)
1525 u8 reserved[12];
1526};
1527
1528/* Set Local LLDP MIB (indirect 0x0A08)
1529 * Used to replace the local MIB of a given LLDP agent. e.g. DCBX
1530 */
1531struct ice_aqc_lldp_set_local_mib {
1532 u8 type;
1533#define SET_LOCAL_MIB_TYPE_DCBX_M BIT(0)
1534#define SET_LOCAL_MIB_TYPE_LOCAL_MIB 0
1535#define SET_LOCAL_MIB_TYPE_CEE_M BIT(1)
1536#define SET_LOCAL_MIB_TYPE_CEE_WILLING 0
1537#define SET_LOCAL_MIB_TYPE_CEE_NON_WILLING SET_LOCAL_MIB_TYPE_CEE_M
1538 u8 reserved0;
1539 __le16 length;
1540 u8 reserved1[4];
1541 __le32 addr_high;
1542 __le32 addr_low;
1543};
1544
1545/* Stop/Start LLDP Agent (direct 0x0A09)
1546 * Used for stopping/starting specific LLDP agent. e.g. DCBX.
1547 * The same structure is used for the response, with the command field
1548 * being used as the status field.
1549 */
1550struct ice_aqc_lldp_stop_start_specific_agent {
1551 u8 command;
1552#define ICE_AQC_START_STOP_AGENT_M BIT(0)
1553#define ICE_AQC_START_STOP_AGENT_STOP_DCBX 0
1554#define ICE_AQC_START_STOP_AGENT_START_DCBX ICE_AQC_START_STOP_AGENT_M
1555 u8 reserved[15];
1556};
1557
1558/* Get/Set RSS key (indirect 0x0B04/0x0B02) */
1559struct ice_aqc_get_set_rss_key {
1560#define ICE_AQC_GSET_RSS_KEY_VSI_VALID BIT(15)
1561#define ICE_AQC_GSET_RSS_KEY_VSI_ID_S 0
1562#define ICE_AQC_GSET_RSS_KEY_VSI_ID_M (0x3FF << ICE_AQC_GSET_RSS_KEY_VSI_ID_S)
1563 __le16 vsi_id;
1564 u8 reserved[6];
1565 __le32 addr_high;
1566 __le32 addr_low;
1567};
1568
1569#define ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE 0x28
1570#define ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE 0xC
1571#define ICE_GET_SET_RSS_KEY_EXTEND_KEY_SIZE \
1572 (ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE + \
1573 ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE)
1574
1575struct ice_aqc_get_set_rss_keys {
1576 u8 standard_rss_key[ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE];
1577 u8 extended_hash_key[ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE];
1578};
1579
1580/* Get/Set RSS LUT (indirect 0x0B05/0x0B03) */
1581struct ice_aqc_get_set_rss_lut {
1582#define ICE_AQC_GSET_RSS_LUT_VSI_VALID BIT(15)
1583#define ICE_AQC_GSET_RSS_LUT_VSI_ID_S 0
1584#define ICE_AQC_GSET_RSS_LUT_VSI_ID_M (0x3FF << ICE_AQC_GSET_RSS_LUT_VSI_ID_S)
1585 __le16 vsi_id;
1586#define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S 0
1587#define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M \
1588 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S)
1589
1590#define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI 0
1591#define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF 1
1592#define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL 2
1593
1594#define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S 2
1595#define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M \
1596 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S)
1597
1598#define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 128
1599#define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG 0
1600#define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 512
1601#define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG 1
1602#define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K 2048
1603#define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG 2
1604
1605#define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S 4
1606#define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M \
1607 (0xF << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S)
1608
1609 __le16 flags;
1610 __le32 reserved;
1611 __le32 addr_high;
1612 __le32 addr_low;
1613};
1614
1615/* Add Tx LAN Queues (indirect 0x0C30) */
1616struct ice_aqc_add_txqs {
1617 u8 num_qgrps;
1618 u8 reserved[3];
1619 __le32 reserved1;
1620 __le32 addr_high;
1621 __le32 addr_low;
1622};
1623
1624/* This is the descriptor of each queue entry for the Add Tx LAN Queues
1625 * command (0x0C30). Only used within struct ice_aqc_add_tx_qgrp.
1626 */
1627struct ice_aqc_add_txqs_perq {
1628 __le16 txq_id;
1629 u8 rsvd[2];
1630 __le32 q_teid;
1631 u8 txq_ctx[22];
1632 u8 rsvd2[2];
1633 struct ice_aqc_txsched_elem info;
1634};
1635
1636/* The format of the command buffer for Add Tx LAN Queues (0x0C30)
1637 * is an array of the following structs. Please note that the length of
1638 * each struct ice_aqc_add_tx_qgrp is variable due
1639 * to the variable number of queues in each group!
1640 */
1641struct ice_aqc_add_tx_qgrp {
1642 __le32 parent_teid;
1643 u8 num_txqs;
1644 u8 rsvd[3];
1645 struct ice_aqc_add_txqs_perq txqs[];
1646};
1647
1648/* Disable Tx LAN Queues (indirect 0x0C31) */
1649struct ice_aqc_dis_txqs {
1650 u8 cmd_type;
1651#define ICE_AQC_Q_DIS_CMD_S 0
1652#define ICE_AQC_Q_DIS_CMD_M (0x3 << ICE_AQC_Q_DIS_CMD_S)
1653#define ICE_AQC_Q_DIS_CMD_NO_FUNC_RESET (0 << ICE_AQC_Q_DIS_CMD_S)
1654#define ICE_AQC_Q_DIS_CMD_VM_RESET BIT(ICE_AQC_Q_DIS_CMD_S)
1655#define ICE_AQC_Q_DIS_CMD_VF_RESET (2 << ICE_AQC_Q_DIS_CMD_S)
1656#define ICE_AQC_Q_DIS_CMD_PF_RESET (3 << ICE_AQC_Q_DIS_CMD_S)
1657#define ICE_AQC_Q_DIS_CMD_SUBSEQ_CALL BIT(2)
1658#define ICE_AQC_Q_DIS_CMD_FLUSH_PIPE BIT(3)
1659 u8 num_entries;
1660 __le16 vmvf_and_timeout;
1661#define ICE_AQC_Q_DIS_VMVF_NUM_S 0
1662#define ICE_AQC_Q_DIS_VMVF_NUM_M (0x3FF << ICE_AQC_Q_DIS_VMVF_NUM_S)
1663#define ICE_AQC_Q_DIS_TIMEOUT_S 10
1664#define ICE_AQC_Q_DIS_TIMEOUT_M (0x3F << ICE_AQC_Q_DIS_TIMEOUT_S)
1665 __le32 blocked_cgds;
1666 __le32 addr_high;
1667 __le32 addr_low;
1668};
1669
1670/* The buffer for Disable Tx LAN Queues (indirect 0x0C31)
1671 * contains the following structures, arrayed one after the
1672 * other.
1673 * Note: Since the q_id is 16 bits wide, if the
1674 * number of queues is even, then 2 bytes of alignment MUST be
1675 * added before the start of the next group, to allow correct
1676 * alignment of the parent_teid field.
1677 */
1678struct ice_aqc_dis_txq_item {
1679 __le32 parent_teid;
1680 u8 num_qs;
1681 u8 rsvd;
1682 /* The length of the q_id array varies according to num_qs */
1683#define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S 15
1684#define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_LAN_Q \
1685 (0 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S)
1686#define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET \
1687 (1 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S)
1688 __le16 q_id[];
1689} __packed;
1690
1691/* Configure Firmware Logging Command (indirect 0xFF09)
1692 * Logging Information Read Response (indirect 0xFF10)
1693 * Note: The 0xFF10 command has no input parameters.
1694 */
1695struct ice_aqc_fw_logging {
1696 u8 log_ctrl;
1697#define ICE_AQC_FW_LOG_AQ_EN BIT(0)
1698#define ICE_AQC_FW_LOG_UART_EN BIT(1)
1699 u8 rsvd0;
1700 u8 log_ctrl_valid; /* Not used by 0xFF10 Response */
1701#define ICE_AQC_FW_LOG_AQ_VALID BIT(0)
1702#define ICE_AQC_FW_LOG_UART_VALID BIT(1)
1703 u8 rsvd1[5];
1704 __le32 addr_high;
1705 __le32 addr_low;
1706};
1707
1708enum ice_aqc_fw_logging_mod {
1709 ICE_AQC_FW_LOG_ID_GENERAL = 0,
1710 ICE_AQC_FW_LOG_ID_CTRL,
1711 ICE_AQC_FW_LOG_ID_LINK,
1712 ICE_AQC_FW_LOG_ID_LINK_TOPO,
1713 ICE_AQC_FW_LOG_ID_DNL,
1714 ICE_AQC_FW_LOG_ID_I2C,
1715 ICE_AQC_FW_LOG_ID_SDP,
1716 ICE_AQC_FW_LOG_ID_MDIO,
1717 ICE_AQC_FW_LOG_ID_ADMINQ,
1718 ICE_AQC_FW_LOG_ID_HDMA,
1719 ICE_AQC_FW_LOG_ID_LLDP,
1720 ICE_AQC_FW_LOG_ID_DCBX,
1721 ICE_AQC_FW_LOG_ID_DCB,
1722 ICE_AQC_FW_LOG_ID_NETPROXY,
1723 ICE_AQC_FW_LOG_ID_NVM,
1724 ICE_AQC_FW_LOG_ID_AUTH,
1725 ICE_AQC_FW_LOG_ID_VPD,
1726 ICE_AQC_FW_LOG_ID_IOSF,
1727 ICE_AQC_FW_LOG_ID_PARSER,
1728 ICE_AQC_FW_LOG_ID_SW,
1729 ICE_AQC_FW_LOG_ID_SCHEDULER,
1730 ICE_AQC_FW_LOG_ID_TXQ,
1731 ICE_AQC_FW_LOG_ID_RSVD,
1732 ICE_AQC_FW_LOG_ID_POST,
1733 ICE_AQC_FW_LOG_ID_WATCHDOG,
1734 ICE_AQC_FW_LOG_ID_TASK_DISPATCH,
1735 ICE_AQC_FW_LOG_ID_MNG,
1736 ICE_AQC_FW_LOG_ID_MAX,
1737};
1738
1739/* Defines for both above FW logging command/response buffers */
1740#define ICE_AQC_FW_LOG_ID_S 0
1741#define ICE_AQC_FW_LOG_ID_M (0xFFF << ICE_AQC_FW_LOG_ID_S)
1742
1743#define ICE_AQC_FW_LOG_CONF_SUCCESS 0 /* Used by response */
1744#define ICE_AQC_FW_LOG_CONF_BAD_INDX BIT(12) /* Used by response */
1745
1746#define ICE_AQC_FW_LOG_EN_S 12
1747#define ICE_AQC_FW_LOG_EN_M (0xF << ICE_AQC_FW_LOG_EN_S)
1748#define ICE_AQC_FW_LOG_INFO_EN BIT(12) /* Used by command */
1749#define ICE_AQC_FW_LOG_INIT_EN BIT(13) /* Used by command */
1750#define ICE_AQC_FW_LOG_FLOW_EN BIT(14) /* Used by command */
1751#define ICE_AQC_FW_LOG_ERR_EN BIT(15) /* Used by command */
1752
1753/* Get/Clear FW Log (indirect 0xFF11) */
1754struct ice_aqc_get_clear_fw_log {
1755 u8 flags;
1756#define ICE_AQC_FW_LOG_CLEAR BIT(0)
1757#define ICE_AQC_FW_LOG_MORE_DATA_AVAIL BIT(1)
1758 u8 rsvd1[7];
1759 __le32 addr_high;
1760 __le32 addr_low;
1761};
1762
1763/* Download Package (indirect 0x0C40) */
1764/* Also used for Update Package (indirect 0x0C42) */
1765struct ice_aqc_download_pkg {
1766 u8 flags;
1767#define ICE_AQC_DOWNLOAD_PKG_LAST_BUF 0x01
1768 u8 reserved[3];
1769 __le32 reserved1;
1770 __le32 addr_high;
1771 __le32 addr_low;
1772};
1773
1774struct ice_aqc_download_pkg_resp {
1775 __le32 error_offset;
1776 __le32 error_info;
1777 __le32 addr_high;
1778 __le32 addr_low;
1779};
1780
1781/* Get Package Info List (indirect 0x0C43) */
1782struct ice_aqc_get_pkg_info_list {
1783 __le32 reserved1;
1784 __le32 reserved2;
1785 __le32 addr_high;
1786 __le32 addr_low;
1787};
1788
1789/* Version format for packages */
1790struct ice_pkg_ver {
1791 u8 major;
1792 u8 minor;
1793 u8 update;
1794 u8 draft;
1795};
1796
1797#define ICE_PKG_NAME_SIZE 32
1798#define ICE_SEG_NAME_SIZE 28
1799
1800struct ice_aqc_get_pkg_info {
1801 struct ice_pkg_ver ver;
1802 char name[ICE_SEG_NAME_SIZE];
1803 __le32 track_id;
1804 u8 is_in_nvm;
1805 u8 is_active;
1806 u8 is_active_at_boot;
1807 u8 is_modified;
1808};
1809
1810/* Get Package Info List response buffer format (0x0C43) */
1811struct ice_aqc_get_pkg_info_resp {
1812 __le32 count;
1813 struct ice_aqc_get_pkg_info pkg_info[];
1814};
1815
1816/* Lan Queue Overflow Event (direct, 0x1001) */
1817struct ice_aqc_event_lan_overflow {
1818 __le32 prtdcb_ruptq;
1819 __le32 qtx_ctl;
1820 u8 reserved[8];
1821};
1822
1823/**
1824 * struct ice_aq_desc - Admin Queue (AQ) descriptor
1825 * @flags: ICE_AQ_FLAG_* flags
1826 * @opcode: AQ command opcode
1827 * @datalen: length in bytes of indirect/external data buffer
1828 * @retval: return value from firmware
1829 * @cookie_h: opaque data high-half
1830 * @cookie_l: opaque data low-half
1831 * @params: command-specific parameters
1832 *
1833 * Descriptor format for commands the driver posts on the Admin Transmit Queue
1834 * (ATQ). The firmware writes back onto the command descriptor and returns
1835 * the result of the command. Asynchronous events that are not an immediate
1836 * result of the command are written to the Admin Receive Queue (ARQ) using
1837 * the same descriptor format. Descriptors are in little-endian notation with
1838 * 32-bit words.
1839 */
1840struct ice_aq_desc {
1841 __le16 flags;
1842 __le16 opcode;
1843 __le16 datalen;
1844 __le16 retval;
1845 __le32 cookie_high;
1846 __le32 cookie_low;
1847 union {
1848 u8 raw[16];
1849 struct ice_aqc_generic generic;
1850 struct ice_aqc_get_ver get_ver;
1851 struct ice_aqc_driver_ver driver_ver;
1852 struct ice_aqc_q_shutdown q_shutdown;
1853 struct ice_aqc_req_res res_owner;
1854 struct ice_aqc_manage_mac_read mac_read;
1855 struct ice_aqc_manage_mac_write mac_write;
1856 struct ice_aqc_clear_pxe clear_pxe;
1857 struct ice_aqc_list_caps get_cap;
1858 struct ice_aqc_get_phy_caps get_phy;
1859 struct ice_aqc_set_phy_cfg set_phy;
1860 struct ice_aqc_restart_an restart_an;
1861 struct ice_aqc_sff_eeprom read_write_sff_param;
1862 struct ice_aqc_set_port_id_led set_port_id_led;
1863 struct ice_aqc_get_sw_cfg get_sw_conf;
1864 struct ice_aqc_sw_rules sw_rules;
1865 struct ice_aqc_get_topo get_topo;
1866 struct ice_aqc_sched_elem_cmd sched_elem_cmd;
1867 struct ice_aqc_query_txsched_res query_sched_res;
1868 struct ice_aqc_query_port_ets port_ets;
1869 struct ice_aqc_rl_profile rl_profile;
1870 struct ice_aqc_nvm nvm;
1871 struct ice_aqc_nvm_checksum nvm_checksum;
1872 struct ice_aqc_nvm_pkg_data pkg_data;
1873 struct ice_aqc_nvm_pass_comp_tbl pass_comp_tbl;
1874 struct ice_aqc_pf_vf_msg virt;
1875 struct ice_aqc_lldp_get_mib lldp_get_mib;
1876 struct ice_aqc_lldp_set_mib_change lldp_set_event;
1877 struct ice_aqc_lldp_stop lldp_stop;
1878 struct ice_aqc_lldp_start lldp_start;
1879 struct ice_aqc_lldp_set_local_mib lldp_set_mib;
1880 struct ice_aqc_lldp_stop_start_specific_agent lldp_agent_ctrl;
1881 struct ice_aqc_get_set_rss_lut get_set_rss_lut;
1882 struct ice_aqc_get_set_rss_key get_set_rss_key;
1883 struct ice_aqc_add_txqs add_txqs;
1884 struct ice_aqc_dis_txqs dis_txqs;
1885 struct ice_aqc_add_get_update_free_vsi vsi_cmd;
1886 struct ice_aqc_add_update_free_vsi_resp add_update_free_vsi_res;
1887 struct ice_aqc_fw_logging fw_logging;
1888 struct ice_aqc_get_clear_fw_log get_clear_fw_log;
1889 struct ice_aqc_download_pkg download_pkg;
1890 struct ice_aqc_set_mac_lb set_mac_lb;
1891 struct ice_aqc_alloc_free_res_cmd sw_res_ctrl;
1892 struct ice_aqc_set_mac_cfg set_mac_cfg;
1893 struct ice_aqc_set_event_mask set_event_mask;
1894 struct ice_aqc_get_link_status get_link_status;
1895 struct ice_aqc_event_lan_overflow lan_overflow;
1896 struct ice_aqc_get_link_topo get_link_topo;
1897 } params;
1898};
1899
1900/* FW defined boundary for a large buffer, 4k >= Large buffer > 512 bytes */
1901#define ICE_AQ_LG_BUF 512
1902
1903#define ICE_AQ_FLAG_ERR_S 2
1904#define ICE_AQ_FLAG_LB_S 9
1905#define ICE_AQ_FLAG_RD_S 10
1906#define ICE_AQ_FLAG_BUF_S 12
1907#define ICE_AQ_FLAG_SI_S 13
1908
1909#define ICE_AQ_FLAG_ERR BIT(ICE_AQ_FLAG_ERR_S) /* 0x4 */
1910#define ICE_AQ_FLAG_LB BIT(ICE_AQ_FLAG_LB_S) /* 0x200 */
1911#define ICE_AQ_FLAG_RD BIT(ICE_AQ_FLAG_RD_S) /* 0x400 */
1912#define ICE_AQ_FLAG_BUF BIT(ICE_AQ_FLAG_BUF_S) /* 0x1000 */
1913#define ICE_AQ_FLAG_SI BIT(ICE_AQ_FLAG_SI_S) /* 0x2000 */
1914
1915/* error codes */
1916enum ice_aq_err {
1917 ICE_AQ_RC_OK = 0, /* Success */
1918 ICE_AQ_RC_EPERM = 1, /* Operation not permitted */
1919 ICE_AQ_RC_ENOENT = 2, /* No such element */
1920 ICE_AQ_RC_ENOMEM = 9, /* Out of memory */
1921 ICE_AQ_RC_EBUSY = 12, /* Device or resource busy */
1922 ICE_AQ_RC_EEXIST = 13, /* Object already exists */
1923 ICE_AQ_RC_EINVAL = 14, /* Invalid argument */
1924 ICE_AQ_RC_ENOSPC = 16, /* No space left or allocation failure */
1925 ICE_AQ_RC_ENOSYS = 17, /* Function not implemented */
1926 ICE_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */
1927 ICE_AQ_RC_ENOSEC = 24, /* Missing security manifest */
1928 ICE_AQ_RC_EBADSIG = 25, /* Bad RSA signature */
1929 ICE_AQ_RC_ESVN = 26, /* SVN number prohibits this package */
1930 ICE_AQ_RC_EBADMAN = 27, /* Manifest hash mismatch */
1931 ICE_AQ_RC_EBADBUF = 28, /* Buffer hash mismatches manifest */
1932};
1933
1934/* Admin Queue command opcodes */
1935enum ice_adminq_opc {
1936 /* AQ commands */
1937 ice_aqc_opc_get_ver = 0x0001,
1938 ice_aqc_opc_driver_ver = 0x0002,
1939 ice_aqc_opc_q_shutdown = 0x0003,
1940
1941 /* resource ownership */
1942 ice_aqc_opc_req_res = 0x0008,
1943 ice_aqc_opc_release_res = 0x0009,
1944
1945 /* device/function capabilities */
1946 ice_aqc_opc_list_func_caps = 0x000A,
1947 ice_aqc_opc_list_dev_caps = 0x000B,
1948
1949 /* manage MAC address */
1950 ice_aqc_opc_manage_mac_read = 0x0107,
1951 ice_aqc_opc_manage_mac_write = 0x0108,
1952
1953 /* PXE */
1954 ice_aqc_opc_clear_pxe_mode = 0x0110,
1955
1956 /* internal switch commands */
1957 ice_aqc_opc_get_sw_cfg = 0x0200,
1958
1959 /* Alloc/Free/Get Resources */
1960 ice_aqc_opc_alloc_res = 0x0208,
1961 ice_aqc_opc_free_res = 0x0209,
1962
1963 /* VSI commands */
1964 ice_aqc_opc_add_vsi = 0x0210,
1965 ice_aqc_opc_update_vsi = 0x0211,
1966 ice_aqc_opc_free_vsi = 0x0213,
1967
1968 /* switch rules population commands */
1969 ice_aqc_opc_add_sw_rules = 0x02A0,
1970 ice_aqc_opc_update_sw_rules = 0x02A1,
1971 ice_aqc_opc_remove_sw_rules = 0x02A2,
1972
1973 ice_aqc_opc_clear_pf_cfg = 0x02A4,
1974
1975 /* transmit scheduler commands */
1976 ice_aqc_opc_get_dflt_topo = 0x0400,
1977 ice_aqc_opc_add_sched_elems = 0x0401,
1978 ice_aqc_opc_cfg_sched_elems = 0x0403,
1979 ice_aqc_opc_get_sched_elems = 0x0404,
1980 ice_aqc_opc_suspend_sched_elems = 0x0409,
1981 ice_aqc_opc_resume_sched_elems = 0x040A,
1982 ice_aqc_opc_query_port_ets = 0x040E,
1983 ice_aqc_opc_delete_sched_elems = 0x040F,
1984 ice_aqc_opc_add_rl_profiles = 0x0410,
1985 ice_aqc_opc_query_sched_res = 0x0412,
1986 ice_aqc_opc_remove_rl_profiles = 0x0415,
1987
1988 /* PHY commands */
1989 ice_aqc_opc_get_phy_caps = 0x0600,
1990 ice_aqc_opc_set_phy_cfg = 0x0601,
1991 ice_aqc_opc_set_mac_cfg = 0x0603,
1992 ice_aqc_opc_restart_an = 0x0605,
1993 ice_aqc_opc_get_link_status = 0x0607,
1994 ice_aqc_opc_set_event_mask = 0x0613,
1995 ice_aqc_opc_set_mac_lb = 0x0620,
1996 ice_aqc_opc_get_link_topo = 0x06E0,
1997 ice_aqc_opc_set_port_id_led = 0x06E9,
1998 ice_aqc_opc_sff_eeprom = 0x06EE,
1999
2000 /* NVM commands */
2001 ice_aqc_opc_nvm_read = 0x0701,
2002 ice_aqc_opc_nvm_erase = 0x0702,
2003 ice_aqc_opc_nvm_write = 0x0703,
2004 ice_aqc_opc_nvm_checksum = 0x0706,
2005 ice_aqc_opc_nvm_write_activate = 0x0707,
2006 ice_aqc_opc_nvm_update_empr = 0x0709,
2007 ice_aqc_opc_nvm_pkg_data = 0x070A,
2008 ice_aqc_opc_nvm_pass_component_tbl = 0x070B,
2009
2010 /* PF/VF mailbox commands */
2011 ice_mbx_opc_send_msg_to_pf = 0x0801,
2012 ice_mbx_opc_send_msg_to_vf = 0x0802,
2013 /* LLDP commands */
2014 ice_aqc_opc_lldp_get_mib = 0x0A00,
2015 ice_aqc_opc_lldp_set_mib_change = 0x0A01,
2016 ice_aqc_opc_lldp_stop = 0x0A05,
2017 ice_aqc_opc_lldp_start = 0x0A06,
2018 ice_aqc_opc_get_cee_dcb_cfg = 0x0A07,
2019 ice_aqc_opc_lldp_set_local_mib = 0x0A08,
2020 ice_aqc_opc_lldp_stop_start_specific_agent = 0x0A09,
2021
2022 /* RSS commands */
2023 ice_aqc_opc_set_rss_key = 0x0B02,
2024 ice_aqc_opc_set_rss_lut = 0x0B03,
2025 ice_aqc_opc_get_rss_key = 0x0B04,
2026 ice_aqc_opc_get_rss_lut = 0x0B05,
2027
2028 /* Tx queue handling commands/events */
2029 ice_aqc_opc_add_txqs = 0x0C30,
2030 ice_aqc_opc_dis_txqs = 0x0C31,
2031
2032 /* package commands */
2033 ice_aqc_opc_download_pkg = 0x0C40,
2034 ice_aqc_opc_update_pkg = 0x0C42,
2035 ice_aqc_opc_get_pkg_info_list = 0x0C43,
2036
2037 /* Standalone Commands/Events */
2038 ice_aqc_opc_event_lan_overflow = 0x1001,
2039
2040 /* debug commands */
2041 ice_aqc_opc_fw_logging = 0xFF09,
2042 ice_aqc_opc_fw_logging_info = 0xFF10,
2043};
2044
2045#endif /* _ICE_ADMINQ_CMD_H_ */