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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * driver/mfd/asic3.c
4 *
5 * Compaq ASIC3 support.
6 *
7 * Copyright 2001 Compaq Computer Corporation.
8 * Copyright 2004-2005 Phil Blundell
9 * Copyright 2007-2008 OpenedHand Ltd.
10 *
11 * Authors: Phil Blundell <pb@handhelds.org>,
12 * Samuel Ortiz <sameo@openedhand.com>
13 */
14
15#include <linux/kernel.h>
16#include <linux/delay.h>
17#include <linux/irq.h>
18#include <linux/gpio/driver.h>
19#include <linux/export.h>
20#include <linux/io.h>
21#include <linux/slab.h>
22#include <linux/spinlock.h>
23#include <linux/platform_device.h>
24
25#include <linux/mfd/asic3.h>
26#include <linux/mfd/core.h>
27#include <linux/mfd/ds1wm.h>
28#include <linux/mfd/tmio.h>
29
30#include <linux/mmc/host.h>
31
32enum {
33 ASIC3_CLOCK_SPI,
34 ASIC3_CLOCK_OWM,
35 ASIC3_CLOCK_PWM0,
36 ASIC3_CLOCK_PWM1,
37 ASIC3_CLOCK_LED0,
38 ASIC3_CLOCK_LED1,
39 ASIC3_CLOCK_LED2,
40 ASIC3_CLOCK_SD_HOST,
41 ASIC3_CLOCK_SD_BUS,
42 ASIC3_CLOCK_SMBUS,
43 ASIC3_CLOCK_EX0,
44 ASIC3_CLOCK_EX1,
45};
46
47struct asic3_clk {
48 int enabled;
49 unsigned int cdex;
50 unsigned long rate;
51};
52
53#define INIT_CDEX(_name, _rate) \
54 [ASIC3_CLOCK_##_name] = { \
55 .cdex = CLOCK_CDEX_##_name, \
56 .rate = _rate, \
57 }
58
59static struct asic3_clk asic3_clk_init[] __initdata = {
60 INIT_CDEX(SPI, 0),
61 INIT_CDEX(OWM, 5000000),
62 INIT_CDEX(PWM0, 0),
63 INIT_CDEX(PWM1, 0),
64 INIT_CDEX(LED0, 0),
65 INIT_CDEX(LED1, 0),
66 INIT_CDEX(LED2, 0),
67 INIT_CDEX(SD_HOST, 24576000),
68 INIT_CDEX(SD_BUS, 12288000),
69 INIT_CDEX(SMBUS, 0),
70 INIT_CDEX(EX0, 32768),
71 INIT_CDEX(EX1, 24576000),
72};
73
74struct asic3 {
75 void __iomem *mapping;
76 unsigned int bus_shift;
77 unsigned int irq_nr;
78 unsigned int irq_base;
79 raw_spinlock_t lock;
80 u16 irq_bothedge[4];
81 struct gpio_chip gpio;
82 struct device *dev;
83 void __iomem *tmio_cnf;
84
85 struct asic3_clk clocks[ARRAY_SIZE(asic3_clk_init)];
86};
87
88static int asic3_gpio_get(struct gpio_chip *chip, unsigned offset);
89
90void asic3_write_register(struct asic3 *asic, unsigned int reg, u32 value)
91{
92 iowrite16(value, asic->mapping +
93 (reg >> asic->bus_shift));
94}
95EXPORT_SYMBOL_GPL(asic3_write_register);
96
97u32 asic3_read_register(struct asic3 *asic, unsigned int reg)
98{
99 return ioread16(asic->mapping +
100 (reg >> asic->bus_shift));
101}
102EXPORT_SYMBOL_GPL(asic3_read_register);
103
104static void asic3_set_register(struct asic3 *asic, u32 reg, u32 bits, bool set)
105{
106 unsigned long flags;
107 u32 val;
108
109 raw_spin_lock_irqsave(&asic->lock, flags);
110 val = asic3_read_register(asic, reg);
111 if (set)
112 val |= bits;
113 else
114 val &= ~bits;
115 asic3_write_register(asic, reg, val);
116 raw_spin_unlock_irqrestore(&asic->lock, flags);
117}
118
119/* IRQs */
120#define MAX_ASIC_ISR_LOOPS 20
121#define ASIC3_GPIO_BASE_INCR \
122 (ASIC3_GPIO_B_BASE - ASIC3_GPIO_A_BASE)
123
124static void asic3_irq_flip_edge(struct asic3 *asic,
125 u32 base, int bit)
126{
127 u16 edge;
128 unsigned long flags;
129
130 raw_spin_lock_irqsave(&asic->lock, flags);
131 edge = asic3_read_register(asic,
132 base + ASIC3_GPIO_EDGE_TRIGGER);
133 edge ^= bit;
134 asic3_write_register(asic,
135 base + ASIC3_GPIO_EDGE_TRIGGER, edge);
136 raw_spin_unlock_irqrestore(&asic->lock, flags);
137}
138
139static void asic3_irq_demux(struct irq_desc *desc)
140{
141 struct asic3 *asic = irq_desc_get_handler_data(desc);
142 struct irq_data *data = irq_desc_get_irq_data(desc);
143 int iter, i;
144 unsigned long flags;
145
146 data->chip->irq_ack(data);
147
148 for (iter = 0 ; iter < MAX_ASIC_ISR_LOOPS; iter++) {
149 u32 status;
150 int bank;
151
152 raw_spin_lock_irqsave(&asic->lock, flags);
153 status = asic3_read_register(asic,
154 ASIC3_OFFSET(INTR, P_INT_STAT));
155 raw_spin_unlock_irqrestore(&asic->lock, flags);
156
157 /* Check all ten register bits */
158 if ((status & 0x3ff) == 0)
159 break;
160
161 /* Handle GPIO IRQs */
162 for (bank = 0; bank < ASIC3_NUM_GPIO_BANKS; bank++) {
163 if (status & (1 << bank)) {
164 unsigned long base, istat;
165
166 base = ASIC3_GPIO_A_BASE
167 + bank * ASIC3_GPIO_BASE_INCR;
168 raw_spin_lock_irqsave(&asic->lock, flags);
169 istat = asic3_read_register(asic,
170 base +
171 ASIC3_GPIO_INT_STATUS);
172 /* Clearing IntStatus */
173 asic3_write_register(asic,
174 base +
175 ASIC3_GPIO_INT_STATUS, 0);
176 raw_spin_unlock_irqrestore(&asic->lock, flags);
177
178 for (i = 0; i < ASIC3_GPIOS_PER_BANK; i++) {
179 int bit = (1 << i);
180 unsigned int irqnr;
181
182 if (!(istat & bit))
183 continue;
184
185 irqnr = asic->irq_base +
186 (ASIC3_GPIOS_PER_BANK * bank)
187 + i;
188 generic_handle_irq(irqnr);
189 if (asic->irq_bothedge[bank] & bit)
190 asic3_irq_flip_edge(asic, base,
191 bit);
192 }
193 }
194 }
195
196 /* Handle remaining IRQs in the status register */
197 for (i = ASIC3_NUM_GPIOS; i < ASIC3_NR_IRQS; i++) {
198 /* They start at bit 4 and go up */
199 if (status & (1 << (i - ASIC3_NUM_GPIOS + 4)))
200 generic_handle_irq(asic->irq_base + i);
201 }
202 }
203
204 if (iter >= MAX_ASIC_ISR_LOOPS)
205 dev_err(asic->dev, "interrupt processing overrun\n");
206}
207
208static inline int asic3_irq_to_bank(struct asic3 *asic, int irq)
209{
210 int n;
211
212 n = (irq - asic->irq_base) >> 4;
213
214 return (n * (ASIC3_GPIO_B_BASE - ASIC3_GPIO_A_BASE));
215}
216
217static inline int asic3_irq_to_index(struct asic3 *asic, int irq)
218{
219 return (irq - asic->irq_base) & 0xf;
220}
221
222static void asic3_mask_gpio_irq(struct irq_data *data)
223{
224 struct asic3 *asic = irq_data_get_irq_chip_data(data);
225 u32 val, bank, index;
226 unsigned long flags;
227
228 bank = asic3_irq_to_bank(asic, data->irq);
229 index = asic3_irq_to_index(asic, data->irq);
230
231 raw_spin_lock_irqsave(&asic->lock, flags);
232 val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK);
233 val |= 1 << index;
234 asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val);
235 raw_spin_unlock_irqrestore(&asic->lock, flags);
236}
237
238static void asic3_mask_irq(struct irq_data *data)
239{
240 struct asic3 *asic = irq_data_get_irq_chip_data(data);
241 int regval;
242 unsigned long flags;
243
244 raw_spin_lock_irqsave(&asic->lock, flags);
245 regval = asic3_read_register(asic,
246 ASIC3_INTR_BASE +
247 ASIC3_INTR_INT_MASK);
248
249 regval &= ~(ASIC3_INTMASK_MASK0 <<
250 (data->irq - (asic->irq_base + ASIC3_NUM_GPIOS)));
251
252 asic3_write_register(asic,
253 ASIC3_INTR_BASE +
254 ASIC3_INTR_INT_MASK,
255 regval);
256 raw_spin_unlock_irqrestore(&asic->lock, flags);
257}
258
259static void asic3_unmask_gpio_irq(struct irq_data *data)
260{
261 struct asic3 *asic = irq_data_get_irq_chip_data(data);
262 u32 val, bank, index;
263 unsigned long flags;
264
265 bank = asic3_irq_to_bank(asic, data->irq);
266 index = asic3_irq_to_index(asic, data->irq);
267
268 raw_spin_lock_irqsave(&asic->lock, flags);
269 val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK);
270 val &= ~(1 << index);
271 asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val);
272 raw_spin_unlock_irqrestore(&asic->lock, flags);
273}
274
275static void asic3_unmask_irq(struct irq_data *data)
276{
277 struct asic3 *asic = irq_data_get_irq_chip_data(data);
278 int regval;
279 unsigned long flags;
280
281 raw_spin_lock_irqsave(&asic->lock, flags);
282 regval = asic3_read_register(asic,
283 ASIC3_INTR_BASE +
284 ASIC3_INTR_INT_MASK);
285
286 regval |= (ASIC3_INTMASK_MASK0 <<
287 (data->irq - (asic->irq_base + ASIC3_NUM_GPIOS)));
288
289 asic3_write_register(asic,
290 ASIC3_INTR_BASE +
291 ASIC3_INTR_INT_MASK,
292 regval);
293 raw_spin_unlock_irqrestore(&asic->lock, flags);
294}
295
296static int asic3_gpio_irq_type(struct irq_data *data, unsigned int type)
297{
298 struct asic3 *asic = irq_data_get_irq_chip_data(data);
299 u32 bank, index;
300 u16 trigger, level, edge, bit;
301 unsigned long flags;
302
303 bank = asic3_irq_to_bank(asic, data->irq);
304 index = asic3_irq_to_index(asic, data->irq);
305 bit = 1<<index;
306
307 raw_spin_lock_irqsave(&asic->lock, flags);
308 level = asic3_read_register(asic,
309 bank + ASIC3_GPIO_LEVEL_TRIGGER);
310 edge = asic3_read_register(asic,
311 bank + ASIC3_GPIO_EDGE_TRIGGER);
312 trigger = asic3_read_register(asic,
313 bank + ASIC3_GPIO_TRIGGER_TYPE);
314 asic->irq_bothedge[(data->irq - asic->irq_base) >> 4] &= ~bit;
315
316 if (type == IRQ_TYPE_EDGE_RISING) {
317 trigger |= bit;
318 edge |= bit;
319 } else if (type == IRQ_TYPE_EDGE_FALLING) {
320 trigger |= bit;
321 edge &= ~bit;
322 } else if (type == IRQ_TYPE_EDGE_BOTH) {
323 trigger |= bit;
324 if (asic3_gpio_get(&asic->gpio, data->irq - asic->irq_base))
325 edge &= ~bit;
326 else
327 edge |= bit;
328 asic->irq_bothedge[(data->irq - asic->irq_base) >> 4] |= bit;
329 } else if (type == IRQ_TYPE_LEVEL_LOW) {
330 trigger &= ~bit;
331 level &= ~bit;
332 } else if (type == IRQ_TYPE_LEVEL_HIGH) {
333 trigger &= ~bit;
334 level |= bit;
335 } else {
336 /*
337 * if type == IRQ_TYPE_NONE, we should mask interrupts, but
338 * be careful to not unmask them if mask was also called.
339 * Probably need internal state for mask.
340 */
341 dev_notice(asic->dev, "irq type not changed\n");
342 }
343 asic3_write_register(asic, bank + ASIC3_GPIO_LEVEL_TRIGGER,
344 level);
345 asic3_write_register(asic, bank + ASIC3_GPIO_EDGE_TRIGGER,
346 edge);
347 asic3_write_register(asic, bank + ASIC3_GPIO_TRIGGER_TYPE,
348 trigger);
349 raw_spin_unlock_irqrestore(&asic->lock, flags);
350 return 0;
351}
352
353static int asic3_gpio_irq_set_wake(struct irq_data *data, unsigned int on)
354{
355 struct asic3 *asic = irq_data_get_irq_chip_data(data);
356 u32 bank, index;
357 u16 bit;
358
359 bank = asic3_irq_to_bank(asic, data->irq);
360 index = asic3_irq_to_index(asic, data->irq);
361 bit = 1<<index;
362
363 asic3_set_register(asic, bank + ASIC3_GPIO_SLEEP_MASK, bit, !on);
364
365 return 0;
366}
367
368static struct irq_chip asic3_gpio_irq_chip = {
369 .name = "ASIC3-GPIO",
370 .irq_ack = asic3_mask_gpio_irq,
371 .irq_mask = asic3_mask_gpio_irq,
372 .irq_unmask = asic3_unmask_gpio_irq,
373 .irq_set_type = asic3_gpio_irq_type,
374 .irq_set_wake = asic3_gpio_irq_set_wake,
375};
376
377static struct irq_chip asic3_irq_chip = {
378 .name = "ASIC3",
379 .irq_ack = asic3_mask_irq,
380 .irq_mask = asic3_mask_irq,
381 .irq_unmask = asic3_unmask_irq,
382};
383
384static int __init asic3_irq_probe(struct platform_device *pdev)
385{
386 struct asic3 *asic = platform_get_drvdata(pdev);
387 unsigned long clksel = 0;
388 unsigned int irq, irq_base;
389 int ret;
390
391 ret = platform_get_irq(pdev, 0);
392 if (ret < 0)
393 return ret;
394 asic->irq_nr = ret;
395
396 /* turn on clock to IRQ controller */
397 clksel |= CLOCK_SEL_CX;
398 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL),
399 clksel);
400
401 irq_base = asic->irq_base;
402
403 for (irq = irq_base; irq < irq_base + ASIC3_NR_IRQS; irq++) {
404 if (irq < asic->irq_base + ASIC3_NUM_GPIOS)
405 irq_set_chip(irq, &asic3_gpio_irq_chip);
406 else
407 irq_set_chip(irq, &asic3_irq_chip);
408
409 irq_set_chip_data(irq, asic);
410 irq_set_handler(irq, handle_level_irq);
411 irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
412 }
413
414 asic3_write_register(asic, ASIC3_OFFSET(INTR, INT_MASK),
415 ASIC3_INTMASK_GINTMASK);
416
417 irq_set_chained_handler_and_data(asic->irq_nr, asic3_irq_demux, asic);
418 irq_set_irq_type(asic->irq_nr, IRQ_TYPE_EDGE_RISING);
419
420 return 0;
421}
422
423static void asic3_irq_remove(struct platform_device *pdev)
424{
425 struct asic3 *asic = platform_get_drvdata(pdev);
426 unsigned int irq, irq_base;
427
428 irq_base = asic->irq_base;
429
430 for (irq = irq_base; irq < irq_base + ASIC3_NR_IRQS; irq++) {
431 irq_set_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
432 irq_set_chip_and_handler(irq, NULL, NULL);
433 irq_set_chip_data(irq, NULL);
434 }
435 irq_set_chained_handler(asic->irq_nr, NULL);
436}
437
438/* GPIOs */
439static int asic3_gpio_direction(struct gpio_chip *chip,
440 unsigned offset, int out)
441{
442 u32 mask = ASIC3_GPIO_TO_MASK(offset), out_reg;
443 unsigned int gpio_base;
444 unsigned long flags;
445 struct asic3 *asic;
446
447 asic = gpiochip_get_data(chip);
448 gpio_base = ASIC3_GPIO_TO_BASE(offset);
449
450 if (gpio_base > ASIC3_GPIO_D_BASE) {
451 dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
452 gpio_base, offset);
453 return -EINVAL;
454 }
455
456 raw_spin_lock_irqsave(&asic->lock, flags);
457
458 out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_DIRECTION);
459
460 /* Input is 0, Output is 1 */
461 if (out)
462 out_reg |= mask;
463 else
464 out_reg &= ~mask;
465
466 asic3_write_register(asic, gpio_base + ASIC3_GPIO_DIRECTION, out_reg);
467
468 raw_spin_unlock_irqrestore(&asic->lock, flags);
469
470 return 0;
471
472}
473
474static int asic3_gpio_direction_input(struct gpio_chip *chip,
475 unsigned offset)
476{
477 return asic3_gpio_direction(chip, offset, 0);
478}
479
480static int asic3_gpio_direction_output(struct gpio_chip *chip,
481 unsigned offset, int value)
482{
483 return asic3_gpio_direction(chip, offset, 1);
484}
485
486static int asic3_gpio_get(struct gpio_chip *chip,
487 unsigned offset)
488{
489 unsigned int gpio_base;
490 u32 mask = ASIC3_GPIO_TO_MASK(offset);
491 struct asic3 *asic;
492
493 asic = gpiochip_get_data(chip);
494 gpio_base = ASIC3_GPIO_TO_BASE(offset);
495
496 if (gpio_base > ASIC3_GPIO_D_BASE) {
497 dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
498 gpio_base, offset);
499 return -EINVAL;
500 }
501
502 return !!(asic3_read_register(asic,
503 gpio_base + ASIC3_GPIO_STATUS) & mask);
504}
505
506static void asic3_gpio_set(struct gpio_chip *chip,
507 unsigned offset, int value)
508{
509 u32 mask, out_reg;
510 unsigned int gpio_base;
511 unsigned long flags;
512 struct asic3 *asic;
513
514 asic = gpiochip_get_data(chip);
515 gpio_base = ASIC3_GPIO_TO_BASE(offset);
516
517 if (gpio_base > ASIC3_GPIO_D_BASE) {
518 dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
519 gpio_base, offset);
520 return;
521 }
522
523 mask = ASIC3_GPIO_TO_MASK(offset);
524
525 raw_spin_lock_irqsave(&asic->lock, flags);
526
527 out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_OUT);
528
529 if (value)
530 out_reg |= mask;
531 else
532 out_reg &= ~mask;
533
534 asic3_write_register(asic, gpio_base + ASIC3_GPIO_OUT, out_reg);
535
536 raw_spin_unlock_irqrestore(&asic->lock, flags);
537}
538
539static int asic3_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
540{
541 struct asic3 *asic = gpiochip_get_data(chip);
542
543 return asic->irq_base + offset;
544}
545
546static __init int asic3_gpio_probe(struct platform_device *pdev,
547 u16 *gpio_config, int num)
548{
549 struct asic3 *asic = platform_get_drvdata(pdev);
550 u16 alt_reg[ASIC3_NUM_GPIO_BANKS];
551 u16 out_reg[ASIC3_NUM_GPIO_BANKS];
552 u16 dir_reg[ASIC3_NUM_GPIO_BANKS];
553 int i;
554
555 memset(alt_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
556 memset(out_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
557 memset(dir_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
558
559 /* Enable all GPIOs */
560 asic3_write_register(asic, ASIC3_GPIO_OFFSET(A, MASK), 0xffff);
561 asic3_write_register(asic, ASIC3_GPIO_OFFSET(B, MASK), 0xffff);
562 asic3_write_register(asic, ASIC3_GPIO_OFFSET(C, MASK), 0xffff);
563 asic3_write_register(asic, ASIC3_GPIO_OFFSET(D, MASK), 0xffff);
564
565 for (i = 0; i < num; i++) {
566 u8 alt, pin, dir, init, bank_num, bit_num;
567 u16 config = gpio_config[i];
568
569 pin = ASIC3_CONFIG_GPIO_PIN(config);
570 alt = ASIC3_CONFIG_GPIO_ALT(config);
571 dir = ASIC3_CONFIG_GPIO_DIR(config);
572 init = ASIC3_CONFIG_GPIO_INIT(config);
573
574 bank_num = ASIC3_GPIO_TO_BANK(pin);
575 bit_num = ASIC3_GPIO_TO_BIT(pin);
576
577 alt_reg[bank_num] |= (alt << bit_num);
578 out_reg[bank_num] |= (init << bit_num);
579 dir_reg[bank_num] |= (dir << bit_num);
580 }
581
582 for (i = 0; i < ASIC3_NUM_GPIO_BANKS; i++) {
583 asic3_write_register(asic,
584 ASIC3_BANK_TO_BASE(i) +
585 ASIC3_GPIO_DIRECTION,
586 dir_reg[i]);
587 asic3_write_register(asic,
588 ASIC3_BANK_TO_BASE(i) + ASIC3_GPIO_OUT,
589 out_reg[i]);
590 asic3_write_register(asic,
591 ASIC3_BANK_TO_BASE(i) +
592 ASIC3_GPIO_ALT_FUNCTION,
593 alt_reg[i]);
594 }
595
596 return gpiochip_add_data(&asic->gpio, asic);
597}
598
599static int asic3_gpio_remove(struct platform_device *pdev)
600{
601 struct asic3 *asic = platform_get_drvdata(pdev);
602
603 gpiochip_remove(&asic->gpio);
604 return 0;
605}
606
607static void asic3_clk_enable(struct asic3 *asic, struct asic3_clk *clk)
608{
609 unsigned long flags;
610 u32 cdex;
611
612 raw_spin_lock_irqsave(&asic->lock, flags);
613 if (clk->enabled++ == 0) {
614 cdex = asic3_read_register(asic, ASIC3_OFFSET(CLOCK, CDEX));
615 cdex |= clk->cdex;
616 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, CDEX), cdex);
617 }
618 raw_spin_unlock_irqrestore(&asic->lock, flags);
619}
620
621static void asic3_clk_disable(struct asic3 *asic, struct asic3_clk *clk)
622{
623 unsigned long flags;
624 u32 cdex;
625
626 WARN_ON(clk->enabled == 0);
627
628 raw_spin_lock_irqsave(&asic->lock, flags);
629 if (--clk->enabled == 0) {
630 cdex = asic3_read_register(asic, ASIC3_OFFSET(CLOCK, CDEX));
631 cdex &= ~clk->cdex;
632 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, CDEX), cdex);
633 }
634 raw_spin_unlock_irqrestore(&asic->lock, flags);
635}
636
637/* MFD cells (SPI, PWM, LED, DS1WM, MMC) */
638static struct ds1wm_driver_data ds1wm_pdata = {
639 .active_high = 1,
640 .reset_recover_delay = 1,
641};
642
643static struct resource ds1wm_resources[] = {
644 {
645 .start = ASIC3_OWM_BASE,
646 .end = ASIC3_OWM_BASE + 0x13,
647 .flags = IORESOURCE_MEM,
648 },
649 {
650 .start = ASIC3_IRQ_OWM,
651 .end = ASIC3_IRQ_OWM,
652 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
653 },
654};
655
656static int ds1wm_enable(struct platform_device *pdev)
657{
658 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
659
660 /* Turn on external clocks and the OWM clock */
661 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX0]);
662 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX1]);
663 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_OWM]);
664 usleep_range(1000, 5000);
665
666 /* Reset and enable DS1WM */
667 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, RESET),
668 ASIC3_EXTCF_OWM_RESET, 1);
669 usleep_range(1000, 5000);
670 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, RESET),
671 ASIC3_EXTCF_OWM_RESET, 0);
672 usleep_range(1000, 5000);
673 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
674 ASIC3_EXTCF_OWM_EN, 1);
675 usleep_range(1000, 5000);
676
677 return 0;
678}
679
680static int ds1wm_disable(struct platform_device *pdev)
681{
682 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
683
684 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
685 ASIC3_EXTCF_OWM_EN, 0);
686
687 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_OWM]);
688 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX0]);
689 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX1]);
690
691 return 0;
692}
693
694static const struct mfd_cell asic3_cell_ds1wm = {
695 .name = "ds1wm",
696 .enable = ds1wm_enable,
697 .disable = ds1wm_disable,
698 .platform_data = &ds1wm_pdata,
699 .pdata_size = sizeof(ds1wm_pdata),
700 .num_resources = ARRAY_SIZE(ds1wm_resources),
701 .resources = ds1wm_resources,
702};
703
704static void asic3_mmc_pwr(struct platform_device *pdev, int state)
705{
706 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
707
708 tmio_core_mmc_pwr(asic->tmio_cnf, 1 - asic->bus_shift, state);
709}
710
711static void asic3_mmc_clk_div(struct platform_device *pdev, int state)
712{
713 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
714
715 tmio_core_mmc_clk_div(asic->tmio_cnf, 1 - asic->bus_shift, state);
716}
717
718static struct tmio_mmc_data asic3_mmc_data = {
719 .hclk = 24576000,
720 .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34,
721 .set_pwr = asic3_mmc_pwr,
722 .set_clk_div = asic3_mmc_clk_div,
723};
724
725static struct resource asic3_mmc_resources[] = {
726 {
727 .start = ASIC3_SD_CTRL_BASE,
728 .end = ASIC3_SD_CTRL_BASE + 0x3ff,
729 .flags = IORESOURCE_MEM,
730 },
731 {
732 .start = 0,
733 .end = 0,
734 .flags = IORESOURCE_IRQ,
735 },
736};
737
738static int asic3_mmc_enable(struct platform_device *pdev)
739{
740 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
741
742 /* Not sure if it must be done bit by bit, but leaving as-is */
743 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
744 ASIC3_SDHWCTRL_LEVCD, 1);
745 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
746 ASIC3_SDHWCTRL_LEVWP, 1);
747 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
748 ASIC3_SDHWCTRL_SUSPEND, 0);
749 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
750 ASIC3_SDHWCTRL_PCLR, 0);
751
752 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX0]);
753 /* CLK32 used for card detection and for interruption detection
754 * when HCLK is stopped.
755 */
756 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX1]);
757 usleep_range(1000, 5000);
758
759 /* HCLK 24.576 MHz, BCLK 12.288 MHz: */
760 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL),
761 CLOCK_SEL_CX | CLOCK_SEL_SD_HCLK_SEL);
762
763 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_SD_HOST]);
764 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_SD_BUS]);
765 usleep_range(1000, 5000);
766
767 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
768 ASIC3_EXTCF_SD_MEM_ENABLE, 1);
769
770 /* Enable SD card slot 3.3V power supply */
771 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
772 ASIC3_SDHWCTRL_SDPWR, 1);
773
774 /* ASIC3_SD_CTRL_BASE assumes 32-bit addressing, TMIO is 16-bit */
775 tmio_core_mmc_enable(asic->tmio_cnf, 1 - asic->bus_shift,
776 ASIC3_SD_CTRL_BASE >> 1);
777
778 return 0;
779}
780
781static int asic3_mmc_disable(struct platform_device *pdev)
782{
783 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
784
785 /* Put in suspend mode */
786 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
787 ASIC3_SDHWCTRL_SUSPEND, 1);
788
789 /* Disable clocks */
790 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_SD_HOST]);
791 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_SD_BUS]);
792 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX0]);
793 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX1]);
794 return 0;
795}
796
797static const struct mfd_cell asic3_cell_mmc = {
798 .name = "tmio-mmc",
799 .enable = asic3_mmc_enable,
800 .disable = asic3_mmc_disable,
801 .suspend = asic3_mmc_disable,
802 .resume = asic3_mmc_enable,
803 .platform_data = &asic3_mmc_data,
804 .pdata_size = sizeof(asic3_mmc_data),
805 .num_resources = ARRAY_SIZE(asic3_mmc_resources),
806 .resources = asic3_mmc_resources,
807};
808
809static const int clock_ledn[ASIC3_NUM_LEDS] = {
810 [0] = ASIC3_CLOCK_LED0,
811 [1] = ASIC3_CLOCK_LED1,
812 [2] = ASIC3_CLOCK_LED2,
813};
814
815static int asic3_leds_enable(struct platform_device *pdev)
816{
817 const struct mfd_cell *cell = mfd_get_cell(pdev);
818 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
819
820 asic3_clk_enable(asic, &asic->clocks[clock_ledn[cell->id]]);
821
822 return 0;
823}
824
825static int asic3_leds_disable(struct platform_device *pdev)
826{
827 const struct mfd_cell *cell = mfd_get_cell(pdev);
828 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
829
830 asic3_clk_disable(asic, &asic->clocks[clock_ledn[cell->id]]);
831
832 return 0;
833}
834
835static int asic3_leds_suspend(struct platform_device *pdev)
836{
837 const struct mfd_cell *cell = mfd_get_cell(pdev);
838 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
839
840 while (asic3_gpio_get(&asic->gpio, ASIC3_GPIO(C, cell->id)) != 0)
841 usleep_range(1000, 5000);
842
843 asic3_clk_disable(asic, &asic->clocks[clock_ledn[cell->id]]);
844
845 return 0;
846}
847
848static struct mfd_cell asic3_cell_leds[ASIC3_NUM_LEDS] = {
849 [0] = {
850 .name = "leds-asic3",
851 .id = 0,
852 .enable = asic3_leds_enable,
853 .disable = asic3_leds_disable,
854 .suspend = asic3_leds_suspend,
855 .resume = asic3_leds_enable,
856 },
857 [1] = {
858 .name = "leds-asic3",
859 .id = 1,
860 .enable = asic3_leds_enable,
861 .disable = asic3_leds_disable,
862 .suspend = asic3_leds_suspend,
863 .resume = asic3_leds_enable,
864 },
865 [2] = {
866 .name = "leds-asic3",
867 .id = 2,
868 .enable = asic3_leds_enable,
869 .disable = asic3_leds_disable,
870 .suspend = asic3_leds_suspend,
871 .resume = asic3_leds_enable,
872 },
873};
874
875static int __init asic3_mfd_probe(struct platform_device *pdev,
876 struct asic3_platform_data *pdata,
877 struct resource *mem)
878{
879 struct asic3 *asic = platform_get_drvdata(pdev);
880 struct resource *mem_sdio;
881 int irq, ret;
882
883 mem_sdio = platform_get_resource(pdev, IORESOURCE_MEM, 1);
884 if (!mem_sdio)
885 dev_dbg(asic->dev, "no SDIO MEM resource\n");
886
887 irq = platform_get_irq(pdev, 1);
888 if (irq < 0)
889 dev_dbg(asic->dev, "no SDIO IRQ resource\n");
890
891 /* DS1WM */
892 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
893 ASIC3_EXTCF_OWM_SMB, 0);
894
895 ds1wm_resources[0].start >>= asic->bus_shift;
896 ds1wm_resources[0].end >>= asic->bus_shift;
897
898 /* MMC */
899 if (mem_sdio) {
900 asic->tmio_cnf = ioremap((ASIC3_SD_CONFIG_BASE >>
901 asic->bus_shift) + mem_sdio->start,
902 ASIC3_SD_CONFIG_SIZE >> asic->bus_shift);
903 if (!asic->tmio_cnf) {
904 ret = -ENOMEM;
905 dev_dbg(asic->dev, "Couldn't ioremap SD_CONFIG\n");
906 goto out;
907 }
908 }
909 asic3_mmc_resources[0].start >>= asic->bus_shift;
910 asic3_mmc_resources[0].end >>= asic->bus_shift;
911
912 if (pdata->clock_rate) {
913 ds1wm_pdata.clock_rate = pdata->clock_rate;
914 ret = mfd_add_devices(&pdev->dev, pdev->id,
915 &asic3_cell_ds1wm, 1, mem, asic->irq_base, NULL);
916 if (ret < 0)
917 goto out;
918 }
919
920 if (mem_sdio && (irq >= 0)) {
921 ret = mfd_add_devices(&pdev->dev, pdev->id,
922 &asic3_cell_mmc, 1, mem_sdio, irq, NULL);
923 if (ret < 0)
924 goto out;
925 }
926
927 ret = 0;
928 if (pdata->leds) {
929 int i;
930
931 for (i = 0; i < ASIC3_NUM_LEDS; ++i) {
932 asic3_cell_leds[i].platform_data = &pdata->leds[i];
933 asic3_cell_leds[i].pdata_size = sizeof(pdata->leds[i]);
934 }
935 ret = mfd_add_devices(&pdev->dev, 0,
936 asic3_cell_leds, ASIC3_NUM_LEDS, NULL, 0, NULL);
937 }
938
939 out:
940 return ret;
941}
942
943static void asic3_mfd_remove(struct platform_device *pdev)
944{
945 struct asic3 *asic = platform_get_drvdata(pdev);
946
947 mfd_remove_devices(&pdev->dev);
948 iounmap(asic->tmio_cnf);
949}
950
951/* Core */
952static int __init asic3_probe(struct platform_device *pdev)
953{
954 struct asic3_platform_data *pdata = dev_get_platdata(&pdev->dev);
955 struct asic3 *asic;
956 struct resource *mem;
957 unsigned long clksel;
958 int ret = 0;
959
960 asic = devm_kzalloc(&pdev->dev,
961 sizeof(struct asic3), GFP_KERNEL);
962 if (!asic)
963 return -ENOMEM;
964
965 raw_spin_lock_init(&asic->lock);
966 platform_set_drvdata(pdev, asic);
967 asic->dev = &pdev->dev;
968
969 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
970 if (!mem) {
971 dev_err(asic->dev, "no MEM resource\n");
972 return -ENOMEM;
973 }
974
975 asic->mapping = ioremap(mem->start, resource_size(mem));
976 if (!asic->mapping) {
977 dev_err(asic->dev, "Couldn't ioremap\n");
978 return -ENOMEM;
979 }
980
981 asic->irq_base = pdata->irq_base;
982
983 /* calculate bus shift from mem resource */
984 asic->bus_shift = 2 - (resource_size(mem) >> 12);
985
986 clksel = 0;
987 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), clksel);
988
989 ret = asic3_irq_probe(pdev);
990 if (ret < 0) {
991 dev_err(asic->dev, "Couldn't probe IRQs\n");
992 goto out_unmap;
993 }
994
995 asic->gpio.label = "asic3";
996 asic->gpio.base = pdata->gpio_base;
997 asic->gpio.ngpio = ASIC3_NUM_GPIOS;
998 asic->gpio.get = asic3_gpio_get;
999 asic->gpio.set = asic3_gpio_set;
1000 asic->gpio.direction_input = asic3_gpio_direction_input;
1001 asic->gpio.direction_output = asic3_gpio_direction_output;
1002 asic->gpio.to_irq = asic3_gpio_to_irq;
1003
1004 ret = asic3_gpio_probe(pdev,
1005 pdata->gpio_config,
1006 pdata->gpio_config_num);
1007 if (ret < 0) {
1008 dev_err(asic->dev, "GPIO probe failed\n");
1009 goto out_irq;
1010 }
1011
1012 /* Making a per-device copy is only needed for the
1013 * theoretical case of multiple ASIC3s on one board:
1014 */
1015 memcpy(asic->clocks, asic3_clk_init, sizeof(asic3_clk_init));
1016
1017 asic3_mfd_probe(pdev, pdata, mem);
1018
1019 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
1020 (ASIC3_EXTCF_CF0_BUF_EN|ASIC3_EXTCF_CF0_PWAIT_EN), 1);
1021
1022 dev_info(asic->dev, "ASIC3 Core driver\n");
1023
1024 return 0;
1025
1026 out_irq:
1027 asic3_irq_remove(pdev);
1028
1029 out_unmap:
1030 iounmap(asic->mapping);
1031
1032 return ret;
1033}
1034
1035static int asic3_remove(struct platform_device *pdev)
1036{
1037 int ret;
1038 struct asic3 *asic = platform_get_drvdata(pdev);
1039
1040 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
1041 (ASIC3_EXTCF_CF0_BUF_EN|ASIC3_EXTCF_CF0_PWAIT_EN), 0);
1042
1043 asic3_mfd_remove(pdev);
1044
1045 ret = asic3_gpio_remove(pdev);
1046 if (ret < 0)
1047 return ret;
1048 asic3_irq_remove(pdev);
1049
1050 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), 0);
1051
1052 iounmap(asic->mapping);
1053
1054 return 0;
1055}
1056
1057static void asic3_shutdown(struct platform_device *pdev)
1058{
1059}
1060
1061static struct platform_driver asic3_device_driver = {
1062 .driver = {
1063 .name = "asic3",
1064 },
1065 .remove = asic3_remove,
1066 .shutdown = asic3_shutdown,
1067};
1068
1069static int __init asic3_init(void)
1070{
1071 int retval = 0;
1072
1073 retval = platform_driver_probe(&asic3_device_driver, asic3_probe);
1074
1075 return retval;
1076}
1077
1078subsys_initcall(asic3_init);
1/*
2 * driver/mfd/asic3.c
3 *
4 * Compaq ASIC3 support.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Copyright 2001 Compaq Computer Corporation.
11 * Copyright 2004-2005 Phil Blundell
12 * Copyright 2007-2008 OpenedHand Ltd.
13 *
14 * Authors: Phil Blundell <pb@handhelds.org>,
15 * Samuel Ortiz <sameo@openedhand.com>
16 *
17 */
18
19#include <linux/kernel.h>
20#include <linux/delay.h>
21#include <linux/irq.h>
22#include <linux/gpio.h>
23#include <linux/export.h>
24#include <linux/io.h>
25#include <linux/slab.h>
26#include <linux/spinlock.h>
27#include <linux/platform_device.h>
28
29#include <linux/mfd/asic3.h>
30#include <linux/mfd/core.h>
31#include <linux/mfd/ds1wm.h>
32#include <linux/mfd/tmio.h>
33
34enum {
35 ASIC3_CLOCK_SPI,
36 ASIC3_CLOCK_OWM,
37 ASIC3_CLOCK_PWM0,
38 ASIC3_CLOCK_PWM1,
39 ASIC3_CLOCK_LED0,
40 ASIC3_CLOCK_LED1,
41 ASIC3_CLOCK_LED2,
42 ASIC3_CLOCK_SD_HOST,
43 ASIC3_CLOCK_SD_BUS,
44 ASIC3_CLOCK_SMBUS,
45 ASIC3_CLOCK_EX0,
46 ASIC3_CLOCK_EX1,
47};
48
49struct asic3_clk {
50 int enabled;
51 unsigned int cdex;
52 unsigned long rate;
53};
54
55#define INIT_CDEX(_name, _rate) \
56 [ASIC3_CLOCK_##_name] = { \
57 .cdex = CLOCK_CDEX_##_name, \
58 .rate = _rate, \
59 }
60
61static struct asic3_clk asic3_clk_init[] __initdata = {
62 INIT_CDEX(SPI, 0),
63 INIT_CDEX(OWM, 5000000),
64 INIT_CDEX(PWM0, 0),
65 INIT_CDEX(PWM1, 0),
66 INIT_CDEX(LED0, 0),
67 INIT_CDEX(LED1, 0),
68 INIT_CDEX(LED2, 0),
69 INIT_CDEX(SD_HOST, 24576000),
70 INIT_CDEX(SD_BUS, 12288000),
71 INIT_CDEX(SMBUS, 0),
72 INIT_CDEX(EX0, 32768),
73 INIT_CDEX(EX1, 24576000),
74};
75
76struct asic3 {
77 void __iomem *mapping;
78 unsigned int bus_shift;
79 unsigned int irq_nr;
80 unsigned int irq_base;
81 spinlock_t lock;
82 u16 irq_bothedge[4];
83 struct gpio_chip gpio;
84 struct device *dev;
85 void __iomem *tmio_cnf;
86
87 struct asic3_clk clocks[ARRAY_SIZE(asic3_clk_init)];
88};
89
90static int asic3_gpio_get(struct gpio_chip *chip, unsigned offset);
91
92void asic3_write_register(struct asic3 *asic, unsigned int reg, u32 value)
93{
94 iowrite16(value, asic->mapping +
95 (reg >> asic->bus_shift));
96}
97EXPORT_SYMBOL_GPL(asic3_write_register);
98
99u32 asic3_read_register(struct asic3 *asic, unsigned int reg)
100{
101 return ioread16(asic->mapping +
102 (reg >> asic->bus_shift));
103}
104EXPORT_SYMBOL_GPL(asic3_read_register);
105
106static void asic3_set_register(struct asic3 *asic, u32 reg, u32 bits, bool set)
107{
108 unsigned long flags;
109 u32 val;
110
111 spin_lock_irqsave(&asic->lock, flags);
112 val = asic3_read_register(asic, reg);
113 if (set)
114 val |= bits;
115 else
116 val &= ~bits;
117 asic3_write_register(asic, reg, val);
118 spin_unlock_irqrestore(&asic->lock, flags);
119}
120
121/* IRQs */
122#define MAX_ASIC_ISR_LOOPS 20
123#define ASIC3_GPIO_BASE_INCR \
124 (ASIC3_GPIO_B_BASE - ASIC3_GPIO_A_BASE)
125
126static void asic3_irq_flip_edge(struct asic3 *asic,
127 u32 base, int bit)
128{
129 u16 edge;
130 unsigned long flags;
131
132 spin_lock_irqsave(&asic->lock, flags);
133 edge = asic3_read_register(asic,
134 base + ASIC3_GPIO_EDGE_TRIGGER);
135 edge ^= bit;
136 asic3_write_register(asic,
137 base + ASIC3_GPIO_EDGE_TRIGGER, edge);
138 spin_unlock_irqrestore(&asic->lock, flags);
139}
140
141static void asic3_irq_demux(struct irq_desc *desc)
142{
143 struct asic3 *asic = irq_desc_get_handler_data(desc);
144 struct irq_data *data = irq_desc_get_irq_data(desc);
145 int iter, i;
146 unsigned long flags;
147
148 data->chip->irq_ack(data);
149
150 for (iter = 0 ; iter < MAX_ASIC_ISR_LOOPS; iter++) {
151 u32 status;
152 int bank;
153
154 spin_lock_irqsave(&asic->lock, flags);
155 status = asic3_read_register(asic,
156 ASIC3_OFFSET(INTR, P_INT_STAT));
157 spin_unlock_irqrestore(&asic->lock, flags);
158
159 /* Check all ten register bits */
160 if ((status & 0x3ff) == 0)
161 break;
162
163 /* Handle GPIO IRQs */
164 for (bank = 0; bank < ASIC3_NUM_GPIO_BANKS; bank++) {
165 if (status & (1 << bank)) {
166 unsigned long base, istat;
167
168 base = ASIC3_GPIO_A_BASE
169 + bank * ASIC3_GPIO_BASE_INCR;
170 spin_lock_irqsave(&asic->lock, flags);
171 istat = asic3_read_register(asic,
172 base +
173 ASIC3_GPIO_INT_STATUS);
174 /* Clearing IntStatus */
175 asic3_write_register(asic,
176 base +
177 ASIC3_GPIO_INT_STATUS, 0);
178 spin_unlock_irqrestore(&asic->lock, flags);
179
180 for (i = 0; i < ASIC3_GPIOS_PER_BANK; i++) {
181 int bit = (1 << i);
182 unsigned int irqnr;
183
184 if (!(istat & bit))
185 continue;
186
187 irqnr = asic->irq_base +
188 (ASIC3_GPIOS_PER_BANK * bank)
189 + i;
190 generic_handle_irq(irqnr);
191 if (asic->irq_bothedge[bank] & bit)
192 asic3_irq_flip_edge(asic, base,
193 bit);
194 }
195 }
196 }
197
198 /* Handle remaining IRQs in the status register */
199 for (i = ASIC3_NUM_GPIOS; i < ASIC3_NR_IRQS; i++) {
200 /* They start at bit 4 and go up */
201 if (status & (1 << (i - ASIC3_NUM_GPIOS + 4)))
202 generic_handle_irq(asic->irq_base + i);
203 }
204 }
205
206 if (iter >= MAX_ASIC_ISR_LOOPS)
207 dev_err(asic->dev, "interrupt processing overrun\n");
208}
209
210static inline int asic3_irq_to_bank(struct asic3 *asic, int irq)
211{
212 int n;
213
214 n = (irq - asic->irq_base) >> 4;
215
216 return (n * (ASIC3_GPIO_B_BASE - ASIC3_GPIO_A_BASE));
217}
218
219static inline int asic3_irq_to_index(struct asic3 *asic, int irq)
220{
221 return (irq - asic->irq_base) & 0xf;
222}
223
224static void asic3_mask_gpio_irq(struct irq_data *data)
225{
226 struct asic3 *asic = irq_data_get_irq_chip_data(data);
227 u32 val, bank, index;
228 unsigned long flags;
229
230 bank = asic3_irq_to_bank(asic, data->irq);
231 index = asic3_irq_to_index(asic, data->irq);
232
233 spin_lock_irqsave(&asic->lock, flags);
234 val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK);
235 val |= 1 << index;
236 asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val);
237 spin_unlock_irqrestore(&asic->lock, flags);
238}
239
240static void asic3_mask_irq(struct irq_data *data)
241{
242 struct asic3 *asic = irq_data_get_irq_chip_data(data);
243 int regval;
244 unsigned long flags;
245
246 spin_lock_irqsave(&asic->lock, flags);
247 regval = asic3_read_register(asic,
248 ASIC3_INTR_BASE +
249 ASIC3_INTR_INT_MASK);
250
251 regval &= ~(ASIC3_INTMASK_MASK0 <<
252 (data->irq - (asic->irq_base + ASIC3_NUM_GPIOS)));
253
254 asic3_write_register(asic,
255 ASIC3_INTR_BASE +
256 ASIC3_INTR_INT_MASK,
257 regval);
258 spin_unlock_irqrestore(&asic->lock, flags);
259}
260
261static void asic3_unmask_gpio_irq(struct irq_data *data)
262{
263 struct asic3 *asic = irq_data_get_irq_chip_data(data);
264 u32 val, bank, index;
265 unsigned long flags;
266
267 bank = asic3_irq_to_bank(asic, data->irq);
268 index = asic3_irq_to_index(asic, data->irq);
269
270 spin_lock_irqsave(&asic->lock, flags);
271 val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK);
272 val &= ~(1 << index);
273 asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val);
274 spin_unlock_irqrestore(&asic->lock, flags);
275}
276
277static void asic3_unmask_irq(struct irq_data *data)
278{
279 struct asic3 *asic = irq_data_get_irq_chip_data(data);
280 int regval;
281 unsigned long flags;
282
283 spin_lock_irqsave(&asic->lock, flags);
284 regval = asic3_read_register(asic,
285 ASIC3_INTR_BASE +
286 ASIC3_INTR_INT_MASK);
287
288 regval |= (ASIC3_INTMASK_MASK0 <<
289 (data->irq - (asic->irq_base + ASIC3_NUM_GPIOS)));
290
291 asic3_write_register(asic,
292 ASIC3_INTR_BASE +
293 ASIC3_INTR_INT_MASK,
294 regval);
295 spin_unlock_irqrestore(&asic->lock, flags);
296}
297
298static int asic3_gpio_irq_type(struct irq_data *data, unsigned int type)
299{
300 struct asic3 *asic = irq_data_get_irq_chip_data(data);
301 u32 bank, index;
302 u16 trigger, level, edge, bit;
303 unsigned long flags;
304
305 bank = asic3_irq_to_bank(asic, data->irq);
306 index = asic3_irq_to_index(asic, data->irq);
307 bit = 1<<index;
308
309 spin_lock_irqsave(&asic->lock, flags);
310 level = asic3_read_register(asic,
311 bank + ASIC3_GPIO_LEVEL_TRIGGER);
312 edge = asic3_read_register(asic,
313 bank + ASIC3_GPIO_EDGE_TRIGGER);
314 trigger = asic3_read_register(asic,
315 bank + ASIC3_GPIO_TRIGGER_TYPE);
316 asic->irq_bothedge[(data->irq - asic->irq_base) >> 4] &= ~bit;
317
318 if (type == IRQ_TYPE_EDGE_RISING) {
319 trigger |= bit;
320 edge |= bit;
321 } else if (type == IRQ_TYPE_EDGE_FALLING) {
322 trigger |= bit;
323 edge &= ~bit;
324 } else if (type == IRQ_TYPE_EDGE_BOTH) {
325 trigger |= bit;
326 if (asic3_gpio_get(&asic->gpio, data->irq - asic->irq_base))
327 edge &= ~bit;
328 else
329 edge |= bit;
330 asic->irq_bothedge[(data->irq - asic->irq_base) >> 4] |= bit;
331 } else if (type == IRQ_TYPE_LEVEL_LOW) {
332 trigger &= ~bit;
333 level &= ~bit;
334 } else if (type == IRQ_TYPE_LEVEL_HIGH) {
335 trigger &= ~bit;
336 level |= bit;
337 } else {
338 /*
339 * if type == IRQ_TYPE_NONE, we should mask interrupts, but
340 * be careful to not unmask them if mask was also called.
341 * Probably need internal state for mask.
342 */
343 dev_notice(asic->dev, "irq type not changed\n");
344 }
345 asic3_write_register(asic, bank + ASIC3_GPIO_LEVEL_TRIGGER,
346 level);
347 asic3_write_register(asic, bank + ASIC3_GPIO_EDGE_TRIGGER,
348 edge);
349 asic3_write_register(asic, bank + ASIC3_GPIO_TRIGGER_TYPE,
350 trigger);
351 spin_unlock_irqrestore(&asic->lock, flags);
352 return 0;
353}
354
355static int asic3_gpio_irq_set_wake(struct irq_data *data, unsigned int on)
356{
357 struct asic3 *asic = irq_data_get_irq_chip_data(data);
358 u32 bank, index;
359 u16 bit;
360
361 bank = asic3_irq_to_bank(asic, data->irq);
362 index = asic3_irq_to_index(asic, data->irq);
363 bit = 1<<index;
364
365 asic3_set_register(asic, bank + ASIC3_GPIO_SLEEP_MASK, bit, !on);
366
367 return 0;
368}
369
370static struct irq_chip asic3_gpio_irq_chip = {
371 .name = "ASIC3-GPIO",
372 .irq_ack = asic3_mask_gpio_irq,
373 .irq_mask = asic3_mask_gpio_irq,
374 .irq_unmask = asic3_unmask_gpio_irq,
375 .irq_set_type = asic3_gpio_irq_type,
376 .irq_set_wake = asic3_gpio_irq_set_wake,
377};
378
379static struct irq_chip asic3_irq_chip = {
380 .name = "ASIC3",
381 .irq_ack = asic3_mask_irq,
382 .irq_mask = asic3_mask_irq,
383 .irq_unmask = asic3_unmask_irq,
384};
385
386static int __init asic3_irq_probe(struct platform_device *pdev)
387{
388 struct asic3 *asic = platform_get_drvdata(pdev);
389 unsigned long clksel = 0;
390 unsigned int irq, irq_base;
391 int ret;
392
393 ret = platform_get_irq(pdev, 0);
394 if (ret < 0)
395 return ret;
396 asic->irq_nr = ret;
397
398 /* turn on clock to IRQ controller */
399 clksel |= CLOCK_SEL_CX;
400 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL),
401 clksel);
402
403 irq_base = asic->irq_base;
404
405 for (irq = irq_base; irq < irq_base + ASIC3_NR_IRQS; irq++) {
406 if (irq < asic->irq_base + ASIC3_NUM_GPIOS)
407 irq_set_chip(irq, &asic3_gpio_irq_chip);
408 else
409 irq_set_chip(irq, &asic3_irq_chip);
410
411 irq_set_chip_data(irq, asic);
412 irq_set_handler(irq, handle_level_irq);
413 irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
414 }
415
416 asic3_write_register(asic, ASIC3_OFFSET(INTR, INT_MASK),
417 ASIC3_INTMASK_GINTMASK);
418
419 irq_set_chained_handler_and_data(asic->irq_nr, asic3_irq_demux, asic);
420 irq_set_irq_type(asic->irq_nr, IRQ_TYPE_EDGE_RISING);
421
422 return 0;
423}
424
425static void asic3_irq_remove(struct platform_device *pdev)
426{
427 struct asic3 *asic = platform_get_drvdata(pdev);
428 unsigned int irq, irq_base;
429
430 irq_base = asic->irq_base;
431
432 for (irq = irq_base; irq < irq_base + ASIC3_NR_IRQS; irq++) {
433 irq_set_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
434 irq_set_chip_and_handler(irq, NULL, NULL);
435 irq_set_chip_data(irq, NULL);
436 }
437 irq_set_chained_handler(asic->irq_nr, NULL);
438}
439
440/* GPIOs */
441static int asic3_gpio_direction(struct gpio_chip *chip,
442 unsigned offset, int out)
443{
444 u32 mask = ASIC3_GPIO_TO_MASK(offset), out_reg;
445 unsigned int gpio_base;
446 unsigned long flags;
447 struct asic3 *asic;
448
449 asic = gpiochip_get_data(chip);
450 gpio_base = ASIC3_GPIO_TO_BASE(offset);
451
452 if (gpio_base > ASIC3_GPIO_D_BASE) {
453 dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
454 gpio_base, offset);
455 return -EINVAL;
456 }
457
458 spin_lock_irqsave(&asic->lock, flags);
459
460 out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_DIRECTION);
461
462 /* Input is 0, Output is 1 */
463 if (out)
464 out_reg |= mask;
465 else
466 out_reg &= ~mask;
467
468 asic3_write_register(asic, gpio_base + ASIC3_GPIO_DIRECTION, out_reg);
469
470 spin_unlock_irqrestore(&asic->lock, flags);
471
472 return 0;
473
474}
475
476static int asic3_gpio_direction_input(struct gpio_chip *chip,
477 unsigned offset)
478{
479 return asic3_gpio_direction(chip, offset, 0);
480}
481
482static int asic3_gpio_direction_output(struct gpio_chip *chip,
483 unsigned offset, int value)
484{
485 return asic3_gpio_direction(chip, offset, 1);
486}
487
488static int asic3_gpio_get(struct gpio_chip *chip,
489 unsigned offset)
490{
491 unsigned int gpio_base;
492 u32 mask = ASIC3_GPIO_TO_MASK(offset);
493 struct asic3 *asic;
494
495 asic = gpiochip_get_data(chip);
496 gpio_base = ASIC3_GPIO_TO_BASE(offset);
497
498 if (gpio_base > ASIC3_GPIO_D_BASE) {
499 dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
500 gpio_base, offset);
501 return -EINVAL;
502 }
503
504 return !!(asic3_read_register(asic,
505 gpio_base + ASIC3_GPIO_STATUS) & mask);
506}
507
508static void asic3_gpio_set(struct gpio_chip *chip,
509 unsigned offset, int value)
510{
511 u32 mask, out_reg;
512 unsigned int gpio_base;
513 unsigned long flags;
514 struct asic3 *asic;
515
516 asic = gpiochip_get_data(chip);
517 gpio_base = ASIC3_GPIO_TO_BASE(offset);
518
519 if (gpio_base > ASIC3_GPIO_D_BASE) {
520 dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
521 gpio_base, offset);
522 return;
523 }
524
525 mask = ASIC3_GPIO_TO_MASK(offset);
526
527 spin_lock_irqsave(&asic->lock, flags);
528
529 out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_OUT);
530
531 if (value)
532 out_reg |= mask;
533 else
534 out_reg &= ~mask;
535
536 asic3_write_register(asic, gpio_base + ASIC3_GPIO_OUT, out_reg);
537
538 spin_unlock_irqrestore(&asic->lock, flags);
539}
540
541static int asic3_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
542{
543 struct asic3 *asic = gpiochip_get_data(chip);
544
545 return asic->irq_base + offset;
546}
547
548static __init int asic3_gpio_probe(struct platform_device *pdev,
549 u16 *gpio_config, int num)
550{
551 struct asic3 *asic = platform_get_drvdata(pdev);
552 u16 alt_reg[ASIC3_NUM_GPIO_BANKS];
553 u16 out_reg[ASIC3_NUM_GPIO_BANKS];
554 u16 dir_reg[ASIC3_NUM_GPIO_BANKS];
555 int i;
556
557 memset(alt_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
558 memset(out_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
559 memset(dir_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
560
561 /* Enable all GPIOs */
562 asic3_write_register(asic, ASIC3_GPIO_OFFSET(A, MASK), 0xffff);
563 asic3_write_register(asic, ASIC3_GPIO_OFFSET(B, MASK), 0xffff);
564 asic3_write_register(asic, ASIC3_GPIO_OFFSET(C, MASK), 0xffff);
565 asic3_write_register(asic, ASIC3_GPIO_OFFSET(D, MASK), 0xffff);
566
567 for (i = 0; i < num; i++) {
568 u8 alt, pin, dir, init, bank_num, bit_num;
569 u16 config = gpio_config[i];
570
571 pin = ASIC3_CONFIG_GPIO_PIN(config);
572 alt = ASIC3_CONFIG_GPIO_ALT(config);
573 dir = ASIC3_CONFIG_GPIO_DIR(config);
574 init = ASIC3_CONFIG_GPIO_INIT(config);
575
576 bank_num = ASIC3_GPIO_TO_BANK(pin);
577 bit_num = ASIC3_GPIO_TO_BIT(pin);
578
579 alt_reg[bank_num] |= (alt << bit_num);
580 out_reg[bank_num] |= (init << bit_num);
581 dir_reg[bank_num] |= (dir << bit_num);
582 }
583
584 for (i = 0; i < ASIC3_NUM_GPIO_BANKS; i++) {
585 asic3_write_register(asic,
586 ASIC3_BANK_TO_BASE(i) +
587 ASIC3_GPIO_DIRECTION,
588 dir_reg[i]);
589 asic3_write_register(asic,
590 ASIC3_BANK_TO_BASE(i) + ASIC3_GPIO_OUT,
591 out_reg[i]);
592 asic3_write_register(asic,
593 ASIC3_BANK_TO_BASE(i) +
594 ASIC3_GPIO_ALT_FUNCTION,
595 alt_reg[i]);
596 }
597
598 return gpiochip_add_data(&asic->gpio, asic);
599}
600
601static int asic3_gpio_remove(struct platform_device *pdev)
602{
603 struct asic3 *asic = platform_get_drvdata(pdev);
604
605 gpiochip_remove(&asic->gpio);
606 return 0;
607}
608
609static void asic3_clk_enable(struct asic3 *asic, struct asic3_clk *clk)
610{
611 unsigned long flags;
612 u32 cdex;
613
614 spin_lock_irqsave(&asic->lock, flags);
615 if (clk->enabled++ == 0) {
616 cdex = asic3_read_register(asic, ASIC3_OFFSET(CLOCK, CDEX));
617 cdex |= clk->cdex;
618 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, CDEX), cdex);
619 }
620 spin_unlock_irqrestore(&asic->lock, flags);
621}
622
623static void asic3_clk_disable(struct asic3 *asic, struct asic3_clk *clk)
624{
625 unsigned long flags;
626 u32 cdex;
627
628 WARN_ON(clk->enabled == 0);
629
630 spin_lock_irqsave(&asic->lock, flags);
631 if (--clk->enabled == 0) {
632 cdex = asic3_read_register(asic, ASIC3_OFFSET(CLOCK, CDEX));
633 cdex &= ~clk->cdex;
634 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, CDEX), cdex);
635 }
636 spin_unlock_irqrestore(&asic->lock, flags);
637}
638
639/* MFD cells (SPI, PWM, LED, DS1WM, MMC) */
640static struct ds1wm_driver_data ds1wm_pdata = {
641 .active_high = 1,
642 .reset_recover_delay = 1,
643};
644
645static struct resource ds1wm_resources[] = {
646 {
647 .start = ASIC3_OWM_BASE,
648 .end = ASIC3_OWM_BASE + 0x13,
649 .flags = IORESOURCE_MEM,
650 },
651 {
652 .start = ASIC3_IRQ_OWM,
653 .end = ASIC3_IRQ_OWM,
654 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
655 },
656};
657
658static int ds1wm_enable(struct platform_device *pdev)
659{
660 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
661
662 /* Turn on external clocks and the OWM clock */
663 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX0]);
664 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX1]);
665 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_OWM]);
666 usleep_range(1000, 5000);
667
668 /* Reset and enable DS1WM */
669 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, RESET),
670 ASIC3_EXTCF_OWM_RESET, 1);
671 usleep_range(1000, 5000);
672 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, RESET),
673 ASIC3_EXTCF_OWM_RESET, 0);
674 usleep_range(1000, 5000);
675 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
676 ASIC3_EXTCF_OWM_EN, 1);
677 usleep_range(1000, 5000);
678
679 return 0;
680}
681
682static int ds1wm_disable(struct platform_device *pdev)
683{
684 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
685
686 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
687 ASIC3_EXTCF_OWM_EN, 0);
688
689 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_OWM]);
690 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX0]);
691 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX1]);
692
693 return 0;
694}
695
696static const struct mfd_cell asic3_cell_ds1wm = {
697 .name = "ds1wm",
698 .enable = ds1wm_enable,
699 .disable = ds1wm_disable,
700 .platform_data = &ds1wm_pdata,
701 .pdata_size = sizeof(ds1wm_pdata),
702 .num_resources = ARRAY_SIZE(ds1wm_resources),
703 .resources = ds1wm_resources,
704};
705
706static void asic3_mmc_pwr(struct platform_device *pdev, int state)
707{
708 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
709
710 tmio_core_mmc_pwr(asic->tmio_cnf, 1 - asic->bus_shift, state);
711}
712
713static void asic3_mmc_clk_div(struct platform_device *pdev, int state)
714{
715 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
716
717 tmio_core_mmc_clk_div(asic->tmio_cnf, 1 - asic->bus_shift, state);
718}
719
720static struct tmio_mmc_data asic3_mmc_data = {
721 .hclk = 24576000,
722 .set_pwr = asic3_mmc_pwr,
723 .set_clk_div = asic3_mmc_clk_div,
724};
725
726static struct resource asic3_mmc_resources[] = {
727 {
728 .start = ASIC3_SD_CTRL_BASE,
729 .end = ASIC3_SD_CTRL_BASE + 0x3ff,
730 .flags = IORESOURCE_MEM,
731 },
732 {
733 .start = 0,
734 .end = 0,
735 .flags = IORESOURCE_IRQ,
736 },
737};
738
739static int asic3_mmc_enable(struct platform_device *pdev)
740{
741 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
742
743 /* Not sure if it must be done bit by bit, but leaving as-is */
744 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
745 ASIC3_SDHWCTRL_LEVCD, 1);
746 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
747 ASIC3_SDHWCTRL_LEVWP, 1);
748 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
749 ASIC3_SDHWCTRL_SUSPEND, 0);
750 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
751 ASIC3_SDHWCTRL_PCLR, 0);
752
753 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX0]);
754 /* CLK32 used for card detection and for interruption detection
755 * when HCLK is stopped.
756 */
757 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX1]);
758 usleep_range(1000, 5000);
759
760 /* HCLK 24.576 MHz, BCLK 12.288 MHz: */
761 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL),
762 CLOCK_SEL_CX | CLOCK_SEL_SD_HCLK_SEL);
763
764 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_SD_HOST]);
765 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_SD_BUS]);
766 usleep_range(1000, 5000);
767
768 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
769 ASIC3_EXTCF_SD_MEM_ENABLE, 1);
770
771 /* Enable SD card slot 3.3V power supply */
772 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
773 ASIC3_SDHWCTRL_SDPWR, 1);
774
775 /* ASIC3_SD_CTRL_BASE assumes 32-bit addressing, TMIO is 16-bit */
776 tmio_core_mmc_enable(asic->tmio_cnf, 1 - asic->bus_shift,
777 ASIC3_SD_CTRL_BASE >> 1);
778
779 return 0;
780}
781
782static int asic3_mmc_disable(struct platform_device *pdev)
783{
784 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
785
786 /* Put in suspend mode */
787 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
788 ASIC3_SDHWCTRL_SUSPEND, 1);
789
790 /* Disable clocks */
791 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_SD_HOST]);
792 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_SD_BUS]);
793 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX0]);
794 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX1]);
795 return 0;
796}
797
798static const struct mfd_cell asic3_cell_mmc = {
799 .name = "tmio-mmc",
800 .enable = asic3_mmc_enable,
801 .disable = asic3_mmc_disable,
802 .suspend = asic3_mmc_disable,
803 .resume = asic3_mmc_enable,
804 .platform_data = &asic3_mmc_data,
805 .pdata_size = sizeof(asic3_mmc_data),
806 .num_resources = ARRAY_SIZE(asic3_mmc_resources),
807 .resources = asic3_mmc_resources,
808};
809
810static const int clock_ledn[ASIC3_NUM_LEDS] = {
811 [0] = ASIC3_CLOCK_LED0,
812 [1] = ASIC3_CLOCK_LED1,
813 [2] = ASIC3_CLOCK_LED2,
814};
815
816static int asic3_leds_enable(struct platform_device *pdev)
817{
818 const struct mfd_cell *cell = mfd_get_cell(pdev);
819 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
820
821 asic3_clk_enable(asic, &asic->clocks[clock_ledn[cell->id]]);
822
823 return 0;
824}
825
826static int asic3_leds_disable(struct platform_device *pdev)
827{
828 const struct mfd_cell *cell = mfd_get_cell(pdev);
829 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
830
831 asic3_clk_disable(asic, &asic->clocks[clock_ledn[cell->id]]);
832
833 return 0;
834}
835
836static int asic3_leds_suspend(struct platform_device *pdev)
837{
838 const struct mfd_cell *cell = mfd_get_cell(pdev);
839 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
840
841 while (asic3_gpio_get(&asic->gpio, ASIC3_GPIO(C, cell->id)) != 0)
842 usleep_range(1000, 5000);
843
844 asic3_clk_disable(asic, &asic->clocks[clock_ledn[cell->id]]);
845
846 return 0;
847}
848
849static struct mfd_cell asic3_cell_leds[ASIC3_NUM_LEDS] = {
850 [0] = {
851 .name = "leds-asic3",
852 .id = 0,
853 .enable = asic3_leds_enable,
854 .disable = asic3_leds_disable,
855 .suspend = asic3_leds_suspend,
856 .resume = asic3_leds_enable,
857 },
858 [1] = {
859 .name = "leds-asic3",
860 .id = 1,
861 .enable = asic3_leds_enable,
862 .disable = asic3_leds_disable,
863 .suspend = asic3_leds_suspend,
864 .resume = asic3_leds_enable,
865 },
866 [2] = {
867 .name = "leds-asic3",
868 .id = 2,
869 .enable = asic3_leds_enable,
870 .disable = asic3_leds_disable,
871 .suspend = asic3_leds_suspend,
872 .resume = asic3_leds_enable,
873 },
874};
875
876static int __init asic3_mfd_probe(struct platform_device *pdev,
877 struct asic3_platform_data *pdata,
878 struct resource *mem)
879{
880 struct asic3 *asic = platform_get_drvdata(pdev);
881 struct resource *mem_sdio;
882 int irq, ret;
883
884 mem_sdio = platform_get_resource(pdev, IORESOURCE_MEM, 1);
885 if (!mem_sdio)
886 dev_dbg(asic->dev, "no SDIO MEM resource\n");
887
888 irq = platform_get_irq(pdev, 1);
889 if (irq < 0)
890 dev_dbg(asic->dev, "no SDIO IRQ resource\n");
891
892 /* DS1WM */
893 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
894 ASIC3_EXTCF_OWM_SMB, 0);
895
896 ds1wm_resources[0].start >>= asic->bus_shift;
897 ds1wm_resources[0].end >>= asic->bus_shift;
898
899 /* MMC */
900 if (mem_sdio) {
901 asic->tmio_cnf = ioremap((ASIC3_SD_CONFIG_BASE >>
902 asic->bus_shift) + mem_sdio->start,
903 ASIC3_SD_CONFIG_SIZE >> asic->bus_shift);
904 if (!asic->tmio_cnf) {
905 ret = -ENOMEM;
906 dev_dbg(asic->dev, "Couldn't ioremap SD_CONFIG\n");
907 goto out;
908 }
909 }
910 asic3_mmc_resources[0].start >>= asic->bus_shift;
911 asic3_mmc_resources[0].end >>= asic->bus_shift;
912
913 if (pdata->clock_rate) {
914 ds1wm_pdata.clock_rate = pdata->clock_rate;
915 ret = mfd_add_devices(&pdev->dev, pdev->id,
916 &asic3_cell_ds1wm, 1, mem, asic->irq_base, NULL);
917 if (ret < 0)
918 goto out;
919 }
920
921 if (mem_sdio && (irq >= 0)) {
922 ret = mfd_add_devices(&pdev->dev, pdev->id,
923 &asic3_cell_mmc, 1, mem_sdio, irq, NULL);
924 if (ret < 0)
925 goto out;
926 }
927
928 ret = 0;
929 if (pdata->leds) {
930 int i;
931
932 for (i = 0; i < ASIC3_NUM_LEDS; ++i) {
933 asic3_cell_leds[i].platform_data = &pdata->leds[i];
934 asic3_cell_leds[i].pdata_size = sizeof(pdata->leds[i]);
935 }
936 ret = mfd_add_devices(&pdev->dev, 0,
937 asic3_cell_leds, ASIC3_NUM_LEDS, NULL, 0, NULL);
938 }
939
940 out:
941 return ret;
942}
943
944static void asic3_mfd_remove(struct platform_device *pdev)
945{
946 struct asic3 *asic = platform_get_drvdata(pdev);
947
948 mfd_remove_devices(&pdev->dev);
949 iounmap(asic->tmio_cnf);
950}
951
952/* Core */
953static int __init asic3_probe(struct platform_device *pdev)
954{
955 struct asic3_platform_data *pdata = dev_get_platdata(&pdev->dev);
956 struct asic3 *asic;
957 struct resource *mem;
958 unsigned long clksel;
959 int ret = 0;
960
961 asic = devm_kzalloc(&pdev->dev,
962 sizeof(struct asic3), GFP_KERNEL);
963 if (!asic)
964 return -ENOMEM;
965
966 spin_lock_init(&asic->lock);
967 platform_set_drvdata(pdev, asic);
968 asic->dev = &pdev->dev;
969
970 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
971 if (!mem) {
972 dev_err(asic->dev, "no MEM resource\n");
973 return -ENOMEM;
974 }
975
976 asic->mapping = ioremap(mem->start, resource_size(mem));
977 if (!asic->mapping) {
978 dev_err(asic->dev, "Couldn't ioremap\n");
979 return -ENOMEM;
980 }
981
982 asic->irq_base = pdata->irq_base;
983
984 /* calculate bus shift from mem resource */
985 asic->bus_shift = 2 - (resource_size(mem) >> 12);
986
987 clksel = 0;
988 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), clksel);
989
990 ret = asic3_irq_probe(pdev);
991 if (ret < 0) {
992 dev_err(asic->dev, "Couldn't probe IRQs\n");
993 goto out_unmap;
994 }
995
996 asic->gpio.label = "asic3";
997 asic->gpio.base = pdata->gpio_base;
998 asic->gpio.ngpio = ASIC3_NUM_GPIOS;
999 asic->gpio.get = asic3_gpio_get;
1000 asic->gpio.set = asic3_gpio_set;
1001 asic->gpio.direction_input = asic3_gpio_direction_input;
1002 asic->gpio.direction_output = asic3_gpio_direction_output;
1003 asic->gpio.to_irq = asic3_gpio_to_irq;
1004
1005 ret = asic3_gpio_probe(pdev,
1006 pdata->gpio_config,
1007 pdata->gpio_config_num);
1008 if (ret < 0) {
1009 dev_err(asic->dev, "GPIO probe failed\n");
1010 goto out_irq;
1011 }
1012
1013 /* Making a per-device copy is only needed for the
1014 * theoretical case of multiple ASIC3s on one board:
1015 */
1016 memcpy(asic->clocks, asic3_clk_init, sizeof(asic3_clk_init));
1017
1018 asic3_mfd_probe(pdev, pdata, mem);
1019
1020 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
1021 (ASIC3_EXTCF_CF0_BUF_EN|ASIC3_EXTCF_CF0_PWAIT_EN), 1);
1022
1023 dev_info(asic->dev, "ASIC3 Core driver\n");
1024
1025 return 0;
1026
1027 out_irq:
1028 asic3_irq_remove(pdev);
1029
1030 out_unmap:
1031 iounmap(asic->mapping);
1032
1033 return ret;
1034}
1035
1036static int asic3_remove(struct platform_device *pdev)
1037{
1038 int ret;
1039 struct asic3 *asic = platform_get_drvdata(pdev);
1040
1041 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
1042 (ASIC3_EXTCF_CF0_BUF_EN|ASIC3_EXTCF_CF0_PWAIT_EN), 0);
1043
1044 asic3_mfd_remove(pdev);
1045
1046 ret = asic3_gpio_remove(pdev);
1047 if (ret < 0)
1048 return ret;
1049 asic3_irq_remove(pdev);
1050
1051 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), 0);
1052
1053 iounmap(asic->mapping);
1054
1055 return 0;
1056}
1057
1058static void asic3_shutdown(struct platform_device *pdev)
1059{
1060}
1061
1062static struct platform_driver asic3_device_driver = {
1063 .driver = {
1064 .name = "asic3",
1065 },
1066 .remove = asic3_remove,
1067 .shutdown = asic3_shutdown,
1068};
1069
1070static int __init asic3_init(void)
1071{
1072 int retval = 0;
1073
1074 retval = platform_driver_probe(&asic3_device_driver, asic3_probe);
1075
1076 return retval;
1077}
1078
1079subsys_initcall(asic3_init);