1/*
  2 * Copyright 2019 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 * Authors: AMD
 23 *
 24 */
 25
 26#ifndef _DMUB_DCN20_H_
 27#define _DMUB_DCN20_H_
 28
 29#include "../inc/dmub_cmd.h"
 30
 31struct dmub_srv;
 32
 33/* DCN20 register definitions. */
 34
 35#define DMUB_COMMON_REGS() \
 36	DMUB_SR(DMCUB_CNTL) \
 37	DMUB_SR(DMCUB_MEM_CNTL) \
 38	DMUB_SR(DMCUB_SEC_CNTL) \
 39	DMUB_SR(DMCUB_INBOX1_BASE_ADDRESS) \
 40	DMUB_SR(DMCUB_INBOX1_SIZE) \
 41	DMUB_SR(DMCUB_INBOX1_RPTR) \
 42	DMUB_SR(DMCUB_INBOX1_WPTR) \
 43	DMUB_SR(DMCUB_REGION3_CW0_OFFSET) \
 44	DMUB_SR(DMCUB_REGION3_CW1_OFFSET) \
 45	DMUB_SR(DMCUB_REGION3_CW2_OFFSET) \
 46	DMUB_SR(DMCUB_REGION3_CW3_OFFSET) \
 47	DMUB_SR(DMCUB_REGION3_CW4_OFFSET) \
 48	DMUB_SR(DMCUB_REGION3_CW5_OFFSET) \
 49	DMUB_SR(DMCUB_REGION3_CW6_OFFSET) \
 50	DMUB_SR(DMCUB_REGION3_CW7_OFFSET) \
 51	DMUB_SR(DMCUB_REGION3_CW0_OFFSET_HIGH) \
 52	DMUB_SR(DMCUB_REGION3_CW1_OFFSET_HIGH) \
 53	DMUB_SR(DMCUB_REGION3_CW2_OFFSET_HIGH) \
 54	DMUB_SR(DMCUB_REGION3_CW3_OFFSET_HIGH) \
 55	DMUB_SR(DMCUB_REGION3_CW4_OFFSET_HIGH) \
 56	DMUB_SR(DMCUB_REGION3_CW5_OFFSET_HIGH) \
 57	DMUB_SR(DMCUB_REGION3_CW6_OFFSET_HIGH) \
 58	DMUB_SR(DMCUB_REGION3_CW7_OFFSET_HIGH) \
 59	DMUB_SR(DMCUB_REGION3_CW0_BASE_ADDRESS) \
 60	DMUB_SR(DMCUB_REGION3_CW1_BASE_ADDRESS) \
 61	DMUB_SR(DMCUB_REGION3_CW2_BASE_ADDRESS) \
 62	DMUB_SR(DMCUB_REGION3_CW3_BASE_ADDRESS) \
 63	DMUB_SR(DMCUB_REGION3_CW4_BASE_ADDRESS) \
 64	DMUB_SR(DMCUB_REGION3_CW5_BASE_ADDRESS) \
 65	DMUB_SR(DMCUB_REGION3_CW6_BASE_ADDRESS) \
 66	DMUB_SR(DMCUB_REGION3_CW7_BASE_ADDRESS) \
 67	DMUB_SR(DMCUB_REGION3_CW0_TOP_ADDRESS) \
 68	DMUB_SR(DMCUB_REGION3_CW1_TOP_ADDRESS) \
 69	DMUB_SR(DMCUB_REGION3_CW2_TOP_ADDRESS) \
 70	DMUB_SR(DMCUB_REGION3_CW3_TOP_ADDRESS) \
 71	DMUB_SR(DMCUB_REGION3_CW4_TOP_ADDRESS) \
 72	DMUB_SR(DMCUB_REGION3_CW5_TOP_ADDRESS) \
 73	DMUB_SR(DMCUB_REGION3_CW6_TOP_ADDRESS) \
 74	DMUB_SR(DMCUB_REGION3_CW7_TOP_ADDRESS) \
 75	DMUB_SR(DMCUB_REGION4_OFFSET) \
 76	DMUB_SR(DMCUB_REGION4_OFFSET_HIGH) \
 77	DMUB_SR(DMCUB_REGION4_TOP_ADDRESS) \
 78	DMUB_SR(DMCUB_SCRATCH0) \
 79	DMUB_SR(DMCUB_SCRATCH1) \
 80	DMUB_SR(DMCUB_SCRATCH2) \
 81	DMUB_SR(DMCUB_SCRATCH3) \
 82	DMUB_SR(DMCUB_SCRATCH4) \
 83	DMUB_SR(DMCUB_SCRATCH5) \
 84	DMUB_SR(DMCUB_SCRATCH6) \
 85	DMUB_SR(DMCUB_SCRATCH7) \
 86	DMUB_SR(DMCUB_SCRATCH8) \
 87	DMUB_SR(DMCUB_SCRATCH9) \
 88	DMUB_SR(DMCUB_SCRATCH10) \
 89	DMUB_SR(DMCUB_SCRATCH11) \
 90	DMUB_SR(DMCUB_SCRATCH12) \
 91	DMUB_SR(DMCUB_SCRATCH13) \
 92	DMUB_SR(DMCUB_SCRATCH14) \
 93	DMUB_SR(DMCUB_SCRATCH15) \
 94	DMUB_SR(DMCUB_GPINT_DATAIN1) \
 95	DMUB_SR(CC_DC_PIPE_DIS) \
 96	DMUB_SR(MMHUBBUB_SOFT_RESET) \
 97	DMUB_SR(DCN_VM_FB_LOCATION_BASE) \
 98	DMUB_SR(DCN_VM_FB_OFFSET)
 99
100#define DMUB_COMMON_FIELDS() \
101	DMUB_SF(DMCUB_CNTL, DMCUB_ENABLE) \
102	DMUB_SF(DMCUB_CNTL, DMCUB_SOFT_RESET) \
103	DMUB_SF(DMCUB_CNTL, DMCUB_TRACEPORT_EN) \
104	DMUB_SF(DMCUB_MEM_CNTL, DMCUB_MEM_READ_SPACE) \
105	DMUB_SF(DMCUB_MEM_CNTL, DMCUB_MEM_WRITE_SPACE) \
106	DMUB_SF(DMCUB_SEC_CNTL, DMCUB_SEC_RESET) \
107	DMUB_SF(DMCUB_SEC_CNTL, DMCUB_MEM_UNIT_ID) \
108	DMUB_SF(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_TOP_ADDRESS) \
109	DMUB_SF(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE) \
110	DMUB_SF(DMCUB_REGION3_CW1_TOP_ADDRESS, DMCUB_REGION3_CW1_TOP_ADDRESS) \
111	DMUB_SF(DMCUB_REGION3_CW1_TOP_ADDRESS, DMCUB_REGION3_CW1_ENABLE) \
112	DMUB_SF(DMCUB_REGION3_CW2_TOP_ADDRESS, DMCUB_REGION3_CW2_TOP_ADDRESS) \
113	DMUB_SF(DMCUB_REGION3_CW2_TOP_ADDRESS, DMCUB_REGION3_CW2_ENABLE) \
114	DMUB_SF(DMCUB_REGION3_CW3_TOP_ADDRESS, DMCUB_REGION3_CW3_TOP_ADDRESS) \
115	DMUB_SF(DMCUB_REGION3_CW3_TOP_ADDRESS, DMCUB_REGION3_CW3_ENABLE) \
116	DMUB_SF(DMCUB_REGION3_CW4_TOP_ADDRESS, DMCUB_REGION3_CW4_TOP_ADDRESS) \
117	DMUB_SF(DMCUB_REGION3_CW4_TOP_ADDRESS, DMCUB_REGION3_CW4_ENABLE) \
118	DMUB_SF(DMCUB_REGION3_CW5_TOP_ADDRESS, DMCUB_REGION3_CW5_TOP_ADDRESS) \
119	DMUB_SF(DMCUB_REGION3_CW5_TOP_ADDRESS, DMCUB_REGION3_CW5_ENABLE) \
120	DMUB_SF(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_TOP_ADDRESS) \
121	DMUB_SF(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE) \
122	DMUB_SF(DMCUB_REGION3_CW7_TOP_ADDRESS, DMCUB_REGION3_CW7_TOP_ADDRESS) \
123	DMUB_SF(DMCUB_REGION3_CW7_TOP_ADDRESS, DMCUB_REGION3_CW7_ENABLE) \
124	DMUB_SF(DMCUB_REGION4_TOP_ADDRESS, DMCUB_REGION4_TOP_ADDRESS) \
125	DMUB_SF(DMCUB_REGION4_TOP_ADDRESS, DMCUB_REGION4_ENABLE) \
126	DMUB_SF(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE) \
127	DMUB_SF(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET) \
128	DMUB_SF(DCN_VM_FB_LOCATION_BASE, FB_BASE) \
129	DMUB_SF(DCN_VM_FB_OFFSET, FB_OFFSET)
130
131struct dmub_srv_common_reg_offset {
132#define DMUB_SR(reg) uint32_t reg;
133	DMUB_COMMON_REGS()
134#undef DMUB_SR
135};
136
137struct dmub_srv_common_reg_shift {
138#define DMUB_SF(reg, field) uint8_t reg##__##field;
139	DMUB_COMMON_FIELDS()
140#undef DMUB_SF
141};
142
143struct dmub_srv_common_reg_mask {
144#define DMUB_SF(reg, field) uint32_t reg##__##field;
145	DMUB_COMMON_FIELDS()
146#undef DMUB_SF
147};
148
149struct dmub_srv_common_regs {
150	const struct dmub_srv_common_reg_offset offset;
151	const struct dmub_srv_common_reg_mask mask;
152	const struct dmub_srv_common_reg_shift shift;
153};
154
155extern const struct dmub_srv_common_regs dmub_srv_dcn20_regs;
156
157/* Hardware functions. */
158
159void dmub_dcn20_init(struct dmub_srv *dmub);
160
161void dmub_dcn20_reset(struct dmub_srv *dmub);
162
163void dmub_dcn20_reset_release(struct dmub_srv *dmub);
164
165void dmub_dcn20_backdoor_load(struct dmub_srv *dmub,
166			      const struct dmub_window *cw0,
167			      const struct dmub_window *cw1);
168
169void dmub_dcn20_setup_windows(struct dmub_srv *dmub,
170			      const struct dmub_window *cw2,
171			      const struct dmub_window *cw3,
172			      const struct dmub_window *cw4,
173			      const struct dmub_window *cw5,
174			      const struct dmub_window *cw6);
175
176void dmub_dcn20_setup_mailbox(struct dmub_srv *dmub,
177			      const struct dmub_region *inbox1);
178
179uint32_t dmub_dcn20_get_inbox1_rptr(struct dmub_srv *dmub);
180
181void dmub_dcn20_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset);
182
183bool dmub_dcn20_is_hw_init(struct dmub_srv *dmub);
184
185bool dmub_dcn20_is_supported(struct dmub_srv *dmub);
186
187void dmub_dcn20_set_gpint(struct dmub_srv *dmub,
188			  union dmub_gpint_data_register reg);
189
190bool dmub_dcn20_is_gpint_acked(struct dmub_srv *dmub,
191			       union dmub_gpint_data_register reg);
192
193uint32_t dmub_dcn20_get_gpint_response(struct dmub_srv *dmub);
194
195#endif /* _DMUB_DCN20_H_ */